Re: [PATCH v1 04/21] mtk-mmsys: add mt8192 mmsys support
Hi, Yongqiang:
Yongqiang Niu 於 2020年8月20日 週四 下午2:16寫道：
>
> add mt8192 mmsys support
>
> Signed-off-by: Yongqiang Niu
> ---
> drivers/soc/mediatek/mmsys/Makefile | 1 +
> drivers/soc/mediatek/mmsys/mt8192-mmsys.c | 159
> ++
> 2 files changed, 160 insertions(+)
> create mode 100644 drivers/soc/mediatek/mmsys/mt8192-mmsys.c
>
> diff --git a/drivers/soc/mediatek/mmsys/Makefile
> b/drivers/soc/mediatek/mmsys/Makefile
> index 62cfedf..c4bb6be 100644
> --- a/drivers/soc/mediatek/mmsys/Makefile
> +++ b/drivers/soc/mediatek/mmsys/Makefile
> @@ -1,3 +1,4 @@
> # SPDX-License-Identifier: GPL-2.0-only
> obj-y += mt2701-mmsys.o
> obj-y += mt8183-mmsys.o
> +obj-y += mt8192-mmsys.o
> diff --git a/drivers/soc/mediatek/mmsys/mt8192-mmsys.c
> b/drivers/soc/mediatek/mmsys/mt8192-mmsys.c
> new file mode 100644
> index 000..006d41d
> --- /dev/null
> +++ b/drivers/soc/mediatek/mmsys/mt8192-mmsys.c
> @@ -0,0 +1,159 @@
> +// SPDX-License-Identifier: GPL-2.0
> +//
> +// Copyright (c) 2020 MediaTek Inc.
> +
> +#include
> +#include
> +#include
> +#include
> +#include
> +
> +#define MT8192_MMSYS_OVL_MOUT_EN 0xf04
> +#define DISP_OVL0_GO_BLEND BIT(0)
> +#define DISP_OVL0_GO_BGBIT(1)
> +#define DISP_OVL0_2L_GO_BLEND BIT(2)
> +#define DISP_OVL0_2L_GO_BG BIT(3)
> +#define MT8192_DISP_OVL0_2L_MOUT_EN0xf18
> +#define MT8192_DISP_OVL0_MOUT_EN 0xf1c
> +#define OVL0_MOUT_EN_DISP_RDMA0BIT(0)
> +#define MT8192_DISP_RDMA0_SEL_IN 0xf2c
> +#define MT8192_RDMA0_SEL_IN_OVL0_2L0x3
> +#define MT8192_DISP_RDMA0_SOUT_SEL 0xf30
> +#define MT8192_RDMA0_SOUT_COLOR0 0x1
> +#define MT8192_DISP_CCORR0_SOUT_SEL0xf34
> +#define MT8192_CCORR0_SOUT_AAL00x1
> +#define MT8192_DISP_AAL0_SEL_IN0xf38
> +#define MT8192_AAL0_SEL_IN_CCORR0 0x1
> +#define MT8192_DISP_DITHER0_MOUT_EN0xf3c
> +#define MT8192_DITHER0_MOUT_DSI0 BIT(0)
> +#define MT8192_DISP_DSI0_SEL_IN0xf40
> +#define MT8192_DSI0_SEL_IN_DITHER0 0x1
> +#define MT8192_DISP_OVL2_2L_MOUT_EN0xf4c
> +#define MT8192_OVL2_2L_MOUT_RDMA4 BIT(0)
> +
> +struct mmsys_path_sel {
> + enum mtk_ddp_comp_id cur;
> + enum mtk_ddp_comp_id next;
> + u32 addr;
> + u32 val;
> +};
> +
> +static struct mmsys_path_sel mmsys_mout_en[] = {
> + {
> + DDP_COMPONENT_OVL_2L0, DDP_COMPONENT_RDMA0,
> + MT8192_DISP_OVL0_MOUT_EN, OVL0_MOUT_EN_DISP_RDMA0,
> + },
> + {
> + DDP_COMPONENT_OVL_2L2, DDP_COMPONENT_RDMA4,
> + MT8192_DISP_OVL2_2L_MOUT_EN, MT8192_OVL2_2L_MOUT_RDMA4,
> + },
> + {
> + DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,
> + MT8192_DISP_DITHER0_MOUT_EN, MT8192_DITHER0_MOUT_DSI0,
> + },
> +};
> +
> +static struct mmsys_path_sel mmsys_sel_in[] = {
> + {
> + DDP_COMPONENT_OVL_2L0, DDP_COMPONENT_RDMA0,
> + MT8192_DISP_RDMA0_SEL_IN, MT8192_RDMA0_SEL_IN_OVL0_2L,
> + },
> + {
> + DDP_COMPONENT_CCORR, DDP_COMPONENT_AAL0,
> + MT8192_DISP_AAL0_SEL_IN, MT8192_AAL0_SEL_IN_CCORR0,
> + },
> + {
> + DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,
> + MT8192_DISP_DSI0_SEL_IN, MT8192_DSI0_SEL_IN_DITHER0,
> + },
> +};
> +
> +static struct mmsys_path_sel mmsys_sout_sel[] = {
> + {
> + DDP_COMPONENT_RDMA0, DDP_COMPONENT_COLOR0,
> + MT8192_DISP_RDMA0_SOUT_SEL, MT8192_RDMA0_SOUT_COLOR0,
> + },
> + {
> + DDP_COMPONENT_CCORR, DDP_COMPONENT_AAL0,
> + MT8192_DISP_CCORR0_SOUT_SEL, MT8192_CCORR0_SOUT_AAL0,
> + }
> +};
> +
> +static unsigned int mtk_mmsys_ddp_mout_en(enum mtk_ddp_comp_id cur,
> + enum mtk_ddp_comp_id next,
> + unsigned int *addr)
> +{
> + u32 i;
> + struct mmsys_path_sel *path;
> +
> + for (i = 0; i < ARRAY_SIZE(mmsys_mout_en); i++) {
> + path = _mout_en[i];
> + if (cur == path->cur && next == path->next) {
> + *addr = path->addr;
> + return path->val;
> + }
> + }
> +
> + return 0;
> +}
> +
> +static unsigned int mtk_mmsys_ddp_sel_in(enum mtk_ddp_comp_id cur,
> +enum mtk_ddp_comp_id next,
> +unsigned int *addr)
> +{
> + u32 i;
> + struct mmsys_path_sel *path;
> +
> + for (i = 0; i < ARRAY_SIZE(mmsys_sel_in); i++) {
> +
[PATCH v1 04/21] mtk-mmsys: add mt8192 mmsys support
add mt8192 mmsys support
Signed-off-by: Yongqiang Niu
---
drivers/soc/mediatek/mmsys/Makefile | 1 +
drivers/soc/mediatek/mmsys/mt8192-mmsys.c | 159 ++
2 files changed, 160 insertions(+)
create mode 100644 drivers/soc/mediatek/mmsys/mt8192-mmsys.c
diff --git a/drivers/soc/mediatek/mmsys/Makefile
b/drivers/soc/mediatek/mmsys/Makefile
index 62cfedf..c4bb6be 100644
--- a/drivers/soc/mediatek/mmsys/Makefile
+++ b/drivers/soc/mediatek/mmsys/Makefile
@@ -1,3 +1,4 @@
# SPDX-License-Identifier: GPL-2.0-only
obj-y += mt2701-mmsys.o
obj-y += mt8183-mmsys.o
+obj-y += mt8192-mmsys.o
diff --git a/drivers/soc/mediatek/mmsys/mt8192-mmsys.c
b/drivers/soc/mediatek/mmsys/mt8192-mmsys.c
new file mode 100644
index 000..006d41d
--- /dev/null
+++ b/drivers/soc/mediatek/mmsys/mt8192-mmsys.c
@@ -0,0 +1,159 @@
+// SPDX-License-Identifier: GPL-2.0
+//
+// Copyright (c) 2020 MediaTek Inc.
+
+#include
+#include
+#include
+#include
+#include
+
+#define MT8192_MMSYS_OVL_MOUT_EN 0xf04
+#define DISP_OVL0_GO_BLEND BIT(0)
+#define DISP_OVL0_GO_BGBIT(1)
+#define DISP_OVL0_2L_GO_BLEND BIT(2)
+#define DISP_OVL0_2L_GO_BG BIT(3)
+#define MT8192_DISP_OVL0_2L_MOUT_EN0xf18
+#define MT8192_DISP_OVL0_MOUT_EN 0xf1c
+#define OVL0_MOUT_EN_DISP_RDMA0BIT(0)
+#define MT8192_DISP_RDMA0_SEL_IN 0xf2c
+#define MT8192_RDMA0_SEL_IN_OVL0_2L0x3
+#define MT8192_DISP_RDMA0_SOUT_SEL 0xf30
+#define MT8192_RDMA0_SOUT_COLOR0 0x1
+#define MT8192_DISP_CCORR0_SOUT_SEL0xf34
+#define MT8192_CCORR0_SOUT_AAL00x1
+#define MT8192_DISP_AAL0_SEL_IN0xf38
+#define MT8192_AAL0_SEL_IN_CCORR0 0x1
+#define MT8192_DISP_DITHER0_MOUT_EN0xf3c
+#define MT8192_DITHER0_MOUT_DSI0 BIT(0)
+#define MT8192_DISP_DSI0_SEL_IN0xf40
+#define MT8192_DSI0_SEL_IN_DITHER0 0x1
+#define MT8192_DISP_OVL2_2L_MOUT_EN0xf4c
+#define MT8192_OVL2_2L_MOUT_RDMA4 BIT(0)
+
+struct mmsys_path_sel {
+ enum mtk_ddp_comp_id cur;
+ enum mtk_ddp_comp_id next;
+ u32 addr;
+ u32 val;
+};
+
+static struct mmsys_path_sel mmsys_mout_en[] = {
+ {
+ DDP_COMPONENT_OVL_2L0, DDP_COMPONENT_RDMA0,
+ MT8192_DISP_OVL0_MOUT_EN, OVL0_MOUT_EN_DISP_RDMA0,
+ },
+ {
+ DDP_COMPONENT_OVL_2L2, DDP_COMPONENT_RDMA4,
+ MT8192_DISP_OVL2_2L_MOUT_EN, MT8192_OVL2_2L_MOUT_RDMA4,
+ },
+ {
+ DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,
+ MT8192_DISP_DITHER0_MOUT_EN, MT8192_DITHER0_MOUT_DSI0,
+ },
+};
+
+static struct mmsys_path_sel mmsys_sel_in[] = {
+ {
+ DDP_COMPONENT_OVL_2L0, DDP_COMPONENT_RDMA0,
+ MT8192_DISP_RDMA0_SEL_IN, MT8192_RDMA0_SEL_IN_OVL0_2L,
+ },
+ {
+ DDP_COMPONENT_CCORR, DDP_COMPONENT_AAL0,
+ MT8192_DISP_AAL0_SEL_IN, MT8192_AAL0_SEL_IN_CCORR0,
+ },
+ {
+ DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,
+ MT8192_DISP_DSI0_SEL_IN, MT8192_DSI0_SEL_IN_DITHER0,
+ },
+};
+
+static struct mmsys_path_sel mmsys_sout_sel[] = {
+ {
+ DDP_COMPONENT_RDMA0, DDP_COMPONENT_COLOR0,
+ MT8192_DISP_RDMA0_SOUT_SEL, MT8192_RDMA0_SOUT_COLOR0,
+ },
+ {
+ DDP_COMPONENT_CCORR, DDP_COMPONENT_AAL0,
+ MT8192_DISP_CCORR0_SOUT_SEL, MT8192_CCORR0_SOUT_AAL0,
+ }
+};
+
+static unsigned int mtk_mmsys_ddp_mout_en(enum mtk_ddp_comp_id cur,
+ enum mtk_ddp_comp_id next,
+ unsigned int *addr)
+{
+ u32 i;
+ struct mmsys_path_sel *path;
+
+ for (i = 0; i < ARRAY_SIZE(mmsys_mout_en); i++) {
+ path = _mout_en[i];
+ if (cur == path->cur && next == path->next) {
+ *addr = path->addr;
+ return path->val;
+ }
+ }
+
+ return 0;
+}
+
+static unsigned int mtk_mmsys_ddp_sel_in(enum mtk_ddp_comp_id cur,
+enum mtk_ddp_comp_id next,
+unsigned int *addr)
+{
+ u32 i;
+ struct mmsys_path_sel *path;
+
+ for (i = 0; i < ARRAY_SIZE(mmsys_sel_in); i++) {
+ path = _sel_in[i];
+ if (cur == path->cur && next == path->next) {
+ *addr = path->addr;
+ return path->val;
+ }
+ }
+
+ return 0;
+}
+
+static void mtk_mmsys_ddp_sout_sel(void __iomem *config_regs,
+
