Re: [PATCH v10 1/2] dt-bindings: display/bridge: Add binding for NWL mipi dsi host controller
Hi, On Wed, Apr 08, 2020 at 07:32:58PM +0200, Sam Ravnborg wrote: > Hi Guido. > > We discussed this binding briefly on IRC: > > 19:28 port 0 is defined as > 19:28 + Input port node to receive pixel data from the > 19:28 + display controller. Exactly one endpoint must be > 19:28 + specified. > 19:28 then there's two endpoints, There's only a single one allowed due to https://lore.kernel.org/linux-arm-kernel/c86b7ca2-7799-eafd-c380-e4b551520...@samsung.com/ Back when doing that i couldn't figure out a way how to specify this but I've figured it out now. Cheers, -- Guido > > > On Fri, Mar 20, 2020 at 07:49:09PM +0100, Guido Günther wrote: > > The Northwest Logic MIPI DSI IP core can be found in NXPs i.MX8 SoCs. > > > > Signed-off-by: Guido Günther > > Tested-by: Robert Chiras > > Reviewed-by: Rob Herring > > Acked-by: Sam Ravnborg > > --- > > .../bindings/display/bridge/nwl-dsi.yaml | 216 ++ > > 1 file changed, 216 insertions(+) > > create mode 100644 > > Documentation/devicetree/bindings/display/bridge/nwl-dsi.yaml > > > > diff --git a/Documentation/devicetree/bindings/display/bridge/nwl-dsi.yaml > > b/Documentation/devicetree/bindings/display/bridge/nwl-dsi.yaml > > new file mode 100644 > > index ..ec1e7e12719d > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/display/bridge/nwl-dsi.yaml > > @@ -0,0 +1,216 @@ > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > > +%YAML 1.2 > > +--- > > +$id: http://devicetree.org/schemas/display/bridge/nwl-dsi.yaml# > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > + > > +title: Northwest Logic MIPI-DSI controller on i.MX SoCs > > + > > +maintainers: > > + - Guido Gúnther > > + - Robert Chiras > > + > > +description: | > > + NWL MIPI-DSI host controller found on i.MX8 platforms. This is a dsi > > bridge for > > + the SOCs NWL MIPI-DSI host controller. > > + > > +properties: > > + compatible: > > +const: fsl,imx8mq-nwl-dsi > > + > > + reg: > > +maxItems: 1 > > + > > + interrupts: > > +maxItems: 1 > > + > > + '#address-cells': > > +const: 1 > > + > > + '#size-cells': > > +const: 0 > > + > > + clocks: > > +items: > > + - description: DSI core clock > > + - description: RX_ESC clock (used in escape mode) > > + - description: TX_ESC clock (used in escape mode) > > + - description: PHY_REF clock > > + - description: LCDIF clock > > + > > + clock-names: > > +items: > > + - const: core > > + - const: rx_esc > > + - const: tx_esc > > + - const: phy_ref > > + - const: lcdif > > + > > + mux-controls: > > +description: > > + mux controller node to use for operating the input mux > > + > > + phys: > > +maxItems: 1 > > +description: > > + A phandle to the phy module representing the DPHY > > + > > + phy-names: > > +items: > > + - const: dphy > > + > > + power-domains: > > +maxItems: 1 > > + > > + resets: > > +items: > > + - description: dsi byte reset line > > + - description: dsi dpi reset line > > + - description: dsi esc reset line > > + - description: dsi pclk reset line > > + > > + reset-names: > > +items: > > + - const: byte > > + - const: dpi > > + - const: esc > > + - const: pclk > > + > > + ports: > > +type: object > > +description: > > + A node containing DSI input & output port nodes with endpoint > > + definitions as documented in > > + Documentation/devicetree/bindings/graph.txt. > > +properties: > > + port@0: > > +type: object > > +description: > > + Input port node to receive pixel data from the > > + display controller. Exactly one endpoint must be > > + specified. > > +properties: > > + '#address-cells': > > +const: 1 > > + > > + '#size-cells': > > +const: 0 > > + > > + endpoint@0: > > +description: sub-node describing the input from LCDIF > > +type: object > > + > > + endpoint@1: > > +description: sub-node describing the input from DCSS > > +type: object > > + > > + reg: > > +const: 0 > > + > > +required: > > + - '#address-cells' > > + - '#size-cells' > > + - reg > > +additionalProperties: false > > + > > + port@1: > > +type: object > > +description: > > + DSI output port node to the panel or the next bridge > > + in the chain > > + > > + '#address-cells': > > +const: 1 > > + > > + '#size-cells': > > +const: 0 > > + > > +required: > > + - '#address-cells' > > + - '#size-cells' > > + - port@0 > > + - port@1 > > + > > +additionalProperties: false > > For the casual reader the above confuses. > Assuming the binding is correct,
Re: [PATCH v10 1/2] dt-bindings: display/bridge: Add binding for NWL mipi dsi host controller
Hi Guido.
We discussed this binding briefly on IRC:
19:28 port 0 is defined as
19:28 + Input port node to receive pixel data from the
19:28 + display controller. Exactly one endpoint must be
19:28 + specified.
19:28 then there's two endpoints,
On Fri, Mar 20, 2020 at 07:49:09PM +0100, Guido Günther wrote:
> The Northwest Logic MIPI DSI IP core can be found in NXPs i.MX8 SoCs.
>
> Signed-off-by: Guido Günther
> Tested-by: Robert Chiras
> Reviewed-by: Rob Herring
> Acked-by: Sam Ravnborg
> ---
> .../bindings/display/bridge/nwl-dsi.yaml | 216 ++
> 1 file changed, 216 insertions(+)
> create mode 100644
> Documentation/devicetree/bindings/display/bridge/nwl-dsi.yaml
>
> diff --git a/Documentation/devicetree/bindings/display/bridge/nwl-dsi.yaml
> b/Documentation/devicetree/bindings/display/bridge/nwl-dsi.yaml
> new file mode 100644
> index ..ec1e7e12719d
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/display/bridge/nwl-dsi.yaml
> @@ -0,0 +1,216 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/display/bridge/nwl-dsi.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Northwest Logic MIPI-DSI controller on i.MX SoCs
> +
> +maintainers:
> + - Guido Gúnther
> + - Robert Chiras
> +
> +description: |
> + NWL MIPI-DSI host controller found on i.MX8 platforms. This is a dsi
> bridge for
> + the SOCs NWL MIPI-DSI host controller.
> +
> +properties:
> + compatible:
> +const: fsl,imx8mq-nwl-dsi
> +
> + reg:
> +maxItems: 1
> +
> + interrupts:
> +maxItems: 1
> +
> + '#address-cells':
> +const: 1
> +
> + '#size-cells':
> +const: 0
> +
> + clocks:
> +items:
> + - description: DSI core clock
> + - description: RX_ESC clock (used in escape mode)
> + - description: TX_ESC clock (used in escape mode)
> + - description: PHY_REF clock
> + - description: LCDIF clock
> +
> + clock-names:
> +items:
> + - const: core
> + - const: rx_esc
> + - const: tx_esc
> + - const: phy_ref
> + - const: lcdif
> +
> + mux-controls:
> +description:
> + mux controller node to use for operating the input mux
> +
> + phys:
> +maxItems: 1
> +description:
> + A phandle to the phy module representing the DPHY
> +
> + phy-names:
> +items:
> + - const: dphy
> +
> + power-domains:
> +maxItems: 1
> +
> + resets:
> +items:
> + - description: dsi byte reset line
> + - description: dsi dpi reset line
> + - description: dsi esc reset line
> + - description: dsi pclk reset line
> +
> + reset-names:
> +items:
> + - const: byte
> + - const: dpi
> + - const: esc
> + - const: pclk
> +
> + ports:
> +type: object
> +description:
> + A node containing DSI input & output port nodes with endpoint
> + definitions as documented in
> + Documentation/devicetree/bindings/graph.txt.
> +properties:
> + port@0:
> +type: object
> +description:
> + Input port node to receive pixel data from the
> + display controller. Exactly one endpoint must be
> + specified.
> +properties:
> + '#address-cells':
> +const: 1
> +
> + '#size-cells':
> +const: 0
> +
> + endpoint@0:
> +description: sub-node describing the input from LCDIF
> +type: object
> +
> + endpoint@1:
> +description: sub-node describing the input from DCSS
> +type: object
> +
> + reg:
> +const: 0
> +
> +required:
> + - '#address-cells'
> + - '#size-cells'
> + - reg
> +additionalProperties: false
> +
> + port@1:
> +type: object
> +description:
> + DSI output port node to the panel or the next bridge
> + in the chain
> +
> + '#address-cells':
> +const: 1
> +
> + '#size-cells':
> +const: 0
> +
> +required:
> + - '#address-cells'
> + - '#size-cells'
> + - port@0
> + - port@1
> +
> +additionalProperties: false
For the casual reader the above confuses.
Assuming the binding is correct, can we have the comment updated.
Sam
> +
> +patternProperties:
> + "^panel@[0-9]+$":
> +type: object
> +
> +required:
> + - '#address-cells'
> + - '#size-cells'
> + - clock-names
> + - clocks
> + - compatible
> + - interrupts
> + - mux-controls
> + - phy-names
> + - phys
> + - ports
> + - reg
> + - reset-names
> + - resets
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> +
> + #include
> + #include
> + #include
> +
> + mipi_dsi: mipi_dsi@30a0 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + compatible = "fsl,imx8mq-nwl-dsi";
> + reg = <0x3
Re: [PATCH v10 1/2] dt-bindings: display/bridge: Add binding for NWL mipi dsi host controller
On Fri, Mar 20, 2020 at 3:49 PM Guido Günther wrote: > > The Northwest Logic MIPI DSI IP core can be found in NXPs i.MX8 SoCs. > > Signed-off-by: Guido Günther > Tested-by: Robert Chiras > Reviewed-by: Rob Herring > Acked-by: Sam Ravnborg Reviewed-by: Fabio Estevam ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH v10 1/2] dt-bindings: display/bridge: Add binding for NWL mipi dsi host controller
The Northwest Logic MIPI DSI IP core can be found in NXPs i.MX8 SoCs.
Signed-off-by: Guido Günther
Tested-by: Robert Chiras
Reviewed-by: Rob Herring
Acked-by: Sam Ravnborg
---
.../bindings/display/bridge/nwl-dsi.yaml | 216 ++
1 file changed, 216 insertions(+)
create mode 100644
Documentation/devicetree/bindings/display/bridge/nwl-dsi.yaml
diff --git a/Documentation/devicetree/bindings/display/bridge/nwl-dsi.yaml
b/Documentation/devicetree/bindings/display/bridge/nwl-dsi.yaml
new file mode 100644
index ..ec1e7e12719d
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/bridge/nwl-dsi.yaml
@@ -0,0 +1,216 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/bridge/nwl-dsi.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Northwest Logic MIPI-DSI controller on i.MX SoCs
+
+maintainers:
+ - Guido Gúnther
+ - Robert Chiras
+
+description: |
+ NWL MIPI-DSI host controller found on i.MX8 platforms. This is a dsi bridge
for
+ the SOCs NWL MIPI-DSI host controller.
+
+properties:
+ compatible:
+const: fsl,imx8mq-nwl-dsi
+
+ reg:
+maxItems: 1
+
+ interrupts:
+maxItems: 1
+
+ '#address-cells':
+const: 1
+
+ '#size-cells':
+const: 0
+
+ clocks:
+items:
+ - description: DSI core clock
+ - description: RX_ESC clock (used in escape mode)
+ - description: TX_ESC clock (used in escape mode)
+ - description: PHY_REF clock
+ - description: LCDIF clock
+
+ clock-names:
+items:
+ - const: core
+ - const: rx_esc
+ - const: tx_esc
+ - const: phy_ref
+ - const: lcdif
+
+ mux-controls:
+description:
+ mux controller node to use for operating the input mux
+
+ phys:
+maxItems: 1
+description:
+ A phandle to the phy module representing the DPHY
+
+ phy-names:
+items:
+ - const: dphy
+
+ power-domains:
+maxItems: 1
+
+ resets:
+items:
+ - description: dsi byte reset line
+ - description: dsi dpi reset line
+ - description: dsi esc reset line
+ - description: dsi pclk reset line
+
+ reset-names:
+items:
+ - const: byte
+ - const: dpi
+ - const: esc
+ - const: pclk
+
+ ports:
+type: object
+description:
+ A node containing DSI input & output port nodes with endpoint
+ definitions as documented in
+ Documentation/devicetree/bindings/graph.txt.
+properties:
+ port@0:
+type: object
+description:
+ Input port node to receive pixel data from the
+ display controller. Exactly one endpoint must be
+ specified.
+properties:
+ '#address-cells':
+const: 1
+
+ '#size-cells':
+const: 0
+
+ endpoint@0:
+description: sub-node describing the input from LCDIF
+type: object
+
+ endpoint@1:
+description: sub-node describing the input from DCSS
+type: object
+
+ reg:
+const: 0
+
+required:
+ - '#address-cells'
+ - '#size-cells'
+ - reg
+additionalProperties: false
+
+ port@1:
+type: object
+description:
+ DSI output port node to the panel or the next bridge
+ in the chain
+
+ '#address-cells':
+const: 1
+
+ '#size-cells':
+const: 0
+
+required:
+ - '#address-cells'
+ - '#size-cells'
+ - port@0
+ - port@1
+
+additionalProperties: false
+
+patternProperties:
+ "^panel@[0-9]+$":
+type: object
+
+required:
+ - '#address-cells'
+ - '#size-cells'
+ - clock-names
+ - clocks
+ - compatible
+ - interrupts
+ - mux-controls
+ - phy-names
+ - phys
+ - ports
+ - reg
+ - reset-names
+ - resets
+
+additionalProperties: false
+
+examples:
+ - |
+
+ #include
+ #include
+ #include
+
+ mipi_dsi: mipi_dsi@30a0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx8mq-nwl-dsi";
+ reg = <0x30A0 0x300>;
+ clocks = <&clk IMX8MQ_CLK_DSI_CORE>,
+ <&clk IMX8MQ_CLK_DSI_AHB>,
+ <&clk IMX8MQ_CLK_DSI_IPG_DIV>,
+ <&clk IMX8MQ_CLK_DSI_PHY_REF>,
+ <&clk IMX8MQ_CLK_LCDIF_PIXEL>;
+ clock-names = "core", "rx_esc", "tx_esc", "phy_ref", "lcdif";
+ interrupts = ;
+ mux-controls = <&mux 0>;
+ power-domains = <&pgc_mipi>;
+ resets = <&src IMX8MQ_RESET_MIPI_DSI_RESET_BYTE_N>,
+ <&src IMX8MQ_RESET_MIPI_DSI_DPI_RESET_N>,
+ <&src IMX8MQ_RESET_MIPI_DSI_ESC_RESET_N>,
+ <&src IMX8MQ_RESET_MIPI_DSI_PCLK_RESET_N>;
+ reset-names = "byte", "dpi", "esc", "pclk";
+ phys = <&dphy>;
+
