Re: [PATCH v10 13/24] drm/mediatek: Manage component's clock with function pointers

2023-10-24 Thread 胡俊光


Re: [PATCH v10 13/24] drm/mediatek: Manage component's clock with function pointers

2023-10-19 Thread AngeloGioacchino Del Regno

Il 19/10/23 07:56, Hsiao Chien Sung ha scritto:

By registering component related functions to the pointers,
we can easily manage them within a for-loop and simplify the
logic of clock control significantly.

Signed-off-by: Hsiao Chien Sung 


Reviewed-by: AngeloGioacchino Del Regno 




[PATCH v10 13/24] drm/mediatek: Manage component's clock with function pointers

2023-10-18 Thread Hsiao Chien Sung
By registering component related functions to the pointers,
we can easily manage them within a for-loop and simplify the
logic of clock control significantly.

Signed-off-by: Hsiao Chien Sung 
---
 .../gpu/drm/mediatek/mtk_disp_ovl_adaptor.c   | 89 +--
 1 file changed, 43 insertions(+), 46 deletions(-)

diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c 
b/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c
index d55d8931a36f..81067f49ea69 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c
+++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c
@@ -53,6 +53,7 @@ struct ovl_adaptor_comp_match {
enum mtk_ovl_adaptor_comp_type type;
enum mtk_ddp_comp_id comp_id;
int alias_id;
+   const struct mtk_ddp_comp_funcs *funcs;
 };
 
 struct mtk_disp_ovl_adaptor {
@@ -67,20 +68,35 @@ static const char * const 
private_comp_stem[OVL_ADAPTOR_TYPE_NUM] = {
[OVL_ADAPTOR_TYPE_ETHDR]= "ethdr",
 };
 
+static const struct mtk_ddp_comp_funcs ethdr = {
+   .clk_enable = mtk_ethdr_clk_enable,
+   .clk_disable = mtk_ethdr_clk_disable,
+};
+
+static const struct mtk_ddp_comp_funcs merge = {
+   .clk_enable = mtk_merge_clk_enable,
+   .clk_disable = mtk_merge_clk_disable,
+};
+
+static const struct mtk_ddp_comp_funcs rdma = {
+   .clk_enable = mtk_mdp_rdma_clk_enable,
+   .clk_disable = mtk_mdp_rdma_clk_disable,
+};
+
 static const struct ovl_adaptor_comp_match comp_matches[OVL_ADAPTOR_ID_MAX] = {
-   [OVL_ADAPTOR_MDP_RDMA0] = { OVL_ADAPTOR_TYPE_MDP_RDMA, 
DDP_COMPONENT_MDP_RDMA0, 0 },
-   [OVL_ADAPTOR_MDP_RDMA1] = { OVL_ADAPTOR_TYPE_MDP_RDMA, 
DDP_COMPONENT_MDP_RDMA1, 1 },
-   [OVL_ADAPTOR_MDP_RDMA2] = { OVL_ADAPTOR_TYPE_MDP_RDMA, 
DDP_COMPONENT_MDP_RDMA2, 2 },
-   [OVL_ADAPTOR_MDP_RDMA3] = { OVL_ADAPTOR_TYPE_MDP_RDMA, 
DDP_COMPONENT_MDP_RDMA3, 3 },
-   [OVL_ADAPTOR_MDP_RDMA4] = { OVL_ADAPTOR_TYPE_MDP_RDMA, 
DDP_COMPONENT_MDP_RDMA4, 4 },
-   [OVL_ADAPTOR_MDP_RDMA5] = { OVL_ADAPTOR_TYPE_MDP_RDMA, 
DDP_COMPONENT_MDP_RDMA5, 5 },
-   [OVL_ADAPTOR_MDP_RDMA6] = { OVL_ADAPTOR_TYPE_MDP_RDMA, 
DDP_COMPONENT_MDP_RDMA6, 6 },
-   [OVL_ADAPTOR_MDP_RDMA7] = { OVL_ADAPTOR_TYPE_MDP_RDMA, 
DDP_COMPONENT_MDP_RDMA7, 7 },
-   [OVL_ADAPTOR_MERGE0] = { OVL_ADAPTOR_TYPE_MERGE, DDP_COMPONENT_MERGE1, 
1 },
-   [OVL_ADAPTOR_MERGE1] = { OVL_ADAPTOR_TYPE_MERGE, DDP_COMPONENT_MERGE2, 
2 },
-   [OVL_ADAPTOR_MERGE2] = { OVL_ADAPTOR_TYPE_MERGE, DDP_COMPONENT_MERGE3, 
3 },
-   [OVL_ADAPTOR_MERGE3] = { OVL_ADAPTOR_TYPE_MERGE, DDP_COMPONENT_MERGE4, 
4 },
-   [OVL_ADAPTOR_ETHDR0] = { OVL_ADAPTOR_TYPE_ETHDR, 
DDP_COMPONENT_ETHDR_MIXER, 0 },
+   [OVL_ADAPTOR_MDP_RDMA0] = { OVL_ADAPTOR_TYPE_MDP_RDMA, 
DDP_COMPONENT_MDP_RDMA0, 0,  },
+   [OVL_ADAPTOR_MDP_RDMA1] = { OVL_ADAPTOR_TYPE_MDP_RDMA, 
DDP_COMPONENT_MDP_RDMA1, 1,  },
+   [OVL_ADAPTOR_MDP_RDMA2] = { OVL_ADAPTOR_TYPE_MDP_RDMA, 
DDP_COMPONENT_MDP_RDMA2, 2,  },
+   [OVL_ADAPTOR_MDP_RDMA3] = { OVL_ADAPTOR_TYPE_MDP_RDMA, 
DDP_COMPONENT_MDP_RDMA3, 3,  },
+   [OVL_ADAPTOR_MDP_RDMA4] = { OVL_ADAPTOR_TYPE_MDP_RDMA, 
DDP_COMPONENT_MDP_RDMA4, 4,  },
+   [OVL_ADAPTOR_MDP_RDMA5] = { OVL_ADAPTOR_TYPE_MDP_RDMA, 
DDP_COMPONENT_MDP_RDMA5, 5,  },
+   [OVL_ADAPTOR_MDP_RDMA6] = { OVL_ADAPTOR_TYPE_MDP_RDMA, 
DDP_COMPONENT_MDP_RDMA6, 6,  },
+   [OVL_ADAPTOR_MDP_RDMA7] = { OVL_ADAPTOR_TYPE_MDP_RDMA, 
DDP_COMPONENT_MDP_RDMA7, 7,  },
+   [OVL_ADAPTOR_MERGE0] = { OVL_ADAPTOR_TYPE_MERGE, DDP_COMPONENT_MERGE1, 
1,  },
+   [OVL_ADAPTOR_MERGE1] = { OVL_ADAPTOR_TYPE_MERGE, DDP_COMPONENT_MERGE2, 
2,  },
+   [OVL_ADAPTOR_MERGE2] = { OVL_ADAPTOR_TYPE_MERGE, DDP_COMPONENT_MERGE3, 
3,  },
+   [OVL_ADAPTOR_MERGE3] = { OVL_ADAPTOR_TYPE_MERGE, DDP_COMPONENT_MERGE4, 
4,  },
+   [OVL_ADAPTOR_ETHDR0] = { OVL_ADAPTOR_TYPE_ETHDR, 
DDP_COMPONENT_ETHDR_MIXER, 0,  },
 };
 
 void mtk_ovl_adaptor_layer_config(struct device *dev, unsigned int idx,
@@ -196,40 +212,25 @@ int mtk_ovl_adaptor_clk_enable(struct device *dev)
ret = pm_runtime_get_sync(comp);
if (ret < 0) {
dev_err(dev, "Failed to enable power domain %d, err 
%d\n", i, ret);
-   goto pwr_err;
+   goto error;
}
}
 
for (i = 0; i < OVL_ADAPTOR_ID_MAX; i++) {
comp = ovl_adaptor->ovl_adaptor_comp[i];
-
-   if (i < OVL_ADAPTOR_MERGE0)
-   ret = mtk_mdp_rdma_clk_enable(comp);
-   else if (i < OVL_ADAPTOR_ETHDR0)
-   ret = mtk_merge_clk_enable(comp);
-   else
-   ret = mtk_ethdr_clk_enable(comp);
+   if (!comp || !comp_matches[i].funcs->clk_enable)
+   continue;
+   ret = comp_matches[i].funcs->clk_enable(comp);
if (ret) {
dev_err(dev, "Failed to enable clock %d, err %d\n", i, 
ret);
-