Re: [PATCH v11 2/2] phy: Add driver for mixel mipi dphy found on NXP's i.MX8 SoCs
Hi, On 24/05/19 9:31 PM, Kishon Vijay Abraham I wrote: > Hi, > > On 24/05/19 5:53 PM, Fabio Estevam wrote: >> Hi Kishon, >> >> On Sun, May 12, 2019 at 7:49 AM Guido Günther wrote: >>> >>> This adds support for the Mixel DPHY as found on i.MX8 CPUs but since >>> this is an IP core it will likely be found on others in the future. So >>> instead of adding this to the nwl host driver make it a generic PHY >>> driver. >>> >>> The driver supports the i.MX8MQ. Support for i.MX8QM and i.MX8QXP can be >>> added once the necessary system controller bits are in via >>> mixel_dphy_devdata. >>> >>> Signed-off-by: Guido Günther >>> Co-developed-by: Robert Chiras >>> Signed-off-by: Robert Chiras >>> Reviewed-by: Fabio Estevam >>> Reviewed-by: Sam Ravnborg >> >> Would you have any comments on this series, please? > > I don't have any comments. I'll queue this once I start queuing patches for > the > next merge window. Can you fix the following checkpatch warning and repost? WARNING: quoted string split across lines #420: FILE: drivers/phy/freescale/phy-fsl-imx8-mipi-dphy.c:280: + dev_dbg(>dev, "hs_prepare: %u, clk_prepare: %u, " + "hs_zero: %u, clk_zero: %u, " WARNING: quoted string split across lines #421: FILE: drivers/phy/freescale/phy-fsl-imx8-mipi-dphy.c:281: + "hs_zero: %u, clk_zero: %u, " + "hs_trail: %u, clk_trail: %u, " WARNING: quoted string split across lines #422: FILE: drivers/phy/freescale/phy-fsl-imx8-mipi-dphy.c:282: + "hs_trail: %u, clk_trail: %u, " + "rxhs_settle: %u\n", Thanks Kishon ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: [PATCH v11 2/2] phy: Add driver for mixel mipi dphy found on NXP's i.MX8 SoCs
Hi, On Thu, Jun 20, 2019 at 02:18:53PM +0530, Kishon Vijay Abraham I wrote: > Hi, > > On 24/05/19 9:31 PM, Kishon Vijay Abraham I wrote: > > Hi, > > > > On 24/05/19 5:53 PM, Fabio Estevam wrote: > >> Hi Kishon, > >> > >> On Sun, May 12, 2019 at 7:49 AM Guido Günther wrote: > >>> > >>> This adds support for the Mixel DPHY as found on i.MX8 CPUs but since > >>> this is an IP core it will likely be found on others in the future. So > >>> instead of adding this to the nwl host driver make it a generic PHY > >>> driver. > >>> > >>> The driver supports the i.MX8MQ. Support for i.MX8QM and i.MX8QXP can be > >>> added once the necessary system controller bits are in via > >>> mixel_dphy_devdata. > >>> > >>> Signed-off-by: Guido Günther > >>> Co-developed-by: Robert Chiras > >>> Signed-off-by: Robert Chiras > >>> Reviewed-by: Fabio Estevam > >>> Reviewed-by: Sam Ravnborg > >> > >> Would you have any comments on this series, please? > > > > I don't have any comments. I'll queue this once I start queuing patches for > > the > > next merge window. > > Can you fix the following checkpatch warning and repost? > WARNING: quoted string split across lines > #420: FILE: drivers/phy/freescale/phy-fsl-imx8-mipi-dphy.c:280: > + dev_dbg(>dev, "hs_prepare: %u, clk_prepare: %u, " > + "hs_zero: %u, clk_zero: %u, " > > WARNING: quoted string split across lines > #421: FILE: drivers/phy/freescale/phy-fsl-imx8-mipi-dphy.c:281: > + "hs_zero: %u, clk_zero: %u, " > + "hs_trail: %u, clk_trail: %u, " > > WARNING: quoted string split across lines > #422: FILE: drivers/phy/freescale/phy-fsl-imx8-mipi-dphy.c:282: > + "hs_trail: %u, clk_trail: %u, " > + "rxhs_settle: %u\n", Fixed in v12. Thanks, -- Guido ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: [PATCH v11 2/2] phy: Add driver for mixel mipi dphy found on NXP's i.MX8 SoCs
Hi, On 24/05/19 5:53 PM, Fabio Estevam wrote: > Hi Kishon, > > On Sun, May 12, 2019 at 7:49 AM Guido Günther wrote: >> >> This adds support for the Mixel DPHY as found on i.MX8 CPUs but since >> this is an IP core it will likely be found on others in the future. So >> instead of adding this to the nwl host driver make it a generic PHY >> driver. >> >> The driver supports the i.MX8MQ. Support for i.MX8QM and i.MX8QXP can be >> added once the necessary system controller bits are in via >> mixel_dphy_devdata. >> >> Signed-off-by: Guido Günther >> Co-developed-by: Robert Chiras >> Signed-off-by: Robert Chiras >> Reviewed-by: Fabio Estevam >> Reviewed-by: Sam Ravnborg > > Would you have any comments on this series, please? I don't have any comments. I'll queue this once I start queuing patches for the next merge window. Thanks Kishon
Re: [PATCH v11 2/2] phy: Add driver for mixel mipi dphy found on NXP's i.MX8 SoCs
Hi Kishon, On Sun, May 12, 2019 at 7:49 AM Guido Günther wrote: > > This adds support for the Mixel DPHY as found on i.MX8 CPUs but since > this is an IP core it will likely be found on others in the future. So > instead of adding this to the nwl host driver make it a generic PHY > driver. > > The driver supports the i.MX8MQ. Support for i.MX8QM and i.MX8QXP can be > added once the necessary system controller bits are in via > mixel_dphy_devdata. > > Signed-off-by: Guido Günther > Co-developed-by: Robert Chiras > Signed-off-by: Robert Chiras > Reviewed-by: Fabio Estevam > Reviewed-by: Sam Ravnborg Would you have any comments on this series, please? Thanks ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH v11 2/2] phy: Add driver for mixel mipi dphy found on NXP's i.MX8 SoCs
This adds support for the Mixel DPHY as found on i.MX8 CPUs but since
this is an IP core it will likely be found on others in the future. So
instead of adding this to the nwl host driver make it a generic PHY
driver.
The driver supports the i.MX8MQ. Support for i.MX8QM and i.MX8QXP can be
added once the necessary system controller bits are in via
mixel_dphy_devdata.
Signed-off-by: Guido Günther
Co-developed-by: Robert Chiras
Signed-off-by: Robert Chiras
Reviewed-by: Fabio Estevam
Reviewed-by: Sam Ravnborg
---
drivers/phy/freescale/Kconfig | 10 +
drivers/phy/freescale/Makefile| 1 +
.../phy/freescale/phy-fsl-imx8-mipi-dphy.c| 500 ++
3 files changed, 511 insertions(+)
create mode 100644 drivers/phy/freescale/phy-fsl-imx8-mipi-dphy.c
diff --git a/drivers/phy/freescale/Kconfig b/drivers/phy/freescale/Kconfig
index 832670b4952b..247be62d0981 100644
--- a/drivers/phy/freescale/Kconfig
+++ b/drivers/phy/freescale/Kconfig
@@ -3,3 +3,13 @@ config PHY_FSL_IMX8MQ_USB
depends on OF && HAS_IOMEM
select GENERIC_PHY
default ARCH_MXC && ARM64
+
+config PHY_MIXEL_MIPI_DPHY
+ tristate "Mixel MIPI DSI PHY support"
+ depends on OF && HAS_IOMEM
+ select GENERIC_PHY
+ select GENERIC_PHY_MIPI_DPHY
+ select REGMAP_MMIO
+ help
+ Enable this to add support for the Mixel DSI PHY as found
+ on NXP's i.MX8 family of SOCs.
diff --git a/drivers/phy/freescale/Makefile b/drivers/phy/freescale/Makefile
index dc2b3f1f2f80..07491c926a2c 100644
--- a/drivers/phy/freescale/Makefile
+++ b/drivers/phy/freescale/Makefile
@@ -1 +1,2 @@
obj-$(CONFIG_PHY_FSL_IMX8MQ_USB) += phy-fsl-imx8mq-usb.o
+obj-$(CONFIG_PHY_MIXEL_MIPI_DPHY) += phy-fsl-imx8-mipi-dphy.o
diff --git a/drivers/phy/freescale/phy-fsl-imx8-mipi-dphy.c
b/drivers/phy/freescale/phy-fsl-imx8-mipi-dphy.c
new file mode 100644
index ..a2ec8b79249d
--- /dev/null
+++ b/drivers/phy/freescale/phy-fsl-imx8-mipi-dphy.c
@@ -0,0 +1,500 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2017,2018 NXP
+ * Copyright 2019 Purism SPC
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+/* DPHY registers */
+#define DPHY_PD_DPHY 0x00
+#define DPHY_M_PRG_HS_PREPARE 0x04
+#define DPHY_MC_PRG_HS_PREPARE 0x08
+#define DPHY_M_PRG_HS_ZERO 0x0c
+#define DPHY_MC_PRG_HS_ZERO0x10
+#define DPHY_M_PRG_HS_TRAIL0x14
+#define DPHY_MC_PRG_HS_TRAIL 0x18
+#define DPHY_PD_PLL0x1c
+#define DPHY_TST 0x20
+#define DPHY_CN0x24
+#define DPHY_CM0x28
+#define DPHY_CO0x2c
+#define DPHY_LOCK 0x30
+#define DPHY_LOCK_BYP 0x34
+#define DPHY_REG_BYPASS_PLL0x4C
+
+#define MBPS(x) ((x) * 100)
+
+#define DATA_RATE_MAX_SPEED MBPS(1500)
+#define DATA_RATE_MIN_SPEED MBPS(80)
+
+#define PLL_LOCK_SLEEP 10
+#define PLL_LOCK_TIMEOUT 1000
+
+#define CN_BUF 0xcb7a89c0
+#define CO_BUF 0x63
+#define CM(x) ( \
+ ((x) < 32) ? 0xe0 | ((x) - 16) : \
+ ((x) < 64) ? 0xc0 | ((x) - 32) : \
+ ((x) < 128) ? 0x80 | ((x) - 64) : \
+ ((x) - 128))
+#define CN(x) (((x) == 1) ? 0x1f : (((CN_BUF) >> ((x) - 1)) & 0x1f))
+#define CO(x) ((CO_BUF) >> (8 - (x)) & 0x03)
+
+/* PHY power on is active low */
+#define PWR_ON 0
+#define PWR_OFF1
+
+enum mixel_dphy_devtype {
+ MIXEL_IMX8MQ,
+};
+
+struct mixel_dphy_devdata {
+ u8 reg_tx_rcal;
+ u8 reg_auto_pd_en;
+ u8 reg_rxlprp;
+ u8 reg_rxcdrp;
+ u8 reg_rxhs_settle;
+};
+
+static const struct mixel_dphy_devdata mixel_dphy_devdata[] = {
+ [MIXEL_IMX8MQ] = {
+ .reg_tx_rcal = 0x38,
+ .reg_auto_pd_en = 0x3c,
+ .reg_rxlprp = 0x40,
+ .reg_rxcdrp = 0x44,
+ .reg_rxhs_settle = 0x48,
+ },
+};
+
+struct mixel_dphy_cfg {
+ /* DPHY PLL parameters */
+ u32 cm;
+ u32 cn;
+ u32 co;
+ /* DPHY register values */
+ u8 mc_prg_hs_prepare;
+ u8 m_prg_hs_prepare;
+ u8 mc_prg_hs_zero;
+ u8 m_prg_hs_zero;
+ u8 mc_prg_hs_trail;
+ u8 m_prg_hs_trail;
+ u8 rxhs_settle;
+};
+
+struct mixel_dphy_priv {
+ struct mixel_dphy_cfg cfg;
+ struct regmap *regmap;
+ struct clk *phy_ref_clk;
+ const struct mixel_dphy_devdata *devdata;
+};
+
+static const struct regmap_config mixel_dphy_regmap_config = {
+ .reg_bits = 8,
+ .val_bits = 32,
+ .reg_stride = 4,
+ .max_register = DPHY_REG_BYPASS_PLL,
+ .name = "mipi-dphy",
+};
+
+static int phy_write(struct phy *phy, u32 value, unsigned int reg)
+{
+ struct
