Re: [PATCH v2] drm/msm/disp/dpu1: add inline rotation support for sc7280 target
On Thu, 3 Mar 2022 at 14:43, Vinod Polimera wrote:
>
> - Some DPU versions support inline rot90. It is supported only for
> limited amount of UBWC formats.
> - There are two versions of inline rotators, v1 (present on sm8250 and
> sm7250) and v2 (sc7280). These versions differ in the list of supported
> formats and in the scaler possibilities.
>
> Changes in RFC:
> - Rebase changes to the latest code base.
> - Append rotation config variables with v2 and
> remove unused variables.(Dmitry)
> - Move pixel_ext setup separately from scaler3 config.(Dmitry)
> - Add 270 degree rotation to supported rotation list.(Dmitry)
>
> Changes in V2:
> - Remove unused macros and fix indentation.
> - Add check if 90 rotation is supported and add supported rotations to
> rot_cfg.
>
> Signed-off-by: Kalyan Thota
> Signed-off-by: Vinod Polimera
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 44 +++---
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 17
> drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 108
> +++--
> drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h | 2 +
> 4 files changed, 134 insertions(+), 37 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> index aa75991..7cd07be 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> @@ -25,6 +25,9 @@
> #define VIG_SM8250_MASK \
> (VIG_MASK | BIT(DPU_SSPP_QOS_8LVL) | BIT(DPU_SSPP_SCALER_QSEED3LITE))
>
> +#define VIG_SC7280_MASK \
> + (VIG_SC7180_MASK | BIT(DPU_SSPP_INLINE_ROTATION))
> +
> #define DMA_SDM845_MASK \
> (BIT(DPU_SSPP_SRC) | BIT(DPU_SSPP_QOS) | BIT(DPU_SSPP_QOS_8LVL) |\
> BIT(DPU_SSPP_TS_PREFILL) | BIT(DPU_SSPP_TS_PREFILL_REC1) |\
> @@ -177,6 +180,11 @@ static const uint32_t plane_formats_yuv[] = {
> DRM_FORMAT_YVU420,
> };
>
> +static const uint32_t rotation_v2_formats[] = {
> + DRM_FORMAT_NV12,
> + /* TODO add formats after validation */
> +};
> +
> /*
> * DPU sub blocks config
> */
> @@ -464,8 +472,7 @@ static const struct dpu_ctl_cfg sc7280_ctl[] = {
> */
>
> /* SSPP common configuration */
> -
> -#define _VIG_SBLK(num, sdma_pri, qseed_ver) \
> +#define _VIG_SBLK(num, sdma_pri, qseed_ver, rot_cfg) \
> { \
> .maxdwnscale = MAX_DOWNSCALE_RATIO, \
> .maxupscale = MAX_UPSCALE_RATIO, \
> @@ -482,6 +489,7 @@ static const struct dpu_ctl_cfg sc7280_ctl[] = {
> .num_formats = ARRAY_SIZE(plane_formats_yuv), \
> .virt_format_list = plane_formats, \
> .virt_num_formats = ARRAY_SIZE(plane_formats), \
> + .rotation_cfg = rot_cfg, \
> }
>
> #define _DMA_SBLK(num, sdma_pri) \
> @@ -497,14 +505,21 @@ static const struct dpu_ctl_cfg sc7280_ctl[] = {
> .virt_num_formats = ARRAY_SIZE(plane_formats), \
> }
>
> +static const struct dpu_rotation_cfg dpu_rot_sc7280_cfg_v2 = {
> + .rot_maxheight = 1088,
> + .rot_num_formats = ARRAY_SIZE(rotation_v2_formats),
> + .rot_format_list = rotation_v2_formats,
> + .rot_supported = DRM_MODE_ROTATE_MASK | DRM_MODE_REFLECT_MASK,
> +};
> +
> static const struct dpu_sspp_sub_blks sdm845_vig_sblk_0 =
> - _VIG_SBLK("0", 5, DPU_SSPP_SCALER_QSEED3);
> + _VIG_SBLK("0", 5, DPU_SSPP_SCALER_QSEED3,
> NULL);
> static const struct dpu_sspp_sub_blks sdm845_vig_sblk_1 =
> - _VIG_SBLK("1", 6, DPU_SSPP_SCALER_QSEED3);
> + _VIG_SBLK("1", 6, DPU_SSPP_SCALER_QSEED3,
> NULL);
> static const struct dpu_sspp_sub_blks sdm845_vig_sblk_2 =
> - _VIG_SBLK("2", 7, DPU_SSPP_SCALER_QSEED3);
> + _VIG_SBLK("2", 7, DPU_SSPP_SCALER_QSEED3,
> NULL);
> static const struct dpu_sspp_sub_blks sdm845_vig_sblk_3 =
> - _VIG_SBLK("3", 8, DPU_SSPP_SCALER_QSEED3);
> + _VIG_SBLK("3", 8, DPU_SSPP_SCALER_QSEED3,
> NULL);
>
> static const struct dpu_sspp_sub_blks sdm845_dma_sblk_0 = _DMA_SBLK("8", 1);
> static const struct dpu_sspp_sub_blks sdm845_dma_sblk_1 = _DMA_SBLK("9", 2);
> @@ -543,7 +558,10 @@ static const struct dpu_sspp_cfg sdm845_sspp[] = {
> };
>
> static const struct dpu_sspp_sub_blks sc7180_vig_sblk_0 =
> - _VIG_SBLK("0", 4, DPU_SSPP_SCALER_QSEED4);
> + _VIG_SBLK("0", 4, DPU_SSPP_SCALER_QSEED4,
> NULL);
> +
> +static const struct dpu_sspp_sub_blks sc7280_vig_sblk_0 =
> + _VIG_SBLK("0", 4, DPU_SSPP_SCALER_QSEED4,
> _rot_sc7280_cfg_v2);
>
> static const struct dpu_sspp_cfg sc7180_sspp[] = {
>
Re: [PATCH v2] drm/msm/disp/dpu1: add inline rotation support for sc7280 target
Quoting Vinod Polimera (2022-03-03 03:42:59)
> - Some DPU versions support inline rot90. It is supported only for
> limited amount of UBWC formats.
> - There are two versions of inline rotators, v1 (present on sm8250 and
> sm7250) and v2 (sc7280). These versions differ in the list of supported
> formats and in the scaler possibilities.
>
> Changes in RFC:
> - Rebase changes to the latest code base.
> - Append rotation config variables with v2 and
> remove unused variables.(Dmitry)
> - Move pixel_ext setup separately from scaler3 config.(Dmitry)
> - Add 270 degree rotation to supported rotation list.(Dmitry)
>
> Changes in V2:
> - Remove unused macros and fix indentation.
> - Add check if 90 rotation is supported and add supported rotations to
> rot_cfg.
>
> Signed-off-by: Kalyan Thota
Missing a Co-developed-by tag here?
> Signed-off-by: Vinod Polimera
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 44 +++---
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 17
> drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 108
> +++--
> drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h | 2 +
> 4 files changed, 134 insertions(+), 37 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> index aa75991..7cd07be 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> @@ -25,6 +25,9 @@
> #define VIG_SM8250_MASK \
> (VIG_MASK | BIT(DPU_SSPP_QOS_8LVL) | BIT(DPU_SSPP_SCALER_QSEED3LITE))
>
> +#define VIG_SC7280_MASK \
> + (VIG_SC7180_MASK | BIT(DPU_SSPP_INLINE_ROTATION))
> +
> #define DMA_SDM845_MASK \
> (BIT(DPU_SSPP_SRC) | BIT(DPU_SSPP_QOS) | BIT(DPU_SSPP_QOS_8LVL) |\
> BIT(DPU_SSPP_TS_PREFILL) | BIT(DPU_SSPP_TS_PREFILL_REC1) |\
> @@ -177,6 +180,11 @@ static const uint32_t plane_formats_yuv[] = {
> DRM_FORMAT_YVU420,
> };
>
> +static const uint32_t rotation_v2_formats[] = {
Just use u32 when in the kernel. It's shorter and is the same.
> + DRM_FORMAT_NV12,
> + /* TODO add formats after validation */
> +};
> +
> /*
> * DPU sub blocks config
> */
> @@ -464,8 +472,7 @@ static const struct dpu_ctl_cfg sc7280_ctl[] = {
> */
>
> /* SSPP common configuration */
> -
> -#define _VIG_SBLK(num, sdma_pri, qseed_ver) \
> +#define _VIG_SBLK(num, sdma_pri, qseed_ver, rot_cfg) \
> { \
> .maxdwnscale = MAX_DOWNSCALE_RATIO, \
> .maxupscale = MAX_UPSCALE_RATIO, \
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> index 31af04a..269eb45 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> @@ -312,6 +314,20 @@ struct dpu_qos_lut_tbl {
> };
>
> /**
> + * struct dpu_rotation_cfg - define inline rotation config
> + * @rot_maxheight: max pre rotated height allowed for rotation
> + * @rot_num_formats: count of the formats
number of elements in @rot_format_list
> + * @rot_format_list: list of supported rotator formats
> + * @rot_supported: allowed rotations
> + */
> +struct dpu_rotation_cfg {
> + u32 rot_maxheight;
> + u32 rot_num_formats;
size_t?
> + const u32 *rot_format_list;
> + u32 rot_supported;
> +};
> +
> +/**
> * struct dpu_caps - define DPU capabilities
> * @max_mixer_widthmax layer mixer line width support.
> * @max_mixer_blendstages max layer mixer blend stages or
> @@ -387,6 +403,7 @@ struct dpu_sspp_sub_blks {
> u32 num_formats;
> const u32 *virt_format_list;
> u32 virt_num_formats;
> + const struct dpu_rotation_cfg *rotation_cfg;
Any kernel-doc update for this new member?
> };
>
> /**
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
> index ca75089..031a0ff 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
> @@ -528,11 +528,19 @@ static void _dpu_plane_setup_scaler3(struct dpu_plane
> *pdpu,
> struct dpu_plane_state *pstate,
> uint32_t src_w, uint32_t src_h, uint32_t dst_w, uint32_t
> dst_h,
> struct dpu_hw_scaler3_cfg *scale_cfg,
> - struct dpu_hw_pixel_ext *pixel_ext,
> const struct dpu_format *fmt,
> uint32_t chroma_subsmpl_h, uint32_t chroma_subsmpl_v)
> {
> uint32_t i;
> + bool inline_rotation = (pstate->rotation & DRM_MODE_ROTATE_90);
Drop useless parenthesis please.
> +
> + /*
> +* For inline rotation cases, scaler config is post-rotation,
> +* so swap the dimensions here. However, pixel extension will
> +* need pre-rotation
[PATCH v2] drm/msm/disp/dpu1: add inline rotation support for sc7280 target
- Some DPU versions support inline rot90. It is supported only for
limited amount of UBWC formats.
- There are two versions of inline rotators, v1 (present on sm8250 and
sm7250) and v2 (sc7280). These versions differ in the list of supported
formats and in the scaler possibilities.
Changes in RFC:
- Rebase changes to the latest code base.
- Append rotation config variables with v2 and
remove unused variables.(Dmitry)
- Move pixel_ext setup separately from scaler3 config.(Dmitry)
- Add 270 degree rotation to supported rotation list.(Dmitry)
Changes in V2:
- Remove unused macros and fix indentation.
- Add check if 90 rotation is supported and add supported rotations to rot_cfg.
Signed-off-by: Kalyan Thota
Signed-off-by: Vinod Polimera
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 44 +++---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 17
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 108 +++--
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h | 2 +
4 files changed, 134 insertions(+), 37 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
index aa75991..7cd07be 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
@@ -25,6 +25,9 @@
#define VIG_SM8250_MASK \
(VIG_MASK | BIT(DPU_SSPP_QOS_8LVL) | BIT(DPU_SSPP_SCALER_QSEED3LITE))
+#define VIG_SC7280_MASK \
+ (VIG_SC7180_MASK | BIT(DPU_SSPP_INLINE_ROTATION))
+
#define DMA_SDM845_MASK \
(BIT(DPU_SSPP_SRC) | BIT(DPU_SSPP_QOS) | BIT(DPU_SSPP_QOS_8LVL) |\
BIT(DPU_SSPP_TS_PREFILL) | BIT(DPU_SSPP_TS_PREFILL_REC1) |\
@@ -177,6 +180,11 @@ static const uint32_t plane_formats_yuv[] = {
DRM_FORMAT_YVU420,
};
+static const uint32_t rotation_v2_formats[] = {
+ DRM_FORMAT_NV12,
+ /* TODO add formats after validation */
+};
+
/*
* DPU sub blocks config
*/
@@ -464,8 +472,7 @@ static const struct dpu_ctl_cfg sc7280_ctl[] = {
*/
/* SSPP common configuration */
-
-#define _VIG_SBLK(num, sdma_pri, qseed_ver) \
+#define _VIG_SBLK(num, sdma_pri, qseed_ver, rot_cfg) \
{ \
.maxdwnscale = MAX_DOWNSCALE_RATIO, \
.maxupscale = MAX_UPSCALE_RATIO, \
@@ -482,6 +489,7 @@ static const struct dpu_ctl_cfg sc7280_ctl[] = {
.num_formats = ARRAY_SIZE(plane_formats_yuv), \
.virt_format_list = plane_formats, \
.virt_num_formats = ARRAY_SIZE(plane_formats), \
+ .rotation_cfg = rot_cfg, \
}
#define _DMA_SBLK(num, sdma_pri) \
@@ -497,14 +505,21 @@ static const struct dpu_ctl_cfg sc7280_ctl[] = {
.virt_num_formats = ARRAY_SIZE(plane_formats), \
}
+static const struct dpu_rotation_cfg dpu_rot_sc7280_cfg_v2 = {
+ .rot_maxheight = 1088,
+ .rot_num_formats = ARRAY_SIZE(rotation_v2_formats),
+ .rot_format_list = rotation_v2_formats,
+ .rot_supported = DRM_MODE_ROTATE_MASK | DRM_MODE_REFLECT_MASK,
+};
+
static const struct dpu_sspp_sub_blks sdm845_vig_sblk_0 =
- _VIG_SBLK("0", 5, DPU_SSPP_SCALER_QSEED3);
+ _VIG_SBLK("0", 5, DPU_SSPP_SCALER_QSEED3, NULL);
static const struct dpu_sspp_sub_blks sdm845_vig_sblk_1 =
- _VIG_SBLK("1", 6, DPU_SSPP_SCALER_QSEED3);
+ _VIG_SBLK("1", 6, DPU_SSPP_SCALER_QSEED3, NULL);
static const struct dpu_sspp_sub_blks sdm845_vig_sblk_2 =
- _VIG_SBLK("2", 7, DPU_SSPP_SCALER_QSEED3);
+ _VIG_SBLK("2", 7, DPU_SSPP_SCALER_QSEED3, NULL);
static const struct dpu_sspp_sub_blks sdm845_vig_sblk_3 =
- _VIG_SBLK("3", 8, DPU_SSPP_SCALER_QSEED3);
+ _VIG_SBLK("3", 8, DPU_SSPP_SCALER_QSEED3, NULL);
static const struct dpu_sspp_sub_blks sdm845_dma_sblk_0 = _DMA_SBLK("8", 1);
static const struct dpu_sspp_sub_blks sdm845_dma_sblk_1 = _DMA_SBLK("9", 2);
@@ -543,7 +558,10 @@ static const struct dpu_sspp_cfg sdm845_sspp[] = {
};
static const struct dpu_sspp_sub_blks sc7180_vig_sblk_0 =
- _VIG_SBLK("0", 4, DPU_SSPP_SCALER_QSEED4);
+ _VIG_SBLK("0", 4, DPU_SSPP_SCALER_QSEED4, NULL);
+
+static const struct dpu_sspp_sub_blks sc7280_vig_sblk_0 =
+ _VIG_SBLK("0", 4, DPU_SSPP_SCALER_QSEED4,
_rot_sc7280_cfg_v2);
static const struct dpu_sspp_cfg sc7180_sspp[] = {
SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, VIG_SC7180_MASK,
@@ -557,13 +575,13 @@ static const struct dpu_sspp_cfg sc7180_sspp[] = {
};
static const struct dpu_sspp_sub_blks sm8250_vig_sblk_0 =
- _VIG_SBLK("0", 5, DPU_SSPP_SCALER_QSEED3LITE);
+
