Re: [PATCH v2] drm/msm/dp: add wide bus support

2022-02-02 Thread Dmitry Baryshkov 

On 02/02/2022 20:49, Kuogee Hsieh wrote:


On 2/2/2022 1:56 AM, Dmitry Baryshkov wrote:

On 02/02/2022 03:30, Kuogee Hsieh wrote:

Normally, mdp will push one pixel of data per pixel clock to
interface to display. Wide bus feature will increase bus
width from 32 bits to 64 bits so that it can push two
pixel of data per pixel clock to interface to display.
This feature is pre requirement to support 4k resolution
since it will reduce pixel clock rate to half of original
rate. Hence pixel clock rate used to drive 4k panel will
not exceed limitation.


Bjorn question is still valid. Why is this required for the 4k panels? 
For which clock frequencies/chipsets?


less clock rate will use less power.

Please let me know exactly which info you are looking for.


I'm trying to make sense from the commit message ('pre requirement to 
support 4k resolutions') and Bjorn using 4k monitor w/o this patch.


Also I'm trying to understand, when should it be used and which imact 
will it have.









changes in v2:
-- remove compression related code from timing
-- remove op_info from  struct msm_drm_private
-- remove unnecessary wide_bus_en variables
-- pass wide_bus_en into timing configuration by struct msm_dp

Signed-off-by: Kuogee Hsieh 
---
  drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c    |  8 ++
  drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h    |  2 +
  .../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c   | 14 +++
  drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c    | 99 
++

  drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h    |  2 +
  drivers/gpu/drm/msm/dp/dp_catalog.c    | 15 +++-
  drivers/gpu/drm/msm/dp/dp_catalog.h    |  2 +-
  drivers/gpu/drm/msm/dp/dp_ctrl.c   | 13 ++-
  drivers/gpu/drm/msm/dp/dp_ctrl.h   |  1 +
  drivers/gpu/drm/msm/dp/dp_display.c    | 11 +++
  drivers/gpu/drm/msm/dp/dp_display.h    | 21 -
  drivers/gpu/drm/msm/dp/dp_panel.c  |  4 +-
  drivers/gpu/drm/msm/dp/dp_panel.h  |  2 +-
  drivers/gpu/drm/msm/msm_drv.h  | 25 ++
  14 files changed, 154 insertions(+), 65 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c

index 1e648db..7bbdfb9 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
@@ -217,6 +217,14 @@ static u32 dither_matrix[DITHER_MATRIX_SZ] = {
  15, 7, 13, 5, 3, 11, 1, 9, 12, 4, 14, 6, 0, 8, 2, 10
  };
  +
+bool dpu_encoder_is_widebus_enabled(struct drm_encoder *drm_enc)
+{
+    struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc);
+
+    return dpu_enc->dp->wide_bus_en;
+}
+
  static void _dpu_encoder_setup_dither(struct dpu_hw_pingpong 
*hw_pp, unsigned bpc)

  {
  struct dpu_hw_dither_cfg dither_cfg = { 0 };
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h

index e241914..0d73550 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h
@@ -168,4 +168,6 @@ int dpu_encoder_get_linecount(struct drm_encoder 
*drm_enc);

   */
  int dpu_encoder_get_vsync_count(struct drm_encoder *drm_enc);
  +bool dpu_encoder_is_widebus_enabled(struct drm_encoder *drm_enc);
+
  #endif /* __DPU_ENCODER_H__ */
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c

index ddd9d89..b72c33b 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
@@ -110,6 +110,20 @@ static void drm_mode_to_intf_timing_params(
  timing->v_back_porch += timing->v_front_porch;
  timing->v_front_porch = 0;
  }
+
+    timing->wide_bus_en = 
dpu_encoder_is_widebus_enabled(phys_enc->parent);

+
+    /*
+ * for DP, divide the horizonal parameters by 2 when
+ * widebus is enabled
+ */
+    if (timing->wide_bus_en) {
+    timing->width = timing->width >> 1;
+    timing->xres = timing->xres >> 1;
+    timing->h_back_porch = timing->h_back_porch >> 1;
+    timing->h_front_porch = timing->h_front_porch >> 1;
+    timing->hsync_pulse_width = timing->hsync_pulse_width >> 1;
+    }
  }
    static u32 get_horizontal_total(const struct intf_timing_params 
*timing)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c

index 116e2b5..35d4aaa 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
@@ -33,6 +33,7 @@
  #define INTF_TP_COLOR1  0x05C
  #define INTF_CONFIG2    0x060
  #define INTF_DISPLAY_DATA_HCTL  0x064
+#define INTF_ACTIVE_DATA_HCTL   0x068
  #define INTF_FRAME_LINE_COUNT_EN    0x0A8
  #define INTF_FRAME_COUNT    0x0AC
  #define   INTF_LINE_COUNT   0x0B0
@@ -90,68

Re: [PATCH v2] drm/msm/dp: add wide bus support

2022-02-02 Thread Kuogee Hsieh 



On 2/2/2022 1:56 AM, Dmitry Baryshkov wrote:

On 02/02/2022 03:30, Kuogee Hsieh wrote:

Normally, mdp will push one pixel of data per pixel clock to
interface to display. Wide bus feature will increase bus
width from 32 bits to 64 bits so that it can push two
pixel of data per pixel clock to interface to display.
This feature is pre requirement to support 4k resolution
since it will reduce pixel clock rate to half of original
rate. Hence pixel clock rate used to drive 4k panel will
not exceed limitation.


Bjorn question is still valid. Why is this required for the 4k panels? 
For which clock frequencies/chipsets?


less clock rate will use less power.

Please let me know exactly which info you are looking for.






changes in v2:
-- remove compression related code from timing
-- remove op_info from  struct msm_drm_private
-- remove unnecessary wide_bus_en variables
-- pass wide_bus_en into timing configuration by struct msm_dp

Signed-off-by: Kuogee Hsieh 
---
  drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c    |  8 ++
  drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h    |  2 +
  .../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c   | 14 +++
  drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c    | 99 
++

  drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h    |  2 +
  drivers/gpu/drm/msm/dp/dp_catalog.c    | 15 +++-
  drivers/gpu/drm/msm/dp/dp_catalog.h    |  2 +-
  drivers/gpu/drm/msm/dp/dp_ctrl.c   | 13 ++-
  drivers/gpu/drm/msm/dp/dp_ctrl.h   |  1 +
  drivers/gpu/drm/msm/dp/dp_display.c    | 11 +++
  drivers/gpu/drm/msm/dp/dp_display.h    | 21 -
  drivers/gpu/drm/msm/dp/dp_panel.c  |  4 +-
  drivers/gpu/drm/msm/dp/dp_panel.h  |  2 +-
  drivers/gpu/drm/msm/msm_drv.h  | 25 ++
  14 files changed, 154 insertions(+), 65 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c

index 1e648db..7bbdfb9 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
@@ -217,6 +217,14 @@ static u32 dither_matrix[DITHER_MATRIX_SZ] = {
  15, 7, 13, 5, 3, 11, 1, 9, 12, 4, 14, 6, 0, 8, 2, 10
  };
  +
+bool dpu_encoder_is_widebus_enabled(struct drm_encoder *drm_enc)
+{
+    struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc);
+
+    return dpu_enc->dp->wide_bus_en;
+}
+
  static void _dpu_encoder_setup_dither(struct dpu_hw_pingpong 
*hw_pp, unsigned bpc)

  {
  struct dpu_hw_dither_cfg dither_cfg = { 0 };
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h

index e241914..0d73550 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h
@@ -168,4 +168,6 @@ int dpu_encoder_get_linecount(struct drm_encoder 
*drm_enc);

   */
  int dpu_encoder_get_vsync_count(struct drm_encoder *drm_enc);
  +bool dpu_encoder_is_widebus_enabled(struct drm_encoder *drm_enc);
+
  #endif /* __DPU_ENCODER_H__ */
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c

index ddd9d89..b72c33b 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
@@ -110,6 +110,20 @@ static void drm_mode_to_intf_timing_params(
  timing->v_back_porch += timing->v_front_porch;
  timing->v_front_porch = 0;
  }
+
+    timing->wide_bus_en = 
dpu_encoder_is_widebus_enabled(phys_enc->parent);

+
+    /*
+ * for DP, divide the horizonal parameters by 2 when
+ * widebus is enabled
+ */
+    if (timing->wide_bus_en) {
+    timing->width = timing->width >> 1;
+    timing->xres = timing->xres >> 1;
+    timing->h_back_porch = timing->h_back_porch >> 1;
+    timing->h_front_porch = timing->h_front_porch >> 1;
+    timing->hsync_pulse_width = timing->hsync_pulse_width >> 1;
+    }
  }
    static u32 get_horizontal_total(const struct intf_timing_params 
*timing)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c

index 116e2b5..35d4aaa 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
@@ -33,6 +33,7 @@
  #define INTF_TP_COLOR1  0x05C
  #define INTF_CONFIG2    0x060
  #define INTF_DISPLAY_DATA_HCTL  0x064
+#define INTF_ACTIVE_DATA_HCTL   0x068
  #define INTF_FRAME_LINE_COUNT_EN    0x0A8
  #define INTF_FRAME_COUNT    0x0AC
  #define   INTF_LINE_COUNT   0x0B0
@@ -90,68 +91,95 @@ static void 
dpu_hw_intf_setup_timing_engine(struct dpu_hw_intf *ctx,

  u32 hsync_period, vsync_period;
  u32 display_v_start, display_v_end;
  u32 hsync_start_x, hsync_end_x;
+    u32 hsync_data_start_x, hsync_data_end_x;
  u32 active_h_start,

Re: [PATCH v2] drm/msm/dp: add wide bus support

2022-02-02 Thread Dmitry Baryshkov 

On 02/02/2022 03:30, Kuogee Hsieh wrote:

Normally, mdp will push one pixel of data per pixel clock to
interface to display. Wide bus feature will increase bus
width from 32 bits to 64 bits so that it can push two
pixel of data per pixel clock to interface to display.
This feature is pre requirement to support 4k resolution
since it will reduce pixel clock rate to half of original
rate. Hence pixel clock rate used to drive 4k panel will
not exceed limitation.


Bjorn question is still valid. Why is this required for the 4k panels? 
For which clock frequencies/chipsets?




changes in v2:
-- remove compression related code from timing
-- remove op_info from  struct msm_drm_private
-- remove unnecessary wide_bus_en variables
-- pass wide_bus_en into timing configuration by struct msm_dp

Signed-off-by: Kuogee Hsieh 
---
  drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c|  8 ++
  drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h|  2 +
  .../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c   | 14 +++
  drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c| 99 ++
  drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h|  2 +
  drivers/gpu/drm/msm/dp/dp_catalog.c| 15 +++-
  drivers/gpu/drm/msm/dp/dp_catalog.h|  2 +-
  drivers/gpu/drm/msm/dp/dp_ctrl.c   | 13 ++-
  drivers/gpu/drm/msm/dp/dp_ctrl.h   |  1 +
  drivers/gpu/drm/msm/dp/dp_display.c| 11 +++
  drivers/gpu/drm/msm/dp/dp_display.h| 21 -
  drivers/gpu/drm/msm/dp/dp_panel.c  |  4 +-
  drivers/gpu/drm/msm/dp/dp_panel.h  |  2 +-
  drivers/gpu/drm/msm/msm_drv.h  | 25 ++
  14 files changed, 154 insertions(+), 65 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
index 1e648db..7bbdfb9 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
@@ -217,6 +217,14 @@ static u32 dither_matrix[DITHER_MATRIX_SZ] = {
15, 7, 13, 5, 3, 11, 1, 9, 12, 4, 14, 6, 0, 8, 2, 10
  };
  
+

+bool dpu_encoder_is_widebus_enabled(struct drm_encoder *drm_enc)
+{
+   struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc);
+
+   return dpu_enc->dp->wide_bus_en;
+}
+
  static void _dpu_encoder_setup_dither(struct dpu_hw_pingpong *hw_pp, unsigned 
bpc)
  {
struct dpu_hw_dither_cfg dither_cfg = { 0 };
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h
index e241914..0d73550 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h
@@ -168,4 +168,6 @@ int dpu_encoder_get_linecount(struct drm_encoder *drm_enc);
   */
  int dpu_encoder_get_vsync_count(struct drm_encoder *drm_enc);
  
+bool dpu_encoder_is_widebus_enabled(struct drm_encoder *drm_enc);

+
  #endif /* __DPU_ENCODER_H__ */
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
index ddd9d89..b72c33b 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
@@ -110,6 +110,20 @@ static void drm_mode_to_intf_timing_params(
timing->v_back_porch += timing->v_front_porch;
timing->v_front_porch = 0;
}
+
+   timing->wide_bus_en = dpu_encoder_is_widebus_enabled(phys_enc->parent);
+
+   /*
+* for DP, divide the horizonal parameters by 2 when
+* widebus is enabled
+*/
+   if (timing->wide_bus_en) {
+   timing->width = timing->width >> 1;
+   timing->xres = timing->xres >> 1;
+   timing->h_back_porch = timing->h_back_porch >> 1;
+   timing->h_front_porch = timing->h_front_porch >> 1;
+   timing->hsync_pulse_width = timing->hsync_pulse_width >> 1;
+   }
  }
  
  static u32 get_horizontal_total(const struct intf_timing_params *timing)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
index 116e2b5..35d4aaa 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
@@ -33,6 +33,7 @@
  #define INTF_TP_COLOR1  0x05C
  #define INTF_CONFIG20x060
  #define INTF_DISPLAY_DATA_HCTL  0x064
+#define INTF_ACTIVE_DATA_HCTL   0x068
  #define INTF_FRAME_LINE_COUNT_EN0x0A8
  #define INTF_FRAME_COUNT0x0AC
  #define   INTF_LINE_COUNT   0x0B0
@@ -90,68 +91,95 @@ static void dpu_hw_intf_setup_timing_engine(struct 
dpu_hw_intf *ctx,
u32 hsync_period, vsync_period;
u32 display_v_start, display_v_end;
u32 hsync_start_x, hsync_end_x;
+   u32 hsync_data_start_x, hsync_data_end_x;
u32 active_h_start, active_h_end;
u32 active_v_start, active_v_end;

[PATCH v2] drm/msm/dp: add wide bus support

2022-02-01 Thread Kuogee Hsieh 
Normally, mdp will push one pixel of data per pixel clock to
interface to display. Wide bus feature will increase bus
width from 32 bits to 64 bits so that it can push two
pixel of data per pixel clock to interface to display.
This feature is pre requirement to support 4k resolution
since it will reduce pixel clock rate to half of original
rate. Hence pixel clock rate used to drive 4k panel will
not exceed limitation.

changes in v2:
-- remove compression related code from timing
-- remove op_info from  struct msm_drm_private
-- remove unnecessary wide_bus_en variables
-- pass wide_bus_en into timing configuration by struct msm_dp

Signed-off-by: Kuogee Hsieh 
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c|  8 ++
 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h|  2 +
 .../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c   | 14 +++
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c| 99 ++
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h|  2 +
 drivers/gpu/drm/msm/dp/dp_catalog.c| 15 +++-
 drivers/gpu/drm/msm/dp/dp_catalog.h|  2 +-
 drivers/gpu/drm/msm/dp/dp_ctrl.c   | 13 ++-
 drivers/gpu/drm/msm/dp/dp_ctrl.h   |  1 +
 drivers/gpu/drm/msm/dp/dp_display.c| 11 +++
 drivers/gpu/drm/msm/dp/dp_display.h| 21 -
 drivers/gpu/drm/msm/dp/dp_panel.c  |  4 +-
 drivers/gpu/drm/msm/dp/dp_panel.h  |  2 +-
 drivers/gpu/drm/msm/msm_drv.h  | 25 ++
 14 files changed, 154 insertions(+), 65 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
index 1e648db..7bbdfb9 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
@@ -217,6 +217,14 @@ static u32 dither_matrix[DITHER_MATRIX_SZ] = {
15, 7, 13, 5, 3, 11, 1, 9, 12, 4, 14, 6, 0, 8, 2, 10
 };
 
+
+bool dpu_encoder_is_widebus_enabled(struct drm_encoder *drm_enc)
+{
+   struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc);
+
+   return dpu_enc->dp->wide_bus_en;
+}
+
 static void _dpu_encoder_setup_dither(struct dpu_hw_pingpong *hw_pp, unsigned 
bpc)
 {
struct dpu_hw_dither_cfg dither_cfg = { 0 };
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h
index e241914..0d73550 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h
@@ -168,4 +168,6 @@ int dpu_encoder_get_linecount(struct drm_encoder *drm_enc);
  */
 int dpu_encoder_get_vsync_count(struct drm_encoder *drm_enc);
 
+bool dpu_encoder_is_widebus_enabled(struct drm_encoder *drm_enc);
+
 #endif /* __DPU_ENCODER_H__ */
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
index ddd9d89..b72c33b 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
@@ -110,6 +110,20 @@ static void drm_mode_to_intf_timing_params(
timing->v_back_porch += timing->v_front_porch;
timing->v_front_porch = 0;
}
+
+   timing->wide_bus_en = dpu_encoder_is_widebus_enabled(phys_enc->parent);
+
+   /*
+* for DP, divide the horizonal parameters by 2 when
+* widebus is enabled
+*/
+   if (timing->wide_bus_en) {
+   timing->width = timing->width >> 1;
+   timing->xres = timing->xres >> 1;
+   timing->h_back_porch = timing->h_back_porch >> 1;
+   timing->h_front_porch = timing->h_front_porch >> 1;
+   timing->hsync_pulse_width = timing->hsync_pulse_width >> 1;
+   }
 }
 
 static u32 get_horizontal_total(const struct intf_timing_params *timing)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
index 116e2b5..35d4aaa 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
@@ -33,6 +33,7 @@
 #define INTF_TP_COLOR1  0x05C
 #define INTF_CONFIG20x060
 #define INTF_DISPLAY_DATA_HCTL  0x064
+#define INTF_ACTIVE_DATA_HCTL   0x068
 #define INTF_FRAME_LINE_COUNT_EN0x0A8
 #define INTF_FRAME_COUNT0x0AC
 #define   INTF_LINE_COUNT   0x0B0
@@ -90,68 +91,95 @@ static void dpu_hw_intf_setup_timing_engine(struct 
dpu_hw_intf *ctx,
u32 hsync_period, vsync_period;
u32 display_v_start, display_v_end;
u32 hsync_start_x, hsync_end_x;
+   u32 hsync_data_start_x, hsync_data_end_x;
u32 active_h_start, active_h_end;
u32 active_v_start, active_v_end;
u32 active_hctl, display_hctl, hsync_ctl;
u32 polarity_ctl, den_polarity, hsync_polarity, vsync_polarity;
u32 panel_format;
-   u32 intf_cfg, intf_cfg2 = 0, display_data_hct