[PATCH v2 06/25] drm/radeon: Add radeon <--> amdkfd interface
On 20/07/14 20:35, Jerome Glisse wrote:
> On Thu, Jul 17, 2014 at 04:29:13PM +0300, Oded Gabbay wrote:
>> This patch adds the interface between the radeon driver and the amdkfd
>> driver.
>> The interface implementation is contained in radeon_kfd.c and radeon_kfd.h.
>>
>> The interface itself is represented by a pointer to struct
>> kfd_dev. The pointer is located inside radeon_device structure.
>>
>> All the register accesses that amdkfd need are done using this interface.
>> This
>> allows us to avoid direct register accesses in amdkfd proper, while also
>> avoiding locking between amdkfd and radeon.
>>
>> The single exception is the doorbells that are used in both of the drivers.
>> However, because they are located in separate pci bar pages, the danger of
>> sharing registers between the drivers is minimal.
>>
>> Having said that, we are planning to move the doorbells as well to radeon.
>>
>> The loading of the amdkfd module is done via symbol lookup. According to the
>> code review discussions, this may change in v3 of the patch set.
>>
>> Signed-off-by: Oded Gabbay
>> ---
>> drivers/gpu/drm/radeon/Makefile | 1 +
>> drivers/gpu/drm/radeon/cik.c| 9 +
>> drivers/gpu/drm/radeon/cik_reg.h| 65 +
>> drivers/gpu/drm/radeon/cikd.h | 51 +++-
>> drivers/gpu/drm/radeon/radeon.h | 3 +
>> drivers/gpu/drm/radeon/radeon_drv.c | 5 +
>> drivers/gpu/drm/radeon/radeon_kfd.c | 566
>>
>> drivers/gpu/drm/radeon/radeon_kfd.h | 119
>> drivers/gpu/drm/radeon/radeon_kms.c | 7 +
>> 9 files changed, 825 insertions(+), 1 deletion(-)
>> create mode 100644 drivers/gpu/drm/radeon/radeon_kfd.c
>> create mode 100644 drivers/gpu/drm/radeon/radeon_kfd.h
>>
>> diff --git a/drivers/gpu/drm/radeon/Makefile
>> b/drivers/gpu/drm/radeon/Makefile
>> index 1b04002..a1c913d 100644
>> --- a/drivers/gpu/drm/radeon/Makefile
>> +++ b/drivers/gpu/drm/radeon/Makefile
>> @@ -104,6 +104,7 @@ radeon-y += \
>> radeon_vce.o \
>> vce_v1_0.o \
>> vce_v2_0.o \
>> +radeon_kfd.o
>>
>> radeon-$(CONFIG_COMPAT) += radeon_ioc32.o
>> radeon-$(CONFIG_VGA_SWITCHEROO) += radeon_atpx_handler.o
>> diff --git a/drivers/gpu/drm/radeon/cik.c b/drivers/gpu/drm/radeon/cik.c
>> index b4bbc22..6f71095 100644
>> --- a/drivers/gpu/drm/radeon/cik.c
>> +++ b/drivers/gpu/drm/radeon/cik.c
>> @@ -32,6 +32,7 @@
>> #include "cik_blit_shaders.h"
>> #include "radeon_ucode.h"
>> #include "clearstate_ci.h"
>> +#include "radeon_kfd.h"
>>
>> MODULE_FIRMWARE("radeon/BONAIRE_pfp.bin");
>> MODULE_FIRMWARE("radeon/BONAIRE_me.bin");
>> @@ -7727,6 +7728,9 @@ restart_ih:
>> while (rptr != wptr) {
>> /* wptr/rptr are in bytes! */
>> ring_index = rptr / 4;
>> +
>> +radeon_kfd_interrupt(rdev, (const void *)
>> >ih.ring[ring_index]);
>> +
>> src_id = le32_to_cpu(rdev->ih.ring[ring_index]) & 0xff;
>> src_data = le32_to_cpu(rdev->ih.ring[ring_index + 1]) &
>> 0xfff;
>> ring_id = le32_to_cpu(rdev->ih.ring[ring_index + 2]) & 0xff;
>> @@ -8386,6 +8390,10 @@ static int cik_startup(struct radeon_device *rdev)
>> if (r)
>> return r;
>>
>> +r = radeon_kfd_resume(rdev);
>> +if (r)
>> +return r;
>> +
>> return 0;
>> }
>>
>> @@ -8434,6 +8442,7 @@ int cik_resume(struct radeon_device *rdev)
>> */
>> int cik_suspend(struct radeon_device *rdev)
>> {
>> +radeon_kfd_suspend(rdev);
>> radeon_pm_suspend(rdev);
>> dce6_audio_fini(rdev);
>> radeon_vm_manager_fini(rdev);
>> diff --git a/drivers/gpu/drm/radeon/cik_reg.h
>> b/drivers/gpu/drm/radeon/cik_reg.h
>> index ca1bb61..1ab3dbc 100644
>> --- a/drivers/gpu/drm/radeon/cik_reg.h
>> +++ b/drivers/gpu/drm/radeon/cik_reg.h
>> @@ -147,4 +147,69 @@
>>
>> #define CIK_LB_DESKTOP_HEIGHT 0x6b0c
>>
>> +struct cik_hqd_registers {
>> +u32 cp_mqd_base_addr;
>> +u32 cp_mqd_base_addr_hi;
>> +u32 cp_hqd_active;
>> +u32 cp_hqd_vmid;
>> +u32 cp_hqd_persistent_state;
>> +u32 cp_hqd_pipe_priority;
>> +u32 cp_hqd_queue_priority;
>> +u32 cp_hqd_quantum;
>> +u32 cp_hqd_pq_base;
>> +u32 cp_hqd_pq_base_hi;
>> +u32 cp_hqd_pq_rptr;
>> +u32 cp_hqd_pq_rptr_report_addr;
>> +u32 cp_hqd_pq_rptr_report_addr_hi;
>> +u32 cp_hqd_pq_wptr_poll_addr;
>> +u32 cp_hqd_pq_wptr_poll_addr_hi;
>> +u32 cp_hqd_pq_doorbell_control;
>> +u32 cp_hqd_pq_wptr;
>> +u32 cp_hqd_pq_control;
>> +u32 cp_hqd_ib_base_addr;
>> +u32 cp_hqd_ib_base_addr_hi;
>> +u32 cp_hqd_ib_rptr;
>> +u32 cp_hqd_ib_control;
>> +u32 cp_hqd_iq_timer;
>> +u32 cp_hqd_iq_rptr;
>> +u32 cp_hqd_dequeue_request;
>> +u32 cp_hqd_dma_offload;
>> +u32 cp_hqd_sema_cmd;
>> +u32 cp_hqd_msg_type;
>> +u32 cp_hqd_atomic0_preop_lo;
>> +u32 cp_hqd_atomic0_preop_hi;
>> +u32 cp_hqd_atomic1_preop_lo;
>> +u32 cp_hqd_atomic1_preop_hi;
[PATCH v2 06/25] drm/radeon: Add radeon <--> amdkfd interface
On Thu, Jul 17, 2014 at 04:29:13PM +0300, Oded Gabbay wrote:
> This patch adds the interface between the radeon driver and the amdkfd driver.
> The interface implementation is contained in radeon_kfd.c and radeon_kfd.h.
>
> The interface itself is represented by a pointer to struct
> kfd_dev. The pointer is located inside radeon_device structure.
>
> All the register accesses that amdkfd need are done using this interface. This
> allows us to avoid direct register accesses in amdkfd proper, while also
> avoiding locking between amdkfd and radeon.
>
> The single exception is the doorbells that are used in both of the drivers.
> However, because they are located in separate pci bar pages, the danger of
> sharing registers between the drivers is minimal.
>
> Having said that, we are planning to move the doorbells as well to radeon.
>
> The loading of the amdkfd module is done via symbol lookup. According to the
> code review discussions, this may change in v3 of the patch set.
>
> Signed-off-by: Oded Gabbay
> ---
> drivers/gpu/drm/radeon/Makefile | 1 +
> drivers/gpu/drm/radeon/cik.c| 9 +
> drivers/gpu/drm/radeon/cik_reg.h| 65 +
> drivers/gpu/drm/radeon/cikd.h | 51 +++-
> drivers/gpu/drm/radeon/radeon.h | 3 +
> drivers/gpu/drm/radeon/radeon_drv.c | 5 +
> drivers/gpu/drm/radeon/radeon_kfd.c | 566
>
> drivers/gpu/drm/radeon/radeon_kfd.h | 119
> drivers/gpu/drm/radeon/radeon_kms.c | 7 +
> 9 files changed, 825 insertions(+), 1 deletion(-)
> create mode 100644 drivers/gpu/drm/radeon/radeon_kfd.c
> create mode 100644 drivers/gpu/drm/radeon/radeon_kfd.h
>
> diff --git a/drivers/gpu/drm/radeon/Makefile b/drivers/gpu/drm/radeon/Makefile
> index 1b04002..a1c913d 100644
> --- a/drivers/gpu/drm/radeon/Makefile
> +++ b/drivers/gpu/drm/radeon/Makefile
> @@ -104,6 +104,7 @@ radeon-y += \
> radeon_vce.o \
> vce_v1_0.o \
> vce_v2_0.o \
> + radeon_kfd.o
>
> radeon-$(CONFIG_COMPAT) += radeon_ioc32.o
> radeon-$(CONFIG_VGA_SWITCHEROO) += radeon_atpx_handler.o
> diff --git a/drivers/gpu/drm/radeon/cik.c b/drivers/gpu/drm/radeon/cik.c
> index b4bbc22..6f71095 100644
> --- a/drivers/gpu/drm/radeon/cik.c
> +++ b/drivers/gpu/drm/radeon/cik.c
> @@ -32,6 +32,7 @@
> #include "cik_blit_shaders.h"
> #include "radeon_ucode.h"
> #include "clearstate_ci.h"
> +#include "radeon_kfd.h"
>
> MODULE_FIRMWARE("radeon/BONAIRE_pfp.bin");
> MODULE_FIRMWARE("radeon/BONAIRE_me.bin");
> @@ -7727,6 +7728,9 @@ restart_ih:
> while (rptr != wptr) {
> /* wptr/rptr are in bytes! */
> ring_index = rptr / 4;
> +
> + radeon_kfd_interrupt(rdev, (const void *)
> >ih.ring[ring_index]);
> +
> src_id = le32_to_cpu(rdev->ih.ring[ring_index]) & 0xff;
> src_data = le32_to_cpu(rdev->ih.ring[ring_index + 1]) &
> 0xfff;
> ring_id = le32_to_cpu(rdev->ih.ring[ring_index + 2]) & 0xff;
> @@ -8386,6 +8390,10 @@ static int cik_startup(struct radeon_device *rdev)
> if (r)
> return r;
>
> + r = radeon_kfd_resume(rdev);
> + if (r)
> + return r;
> +
> return 0;
> }
>
> @@ -8434,6 +8442,7 @@ int cik_resume(struct radeon_device *rdev)
> */
> int cik_suspend(struct radeon_device *rdev)
> {
> + radeon_kfd_suspend(rdev);
> radeon_pm_suspend(rdev);
> dce6_audio_fini(rdev);
> radeon_vm_manager_fini(rdev);
> diff --git a/drivers/gpu/drm/radeon/cik_reg.h
> b/drivers/gpu/drm/radeon/cik_reg.h
> index ca1bb61..1ab3dbc 100644
> --- a/drivers/gpu/drm/radeon/cik_reg.h
> +++ b/drivers/gpu/drm/radeon/cik_reg.h
> @@ -147,4 +147,69 @@
>
> #define CIK_LB_DESKTOP_HEIGHT 0x6b0c
>
> +struct cik_hqd_registers {
> + u32 cp_mqd_base_addr;
> + u32 cp_mqd_base_addr_hi;
> + u32 cp_hqd_active;
> + u32 cp_hqd_vmid;
> + u32 cp_hqd_persistent_state;
> + u32 cp_hqd_pipe_priority;
> + u32 cp_hqd_queue_priority;
> + u32 cp_hqd_quantum;
> + u32 cp_hqd_pq_base;
> + u32 cp_hqd_pq_base_hi;
> + u32 cp_hqd_pq_rptr;
> + u32 cp_hqd_pq_rptr_report_addr;
> + u32 cp_hqd_pq_rptr_report_addr_hi;
> + u32 cp_hqd_pq_wptr_poll_addr;
> + u32 cp_hqd_pq_wptr_poll_addr_hi;
> + u32 cp_hqd_pq_doorbell_control;
> + u32 cp_hqd_pq_wptr;
> + u32 cp_hqd_pq_control;
> + u32 cp_hqd_ib_base_addr;
> + u32 cp_hqd_ib_base_addr_hi;
> + u32 cp_hqd_ib_rptr;
> + u32 cp_hqd_ib_control;
> + u32 cp_hqd_iq_timer;
> + u32 cp_hqd_iq_rptr;
> + u32 cp_hqd_dequeue_request;
> + u32 cp_hqd_dma_offload;
> + u32 cp_hqd_sema_cmd;
> + u32 cp_hqd_msg_type;
> + u32 cp_hqd_atomic0_preop_lo;
> + u32 cp_hqd_atomic0_preop_hi;
> + u32 cp_hqd_atomic1_preop_lo;
> + u32 cp_hqd_atomic1_preop_hi;
> + u32 cp_hqd_hq_scheduler0;
> + u32 cp_hqd_hq_scheduler1;
> + u32 cp_mqd_control;
> +};
> +
> +struct cik_mqd {
>
[PATCH v2 06/25] drm/radeon: Add radeon <--> amdkfd interface
This patch adds the interface between the radeon driver and the amdkfd driver.
The interface implementation is contained in radeon_kfd.c and radeon_kfd.h.
The interface itself is represented by a pointer to struct
kfd_dev. The pointer is located inside radeon_device structure.
All the register accesses that amdkfd need are done using this interface. This
allows us to avoid direct register accesses in amdkfd proper, while also
avoiding locking between amdkfd and radeon.
The single exception is the doorbells that are used in both of the drivers.
However, because they are located in separate pci bar pages, the danger of
sharing registers between the drivers is minimal.
Having said that, we are planning to move the doorbells as well to radeon.
The loading of the amdkfd module is done via symbol lookup. According to the
code review discussions, this may change in v3 of the patch set.
Signed-off-by: Oded Gabbay
---
drivers/gpu/drm/radeon/Makefile | 1 +
drivers/gpu/drm/radeon/cik.c| 9 +
drivers/gpu/drm/radeon/cik_reg.h| 65 +
drivers/gpu/drm/radeon/cikd.h | 51 +++-
drivers/gpu/drm/radeon/radeon.h | 3 +
drivers/gpu/drm/radeon/radeon_drv.c | 5 +
drivers/gpu/drm/radeon/radeon_kfd.c | 566
drivers/gpu/drm/radeon/radeon_kfd.h | 119
drivers/gpu/drm/radeon/radeon_kms.c | 7 +
9 files changed, 825 insertions(+), 1 deletion(-)
create mode 100644 drivers/gpu/drm/radeon/radeon_kfd.c
create mode 100644 drivers/gpu/drm/radeon/radeon_kfd.h
diff --git a/drivers/gpu/drm/radeon/Makefile b/drivers/gpu/drm/radeon/Makefile
index 1b04002..a1c913d 100644
--- a/drivers/gpu/drm/radeon/Makefile
+++ b/drivers/gpu/drm/radeon/Makefile
@@ -104,6 +104,7 @@ radeon-y += \
radeon_vce.o \
vce_v1_0.o \
vce_v2_0.o \
+ radeon_kfd.o
radeon-$(CONFIG_COMPAT) += radeon_ioc32.o
radeon-$(CONFIG_VGA_SWITCHEROO) += radeon_atpx_handler.o
diff --git a/drivers/gpu/drm/radeon/cik.c b/drivers/gpu/drm/radeon/cik.c
index b4bbc22..6f71095 100644
--- a/drivers/gpu/drm/radeon/cik.c
+++ b/drivers/gpu/drm/radeon/cik.c
@@ -32,6 +32,7 @@
#include "cik_blit_shaders.h"
#include "radeon_ucode.h"
#include "clearstate_ci.h"
+#include "radeon_kfd.h"
MODULE_FIRMWARE("radeon/BONAIRE_pfp.bin");
MODULE_FIRMWARE("radeon/BONAIRE_me.bin");
@@ -7727,6 +7728,9 @@ restart_ih:
while (rptr != wptr) {
/* wptr/rptr are in bytes! */
ring_index = rptr / 4;
+
+ radeon_kfd_interrupt(rdev, (const void *)
>ih.ring[ring_index]);
+
src_id = le32_to_cpu(rdev->ih.ring[ring_index]) & 0xff;
src_data = le32_to_cpu(rdev->ih.ring[ring_index + 1]) &
0xfff;
ring_id = le32_to_cpu(rdev->ih.ring[ring_index + 2]) & 0xff;
@@ -8386,6 +8390,10 @@ static int cik_startup(struct radeon_device *rdev)
if (r)
return r;
+ r = radeon_kfd_resume(rdev);
+ if (r)
+ return r;
+
return 0;
}
@@ -8434,6 +8442,7 @@ int cik_resume(struct radeon_device *rdev)
*/
int cik_suspend(struct radeon_device *rdev)
{
+ radeon_kfd_suspend(rdev);
radeon_pm_suspend(rdev);
dce6_audio_fini(rdev);
radeon_vm_manager_fini(rdev);
diff --git a/drivers/gpu/drm/radeon/cik_reg.h b/drivers/gpu/drm/radeon/cik_reg.h
index ca1bb61..1ab3dbc 100644
--- a/drivers/gpu/drm/radeon/cik_reg.h
+++ b/drivers/gpu/drm/radeon/cik_reg.h
@@ -147,4 +147,69 @@
#define CIK_LB_DESKTOP_HEIGHT 0x6b0c
+struct cik_hqd_registers {
+ u32 cp_mqd_base_addr;
+ u32 cp_mqd_base_addr_hi;
+ u32 cp_hqd_active;
+ u32 cp_hqd_vmid;
+ u32 cp_hqd_persistent_state;
+ u32 cp_hqd_pipe_priority;
+ u32 cp_hqd_queue_priority;
+ u32 cp_hqd_quantum;
+ u32 cp_hqd_pq_base;
+ u32 cp_hqd_pq_base_hi;
+ u32 cp_hqd_pq_rptr;
+ u32 cp_hqd_pq_rptr_report_addr;
+ u32 cp_hqd_pq_rptr_report_addr_hi;
+ u32 cp_hqd_pq_wptr_poll_addr;
+ u32 cp_hqd_pq_wptr_poll_addr_hi;
+ u32 cp_hqd_pq_doorbell_control;
+ u32 cp_hqd_pq_wptr;
+ u32 cp_hqd_pq_control;
+ u32 cp_hqd_ib_base_addr;
+ u32 cp_hqd_ib_base_addr_hi;
+ u32 cp_hqd_ib_rptr;
+ u32 cp_hqd_ib_control;
+ u32 cp_hqd_iq_timer;
+ u32 cp_hqd_iq_rptr;
+ u32 cp_hqd_dequeue_request;
+ u32 cp_hqd_dma_offload;
+ u32 cp_hqd_sema_cmd;
+ u32 cp_hqd_msg_type;
+ u32 cp_hqd_atomic0_preop_lo;
+ u32 cp_hqd_atomic0_preop_hi;
+ u32 cp_hqd_atomic1_preop_lo;
+ u32 cp_hqd_atomic1_preop_hi;
+ u32 cp_hqd_hq_scheduler0;
+ u32 cp_hqd_hq_scheduler1;
+ u32 cp_mqd_control;
+};
+
+struct cik_mqd {
+ u32 header;
+ u32 dispatch_initiator;
+ u32 dimensions[3];
+ u32 start_idx[3];
+ u32 num_threads[3];
+ u32 pipeline_stat_enable;
+ u32 perf_counter_enable;
+ u32 pgm[2];
+ u32
