subject:"\[PATCH v2 1\/3\] drm\/i915\/xehp\: GAM registers don't need to be re\-applied on engine resets"

Re: [PATCH v2 1/3] drm/i915/xehp: GAM registers don't need to be re-applied on engine resets

2023-01-26 Thread Gustavo Sousa

On Wed, Jan 25, 2023 at 03:41:57PM -0800, Matt Roper wrote:
> Register reset characteristics (i.e., whether the register maintains or
> loses its value on engine reset) is an important factor that determines
> which wa_list we want to add workarounds to.  We recently found out that
> the bspec documentation for the Xe_HP's "GAM" registers in the 0xC800 -
> 0xCFFF range was misleading; these registers do not actually lose their
> value on engine resets as the documentation implied.  This means there's
> no need to re-apply workarounds touching these registers after a reset,
> and the corresponding workarounds should be moved from the 'engine'
> lists back to the 'gt' list.
> 
> v2:
>  - Don't add Wa_18018781329 to xehpsdv; the original condition didn't
>include that platform.  (Gustavo)
>  - Move the MTL code to the GT function as-is for now; we'll take care
>of the additional fixes needed in a follow-up patch.
> 
> Cc: Gustavo Sousa 
> Fixes: edf176f48d87 ("drm/i915/dg2: Move misplaced 'ctx' & 'gt' wa's to 
> engine wa list")
> Fixes: b2006061ae28 ("drm/i915/xehpsdv: Move render/compute engine reset 
> domains related workarounds")
> Fixes: 41bb543f5598 ("drm/i915/mtl: Add initial gt workarounds")
> Signed-off-by: Matt Roper 

Reviewed-by: Gustavo Sousa 

> ---
>  drivers/gpu/drm/i915/gt/intel_workarounds.c | 77 -
>  1 file changed, 44 insertions(+), 33 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c 
> b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index 4efc1a532982..9db60078460a 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -1559,6 +1559,13 @@ xehpsdv_gt_workarounds_init(struct intel_gt *gt, 
> struct i915_wa_list *wal)
>  
>   /* Wa_14011060649:xehpsdv */
>   wa_14011060649(gt, wal);
> +
> + /* Wa_14012362059:xehpsdv */
> + wa_mcr_write_or(wal, XEHP_MERT_MOD_CTRL, FORCE_MISS_FTLB);
> +
> + /* Wa_14014368820:xehpsdv */
> + wa_write_or(wal, GEN12_GAMCNTRL_CTRL,
> + INVALIDATION_BROADCAST_MODE_DIS | GLOBAL_INVALIDATION_MODE);
>  }
>  
>  static void
> @@ -1599,6 +1606,12 @@ dg2_gt_workarounds_init(struct intel_gt *gt, struct 
> i915_wa_list *wal)
>   DSS_ROUTER_CLKGATE_DIS);
>   }
>  
> + if (IS_DG2_GRAPHICS_STEP(gt->i915, G10, STEP_A0, STEP_B0) ||
> + IS_DG2_GRAPHICS_STEP(gt->i915, G11, STEP_A0, STEP_B0)) {
> + /* Wa_14012362059:dg2 */
> + wa_mcr_write_or(wal, XEHP_MERT_MOD_CTRL, FORCE_MISS_FTLB);
> + }
> +
>   if (IS_DG2_GRAPHICS_STEP(gt->i915, G10, STEP_A0, STEP_B0)) {
>   /* Wa_14010948348:dg2_g10 */
>   wa_write_or(wal, UNSLCGCTL9430, MSQDUNIT_CLKGATE_DIS);
> @@ -1644,6 +1657,12 @@ dg2_gt_workarounds_init(struct intel_gt *gt, struct 
> i915_wa_list *wal)
>  
>   /* Wa_14011028019:dg2_g10 */
>   wa_mcr_write_or(wal, SSMCGCTL9530, RTFUNIT_CLKGATE_DIS);
> +
> + /* Wa_14010680813:dg2_g10 */
> + wa_write_or(wal, GEN12_GAMSTLB_CTRL,
> + CONTROL_BLOCK_CLKGATE_DIS |
> + EGRESS_BLOCK_CLKGATE_DIS |
> + TAG_BLOCK_CLKGATE_DIS);
>   }
>  
>   /* Wa_14014830051:dg2 */
> @@ -1658,6 +1677,16 @@ dg2_gt_workarounds_init(struct intel_gt *gt, struct 
> i915_wa_list *wal)
>  
>   /* Wa_14015795083 */
>   wa_mcr_write_clr(wal, GEN8_MISCCPCTL, 
> GEN12_DOP_CLOCK_GATE_RENDER_ENABLE);
> +
> + /* Wa_18018781329 */
> + wa_mcr_write_or(wal, RENDER_MOD_CTRL, FORCE_MISS_FTLB);
> + wa_mcr_write_or(wal, COMP_MOD_CTRL, FORCE_MISS_FTLB);
> + wa_mcr_write_or(wal, VDBX_MOD_CTRL, FORCE_MISS_FTLB);
> + wa_mcr_write_or(wal, VEBX_MOD_CTRL, FORCE_MISS_FTLB);
> +
> + /* Wa_1509235366:dg2 */
> + wa_write_or(wal, GEN12_GAMCNTRL_CTRL,
> + INVALIDATION_BROADCAST_MODE_DIS | GLOBAL_INVALIDATION_MODE);
>  }
>  
>  static void
> @@ -1667,16 +1696,29 @@ pvc_gt_workarounds_init(struct intel_gt *gt, struct 
> i915_wa_list *wal)
>  
>   /* Wa_14015795083 */
>   wa_mcr_write_clr(wal, GEN8_MISCCPCTL, 
> GEN12_DOP_CLOCK_GATE_RENDER_ENABLE);
> +
> + /* Wa_18018781329 */
> + wa_mcr_write_or(wal, RENDER_MOD_CTRL, FORCE_MISS_FTLB);
> + wa_mcr_write_or(wal, COMP_MOD_CTRL, FORCE_MISS_FTLB);
> + wa_mcr_write_or(wal, VDBX_MOD_CTRL, FORCE_MISS_FTLB);
> + wa_mcr_write_or(wal, VEBX_MOD_CTRL, FORCE_MISS_FTLB);
>  }
>  
>  static void
>  xelpg_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
>  {
> - /* Wa_14014830051 */
>   if (IS_MTL_GRAPHICS_STEP(gt->i915, M, STEP_A0, STEP_B0) ||
> - IS_MTL_GRAPHICS_STEP(gt->i915, P, STEP_A0, STEP_B0))
> + IS_MTL_GRAPHICS_STEP(gt->i915, P, STEP_A0, STEP_B0)) {
> + /* Wa_14014830051 */
>   wa_mcr_write_clr(wal, SARB_CHICKEN1, COMP_CKN_IN);
>  
> + /* Wa_18018781329 */
> + wa_mcr_w

[PATCH v2 1/3] drm/i915/xehp: GAM registers don't need to be re-applied on engine resets

2023-01-25 Thread Matt Roper

Register reset characteristics (i.e., whether the register maintains or
loses its value on engine reset) is an important factor that determines
which wa_list we want to add workarounds to.  We recently found out that
the bspec documentation for the Xe_HP's "GAM" registers in the 0xC800 -
0xCFFF range was misleading; these registers do not actually lose their
value on engine resets as the documentation implied.  This means there's
no need to re-apply workarounds touching these registers after a reset,
and the corresponding workarounds should be moved from the 'engine'
lists back to the 'gt' list.

v2:
 - Don't add Wa_18018781329 to xehpsdv; the original condition didn't
   include that platform.  (Gustavo)
 - Move the MTL code to the GT function as-is for now; we'll take care
   of the additional fixes needed in a follow-up patch.

Cc: Gustavo Sousa 
Fixes: edf176f48d87 ("drm/i915/dg2: Move misplaced 'ctx' & 'gt' wa's to engine 
wa list")
Fixes: b2006061ae28 ("drm/i915/xehpsdv: Move render/compute engine reset 
domains related workarounds")
Fixes: 41bb543f5598 ("drm/i915/mtl: Add initial gt workarounds")
Signed-off-by: Matt Roper 
---
 drivers/gpu/drm/i915/gt/intel_workarounds.c | 77 -
 1 file changed, 44 insertions(+), 33 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c 
b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 4efc1a532982..9db60078460a 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -1559,6 +1559,13 @@ xehpsdv_gt_workarounds_init(struct intel_gt *gt, struct 
i915_wa_list *wal)
 
/* Wa_14011060649:xehpsdv */
wa_14011060649(gt, wal);
+
+   /* Wa_14012362059:xehpsdv */
+   wa_mcr_write_or(wal, XEHP_MERT_MOD_CTRL, FORCE_MISS_FTLB);
+
+   /* Wa_14014368820:xehpsdv */
+   wa_write_or(wal, GEN12_GAMCNTRL_CTRL,
+   INVALIDATION_BROADCAST_MODE_DIS | GLOBAL_INVALIDATION_MODE);
 }
 
 static void
@@ -1599,6 +1606,12 @@ dg2_gt_workarounds_init(struct intel_gt *gt, struct 
i915_wa_list *wal)
DSS_ROUTER_CLKGATE_DIS);
}
 
+   if (IS_DG2_GRAPHICS_STEP(gt->i915, G10, STEP_A0, STEP_B0) ||
+   IS_DG2_GRAPHICS_STEP(gt->i915, G11, STEP_A0, STEP_B0)) {
+   /* Wa_14012362059:dg2 */
+   wa_mcr_write_or(wal, XEHP_MERT_MOD_CTRL, FORCE_MISS_FTLB);
+   }
+
if (IS_DG2_GRAPHICS_STEP(gt->i915, G10, STEP_A0, STEP_B0)) {
/* Wa_14010948348:dg2_g10 */
wa_write_or(wal, UNSLCGCTL9430, MSQDUNIT_CLKGATE_DIS);
@@ -1644,6 +1657,12 @@ dg2_gt_workarounds_init(struct intel_gt *gt, struct 
i915_wa_list *wal)
 
/* Wa_14011028019:dg2_g10 */
wa_mcr_write_or(wal, SSMCGCTL9530, RTFUNIT_CLKGATE_DIS);
+
+   /* Wa_14010680813:dg2_g10 */
+   wa_write_or(wal, GEN12_GAMSTLB_CTRL,
+   CONTROL_BLOCK_CLKGATE_DIS |
+   EGRESS_BLOCK_CLKGATE_DIS |
+   TAG_BLOCK_CLKGATE_DIS);
}
 
/* Wa_14014830051:dg2 */
@@ -1658,6 +1677,16 @@ dg2_gt_workarounds_init(struct intel_gt *gt, struct 
i915_wa_list *wal)
 
/* Wa_14015795083 */
wa_mcr_write_clr(wal, GEN8_MISCCPCTL, 
GEN12_DOP_CLOCK_GATE_RENDER_ENABLE);
+
+   /* Wa_18018781329 */
+   wa_mcr_write_or(wal, RENDER_MOD_CTRL, FORCE_MISS_FTLB);
+   wa_mcr_write_or(wal, COMP_MOD_CTRL, FORCE_MISS_FTLB);
+   wa_mcr_write_or(wal, VDBX_MOD_CTRL, FORCE_MISS_FTLB);
+   wa_mcr_write_or(wal, VEBX_MOD_CTRL, FORCE_MISS_FTLB);
+
+   /* Wa_1509235366:dg2 */
+   wa_write_or(wal, GEN12_GAMCNTRL_CTRL,
+   INVALIDATION_BROADCAST_MODE_DIS | GLOBAL_INVALIDATION_MODE);
 }
 
 static void
@@ -1667,16 +1696,29 @@ pvc_gt_workarounds_init(struct intel_gt *gt, struct 
i915_wa_list *wal)
 
/* Wa_14015795083 */
wa_mcr_write_clr(wal, GEN8_MISCCPCTL, 
GEN12_DOP_CLOCK_GATE_RENDER_ENABLE);
+
+   /* Wa_18018781329 */
+   wa_mcr_write_or(wal, RENDER_MOD_CTRL, FORCE_MISS_FTLB);
+   wa_mcr_write_or(wal, COMP_MOD_CTRL, FORCE_MISS_FTLB);
+   wa_mcr_write_or(wal, VDBX_MOD_CTRL, FORCE_MISS_FTLB);
+   wa_mcr_write_or(wal, VEBX_MOD_CTRL, FORCE_MISS_FTLB);
 }
 
 static void
 xelpg_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
 {
-   /* Wa_14014830051 */
if (IS_MTL_GRAPHICS_STEP(gt->i915, M, STEP_A0, STEP_B0) ||
-   IS_MTL_GRAPHICS_STEP(gt->i915, P, STEP_A0, STEP_B0))
+   IS_MTL_GRAPHICS_STEP(gt->i915, P, STEP_A0, STEP_B0)) {
+   /* Wa_14014830051 */
wa_mcr_write_clr(wal, SARB_CHICKEN1, COMP_CKN_IN);
 
+   /* Wa_18018781329 */
+   wa_mcr_write_or(wal, RENDER_MOD_CTRL, FORCE_MISS_FTLB);
+   wa_mcr_write_or(wal, COMP_MOD_CTRL, FORCE_MISS_FTLB);
+   wa_mcr_write_or(wal, VDBX_MOD_CTRL, FORCE_MISS_FTLB);
+   wa_mcr_write_or(wal, VEB

Re: [PATCH v2 1/3] drm/i915/xehp: GAM registers don't need to be re-applied on engine resets

[PATCH v2 1/3] drm/i915/xehp: GAM registers don't need to be re-applied on engine resets

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