Re: [PATCH v2 1/3] dt-bindings: drm/bridge: Document Cadence MHDP bridge bindings in yaml format
On Mon, Dec 23, 2019 at 04:16:40PM +0100, Yuti Amonkar wrote:
> Document the bindings used for the Cadence MHDP DPI/DP bridge in
> yaml format.
>
> Signed-off-by: Yuti Amonkar
> ---
> .../bindings/display/bridge/cdns,mhdp.yaml | 109
> +
> 1 file changed, 109 insertions(+)
> create mode 100644
> Documentation/devicetree/bindings/display/bridge/cdns,mhdp.yaml
>
> diff --git a/Documentation/devicetree/bindings/display/bridge/cdns,mhdp.yaml
> b/Documentation/devicetree/bindings/display/bridge/cdns,mhdp.yaml
> new file mode 100644
> index 000..aed6224
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/display/bridge/cdns,mhdp.yaml
> @@ -0,0 +1,109 @@
> +%YAML 1.2
> +---
> +$id: "http://devicetree.org/schemas/display/bridge/cdns,mhdp.yaml#;
> +$schema: "http://devicetree.org/meta-schemas/core.yaml#;
> +
> +title: Cadence MHDP bridge
> +
> +maintainers:
> + - Swapnil Jakhade
> + - Yuti Amonkar
> +
> +properties:
> + compatible:
> +enum:
> + - cdns,mhdp8546
> + - ti,j721e-mhdp8546
> +
> + clocks:
> +maxItems: 1
> +description:
> + DP bridge clock, it's used by the IP to know how to translate a number
> of
> + clock cycles into a time (which is used to comply with DP standard
> timings
> + and delays).
> +
> + reg:
> +minItems: 1
> +maxItems: 2
> +items:
> + - description:
> + Register block of mhdptx apb registers upto PHY mapped
> area(AUX_CONFIG_P).
> + The AUX and PMA registers are mapped to associated phy driver.
> + - description:
> + Register block for DSS_EDP0_INTG_CFG_VP registers in case of TI J7
> SoCs.
> +
> + reg-names:
> +minItems: 1
> +maxItems: 2
> +items:
> + - const: mhdptx
> + - const: j721e-intg
> +
> + phys:
> +description: see the
> Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml
> +
> + phy-names:
> +const: dpphy
> +
> + ports:
> +type: object
> +description:
> + Ports as described in Documentation/devicetree/bindings/graph.txt
> +properties:
> + '#address-cells':
> + const: 1
> + '#size-cells':
> + const: 0
> + port@0:
type: object
> + description:
> + input port representing the DP bridge input
> +
> + port@1:
type: object
> + description:
> + output port representing the DP bridge output
> +required:
> + - port@0
> + - port@1
> + - '#address-cells'
> + - '#size-cells'
> +
> +required:
> + - compatible
> + - clocks
> + - reg
> + - phys
> + - phy-names
> + - ports
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> +mhdp: dp-bridge@f0fb00 {
> +compatible = "cdns,mhdp8546";
> +reg = <0xf0 0xfb00 0x0 0x100>,
> + <0xf0 0xfc00 0x0 0x200>;
> +clocks = <_clock>;
> +phys = <_phy>;
> +phy-names = "dpphy";
> +
> +ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> + dp_bridge_input: endpoint {
> +remote-endpoint = <_dpi_output>;
> + };
> + };
> +
> + port@1 {
> + reg = <1>;
> + dp_bridge_output: endpoint {
> + remote-endpoint =
> <_dp_connector_input>;
> + };
> + };
> + };
> +};
> +...
> --
> 2.7.4
>
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Re: [PATCH v2 1/3] dt-bindings: drm/bridge: Document Cadence MHDP bridge bindings in yaml format
On Mon, Dec 23, 2019 at 04:16:40PM +0100, Yuti Amonkar wrote:
> Document the bindings used for the Cadence MHDP DPI/DP bridge in
> yaml format.
>
> Signed-off-by: Yuti Amonkar
> ---
> .../bindings/display/bridge/cdns,mhdp.yaml | 109
> +
> 1 file changed, 109 insertions(+)
> create mode 100644
> Documentation/devicetree/bindings/display/bridge/cdns,mhdp.yaml
>
> diff --git a/Documentation/devicetree/bindings/display/bridge/cdns,mhdp.yaml
> b/Documentation/devicetree/bindings/display/bridge/cdns,mhdp.yaml
> new file mode 100644
> index 000..aed6224
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/display/bridge/cdns,mhdp.yaml
> @@ -0,0 +1,109 @@
> +%YAML 1.2
> +---
> +$id: "http://devicetree.org/schemas/display/bridge/cdns,mhdp.yaml#;
> +$schema: "http://devicetree.org/meta-schemas/core.yaml#;
> +
> +title: Cadence MHDP bridge
> +
> +maintainers:
> + - Swapnil Jakhade
> + - Yuti Amonkar
> +
> +properties:
> + compatible:
> +enum:
> + - cdns,mhdp8546
> + - ti,j721e-mhdp8546
> +
> + clocks:
> +maxItems: 1
> +description:
> + DP bridge clock, it's used by the IP to know how to translate a number
> of
> + clock cycles into a time (which is used to comply with DP standard
> timings
> + and delays).
> +
> + reg:
> +minItems: 1
> +maxItems: 2
> +items:
> + - description:
> + Register block of mhdptx apb registers upto PHY mapped
> area(AUX_CONFIG_P).
> + The AUX and PMA registers are mapped to associated phy driver.
> + - description:
> + Register block for DSS_EDP0_INTG_CFG_VP registers in case of TI J7
> SoCs.
> +
> + reg-names:
> +minItems: 1
> +maxItems: 2
> +items:
> + - const: mhdptx
> + - const: j721e-intg
You should have an if / then clause to validate that the length is the
proper one based on the value of the compatible.
> + phys:
> +description: see the
> Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml
phys is a generic property, so we shouldn't tie it to one particular
phy. Especially since there's nothing in it that really explain what
this property is supposed to be.
> + phy-names:
> +const: dpphy
> +
> + ports:
> +type: object
> +description:
> + Ports as described in Documentation/devicetree/bindings/graph.txt
> +properties:
> + '#address-cells':
> + const: 1
> + '#size-cells':
> + const: 0
> + port@0:
> + description:
> + input port representing the DP bridge input
> +
> + port@1:
> + description:
> + output port representing the DP bridge output
> +required:
> + - port@0
> + - port@1
> + - '#address-cells'
> + - '#size-cells'
> +
> +required:
> + - compatible
> + - clocks
> + - reg
> + - phys
> + - phy-names
> + - ports
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> +mhdp: dp-bridge@f0fb00 {
> +compatible = "cdns,mhdp8546";
> +reg = <0xf0 0xfb00 0x0 0x100>,
> + <0xf0 0xfc00 0x0 0x200>;
There's two items here, yet you're not using the TI compatible?
Maxime
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[PATCH v2 1/3] dt-bindings: drm/bridge: Document Cadence MHDP bridge bindings in yaml format
Document the bindings used for the Cadence MHDP DPI/DP bridge in
yaml format.
Signed-off-by: Yuti Amonkar
---
.../bindings/display/bridge/cdns,mhdp.yaml | 109 +
1 file changed, 109 insertions(+)
create mode 100644
Documentation/devicetree/bindings/display/bridge/cdns,mhdp.yaml
diff --git a/Documentation/devicetree/bindings/display/bridge/cdns,mhdp.yaml
b/Documentation/devicetree/bindings/display/bridge/cdns,mhdp.yaml
new file mode 100644
index 000..aed6224
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/bridge/cdns,mhdp.yaml
@@ -0,0 +1,109 @@
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/display/bridge/cdns,mhdp.yaml#;
+$schema: "http://devicetree.org/meta-schemas/core.yaml#;
+
+title: Cadence MHDP bridge
+
+maintainers:
+ - Swapnil Jakhade
+ - Yuti Amonkar
+
+properties:
+ compatible:
+enum:
+ - cdns,mhdp8546
+ - ti,j721e-mhdp8546
+
+ clocks:
+maxItems: 1
+description:
+ DP bridge clock, it's used by the IP to know how to translate a number of
+ clock cycles into a time (which is used to comply with DP standard
timings
+ and delays).
+
+ reg:
+minItems: 1
+maxItems: 2
+items:
+ - description:
+ Register block of mhdptx apb registers upto PHY mapped
area(AUX_CONFIG_P).
+ The AUX and PMA registers are mapped to associated phy driver.
+ - description:
+ Register block for DSS_EDP0_INTG_CFG_VP registers in case of TI J7
SoCs.
+
+ reg-names:
+minItems: 1
+maxItems: 2
+items:
+ - const: mhdptx
+ - const: j721e-intg
+
+ phys:
+description: see the
Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml
+
+ phy-names:
+const: dpphy
+
+ ports:
+type: object
+description:
+ Ports as described in Documentation/devicetree/bindings/graph.txt
+properties:
+ '#address-cells':
+ const: 1
+ '#size-cells':
+ const: 0
+ port@0:
+ description:
+ input port representing the DP bridge input
+
+ port@1:
+ description:
+ output port representing the DP bridge output
+required:
+ - port@0
+ - port@1
+ - '#address-cells'
+ - '#size-cells'
+
+required:
+ - compatible
+ - clocks
+ - reg
+ - phys
+ - phy-names
+ - ports
+
+additionalProperties: false
+
+examples:
+ - |
+mhdp: dp-bridge@f0fb00 {
+compatible = "cdns,mhdp8546";
+reg = <0xf0 0xfb00 0x0 0x100>,
+ <0xf0 0xfc00 0x0 0x200>;
+clocks = <_clock>;
+phys = <_phy>;
+phy-names = "dpphy";
+
+ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ dp_bridge_input: endpoint {
+remote-endpoint = <_dpi_output>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ dp_bridge_output: endpoint {
+ remote-endpoint =
<_dp_connector_input>;
+ };
+ };
+ };
+};
+...
--
2.7.4
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