[PATCH v2 24/25] arm64: dts: msm8916: Add display support
Hi Rob,
On 06/23/2016 07:43 PM, Archit Taneja wrote:
> The MSM8916 SoC contains a MDP5 based display block, and one DSI output.
> Add the top level MDSS DT node, and the MDP5, DSI and DSI PHY children
> sub-blocks. Establish the link between MDP5's INTF1 output port and DSI's
> input port.
>
> Cc: Andy Gross
> Cc: Rob Herring
> Cc: devicetree at vger.kernel.org
Can I get an Ack on this?
Thanks,
Archit
>
> Signed-off-by: Archit Taneja
> ---
> v2:
> - Removed "qcom,dsi-host-index" and "qcom,dsi-phy-index" props
>
> arch/arm64/boot/dts/qcom/msm8916.dtsi | 117
> ++
> 1 file changed, 117 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi
> b/arch/arm64/boot/dts/qcom/msm8916.dtsi
> index 9681200..fe74fea 100644
> --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi
> +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi
> @@ -537,6 +537,123 @@
> clocks = < GCC_PRNG_AHB_CLK>;
> clock-names = "core";
> };
> +
> + mdss: mdss at 1a0 {
> + compatible = "qcom,mdss";
> + reg = <0x1a0 0x1000>,
> + <0x1ac8000 0x3000>;
> + reg-names = "mdss_phys", "vbif_phys";
> +
> + power-domains = < MDSS_GDSC>;
> +
> + clocks = < GCC_MDSS_AHB_CLK>,
> + < GCC_MDSS_AXI_CLK>,
> + < GCC_MDSS_VSYNC_CLK>;
> + clock-names = "iface_clk",
> + "bus_clk",
> + "vsync_clk";
> +
> + interrupts = <0 72 0>;
> +
> + interrupt-controller;
> + #interrupt-cells = <1>;
> +
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges;
> +
> + mdp: mdp at 1a01000 {
> + compatible = "qcom,mdp5";
> + reg = <0x1a01000 0x9>;
> + reg-names = "mdp_phys";
> +
> + interrupt-parent = <>;
> + interrupts = <0 0>;
> +
> + clocks = < GCC_MDSS_AHB_CLK>,
> + < GCC_MDSS_AXI_CLK>,
> + < GCC_MDSS_MDP_CLK>,
> + < GCC_MDSS_VSYNC_CLK>;
> + clock-names = "iface_clk",
> + "bus_clk",
> + "core_clk",
> + "vsync_clk";
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port at 0 {
> + reg = <0>;
> + mdp5_intf1_out: endpoint {
> + remote-endpoint =
> <_in>;
> + };
> + };
> + };
> + };
> +
> + dsi0: dsi at 1a98000 {
> + compatible = "qcom,mdss-dsi-ctrl";
> + reg = <0x1a98000 0x25c>;
> + reg-names = "dsi_ctrl";
> +
> + interrupt-parent = <>;
> + interrupts = <4 0>;
> +
> + assigned-clocks = < BYTE0_CLK_SRC>,
> + < PCLK0_CLK_SRC>;
> + assigned-clock-parents = <_phy0 0>,
> + <_phy0 1>;
> +
> + clocks = < GCC_MDSS_MDP_CLK>,
> + < GCC_MDSS_AHB_CLK>,
> + < GCC_MDSS_AXI_CLK>,
> + < GCC_MDSS_BYTE0_CLK>,
> + < GCC_MDSS_PCLK0_CLK>,
> + < GCC_MDSS_ESC0_CLK>;
> + clock-names = "mdp_core_clk",
> + "iface_clk",
> + "bus_clk",
> + "byte_clk",
> + "pixel_clk",
> + "core_clk";
> + phys = <_phy0>;
> + phy-names = "dsi-phy";
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> +
[PATCH v2 24/25] arm64: dts: msm8916: Add display support
On Thu, Aug 25, 2016 at 11:57 PM, Archit Taneja
wrote:
> Hi Rob,
>
> On 06/23/2016 07:43 PM, Archit Taneja wrote:
>>
>> The MSM8916 SoC contains a MDP5 based display block, and one DSI output.
>> Add the top level MDSS DT node, and the MDP5, DSI and DSI PHY children
>> sub-blocks. Establish the link between MDP5's INTF1 output port and DSI's
>> input port.
>>
>> Cc: Andy Gross
>> Cc: Rob Herring
>> Cc: devicetree at vger.kernel.org
>
>
> Can I get an Ack on this?
I don't regularly ack the dts files and leave that to the platform
maintainers, but looks fine to me:
Acked-by: Rob Herring
Rob
>
> Thanks,
> Archit
>
>
>>
>> Signed-off-by: Archit Taneja
>> ---
>> v2:
>> - Removed "qcom,dsi-host-index" and "qcom,dsi-phy-index" props
>>
>> arch/arm64/boot/dts/qcom/msm8916.dtsi | 117
>> ++
>> 1 file changed, 117 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi
>> b/arch/arm64/boot/dts/qcom/msm8916.dtsi
>> index 9681200..fe74fea 100644
>> --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi
>> @@ -537,6 +537,123 @@
>> clocks = < GCC_PRNG_AHB_CLK>;
>> clock-names = "core";
>> };
>> +
>> + mdss: mdss at 1a0 {
>> + compatible = "qcom,mdss";
>> + reg = <0x1a0 0x1000>,
>> + <0x1ac8000 0x3000>;
>> + reg-names = "mdss_phys", "vbif_phys";
>> +
>> + power-domains = < MDSS_GDSC>;
>> +
>> + clocks = < GCC_MDSS_AHB_CLK>,
>> +< GCC_MDSS_AXI_CLK>,
>> +< GCC_MDSS_VSYNC_CLK>;
>> + clock-names = "iface_clk",
>> + "bus_clk",
>> + "vsync_clk";
>> +
>> + interrupts = <0 72 0>;
>> +
>> + interrupt-controller;
>> + #interrupt-cells = <1>;
>> +
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> + ranges;
>> +
>> + mdp: mdp at 1a01000 {
>> + compatible = "qcom,mdp5";
>> + reg = <0x1a01000 0x9>;
>> + reg-names = "mdp_phys";
>> +
>> + interrupt-parent = <>;
>> + interrupts = <0 0>;
>> +
>> + clocks = < GCC_MDSS_AHB_CLK>,
>> +< GCC_MDSS_AXI_CLK>,
>> +< GCC_MDSS_MDP_CLK>,
>> +< GCC_MDSS_VSYNC_CLK>;
>> + clock-names = "iface_clk",
>> + "bus_clk",
>> + "core_clk",
>> + "vsync_clk";
>> +
>> + ports {
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> +
>> + port at 0 {
>> + reg = <0>;
>> + mdp5_intf1_out: endpoint {
>> + remote-endpoint =
>> <_in>;
>> + };
>> + };
>> + };
>> + };
>> +
>> + dsi0: dsi at 1a98000 {
>> + compatible = "qcom,mdss-dsi-ctrl";
>> + reg = <0x1a98000 0x25c>;
>> + reg-names = "dsi_ctrl";
>> +
>> + interrupt-parent = <>;
>> + interrupts = <4 0>;
>> +
>> + assigned-clocks = < BYTE0_CLK_SRC>,
>> + < PCLK0_CLK_SRC>;
>> + assigned-clock-parents = <_phy0 0>,
>> +<_phy0 1>;
>> +
>> + clocks = < GCC_MDSS_MDP_CLK>,
>> +< GCC_MDSS_AHB_CLK>,
>> +< GCC_MDSS_AXI_CLK>,
>> +< GCC_MDSS_BYTE0_CLK>,
>> +< GCC_MDSS_PCLK0_CLK>,
>> +< GCC_MDSS_ESC0_CLK>;
>> + clock-names = "mdp_core_clk",
>> + "iface_clk",
>> + "bus_clk",
>> +
[PATCH v2 24/25] arm64: dts: msm8916: Add display support
On Thu, Jun 23, 2016 at 07:43:29PM +0530, Archit Taneja wrote: > The MSM8916 SoC contains a MDP5 based display block, and one DSI output. > Add the top level MDSS DT node, and the MDP5, DSI and DSI PHY children > sub-blocks. Establish the link between MDP5's INTF1 output port and DSI's > input port. > > Cc: Andy Gross > Cc: Rob Herring > Cc: devicetree at vger.kernel.org This looks fine to me. Regards, Andy
[PATCH v2 24/25] arm64: dts: msm8916: Add display support
The MSM8916 SoC contains a MDP5 based display block, and one DSI output.
Add the top level MDSS DT node, and the MDP5, DSI and DSI PHY children
sub-blocks. Establish the link between MDP5's INTF1 output port and DSI's
input port.
Cc: Andy Gross
Cc: Rob Herring
Cc: devicetree at vger.kernel.org
Signed-off-by: Archit Taneja
---
v2:
- Removed "qcom,dsi-host-index" and "qcom,dsi-phy-index" props
arch/arm64/boot/dts/qcom/msm8916.dtsi | 117 ++
1 file changed, 117 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi
b/arch/arm64/boot/dts/qcom/msm8916.dtsi
index 9681200..fe74fea 100644
--- a/arch/arm64/boot/dts/qcom/msm8916.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi
@@ -537,6 +537,123 @@
clocks = < GCC_PRNG_AHB_CLK>;
clock-names = "core";
};
+
+ mdss: mdss at 1a0 {
+ compatible = "qcom,mdss";
+ reg = <0x1a0 0x1000>,
+ <0x1ac8000 0x3000>;
+ reg-names = "mdss_phys", "vbif_phys";
+
+ power-domains = < MDSS_GDSC>;
+
+ clocks = < GCC_MDSS_AHB_CLK>,
+< GCC_MDSS_AXI_CLK>,
+< GCC_MDSS_VSYNC_CLK>;
+ clock-names = "iface_clk",
+ "bus_clk",
+ "vsync_clk";
+
+ interrupts = <0 72 0>;
+
+ interrupt-controller;
+ #interrupt-cells = <1>;
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ mdp: mdp at 1a01000 {
+ compatible = "qcom,mdp5";
+ reg = <0x1a01000 0x9>;
+ reg-names = "mdp_phys";
+
+ interrupt-parent = <>;
+ interrupts = <0 0>;
+
+ clocks = < GCC_MDSS_AHB_CLK>,
+< GCC_MDSS_AXI_CLK>,
+< GCC_MDSS_MDP_CLK>,
+< GCC_MDSS_VSYNC_CLK>;
+ clock-names = "iface_clk",
+ "bus_clk",
+ "core_clk",
+ "vsync_clk";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port at 0 {
+ reg = <0>;
+ mdp5_intf1_out: endpoint {
+ remote-endpoint =
<_in>;
+ };
+ };
+ };
+ };
+
+ dsi0: dsi at 1a98000 {
+ compatible = "qcom,mdss-dsi-ctrl";
+ reg = <0x1a98000 0x25c>;
+ reg-names = "dsi_ctrl";
+
+ interrupt-parent = <>;
+ interrupts = <4 0>;
+
+ assigned-clocks = < BYTE0_CLK_SRC>,
+ < PCLK0_CLK_SRC>;
+ assigned-clock-parents = <_phy0 0>,
+<_phy0 1>;
+
+ clocks = < GCC_MDSS_MDP_CLK>,
+< GCC_MDSS_AHB_CLK>,
+< GCC_MDSS_AXI_CLK>,
+< GCC_MDSS_BYTE0_CLK>,
+< GCC_MDSS_PCLK0_CLK>,
+< GCC_MDSS_ESC0_CLK>;
+ clock-names = "mdp_core_clk",
+ "iface_clk",
+ "bus_clk",
+ "byte_clk",
+ "pixel_clk",
+ "core_clk";
+ phys = <_phy0>;
+ phy-names = "dsi-phy";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port at 0 {
+ reg = <0>;
+ dsi0_in: endpoint {
+
