Re: [PATCH v2 3/3] phy: Add driver for mixel dphy found on imx8
Hi, On Fri, Feb 08, 2019 at 11:55:41AM +, Robert Chiras wrote: [..snip..] > > > version of eLCDIF with Raydium RM67191 DSI panel on mScale850D > > > (i.MX8MQ). And I tried using this driver but there is no signal on > > > the > > > screen, even through the register values are all identical. Next, > > > I'll > > > try to debug why isn't this working on my setup. > > I'm testing this on the Librem 5 devkit with a rockchip panel atm > > using > > DCSS not eLCDIF though. My plan is to move to the NXP evk in the not > > so > > far future to make this easier to reproduce. > > Good to know. Currently I am working on the eLCDIF pipeline on 850D to > make it ready for upstream. Since you took my DPHY driver and submitted > upstream in a better shape, I will make use of it. I've submitted a v6. In case you're already using it maybe adding a Tested-By or even Reviewed-By: from you might help mainline adoption? Cheers, -- Guido ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: [PATCH v2 3/3] phy: Add driver for mixel dphy found on imx8
Hi, On Fri, Feb 08, 2019 at 11:55:41AM +, Robert Chiras wrote: > Hi Guido > > On Vi, 2019-02-08 at 12:40 +0100, Guido Günther wrote: > > Hi Robert, > > On Wed, Feb 06, 2019 at 03:28:07PM +, Robert Chiras wrote: > > > > > > Hi Guido, > > > > > > Thanks for picking this up. It's interesting to see that a lot has > > > changed in the PHY API and the phy can be now configured through > > > the > > > API instead of exported function as I did in the NXP tree. > > > > > > I was going through your implementation and I noticed you also > > > added > > > the phy_ref clock to this driver too. This is good, since the DPHY > > > needs this clock, but I have a question related to the other > > > clocks: > > > According to the Northwest Logic reference manual (the DSI host > > > that > > > uses this DPHY), the host relies on the TX clock in order to > > > configure > > > the DPHY. Is this driver relying on it's user to also enable the TX > > > clock? > > Yes, I think that would be best. In fact due to lack of reference > > manuals for nwl and mixel I didn't even know exactly which clocks > > needed > > to be on already so I currently set for enabling this after the nwl > > clocks. Are these manuals available publicly somewhere, I couldn't > > find > > them? > > That's OK, I guess. Regarding the manuals: we have them from the vendor > so I can't share them. Too bad. Any contact I could ping there would also be nice? > > > > > > > > > Also: did you test this driver? Because I have a version of the > > > patches > > > from NXP tree rebased on top of latest linux-next and I have a > > > working > > Hmm...could you (maybe off list) send the boot output with DEBUG 1 > > at the top of the driver and drm.debug=0x2f on the kernel command > > line? > > Maybe I can spot something. > > Eventually I got it working. On i.MX8MQ there is a System Reset > Controller that controls the clocks on each individual block. For some > reason, before asserting the MIPI clock domain in this SRC, a delay is > needed (right now, the hack is a sleep). Probably there is a component > that is not ready yet. Right now I am trying to figure out which one is > it and how can I wait for it. > > > > > > > > > version of eLCDIF with Raydium RM67191 DSI panel on mScale850D > > > (i.MX8MQ). And I tried using this driver but there is no signal on > > > the > > > screen, even through the register values are all identical. Next, > > > I'll > > > try to debug why isn't this working on my setup. > > I'm testing this on the Librem 5 devkit with a rockchip panel atm > > using > > DCSS not eLCDIF though. My plan is to move to the NXP evk in the not > > so > > far future to make this easier to reproduce. > > Good to know. Currently I am working on the eLCDIF pipeline on 850D to > make it ready for upstream. Since you took my DPHY driver and submitted > upstream in a better shape, I will make use of it. Cool. I have an initial version of nwl mostly in shape now too (hope to send it out in a couple of days). eLCDIF will be handy to test the whole stack on 5.x. Cheers, -- Guido ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: [PATCH v2 3/3] phy: Add driver for mixel dphy found on imx8
Hi Guido On Vi, 2019-02-08 at 12:40 +0100, Guido Günther wrote: > Hi Robert, > On Wed, Feb 06, 2019 at 03:28:07PM +, Robert Chiras wrote: > > > > Hi Guido, > > > > Thanks for picking this up. It's interesting to see that a lot has > > changed in the PHY API and the phy can be now configured through > > the > > API instead of exported function as I did in the NXP tree. > > > > I was going through your implementation and I noticed you also > > added > > the phy_ref clock to this driver too. This is good, since the DPHY > > needs this clock, but I have a question related to the other > > clocks: > > According to the Northwest Logic reference manual (the DSI host > > that > > uses this DPHY), the host relies on the TX clock in order to > > configure > > the DPHY. Is this driver relying on it's user to also enable the TX > > clock? > Yes, I think that would be best. In fact due to lack of reference > manuals for nwl and mixel I didn't even know exactly which clocks > needed > to be on already so I currently set for enabling this after the nwl > clocks. Are these manuals available publicly somewhere, I couldn't > find > them? That's OK, I guess. Regarding the manuals: we have them from the vendor so I can't share them. > > > > > Also: did you test this driver? Because I have a version of the > > patches > > from NXP tree rebased on top of latest linux-next and I have a > > working > Hmm...could you (maybe off list) send the boot output with DEBUG 1 > at the top of the driver and drm.debug=0x2f on the kernel command > line? > Maybe I can spot something. Eventually I got it working. On i.MX8MQ there is a System Reset Controller that controls the clocks on each individual block. For some reason, before asserting the MIPI clock domain in this SRC, a delay is needed (right now, the hack is a sleep). Probably there is a component that is not ready yet. Right now I am trying to figure out which one is it and how can I wait for it. > > > > > version of eLCDIF with Raydium RM67191 DSI panel on mScale850D > > (i.MX8MQ). And I tried using this driver but there is no signal on > > the > > screen, even through the register values are all identical. Next, > > I'll > > try to debug why isn't this working on my setup. > I'm testing this on the Librem 5 devkit with a rockchip panel atm > using > DCSS not eLCDIF though. My plan is to move to the NXP evk in the not > so > far future to make this easier to reproduce. Good to know. Currently I am working on the eLCDIF pipeline on 850D to make it ready for upstream. Since you took my DPHY driver and submitted upstream in a better shape, I will make use of it. > > > > > Other than the above questions, I have some suggestions inline. > > > > Best regards, > > Robert > > > > > > On Vi, 2019-02-01 at 09:49 +0100, Guido Günther wrote: > > > > > > This adds support for the Mixel DPHY as found on i.MX8 CPUs but > > > since > > > this is an IP core it will likely be found on others in the > > > future. > > > So > > > instead of adding this to the nwl host driver make it a generic > > > PHY > > > driver. > > > > > > The driver supports the i.MX8MQ. Support for i.MX8QM and i.MX8QXP > > > can > > > be > > > added once the necessary system controller bits are in via > > > mixel_dphy_devdata. > > > > > > Signed-off-by: Guido Günther > > > --- > > > drivers/phy/freescale/Kconfig | 9 + > > > drivers/phy/freescale/Makefile| 1 + > > > .../phy/freescale/phy-fsl-imx8-mipi-dphy.c| 494 > > > ++ > > > 3 files changed, 504 insertions(+) > > > create mode 100644 drivers/phy/freescale/phy-fsl-imx8-mipi- > > > dphy.c > > > > > > diff --git a/drivers/phy/freescale/Kconfig > > > b/drivers/phy/freescale/Kconfig > > > index 832670b4952b..43a5ca25d44b 100644 > > > --- a/drivers/phy/freescale/Kconfig > > > +++ b/drivers/phy/freescale/Kconfig > > > @@ -3,3 +3,12 @@ config PHY_FSL_IMX8MQ_USB > > > depends on OF && HAS_IOMEM > > > select GENERIC_PHY > > > default ARCH_MXC && ARM64 > > > + > > > +config PHY_MIXEL_MIPI_DPHY > > > + tristate "Mixel MIPI DSI PHY support" > > > + depends on OF > > > + select GENERIC_PHY > > > + select GENERIC_PHY_MIPI_DPHY > > > + help > > > + Enable this to add support for the Mixel DSI PHY as > > > found > > > + on NXP's i.MX8 family of SOCs. > > > diff --git a/drivers/phy/freescale/Makefile > > > b/drivers/phy/freescale/Makefile > > > index dc2b3f1f2f80..07491c926a2c 100644 > > > --- a/drivers/phy/freescale/Makefile > > > +++ b/drivers/phy/freescale/Makefile > > > @@ -1 +1,2 @@ > > > obj-$(CONFIG_PHY_FSL_IMX8MQ_USB) += phy-fsl-imx8mq-usb.o > > > +obj-$(CONFIG_PHY_MIXEL_MIPI_DPHY)+= phy-fsl-imx8-mipi- > > > dphy.o > > > diff --git a/drivers/phy/freescale/phy-fsl-imx8-mipi-dphy.c > > > b/drivers/phy/freescale/phy-fsl-imx8-mipi-dphy.c > > > new file mode 100644 > > > index ..4b182f2eaa6e > > > --- /dev/null > > > +++ b/drivers/phy/freescale/phy-fsl-imx8-mipi-dphy.c > > >
Re: [PATCH v2 3/3] phy: Add driver for mixel dphy found on imx8
Hi Robert, On Wed, Feb 06, 2019 at 03:28:07PM +, Robert Chiras wrote: > Hi Guido, > > Thanks for picking this up. It's interesting to see that a lot has > changed in the PHY API and the phy can be now configured through the > API instead of exported function as I did in the NXP tree. > > I was going through your implementation and I noticed you also added > the phy_ref clock to this driver too. This is good, since the DPHY > needs this clock, but I have a question related to the other clocks: > According to the Northwest Logic reference manual (the DSI host that > uses this DPHY), the host relies on the TX clock in order to configure > the DPHY. Is this driver relying on it's user to also enable the TX > clock? Yes, I think that would be best. In fact due to lack of reference manuals for nwl and mixel I didn't even know exactly which clocks needed to be on already so I currently set for enabling this after the nwl clocks. Are these manuals available publicly somewhere, I couldn't find them? > Also: did you test this driver? Because I have a version of the patches > from NXP tree rebased on top of latest linux-next and I have a working Hmm...could you (maybe off list) send the boot output with DEBUG 1 at the top of the driver and drm.debug=0x2f on the kernel command line? Maybe I can spot something. > version of eLCDIF with Raydium RM67191 DSI panel on mScale850D > (i.MX8MQ). And I tried using this driver but there is no signal on the > screen, even through the register values are all identical. Next, I'll > try to debug why isn't this working on my setup. I'm testing this on the Librem 5 devkit with a rockchip panel atm using DCSS not eLCDIF though. My plan is to move to the NXP evk in the not so far future to make this easier to reproduce. > Other than the above questions, I have some suggestions inline. > > Best regards, > Robert > > > On Vi, 2019-02-01 at 09:49 +0100, Guido Günther wrote: > > This adds support for the Mixel DPHY as found on i.MX8 CPUs but since > > this is an IP core it will likely be found on others in the future. > > So > > instead of adding this to the nwl host driver make it a generic PHY > > driver. > > > > The driver supports the i.MX8MQ. Support for i.MX8QM and i.MX8QXP can > > be > > added once the necessary system controller bits are in via > > mixel_dphy_devdata. > > > > Signed-off-by: Guido Günther > > --- > > drivers/phy/freescale/Kconfig | 9 + > > drivers/phy/freescale/Makefile| 1 + > > .../phy/freescale/phy-fsl-imx8-mipi-dphy.c| 494 > > ++ > > 3 files changed, 504 insertions(+) > > create mode 100644 drivers/phy/freescale/phy-fsl-imx8-mipi-dphy.c > > > > diff --git a/drivers/phy/freescale/Kconfig > > b/drivers/phy/freescale/Kconfig > > index 832670b4952b..43a5ca25d44b 100644 > > --- a/drivers/phy/freescale/Kconfig > > +++ b/drivers/phy/freescale/Kconfig > > @@ -3,3 +3,12 @@ config PHY_FSL_IMX8MQ_USB > > depends on OF && HAS_IOMEM > > select GENERIC_PHY > > default ARCH_MXC && ARM64 > > + > > +config PHY_MIXEL_MIPI_DPHY > > + tristate "Mixel MIPI DSI PHY support" > > + depends on OF > > + select GENERIC_PHY > > + select GENERIC_PHY_MIPI_DPHY > > + help > > + Enable this to add support for the Mixel DSI PHY as found > > + on NXP's i.MX8 family of SOCs. > > diff --git a/drivers/phy/freescale/Makefile > > b/drivers/phy/freescale/Makefile > > index dc2b3f1f2f80..07491c926a2c 100644 > > --- a/drivers/phy/freescale/Makefile > > +++ b/drivers/phy/freescale/Makefile > > @@ -1 +1,2 @@ > > obj-$(CONFIG_PHY_FSL_IMX8MQ_USB) += phy-fsl-imx8mq-usb.o > > +obj-$(CONFIG_PHY_MIXEL_MIPI_DPHY) += phy-fsl-imx8-mipi-dphy.o > > diff --git a/drivers/phy/freescale/phy-fsl-imx8-mipi-dphy.c > > b/drivers/phy/freescale/phy-fsl-imx8-mipi-dphy.c > > new file mode 100644 > > index ..4b182f2eaa6e > > --- /dev/null > > +++ b/drivers/phy/freescale/phy-fsl-imx8-mipi-dphy.c > > @@ -0,0 +1,494 @@ > > +// SPDX-License-Identifier: GPL-2.0+ > > +/* > > + * Copyright 2017,2018 NXP > > + * Copyright 2019 Purism SPC > > + */ > > + > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > + > > +/* DPHY registers */ > > +#define DPHY_PD_DPHY 0x00 > > +#define DPHY_M_PRG_HS_PREPARE 0x04 > > +#define DPHY_MC_PRG_HS_PREPARE 0x08 > > +#define DPHY_M_PRG_HS_ZERO 0x0c > > +#define DPHY_MC_PRG_HS_ZERO0x10 > > +#define DPHY_M_PRG_HS_TRAIL0x14 > > +#define DPHY_MC_PRG_HS_TRAIL 0x18 > > +#define DPHY_PD_PLL0x1c > > +#define DPHY_TST 0x20 > > +#define DPHY_CN0x24 > > +#define DPHY_CM0x28 > > +#define DPHY_CO0x2c > > +#define DPHY_LOCK 0x30 > > +#define DPH
Re: [PATCH v2 3/3] phy: Add driver for mixel dphy found on imx8
Hi,
On Fri, Feb 01, 2019 at 09:26:50AM -0200, Fabio Estevam wrote:
> Hi Guido,
>
> Thanks for the respin. It looks better :-)
Thanks for having a look! All your comments made sense to me and I've
folded them into v3.
Cheers,
-- Guido
>
> On Fri, Feb 1, 2019 at 6:50 AM Guido Günther wrote:
>
> > +config PHY_MIXEL_MIPI_DPHY
> > + tristate "Mixel MIPI DSI PHY support"
> > + depends on OF
> > + select GENERIC_PHY
> > + select GENERIC_PHY_MIPI_DPHY
>
> Since you converted to regmap, I guess you need:
> select REGMAP_MMIO now?
>
> > + help
> > + Enable this to add support for the Mixel DSI PHY as found
> > + on NXP's i.MX8 family of SOCs.
> > diff --git a/drivers/phy/freescale/Makefile b/drivers/phy/freescale/Makefile
> > index dc2b3f1f2f80..07491c926a2c 100644
> > --- a/drivers/phy/freescale/Makefile
> > +++ b/drivers/phy/freescale/Makefile
> > @@ -1 +1,2 @@
> > obj-$(CONFIG_PHY_FSL_IMX8MQ_USB) += phy-fsl-imx8mq-usb.o
> > +obj-$(CONFIG_PHY_MIXEL_MIPI_DPHY) += phy-fsl-imx8-mipi-dphy.o
> > diff --git a/drivers/phy/freescale/phy-fsl-imx8-mipi-dphy.c
> > b/drivers/phy/freescale/phy-fsl-imx8-mipi-dphy.c
> > new file mode 100644
> > index ..4b182f2eaa6e
> > --- /dev/null
> > +++ b/drivers/phy/freescale/phy-fsl-imx8-mipi-dphy.c
> > @@ -0,0 +1,494 @@
> > +// SPDX-License-Identifier: GPL-2.0+
> > +/*
> > + * Copyright 2017,2018 NXP
> > + * Copyright 2019 Purism SPC
> > + */
> > +
> > +#include
> > +#include
> > +#include
> > +#include
> > +#include
> > +#include
> > +#include
> > +#include
> > +#include
> > +#include
> > +#include
> > +
> > +/* DPHY registers */
> > +#define DPHY_PD_DPHY 0x00
> > +#define DPHY_M_PRG_HS_PREPARE 0x04
> > +#define DPHY_MC_PRG_HS_PREPARE 0x08
> > +#define DPHY_M_PRG_HS_ZERO 0x0c
> > +#define DPHY_MC_PRG_HS_ZERO0x10
> > +#define DPHY_M_PRG_HS_TRAIL0x14
> > +#define DPHY_MC_PRG_HS_TRAIL 0x18
> > +#define DPHY_PD_PLL0x1c
> > +#define DPHY_TST 0x20
> > +#define DPHY_CN0x24
> > +#define DPHY_CM0x28
> > +#define DPHY_CO0x2c
> > +#define DPHY_LOCK 0x30
> > +#define DPHY_LOCK_BYP 0x34
> > +#define DPHY_REG_BYPASS_PLL0x4C
> > +
> > +#define MBPS(x) ((x) * 100)
> > +
> > +#define DATA_RATE_MAX_SPEED MBPS(1500)
> > +#define DATA_RATE_MIN_SPEED MBPS(80)
> > +
> > +#define CN_BUF 0xcb7a89c0
> > +#define CO_BUF 0x63
> > +#define CM(x) ( \
> > + ((x) < 32)?0xe0|((x)-16) : \
>
> Doesn't checkpatch complain about the need of space between operators?
>
> > + ((x) < 64)?0xc0|((x)-32) : \
> > + ((x) < 128)?0x80|((x)-64) : \
> > + ((x) - 128))
> > +#define CN(x) (((x) == 1)?0x1f : (((CN_BUF)>>((x)-1))&0x1f))
> > +#define CO(x) ((CO_BUF)>>(8-(x))&0x3)
> > +
> > +/* PHY power on is LOW_ENABLE */
>
> active low is probably a better term.
>
> > +#define PWR_ON 0
> > +#define PWR_OFF1
>
> > +static inline u32 phy_read(struct phy *phy, unsigned int reg)
>
> After the conversion to regmap this function is unused now and you
> should remove it.
>
> > +static inline void phy_write(struct phy *phy, u32 value, unsigned int reg)
>
> No need for "inline".
>
> Make it static int instead.
>
> > +{
> > + struct mixel_dphy_priv *priv = phy_get_drvdata(phy);
> > + int ret;
> > +
> > + ret = regmap_write(priv->regs, reg, value);
>
> Or maybe get rid of this function and use regmap_write() instead.
>
> > + frequency = ref_clk * numerator / (2 * denominator);
> > + dev_info(&phy->dev, "freq=%ld, hs_clk/ref_clk=%ld/%ld ⩰ %ld/%ld\n",
>
> dev_dbg() would be better?
>
> > +frequency, dphy_opts->hs_clk_rate, ref_clk,
> > +numerator, denominator);
> > +
> > + /* LP clock period */
> > + lp_t = 1L / dphy_opts->lp_clk_rate; /* ps */
> > + dev_dbg(&phy->dev, "LP clock %lu, period: %lu ps\n",
> > + dphy_opts->lp_clk_rate, lp_t);
> > + /*
> > +* hs_prepare: in lp clock periods
> > +*/
>
> Please use single line comment style instead.
>
> > + if (2 * dphy_opts->hs_prepare > 5 * lp_t) {
> > + dev_err(&phy->dev,
> > + "hs_prepare (%u) > 2.5 * lp clock period (%lu)",
> > + dphy_opts->hs_prepare, lp_t);
> > + return -EINVAL;
> > + }
> > + /* 00: lp_t, 01: 1.5 * lp_t, 10: 2 * lp_t, 11: 2.5 * lp_t */
> > + if (dphy_opts->hs_prepare < lp_t)
> > + n = 0;
> > + else
> > + n = 2 * (dphy_opts->hs_prepare - lp_t) / lp_t;
> > + cfg->m_prg_hs_prepare = n;
> > +
> > + /*
> > +* clk_prepare: in lp clock
Re: [PATCH v2 3/3] phy: Add driver for mixel dphy found on imx8
Hi Guido,
Thanks for picking this up. It's interesting to see that a lot has
changed in the PHY API and the phy can be now configured through the
API instead of exported function as I did in the NXP tree.
I was going through your implementation and I noticed you also added
the phy_ref clock to this driver too. This is good, since the DPHY
needs this clock, but I have a question related to the other clocks:
According to the Northwest Logic reference manual (the DSI host that
uses this DPHY), the host relies on the TX clock in order to configure
the DPHY. Is this driver relying on it's user to also enable the TX
clock?
Also: did you test this driver? Because I have a version of the patches
from NXP tree rebased on top of latest linux-next and I have a working
version of eLCDIF with Raydium RM67191 DSI panel on mScale850D
(i.MX8MQ). And I tried using this driver but there is no signal on the
screen, even through the register values are all identical. Next, I'll
try to debug why isn't this working on my setup.
Other than the above questions, I have some suggestions inline.
Best regards,
Robert
On Vi, 2019-02-01 at 09:49 +0100, Guido Günther wrote:
> This adds support for the Mixel DPHY as found on i.MX8 CPUs but since
> this is an IP core it will likely be found on others in the future.
> So
> instead of adding this to the nwl host driver make it a generic PHY
> driver.
>
> The driver supports the i.MX8MQ. Support for i.MX8QM and i.MX8QXP can
> be
> added once the necessary system controller bits are in via
> mixel_dphy_devdata.
>
> Signed-off-by: Guido Günther
> ---
> drivers/phy/freescale/Kconfig | 9 +
> drivers/phy/freescale/Makefile| 1 +
> .../phy/freescale/phy-fsl-imx8-mipi-dphy.c| 494
> ++
> 3 files changed, 504 insertions(+)
> create mode 100644 drivers/phy/freescale/phy-fsl-imx8-mipi-dphy.c
>
> diff --git a/drivers/phy/freescale/Kconfig
> b/drivers/phy/freescale/Kconfig
> index 832670b4952b..43a5ca25d44b 100644
> --- a/drivers/phy/freescale/Kconfig
> +++ b/drivers/phy/freescale/Kconfig
> @@ -3,3 +3,12 @@ config PHY_FSL_IMX8MQ_USB
> depends on OF && HAS_IOMEM
> select GENERIC_PHY
> default ARCH_MXC && ARM64
> +
> +config PHY_MIXEL_MIPI_DPHY
> + tristate "Mixel MIPI DSI PHY support"
> + depends on OF
> + select GENERIC_PHY
> + select GENERIC_PHY_MIPI_DPHY
> + help
> + Enable this to add support for the Mixel DSI PHY as found
> + on NXP's i.MX8 family of SOCs.
> diff --git a/drivers/phy/freescale/Makefile
> b/drivers/phy/freescale/Makefile
> index dc2b3f1f2f80..07491c926a2c 100644
> --- a/drivers/phy/freescale/Makefile
> +++ b/drivers/phy/freescale/Makefile
> @@ -1 +1,2 @@
> obj-$(CONFIG_PHY_FSL_IMX8MQ_USB) += phy-fsl-imx8mq-usb.o
> +obj-$(CONFIG_PHY_MIXEL_MIPI_DPHY)+= phy-fsl-imx8-mipi-dphy.o
> diff --git a/drivers/phy/freescale/phy-fsl-imx8-mipi-dphy.c
> b/drivers/phy/freescale/phy-fsl-imx8-mipi-dphy.c
> new file mode 100644
> index ..4b182f2eaa6e
> --- /dev/null
> +++ b/drivers/phy/freescale/phy-fsl-imx8-mipi-dphy.c
> @@ -0,0 +1,494 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright 2017,2018 NXP
> + * Copyright 2019 Purism SPC
> + */
> +
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +
> +/* DPHY registers */
> +#define DPHY_PD_DPHY 0x00
> +#define DPHY_M_PRG_HS_PREPARE0x04
> +#define DPHY_MC_PRG_HS_PREPARE 0x08
> +#define DPHY_M_PRG_HS_ZERO 0x0c
> +#define DPHY_MC_PRG_HS_ZERO 0x10
> +#define DPHY_M_PRG_HS_TRAIL 0x14
> +#define DPHY_MC_PRG_HS_TRAIL 0x18
> +#define DPHY_PD_PLL 0x1c
> +#define DPHY_TST 0x20
> +#define DPHY_CN 0x24
> +#define DPHY_CM 0x28
> +#define DPHY_CO 0x2c
> +#define DPHY_LOCK0x30
> +#define DPHY_LOCK_BYP0x34
> +#define DPHY_REG_BYPASS_PLL 0x4C
> +
> +#define MBPS(x) ((x) * 100)
> +
> +#define DATA_RATE_MAX_SPEED MBPS(1500)
> +#define DATA_RATE_MIN_SPEED MBPS(80)
> +
> +#define CN_BUF 0xcb7a89c0
> +#define CO_BUF 0x63
> +#define CM(x)( \
> + ((x) < 32)?0xe0|((x)-16) : \
> + ((x) < 64)?0xc0|((x)-32) : \
> + ((x) < 128)?0x80|((x)-64) : \
> + ((x) - 128))
> +#define CN(x)(((x) == 1)?0x1f : (((CN_BUF)>>((x)-1))&0x1f))
> +#define CO(x)((CO_BUF)>>(8-(x))&0x3)
> +
> +/* PHY power on is LOW_ENABLE */
> +#define PWR_ON 0
> +#define PWR_OFF 1
> +
> +enum mixel_dphy_devtype {
> + MIXEL_IMX8MQ,
> +};
> +
> +struct mixel_dphy_devdata {
> + u8 reg_tx_rcal;
> + u8 reg_auto_pd_en;
> + u8 reg_rxlprp;
> + u8 reg_rxcdrp;
> + u8 reg_
Re: [PATCH v2 3/3] phy: Add driver for mixel dphy found on imx8
Hi Guido, Thank you for the patch! Yet something to improve: [auto build test ERROR on phy/next] [also build test ERROR on next-20190201] [cannot apply to v5.0-rc4] [if your patch is applied to the wrong git tree, please drop us a note to help improve the system] url: https://github.com/0day-ci/linux/commits/Guido-G-nther/Mixel-DPHY-support-for-i-MX8/20190202-015852 base: https://git.kernel.org/pub/scm/linux/kernel/git/kishon/linux-phy.git next config: um-allyesconfig (attached as .config) compiler: gcc-8 (Debian 8.2.0-14) 8.2.0 reproduce: # save the attached .config to linux build tree make ARCH=um All errors (new ones prefixed by >>): /usr/bin/ld: arch/um/drivers/vde.o: in function `vde_open_real': (.text+0x7d1): warning: Using 'getgrnam' in statically linked applications requires at runtime the shared libraries from the glibc version used for linking /usr/bin/ld: (.text+0x61c): warning: Using 'getpwuid' in statically linked applications requires at runtime the shared libraries from the glibc version used for linking /usr/bin/ld: arch/um/drivers/vector_user.o: in function `user_init_socket_fds': vector_user.c:(.text+0x29d): warning: Using 'getaddrinfo' in statically linked applications requires at runtime the shared libraries from the glibc version used for linking /usr/bin/ld: arch/um/drivers/pcap.o: in function `pcap_nametoaddr': (.text+0xde75): warning: Using 'gethostbyname' in statically linked applications requires at runtime the shared libraries from the glibc version used for linking /usr/bin/ld: arch/um/drivers/pcap.o: in function `pcap_nametonetaddr': (.text+0xdf15): warning: Using 'getnetbyname' in statically linked applications requires at runtime the shared libraries from the glibc version used for linking /usr/bin/ld: arch/um/drivers/pcap.o: in function `pcap_nametoproto': (.text+0xe135): warning: Using 'getprotobyname' in statically linked applications requires at runtime the shared libraries from the glibc version used for linking /usr/bin/ld: arch/um/drivers/pcap.o: in function `pcap_nametoport': (.text+0xdf67): warning: Using 'getservbyname' in statically linked applications requires at runtime the shared libraries from the glibc version used for linking /usr/bin/ld: drivers/phy/freescale/phy-fsl-imx8-mipi-dphy.o: in function `mixel_dphy_probe': >> phy-fsl-imx8-mipi-dphy.c:(.text+0x3d0): undefined reference to `devm_ioremap' >> /usr/bin/ld: phy-fsl-imx8-mipi-dphy.c:(.text+0x440): undefined reference to >> `__devm_regmap_init_mmio_clk' collect2: error: ld returned 1 exit status --- 0-DAY kernel test infrastructureOpen Source Technology Center https://lists.01.org/pipermail/kbuild-all Intel Corporation .config.gz Description: application/gzip ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: [PATCH v2 3/3] phy: Add driver for mixel dphy found on imx8
Hi Guido,
Thanks for the respin. It looks better :-)
On Fri, Feb 1, 2019 at 6:50 AM Guido Günther wrote:
> +config PHY_MIXEL_MIPI_DPHY
> + tristate "Mixel MIPI DSI PHY support"
> + depends on OF
> + select GENERIC_PHY
> + select GENERIC_PHY_MIPI_DPHY
Since you converted to regmap, I guess you need:
select REGMAP_MMIO now?
> + help
> + Enable this to add support for the Mixel DSI PHY as found
> + on NXP's i.MX8 family of SOCs.
> diff --git a/drivers/phy/freescale/Makefile b/drivers/phy/freescale/Makefile
> index dc2b3f1f2f80..07491c926a2c 100644
> --- a/drivers/phy/freescale/Makefile
> +++ b/drivers/phy/freescale/Makefile
> @@ -1 +1,2 @@
> obj-$(CONFIG_PHY_FSL_IMX8MQ_USB) += phy-fsl-imx8mq-usb.o
> +obj-$(CONFIG_PHY_MIXEL_MIPI_DPHY) += phy-fsl-imx8-mipi-dphy.o
> diff --git a/drivers/phy/freescale/phy-fsl-imx8-mipi-dphy.c
> b/drivers/phy/freescale/phy-fsl-imx8-mipi-dphy.c
> new file mode 100644
> index ..4b182f2eaa6e
> --- /dev/null
> +++ b/drivers/phy/freescale/phy-fsl-imx8-mipi-dphy.c
> @@ -0,0 +1,494 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright 2017,2018 NXP
> + * Copyright 2019 Purism SPC
> + */
> +
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +
> +/* DPHY registers */
> +#define DPHY_PD_DPHY 0x00
> +#define DPHY_M_PRG_HS_PREPARE 0x04
> +#define DPHY_MC_PRG_HS_PREPARE 0x08
> +#define DPHY_M_PRG_HS_ZERO 0x0c
> +#define DPHY_MC_PRG_HS_ZERO0x10
> +#define DPHY_M_PRG_HS_TRAIL0x14
> +#define DPHY_MC_PRG_HS_TRAIL 0x18
> +#define DPHY_PD_PLL0x1c
> +#define DPHY_TST 0x20
> +#define DPHY_CN0x24
> +#define DPHY_CM0x28
> +#define DPHY_CO0x2c
> +#define DPHY_LOCK 0x30
> +#define DPHY_LOCK_BYP 0x34
> +#define DPHY_REG_BYPASS_PLL0x4C
> +
> +#define MBPS(x) ((x) * 100)
> +
> +#define DATA_RATE_MAX_SPEED MBPS(1500)
> +#define DATA_RATE_MIN_SPEED MBPS(80)
> +
> +#define CN_BUF 0xcb7a89c0
> +#define CO_BUF 0x63
> +#define CM(x) ( \
> + ((x) < 32)?0xe0|((x)-16) : \
Doesn't checkpatch complain about the need of space between operators?
> + ((x) < 64)?0xc0|((x)-32) : \
> + ((x) < 128)?0x80|((x)-64) : \
> + ((x) - 128))
> +#define CN(x) (((x) == 1)?0x1f : (((CN_BUF)>>((x)-1))&0x1f))
> +#define CO(x) ((CO_BUF)>>(8-(x))&0x3)
> +
> +/* PHY power on is LOW_ENABLE */
active low is probably a better term.
> +#define PWR_ON 0
> +#define PWR_OFF1
> +static inline u32 phy_read(struct phy *phy, unsigned int reg)
After the conversion to regmap this function is unused now and you
should remove it.
> +static inline void phy_write(struct phy *phy, u32 value, unsigned int reg)
No need for "inline".
Make it static int instead.
> +{
> + struct mixel_dphy_priv *priv = phy_get_drvdata(phy);
> + int ret;
> +
> + ret = regmap_write(priv->regs, reg, value);
Or maybe get rid of this function and use regmap_write() instead.
> + frequency = ref_clk * numerator / (2 * denominator);
> + dev_info(&phy->dev, "freq=%ld, hs_clk/ref_clk=%ld/%ld ⩰ %ld/%ld\n",
dev_dbg() would be better?
> +frequency, dphy_opts->hs_clk_rate, ref_clk,
> +numerator, denominator);
> +
> + /* LP clock period */
> + lp_t = 1L / dphy_opts->lp_clk_rate; /* ps */
> + dev_dbg(&phy->dev, "LP clock %lu, period: %lu ps\n",
> + dphy_opts->lp_clk_rate, lp_t);
> + /*
> +* hs_prepare: in lp clock periods
> +*/
Please use single line comment style instead.
> + if (2 * dphy_opts->hs_prepare > 5 * lp_t) {
> + dev_err(&phy->dev,
> + "hs_prepare (%u) > 2.5 * lp clock period (%lu)",
> + dphy_opts->hs_prepare, lp_t);
> + return -EINVAL;
> + }
> + /* 00: lp_t, 01: 1.5 * lp_t, 10: 2 * lp_t, 11: 2.5 * lp_t */
> + if (dphy_opts->hs_prepare < lp_t)
> + n = 0;
> + else
> + n = 2 * (dphy_opts->hs_prepare - lp_t) / lp_t;
> + cfg->m_prg_hs_prepare = n;
> +
> + /*
> +* clk_prepare: in lp clock periods
> +*/
Same here.
> + if (2 * dphy_opts->clk_prepare > 3 * lp_t) {
> + dev_err(&phy->dev,
> + "clk_prepare (%u) > 1.5 * lp clock period (%lu)",
> + dphy_opts->clk_prepare, lp_t);
> + return -EINVAL;
> + }
> + /* 00: lp_t, 01: 1.5 * lp_t */
> + cfg->mc_prg_hs_prepare = dphy_opts->clk_prepare > lp_t ? 1 : 0;
> +
> + /*
> +* hs_zero: forumu
[PATCH v2 3/3] phy: Add driver for mixel dphy found on imx8
This adds support for the Mixel DPHY as found on i.MX8 CPUs but since
this is an IP core it will likely be found on others in the future. So
instead of adding this to the nwl host driver make it a generic PHY
driver.
The driver supports the i.MX8MQ. Support for i.MX8QM and i.MX8QXP can be
added once the necessary system controller bits are in via
mixel_dphy_devdata.
Signed-off-by: Guido Günther
---
drivers/phy/freescale/Kconfig | 9 +
drivers/phy/freescale/Makefile| 1 +
.../phy/freescale/phy-fsl-imx8-mipi-dphy.c| 494 ++
3 files changed, 504 insertions(+)
create mode 100644 drivers/phy/freescale/phy-fsl-imx8-mipi-dphy.c
diff --git a/drivers/phy/freescale/Kconfig b/drivers/phy/freescale/Kconfig
index 832670b4952b..43a5ca25d44b 100644
--- a/drivers/phy/freescale/Kconfig
+++ b/drivers/phy/freescale/Kconfig
@@ -3,3 +3,12 @@ config PHY_FSL_IMX8MQ_USB
depends on OF && HAS_IOMEM
select GENERIC_PHY
default ARCH_MXC && ARM64
+
+config PHY_MIXEL_MIPI_DPHY
+ tristate "Mixel MIPI DSI PHY support"
+ depends on OF
+ select GENERIC_PHY
+ select GENERIC_PHY_MIPI_DPHY
+ help
+ Enable this to add support for the Mixel DSI PHY as found
+ on NXP's i.MX8 family of SOCs.
diff --git a/drivers/phy/freescale/Makefile b/drivers/phy/freescale/Makefile
index dc2b3f1f2f80..07491c926a2c 100644
--- a/drivers/phy/freescale/Makefile
+++ b/drivers/phy/freescale/Makefile
@@ -1 +1,2 @@
obj-$(CONFIG_PHY_FSL_IMX8MQ_USB) += phy-fsl-imx8mq-usb.o
+obj-$(CONFIG_PHY_MIXEL_MIPI_DPHY) += phy-fsl-imx8-mipi-dphy.o
diff --git a/drivers/phy/freescale/phy-fsl-imx8-mipi-dphy.c
b/drivers/phy/freescale/phy-fsl-imx8-mipi-dphy.c
new file mode 100644
index ..4b182f2eaa6e
--- /dev/null
+++ b/drivers/phy/freescale/phy-fsl-imx8-mipi-dphy.c
@@ -0,0 +1,494 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2017,2018 NXP
+ * Copyright 2019 Purism SPC
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+/* DPHY registers */
+#define DPHY_PD_DPHY 0x00
+#define DPHY_M_PRG_HS_PREPARE 0x04
+#define DPHY_MC_PRG_HS_PREPARE 0x08
+#define DPHY_M_PRG_HS_ZERO 0x0c
+#define DPHY_MC_PRG_HS_ZERO0x10
+#define DPHY_M_PRG_HS_TRAIL0x14
+#define DPHY_MC_PRG_HS_TRAIL 0x18
+#define DPHY_PD_PLL0x1c
+#define DPHY_TST 0x20
+#define DPHY_CN0x24
+#define DPHY_CM0x28
+#define DPHY_CO0x2c
+#define DPHY_LOCK 0x30
+#define DPHY_LOCK_BYP 0x34
+#define DPHY_REG_BYPASS_PLL0x4C
+
+#define MBPS(x) ((x) * 100)
+
+#define DATA_RATE_MAX_SPEED MBPS(1500)
+#define DATA_RATE_MIN_SPEED MBPS(80)
+
+#define CN_BUF 0xcb7a89c0
+#define CO_BUF 0x63
+#define CM(x) ( \
+ ((x) < 32)?0xe0|((x)-16) : \
+ ((x) < 64)?0xc0|((x)-32) : \
+ ((x) < 128)?0x80|((x)-64) : \
+ ((x) - 128))
+#define CN(x) (((x) == 1)?0x1f : (((CN_BUF)>>((x)-1))&0x1f))
+#define CO(x) ((CO_BUF)>>(8-(x))&0x3)
+
+/* PHY power on is LOW_ENABLE */
+#define PWR_ON 0
+#define PWR_OFF1
+
+enum mixel_dphy_devtype {
+ MIXEL_IMX8MQ,
+};
+
+struct mixel_dphy_devdata {
+ u8 reg_tx_rcal;
+ u8 reg_auto_pd_en;
+ u8 reg_rxlprp;
+ u8 reg_rxcdrp;
+ u8 reg_rxhs_settle;
+};
+
+static const struct mixel_dphy_devdata mixel_dphy_devdata[] = {
+ [MIXEL_IMX8MQ] = {
+ .reg_tx_rcal = 0x38,
+ .reg_auto_pd_en = 0x3c,
+ .reg_rxlprp = 0x40,
+ .reg_rxcdrp = 0x44,
+ .reg_rxhs_settle = 0x48,
+ },
+};
+
+struct mixel_dphy_cfg {
+ /* DPHY PLL parameters */
+ u32 cm;
+ u32 cn;
+ u32 co;
+ /* DPHY register values */
+ u8 mc_prg_hs_prepare;
+ u8 m_prg_hs_prepare;
+ u8 mc_prg_hs_zero;
+ u8 m_prg_hs_zero;
+ u8 mc_prg_hs_trail;
+ u8 m_prg_hs_trail;
+ u8 rxhs_settle;
+};
+
+struct mixel_dphy_priv {
+ struct mixel_dphy_cfg cfg;
+ struct regmap *regs;
+ struct clk *phy_ref_clk;
+ const struct mixel_dphy_devdata *devdata;
+};
+
+static const struct regmap_config mixel_dphy_regmap_config = {
+ .reg_bits = 8,
+ .val_bits = 32,
+ .reg_stride = 4,
+ .max_register = DPHY_REG_BYPASS_PLL,
+ .name = "mipi-dphy",
+};
+
+static inline u32 phy_read(struct phy *phy, unsigned int reg)
+{
+ struct mixel_dphy_priv *priv = phy_get_drvdata(phy);
+ u32 val;
+ int ret;
+
+ ret = regmap_read(priv->regs, reg, &val);
+ if (ret < 0)
+ dev_err(&phy->dev, "Failed to read DPHY reg %d: %d", reg, ret);
+ return val;
