[PATCH v2 3/7] drm: add Atmel HLCDC Display Controller support
Hello,
It's been almost a month and I only got reviews pointing minor issues.
I'd really like to get feedback/reviews from DRM/KMS maintainers and/or
experienced developers (this is my first DRM/KMS driver I'm pretty sure
there are things to fix).
Best Regards,
Boris
On Mon, 9 Jun 2014 18:04:16 +0200
Boris BREZILLON wrote:
> The Atmel HLCDC (High LCD Controller) IP available on some Atmel SoCs (i.e.
> at91sam9n12, at91sam9x5 family or sama5d3 family) provides a display
> controller device.
>
> This display controller support at least one primary plane and might
> provide several overlays and an hardware cursor depending on the IP
> version.
>
> Signed-off-by: Boris BREZILLON
> ---
> .../devicetree/bindings/drm/atmel-hlcdc-dc.txt | 59 ++
> drivers/gpu/drm/Kconfig| 2 +
> drivers/gpu/drm/Makefile | 1 +
> drivers/gpu/drm/atmel-hlcdc/Kconfig| 11 +
> drivers/gpu/drm/atmel-hlcdc/Makefile | 7 +
> drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c | 529
> drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c | 477 ++
> drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.h | 178 ++
> drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_layer.c| 701
> +
> drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_layer.h| 417
> drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_panel.c| 351 +++
> drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c| 658 +++
> drivers/gpu/drm/atmel_hlcdc/Kconfig| 11 +
> drivers/gpu/drm/atmel_hlcdc/Makefile | 8 +
> 14 files changed, 3410 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/drm/atmel-hlcdc-dc.txt
> create mode 100644 drivers/gpu/drm/atmel-hlcdc/Kconfig
> create mode 100644 drivers/gpu/drm/atmel-hlcdc/Makefile
> create mode 100644 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c
> create mode 100644 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c
> create mode 100644 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.h
> create mode 100644 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_layer.c
> create mode 100644 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_layer.h
> create mode 100644 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_panel.c
> create mode 100644 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c
> create mode 100644 drivers/gpu/drm/atmel_hlcdc/Kconfig
> create mode 100644 drivers/gpu/drm/atmel_hlcdc/Makefile
>
> diff --git a/Documentation/devicetree/bindings/drm/atmel-hlcdc-dc.txt
> b/Documentation/devicetree/bindings/drm/atmel-hlcdc-dc.txt
> new file mode 100644
> index 000..594bdb2
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/drm/atmel-hlcdc-dc.txt
> @@ -0,0 +1,59 @@
> +Device-Tree bindings for Atmel's HLCDC (High LCD Controller) DRM driver
> +
> +The Atmel HLCDC Display Controller is subdevice of the HLCDC MFD device.
> +See Documentation/devicetree/bindings/mfd/atmel-hlcdc.txt for more details.
> +
> +Required properties:
> + - compatible: value should be one of the following:
> + "atmel,hlcdc-dc"
> + - interrupts: the HLCDC interrupt definition
> + - pinctrl-names: the pin control state names. Should contain "default",
> + "rgb-444", "rgb-565", "rgb-666" and "rgb-888".
> + - pinctrl-[0-4]: should contain the pinctrl states described by pinctrl
> + names.
> + - atmel,panel: Should contain a phandle with 2 parameters.
> + The first cell is a phandle to a DRM panel device
> + The second cell encodes the RGB mode, which can take the following values:
> + * 0: RGB444
> + * 1: RGB565
> + * 2: RGB666
> + * 3: RGB888
> + The third cell encodes specific flags describing LCD signals configuration
> + (see Atmel's datasheet for a full description of these fields):
> + * bit 0: HSPOL: Horizontal Synchronization Pulse Polarity
> + * bit 1: VSPOL: Vertical Synchronization Pulse Polarity
> + * bit 2: VSPDLYS: Vertical Synchronization Pulse Start
> + * bit 3: VSPDLYE: Vertical Synchronization Pulse End
> + * bit 4: DISPPOL: Display Signal Polarity
> + * bit 7: DISPDLY: LCD Controller Display Power Signal Synchronization
> + * bit 12: VSPSU: LCD Controller Vertical synchronization Pulse Setup
> Configuration
> + * bit 13: VSPHO: LCD Controller Vertical synchronization Pulse Hold
> Configuration
> + * bit 16-20: GUARDTIME: LCD DISPLAY Guard Time
> +
> +Example:
> +
> + hlcdc: hlcdc at f003 {
> + compatible = "atmel,sama5d3-hlcdc";
> + reg = <0xf003 0x2000>;
> + clocks = <&lcdc_clk>, <&lcdck>, <&clk32k>;
> + clock-names = "periph_clk","sys_clk", "slow_clk";
> + status = "disabled";
> +
> + hlcdc-display-controller {
> + compatible = "atmel,hlcdc-dc";
> + interrupts = <36 IRQ_TYPE_LEVEL_HIGH 0>;
> + pinctrl-names = "default", "rgb-444", "rgb-565",
> "rgb-666", "rgb-888"
[PATCH v2 3/7] drm: add Atmel HLCDC Display Controller support
On 09/06/2014 18:04, Boris BREZILLON wrote:
> The Atmel HLCDC (High LCD Controller) IP available on some Atmel SoCs (i.e.
> at91sam9n12, at91sam9x5 family or sama5d3 family) provides a display
> controller device.
>
> This display controller support at least one primary plane and might
> provide several overlays and an hardware cursor depending on the IP
> version.
>
> Signed-off-by: Boris BREZILLON
> ---
> .../devicetree/bindings/drm/atmel-hlcdc-dc.txt | 59 ++
> drivers/gpu/drm/Kconfig| 2 +
> drivers/gpu/drm/Makefile | 1 +
> drivers/gpu/drm/atmel-hlcdc/Kconfig| 11 +
> drivers/gpu/drm/atmel-hlcdc/Makefile | 7 +
> drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c | 529
> drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c | 477 ++
> drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.h | 178 ++
> drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_layer.c| 701
> +
> drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_layer.h| 417
> drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_panel.c| 351 +++
> drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c| 658 +++
> drivers/gpu/drm/atmel_hlcdc/Kconfig| 11 +
> drivers/gpu/drm/atmel_hlcdc/Makefile | 8 +
These two files should not be part of the driver. I'll fix that.
> 14 files changed, 3410 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/drm/atmel-hlcdc-dc.txt
> create mode 100644 drivers/gpu/drm/atmel-hlcdc/Kconfig
> create mode 100644 drivers/gpu/drm/atmel-hlcdc/Makefile
> create mode 100644 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c
> create mode 100644 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c
> create mode 100644 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.h
> create mode 100644 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_layer.c
> create mode 100644 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_layer.h
> create mode 100644 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_panel.c
> create mode 100644 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c
> create mode 100644 drivers/gpu/drm/atmel_hlcdc/Kconfig
> create mode 100644 drivers/gpu/drm/atmel_hlcdc/Makefile
>
> diff --git a/Documentation/devicetree/bindings/drm/atmel-hlcdc-dc.txt
> b/Documentation/devicetree/bindings/drm/atmel-hlcdc-dc.txt
> new file mode 100644
> index 000..594bdb2
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/drm/atmel-hlcdc-dc.txt
> @@ -0,0 +1,59 @@
> +Device-Tree bindings for Atmel's HLCDC (High LCD Controller) DRM driver
> +
> +The Atmel HLCDC Display Controller is subdevice of the HLCDC MFD device.
> +See Documentation/devicetree/bindings/mfd/atmel-hlcdc.txt for more details.
> +
> +Required properties:
> + - compatible: value should be one of the following:
> + "atmel,hlcdc-dc"
> + - interrupts: the HLCDC interrupt definition
> + - pinctrl-names: the pin control state names. Should contain "default",
> + "rgb-444", "rgb-565", "rgb-666" and "rgb-888".
> + - pinctrl-[0-4]: should contain the pinctrl states described by pinctrl
> + names.
> + - atmel,panel: Should contain a phandle with 2 parameters.
> + The first cell is a phandle to a DRM panel device
> + The second cell encodes the RGB mode, which can take the following values:
> + * 0: RGB444
> + * 1: RGB565
> + * 2: RGB666
> + * 3: RGB888
> + The third cell encodes specific flags describing LCD signals configuration
> + (see Atmel's datasheet for a full description of these fields):
> + * bit 0: HSPOL: Horizontal Synchronization Pulse Polarity
> + * bit 1: VSPOL: Vertical Synchronization Pulse Polarity
> + * bit 2: VSPDLYS: Vertical Synchronization Pulse Start
> + * bit 3: VSPDLYE: Vertical Synchronization Pulse End
> + * bit 4: DISPPOL: Display Signal Polarity
> + * bit 7: DISPDLY: LCD Controller Display Power Signal Synchronization
> + * bit 12: VSPSU: LCD Controller Vertical synchronization Pulse Setup
> Configuration
> + * bit 13: VSPHO: LCD Controller Vertical synchronization Pulse Hold
> Configuration
> + * bit 16-20: GUARDTIME: LCD DISPLAY Guard Time
> +
> +Example:
> +
> + hlcdc: hlcdc at f003 {
> + compatible = "atmel,sama5d3-hlcdc";
> + reg = <0xf003 0x2000>;
> + clocks = <&lcdc_clk>, <&lcdck>, <&clk32k>;
> + clock-names = "periph_clk","sys_clk", "slow_clk";
> + status = "disabled";
> +
> + hlcdc-display-controller {
> + compatible = "atmel,hlcdc-dc";
> + interrupts = <36 IRQ_TYPE_LEVEL_HIGH 0>;
> + pinctrl-names = "default", "rgb-444", "rgb-565",
> "rgb-666", "rgb-888";
> + pinctrl-0 = <&pinctrl_lcd_base>;
> + pinctrl-1 = <&pinctrl_lcd_base &pinctrl_lcd_rgb444>;
> + pinctrl-2 = <&pinctrl_lcd_base &pinctrl_lcd_rgb565>;
> +
[PATCH v2 3/7] drm: add Atmel HLCDC Display Controller support
Hello JJ, On 15/06/2014 11:32, Jean-Jacques Hiblot wrote: > > On 06/09/2014 06:04 PM, Boris BREZILLON wrote: >> The Atmel HLCDC (High LCD Controller) IP available on some Atmel SoCs (i.e. >> at91sam9n12, at91sam9x5 family or sama5d3 family) provides a display >> controller device. >> >> This display controller support at least one primary plane and might >> provide several overlays and an hardware cursor depending on the IP >> version. >> >> Signed-off-by: Boris BREZILLON >> --- [...] >> +vm.vfront_porch > 0x40 || vm.vfront_porch < 0 || >> +vm.vback_porch > 0x40 || vm.vback_porch < 0 || >> +vm.hfront_porch > 0x200 || vm.hfront_porch < 0 || >> +vm.hback_porch > 0x200 || vm.hback_porch < 0 || >> +mode->hdisplay > 2048 || mode->hdisplay < 0 || >> +mode->vdisplay > 2048 || mode->vdisplay < 0) >> +return -EINVAL; >> + >> +regmap_write(regmap, ATMEL_HLCDC_CFG(1), >> + (vm.hsync_len - 1) | ((vm.vsync_len - 1) << 16)); >> + >> +regmap_write(regmap, ATMEL_HLCDC_CFG(2), >> + (vm.vfront_porch - 1) | ((vm.vback_porch - 1) << 16)); > Acording to the datasheet, it's vm.vback_porch instead of > (vm.vback_porch -1). Oh, nice catch! I'll check with Atmel that this is not a typo in their datasheet, because all other fields need the minus 1. Thanks for your review. Best Regards, Boris -- Boris Brezillon, Free Electrons Embedded Linux and Kernel engineering http://free-electrons.com
[PATCH v2 3/7] drm: add Atmel HLCDC Display Controller support
On 06/09/2014 06:04 PM, Boris BREZILLON wrote:
> The Atmel HLCDC (High LCD Controller) IP available on some Atmel SoCs (i.e.
> at91sam9n12, at91sam9x5 family or sama5d3 family) provides a display
> controller device.
>
> This display controller support at least one primary plane and might
> provide several overlays and an hardware cursor depending on the IP
> version.
>
> Signed-off-by: Boris BREZILLON
> ---
> .../devicetree/bindings/drm/atmel-hlcdc-dc.txt | 59 ++
> drivers/gpu/drm/Kconfig| 2 +
> drivers/gpu/drm/Makefile | 1 +
> drivers/gpu/drm/atmel-hlcdc/Kconfig| 11 +
> drivers/gpu/drm/atmel-hlcdc/Makefile | 7 +
> drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c | 529
> drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c | 477 ++
> drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.h | 178 ++
> drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_layer.c| 701
> +
> drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_layer.h| 417
> drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_panel.c| 351 +++
> drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c| 658 +++
> drivers/gpu/drm/atmel_hlcdc/Kconfig| 11 +
> drivers/gpu/drm/atmel_hlcdc/Makefile | 8 +
> 14 files changed, 3410 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/drm/atmel-hlcdc-dc.txt
> create mode 100644 drivers/gpu/drm/atmel-hlcdc/Kconfig
> create mode 100644 drivers/gpu/drm/atmel-hlcdc/Makefile
> create mode 100644 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c
> create mode 100644 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c
> create mode 100644 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.h
> create mode 100644 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_layer.c
> create mode 100644 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_layer.h
> create mode 100644 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_panel.c
> create mode 100644 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c
> create mode 100644 drivers/gpu/drm/atmel_hlcdc/Kconfig
> create mode 100644 drivers/gpu/drm/atmel_hlcdc/Makefile
>
> diff --git a/Documentation/devicetree/bindings/drm/atmel-hlcdc-dc.txt
> b/Documentation/devicetree/bindings/drm/atmel-hlcdc-dc.txt
> new file mode 100644
> index 000..594bdb2
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/drm/atmel-hlcdc-dc.txt
> @@ -0,0 +1,59 @@
> +Device-Tree bindings for Atmel's HLCDC (High LCD Controller) DRM driver
> +
> +The Atmel HLCDC Display Controller is subdevice of the HLCDC MFD device.
> +See Documentation/devicetree/bindings/mfd/atmel-hlcdc.txt for more details.
> +
> +Required properties:
> + - compatible: value should be one of the following:
> + "atmel,hlcdc-dc"
> + - interrupts: the HLCDC interrupt definition
> + - pinctrl-names: the pin control state names. Should contain "default",
> + "rgb-444", "rgb-565", "rgb-666" and "rgb-888".
> + - pinctrl-[0-4]: should contain the pinctrl states described by pinctrl
> + names.
> + - atmel,panel: Should contain a phandle with 2 parameters.
> + The first cell is a phandle to a DRM panel device
> + The second cell encodes the RGB mode, which can take the following values:
> + * 0: RGB444
> + * 1: RGB565
> + * 2: RGB666
> + * 3: RGB888
> + The third cell encodes specific flags describing LCD signals configuration
> + (see Atmel's datasheet for a full description of these fields):
> + * bit 0: HSPOL: Horizontal Synchronization Pulse Polarity
> + * bit 1: VSPOL: Vertical Synchronization Pulse Polarity
> + * bit 2: VSPDLYS: Vertical Synchronization Pulse Start
> + * bit 3: VSPDLYE: Vertical Synchronization Pulse End
> + * bit 4: DISPPOL: Display Signal Polarity
> + * bit 7: DISPDLY: LCD Controller Display Power Signal Synchronization
> + * bit 12: VSPSU: LCD Controller Vertical synchronization Pulse Setup
> Configuration
> + * bit 13: VSPHO: LCD Controller Vertical synchronization Pulse Hold
> Configuration
> + * bit 16-20: GUARDTIME: LCD DISPLAY Guard Time
> +
> +Example:
> +
> + hlcdc: hlcdc at f003 {
> + compatible = "atmel,sama5d3-hlcdc";
> + reg = <0xf003 0x2000>;
> + clocks = <&lcdc_clk>, <&lcdck>, <&clk32k>;
> + clock-names = "periph_clk","sys_clk", "slow_clk";
> + status = "disabled";
> +
> + hlcdc-display-controller {
> + compatible = "atmel,hlcdc-dc";
> + interrupts = <36 IRQ_TYPE_LEVEL_HIGH 0>;
> + pinctrl-names = "default", "rgb-444", "rgb-565",
> "rgb-666", "rgb-888";
> + pinctrl-0 = <&pinctrl_lcd_base>;
> + pinctrl-1 = <&pinctrl_lcd_base &pinctrl_lcd_rgb444>;
> + pinctrl-2 = <&pinctrl_lcd_base &pinctrl_lcd_rgb565>;
> + pinctrl-3 = <&pinctrl_lcd_base &pinctrl_lcd_rgb6
[PATCH v2 3/7] drm: add Atmel HLCDC Display Controller support
The Atmel HLCDC (High LCD Controller) IP available on some Atmel SoCs (i.e.
at91sam9n12, at91sam9x5 family or sama5d3 family) provides a display
controller device.
This display controller support at least one primary plane and might
provide several overlays and an hardware cursor depending on the IP
version.
Signed-off-by: Boris BREZILLON
---
.../devicetree/bindings/drm/atmel-hlcdc-dc.txt | 59 ++
drivers/gpu/drm/Kconfig| 2 +
drivers/gpu/drm/Makefile | 1 +
drivers/gpu/drm/atmel-hlcdc/Kconfig| 11 +
drivers/gpu/drm/atmel-hlcdc/Makefile | 7 +
drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c | 529
drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c | 477 ++
drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.h | 178 ++
drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_layer.c| 701 +
drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_layer.h| 417
drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_panel.c| 351 +++
drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c| 658 +++
drivers/gpu/drm/atmel_hlcdc/Kconfig| 11 +
drivers/gpu/drm/atmel_hlcdc/Makefile | 8 +
14 files changed, 3410 insertions(+)
create mode 100644 Documentation/devicetree/bindings/drm/atmel-hlcdc-dc.txt
create mode 100644 drivers/gpu/drm/atmel-hlcdc/Kconfig
create mode 100644 drivers/gpu/drm/atmel-hlcdc/Makefile
create mode 100644 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c
create mode 100644 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c
create mode 100644 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.h
create mode 100644 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_layer.c
create mode 100644 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_layer.h
create mode 100644 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_panel.c
create mode 100644 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c
create mode 100644 drivers/gpu/drm/atmel_hlcdc/Kconfig
create mode 100644 drivers/gpu/drm/atmel_hlcdc/Makefile
diff --git a/Documentation/devicetree/bindings/drm/atmel-hlcdc-dc.txt
b/Documentation/devicetree/bindings/drm/atmel-hlcdc-dc.txt
new file mode 100644
index 000..594bdb2
--- /dev/null
+++ b/Documentation/devicetree/bindings/drm/atmel-hlcdc-dc.txt
@@ -0,0 +1,59 @@
+Device-Tree bindings for Atmel's HLCDC (High LCD Controller) DRM driver
+
+The Atmel HLCDC Display Controller is subdevice of the HLCDC MFD device.
+See Documentation/devicetree/bindings/mfd/atmel-hlcdc.txt for more details.
+
+Required properties:
+ - compatible: value should be one of the following:
+ "atmel,hlcdc-dc"
+ - interrupts: the HLCDC interrupt definition
+ - pinctrl-names: the pin control state names. Should contain "default",
+ "rgb-444", "rgb-565", "rgb-666" and "rgb-888".
+ - pinctrl-[0-4]: should contain the pinctrl states described by pinctrl
+ names.
+ - atmel,panel: Should contain a phandle with 2 parameters.
+ The first cell is a phandle to a DRM panel device
+ The second cell encodes the RGB mode, which can take the following values:
+ * 0: RGB444
+ * 1: RGB565
+ * 2: RGB666
+ * 3: RGB888
+ The third cell encodes specific flags describing LCD signals configuration
+ (see Atmel's datasheet for a full description of these fields):
+ * bit 0: HSPOL: Horizontal Synchronization Pulse Polarity
+ * bit 1: VSPOL: Vertical Synchronization Pulse Polarity
+ * bit 2: VSPDLYS: Vertical Synchronization Pulse Start
+ * bit 3: VSPDLYE: Vertical Synchronization Pulse End
+ * bit 4: DISPPOL: Display Signal Polarity
+ * bit 7: DISPDLY: LCD Controller Display Power Signal Synchronization
+ * bit 12: VSPSU: LCD Controller Vertical synchronization Pulse Setup
Configuration
+ * bit 13: VSPHO: LCD Controller Vertical synchronization Pulse Hold
Configuration
+ * bit 16-20: GUARDTIME: LCD DISPLAY Guard Time
+
+Example:
+
+ hlcdc: hlcdc at f003 {
+ compatible = "atmel,sama5d3-hlcdc";
+ reg = <0xf003 0x2000>;
+ clocks = <&lcdc_clk>, <&lcdck>, <&clk32k>;
+ clock-names = "periph_clk","sys_clk", "slow_clk";
+ status = "disabled";
+
+ hlcdc-display-controller {
+ compatible = "atmel,hlcdc-dc";
+ interrupts = <36 IRQ_TYPE_LEVEL_HIGH 0>;
+ pinctrl-names = "default", "rgb-444", "rgb-565",
"rgb-666", "rgb-888";
+ pinctrl-0 = <&pinctrl_lcd_base>;
+ pinctrl-1 = <&pinctrl_lcd_base &pinctrl_lcd_rgb444>;
+ pinctrl-2 = <&pinctrl_lcd_base &pinctrl_lcd_rgb565>;
+ pinctrl-3 = <&pinctrl_lcd_base &pinctrl_lcd_rgb666>;
+ pinctrl-4 = <&pinctrl_lcd_base &pinctrl_lcd_rgb888>;
+ };
+
+ hlcdc_pwm: hlcdc-pwm {
+ compatible = "atmel,hlcdc-pwm";
+
