Re: [PATCH v2 6/6] arm64: dts: qcom: sdm670: add display subsystem

2023-10-06 Thread Dmitry Baryshkov 

On 03/10/2023 04:21, Richard Acayan wrote:

The Snapdragon 670 has a display subsystem for controlling and
outputting to the display. Add support for it in the device tree.

Signed-off-by: Richard Acayan 
---
  arch/arm64/boot/dts/qcom/sdm670.dtsi | 294 +++
  1 file changed, 294 insertions(+)


Two minor issues below. With them fixed:

Reviewed-by: Dmitry Baryshkov 




diff --git a/arch/arm64/boot/dts/qcom/sdm670.dtsi 
b/arch/arm64/boot/dts/qcom/sdm670.dtsi
index 84cd2e39266f..427415ed4e4a 100644
--- a/arch/arm64/boot/dts/qcom/sdm670.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm670.dtsi
@@ -6,6 +6,7 @@
   * Copyright (c) 2022, Richard Acayan. All rights reserved.
   */
  
+#include 

  #include 
  #include 
  #include 
@@ -400,6 +401,30 @@ cpu6_opp10: opp-199680 {
};
};
  
+	dsi_opp_table: opp-table-dsi {

+   compatible = "operating-points-v2";
+
+   opp-1920 {
+   opp-hz = /bits/ 64 <1920>;
+   required-opps = <_opp_min_svs>;
+   };
+
+   opp-18000 {
+   opp-hz = /bits/ 64 <18000>;
+   required-opps = <_opp_low_svs>;
+   };
+
+   opp-27500 {
+   opp-hz = /bits/ 64 <27500>;
+   required-opps = <_opp_svs>;
+   };
+
+   opp-35800 {
+   opp-hz = /bits/ 64 <35800>;
+   required-opps = <_opp_svs_l1>;
+   };
+   };
+
psci {
compatible = "arm,psci-1.0";
method = "smc";
@@ -1352,6 +1377,275 @@ spmi_bus: spmi@c44 {
#interrupt-cells = <4>;
};
  
+		mdss: display-subsystem@ae0 {

+   compatible = "qcom,sdm670-mdss";
+   reg = <0 0x0ae0 0 0x1000>;
+   reg-names = "mdss";
+
+   power-domains = < MDSS_GDSC>;
+
+   clocks = < DISP_CC_MDSS_AHB_CLK>,
+< DISP_CC_MDSS_MDP_CLK>;
+   clock-names = "iface", "core";
+
+   interrupts = ;
+   interrupt-controller;
+   #interrupt-cells = <1>;
+
+   interconnects = <_noc MASTER_MDP_PORT0 0 _noc 
SLAVE_EBI_CH0 0>,
+   <_noc MASTER_MDP_PORT1 0 _noc 
SLAVE_EBI_CH0 0>;
+   interconnect-names = "mdp0-mem", "mdp1-mem";
+
+   iommus = <_smmu 0x880 0x8>,
+<_smmu 0xc80 0x8>;
+
+   status = "disabled";
+
+   #address-cells = <2>;
+   #size-cells = <2>;
+   ranges;
+
+   mdss_mdp: display-controller@ae01000 {
+   compatible = "qcom,sdm670-dpu";
+   reg = <0 0x0ae01000 0 0x8f000>,
+ <0 0x0aeb 0 0x2008>;
+   reg-names = "mdp", "vbif";
+
+   clocks = < GCC_DISP_AXI_CLK>,
+< DISP_CC_MDSS_AHB_CLK>,
+< DISP_CC_MDSS_AXI_CLK>,
+< DISP_CC_MDSS_MDP_CLK>,
+< DISP_CC_MDSS_VSYNC_CLK>;
+   clock-names = "gcc-bus", "iface", "bus", "core", 
"vsync";
+
+   assigned-clocks = < 
DISP_CC_MDSS_VSYNC_CLK>;
+   assigned-clock-rates = <1920>;
+   operating-points-v2 = <_opp_table>;
+   power-domains = < SDM670_CX>;
+
+   interrupt-parent = <>;
+   interrupts = <0>;
+
+   ports {
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   port@0 {
+   reg = <0>;
+   dpu_intf0_out: endpoint {
+   remote-endpoint = 
<_dsi0_in>;
+   };
+   };
+
+   port@1 {
+   reg = <1>;
+   dpu_intf1_out: endpoint {
+   remote-endpoint = 
<_dsi1_in>;
+   };
+   };
+   };
+
+   mdp_opp_table: opp-table {
+

[PATCH v2 6/6] arm64: dts: qcom: sdm670: add display subsystem

2023-10-02 Thread Richard Acayan 
The Snapdragon 670 has a display subsystem for controlling and
outputting to the display. Add support for it in the device tree.

Signed-off-by: Richard Acayan 
---
 arch/arm64/boot/dts/qcom/sdm670.dtsi | 294 +++
 1 file changed, 294 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/sdm670.dtsi 
b/arch/arm64/boot/dts/qcom/sdm670.dtsi
index 84cd2e39266f..427415ed4e4a 100644
--- a/arch/arm64/boot/dts/qcom/sdm670.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm670.dtsi
@@ -6,6 +6,7 @@
  * Copyright (c) 2022, Richard Acayan. All rights reserved.
  */
 
+#include 
 #include 
 #include 
 #include 
@@ -400,6 +401,30 @@ cpu6_opp10: opp-199680 {
};
};
 
+   dsi_opp_table: opp-table-dsi {
+   compatible = "operating-points-v2";
+
+   opp-1920 {
+   opp-hz = /bits/ 64 <1920>;
+   required-opps = <_opp_min_svs>;
+   };
+
+   opp-18000 {
+   opp-hz = /bits/ 64 <18000>;
+   required-opps = <_opp_low_svs>;
+   };
+
+   opp-27500 {
+   opp-hz = /bits/ 64 <27500>;
+   required-opps = <_opp_svs>;
+   };
+
+   opp-35800 {
+   opp-hz = /bits/ 64 <35800>;
+   required-opps = <_opp_svs_l1>;
+   };
+   };
+
psci {
compatible = "arm,psci-1.0";
method = "smc";
@@ -1352,6 +1377,275 @@ spmi_bus: spmi@c44 {
#interrupt-cells = <4>;
};
 
+   mdss: display-subsystem@ae0 {
+   compatible = "qcom,sdm670-mdss";
+   reg = <0 0x0ae0 0 0x1000>;
+   reg-names = "mdss";
+
+   power-domains = < MDSS_GDSC>;
+
+   clocks = < DISP_CC_MDSS_AHB_CLK>,
+< DISP_CC_MDSS_MDP_CLK>;
+   clock-names = "iface", "core";
+
+   interrupts = ;
+   interrupt-controller;
+   #interrupt-cells = <1>;
+
+   interconnects = <_noc MASTER_MDP_PORT0 0 _noc 
SLAVE_EBI_CH0 0>,
+   <_noc MASTER_MDP_PORT1 0 _noc 
SLAVE_EBI_CH0 0>;
+   interconnect-names = "mdp0-mem", "mdp1-mem";
+
+   iommus = <_smmu 0x880 0x8>,
+<_smmu 0xc80 0x8>;
+
+   status = "disabled";
+
+   #address-cells = <2>;
+   #size-cells = <2>;
+   ranges;
+
+   mdss_mdp: display-controller@ae01000 {
+   compatible = "qcom,sdm670-dpu";
+   reg = <0 0x0ae01000 0 0x8f000>,
+ <0 0x0aeb 0 0x2008>;
+   reg-names = "mdp", "vbif";
+
+   clocks = < GCC_DISP_AXI_CLK>,
+< DISP_CC_MDSS_AHB_CLK>,
+< DISP_CC_MDSS_AXI_CLK>,
+< DISP_CC_MDSS_MDP_CLK>,
+< DISP_CC_MDSS_VSYNC_CLK>;
+   clock-names = "gcc-bus", "iface", "bus", 
"core", "vsync";
+
+   assigned-clocks = < 
DISP_CC_MDSS_VSYNC_CLK>;
+   assigned-clock-rates = <1920>;
+   operating-points-v2 = <_opp_table>;
+   power-domains = < SDM670_CX>;
+
+   interrupt-parent = <>;
+   interrupts = <0>;
+
+   ports {
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   port@0 {
+   reg = <0>;
+   dpu_intf0_out: endpoint {
+   remote-endpoint = 
<_dsi0_in>;
+   };
+   };
+
+   port@1 {
+   reg = <1>;
+   dpu_intf1_out: endpoint {
+   remote-endpoint = 
<_dsi1_in>;
+   };
+   };
+   };
+
+   mdp_opp_table: opp-table {
+   compatible = "operating-points-v2";
+
+