[PATCH v2 6/8] ARM: dts: sun6i: Add device nodes for first display pipeline

[Maxime Ripard]

On Thu, Oct 20, 2016 at 11:43:42AM +0800, Chen-Yu Tsai wrote:
> The A31 has 2 parallel display pipelines, which can be intermixed.
> However the driver currently only supports one of them.
> 
> Signed-off-by: Chen-Yu Tsai 

Applied, thanks!
Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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[PATCH v2 6/8] ARM: dts: sun6i: Add device nodes for first display pipeline

[Chen-Yu Tsai]

The A31 has 2 parallel display pipelines, which can be intermixed.
However the driver currently only supports one of them.

Signed-off-by: Chen-Yu Tsai 
---
 arch/arm/boot/dts/sun6i-a31.dtsi  | 152 ++
 arch/arm/boot/dts/sun6i-a31s.dtsi |   8 ++
 2 files changed, 160 insertions(+)

diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi
index c1b891e75f18..4d2c7786b92a 100644
--- a/arch/arm/boot/dts/sun6i-a31.dtsi
+++ b/arch/arm/boot/dts/sun6i-a31.dtsi
@@ -231,6 +231,11 @@
};
};

+   de: display-engine {
+   compatible = "allwinner,sun6i-a31-display-engine";
+   allwinner,pipelines = <>;
+   };
+
soc at 01c0 {
compatible = "simple-bus";
#address-cells = <1>;
@@ -246,6 +251,44 @@
#dma-cells = <1>;
};

+   tcon0: lcd-controller at 01c0c000 {
+   compatible = "allwinner,sun6i-a31-tcon";
+   reg = <0x01c0c000 0x1000>;
+   interrupts = ;
+   resets = < RST_AHB1_LCD0>;
+   reset-names = "lcd";
+   clocks = < CLK_AHB1_LCD0>,
+< CLK_LCD0_CH0>,
+< CLK_LCD0_CH1>;
+   clock-names = "ahb",
+ "tcon-ch0",
+ "tcon-ch1";
+   clock-output-names = "tcon0-pixel-clock";
+   status = "disabled";
+
+   ports {
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   tcon0_in: port at 0 {
+   #address-cells = <1>;
+   #size-cells = <0>;
+   reg = <0>;
+
+   tcon0_in_drc0: endpoint at 0 {
+   reg = <0>;
+   remote-endpoint = 
<_out_tcon0>;
+   };
+   };
+
+   tcon0_out: port at 1 {
+   #address-cells = <1>;
+   #size-cells = <0>;
+   reg = <1>;
+   };
+   };
+   };
+
mmc0: mmc at 01c0f000 {
compatible = "allwinner,sun7i-a20-mmc";
reg = <0x01c0f000 0x1000>;
@@ -799,6 +842,115 @@
interrupts = ;
};

+   fe0: display-frontend at 01e0 {
+   compatible = "allwinner,sun6i-a31-display-frontend";
+   reg = <0x01e0 0x2>;
+   interrupts = ;
+   clocks = < CLK_AHB1_FE0>, < CLK_FE0>,
+< CLK_DRAM_FE0>;
+   clock-names = "ahb", "mod",
+ "ram";
+   resets = < RST_AHB1_FE0>;
+
+   ports {
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   fe0_out: port at 1 {
+   #address-cells = <1>;
+   #size-cells = <0>;
+   reg = <1>;
+
+   fe0_out_be0: endpoint at 0 {
+   reg = <0>;
+   remote-endpoint = <_in_fe0>;
+   };
+   };
+   };
+   };
+
+   be0: display-backend at 01e6 {
+   compatible = "allwinner,sun6i-a31-display-backend";
+   reg = <0x01e6 0x1>;
+   interrupts = ;
+   clocks = < CLK_AHB1_BE0>, < CLK_BE0>,
+< CLK_DRAM_BE0>;
+   clock-names = "ahb", "mod",
+ "ram";
+   resets = < RST_AHB1_BE0>;
+
+   assigned-clocks = < CLK_BE0>;
+   assigned-clock-rates = <3>;
+
+   ports {
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   be0_in: port at 0 {
+   #address-cells = <1>;
+   #size-cells = <0>;
+   reg = <0>;
+
+