Re: [PATCH v3, 03/15] arm64: dts: mt8192: add display node

2021-01-11 Thread Chun-Kuang Hu 
Hi, Yongqiang:

Yongqiang Niu  於 2021年1月11日 週一 下午3:48寫道：
>
> add display node
>
> Signed-off-by: Yongqiang Niu 
> ---
>  arch/arm64/boot/dts/mediatek/mt8192.dtsi | 134 
> +++
>  1 file changed, 134 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi 
> b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> index e12e024..dcf9fdf 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> @@ -15,6 +15,11 @@
> #address-cells = <2>;
> #size-cells = <2>;
>
> +   aliases {
> +   ovl2-2l2 = _2l2;
> +   rdma4 = 
> +   };
> +
> clk26m: oscillator0 {
> compatible = "fixed-clock";
> #clock-cells = <0>;
> @@ -508,5 +513,134 @@
> #size-cells = <0>;
> status = "disabled";
> };
> +
> +   mmsys: syscon@1400 {
> +   compatible = "mediatek,mt8192-mmsys", "syscon";
> +   reg = <0 0x1400 0 0x1000>;
> +   //mboxes = < 0 CMDQ_THR_PRIO_HIGHEST 1>,
> +   //   < 1 CMDQ_THR_PRIO_HIGHEST 1>;
> +   //mediatek,gce-client-reg = < SUBSYS_1400 0 
> 0x1000>;
> +   #clock-cells = <1>;
> +   };
> +
> +mutex: mutex@14001000 {
> +   compatible = "mediatek,mt8192-disp-mutex";
> +   reg = <0 0x14001000 0 0x1000>;
> +   interrupts = ;
> +   //clocks = < CLK_MM_DISP_MUTEX0>;
> +   //mediatek,gce-events = 
> ,
> +   //
> ;
> +   };
> +
> +   ovl0: ovl@14005000 {
> +   compatible = "mediatek,mt8192-disp-ovl";
> +   reg = <0 0x14005000 0 0x1000>;
> +   interrupts = ;
> +   //clocks = < CLK_MM_DISP_OVL0>;
> +   //iommus = < M4U_PORT_L0_OVL_RDMA0>;
> +   //power-domains = < MT8192_POWER_DOMAIN_DISP>;

I think you should not mark these property.

Regards,
Chun-Kuang.

> +   //mediatek,gce-client-reg = < SUBSYS_1400 
> 0x5000 0x1000>;
> +   };
> +
> +   ovl_2l0: ovl@14006000 {
> +   compatible = "mediatek,mt8192-disp-ovl-2l";
> +   reg = <0 0x14006000 0 0x1000>;
> +   interrupts = ;
> +   //power-domains = < MT8192_POWER_DOMAIN_DISP>;
> +   //clocks = < CLK_MM_DISP_OVL0_2L>;
> +   //iommus = < M4U_PORT_L1_OVL_2L_RDMA0>;
> +   //mediatek,gce-client-reg = < SUBSYS_1400 
> 0x6000 0x1000>;
> +   };
> +
> +   rdma0: rdma@14007000 {
> +   compatible = "mediatek,mt8192-disp-rdma";
> +   reg = <0 0x14007000 0 0x1000>;
> +   interrupts = ;
> +   //clocks = < CLK_MM_DISP_RDMA0>;
> +   //iommus = < M4U_PORT_L0_DISP_RDMA0>;
> +   //mediatek,larb = <>;
> +   //mediatek,rdma-fifo-size = <5120>;
> +   //power-domains = < MT8192_POWER_DOMAIN_DISP>;
> +   //mediatek,gce-client-reg = < SUBSYS_1400 
> 0x7000 0x1000>;
> +   };
> +
> +   color0: color@14009000 {
> +   compatible = "mediatek,mt8192-disp-color",
> +"mediatek,mt8173-disp-color";
> +   reg = <0 0x14009000 0 0x1000>;
> +   interrupts = ;
> +   //power-domains = < MT8192_POWER_DOMAIN_DISP>;
> +   //clocks = < CLK_MM_DISP_COLOR0>;
> +   //mediatek,gce-client-reg = < SUBSYS_1400 
> 0x9000 0x1000>;
> +   };
> +
> +   ccorr0: ccorr@1400a000 {
> +   compatible = "mediatek,mt8192-disp-ccorr";
> +   reg = <0 0x1400a000 0 0x1000>;
> +   interrupts = ;
> +   //power-domains = < MT8192_POWER_DOMAIN_DISP>;
> +   //clocks = < CLK_MM_DISP_CCORR0>;
> +   //mediatek,gce-client-reg = < SUBSYS_1400 
> 0xa000 0x1000>;
> +   };
> +
> +   aal0: aal@1400b000 {
> +   compatible = "mediatek,mt8192-disp-aal";
> +   reg = <0 0x1400b000 0 0x1000>;
> +   interrupts = ;
> +   //power-domains = < MT8192_POWER_DOMAIN_DISP>;
> +   //clocks = < CLK_MM_DISP_AAL0>;
> +   //mediatek,gce-client-reg = < SUBSYS_1400 
> 0xb000 0x1000>;
> +   };
> +
> +   gamma0: gamma@1400c000 {

[PATCH v3, 03/15] arm64: dts: mt8192: add display node

2021-01-11 Thread Yongqiang Niu 
add display node

Signed-off-by: Yongqiang Niu 
---
 arch/arm64/boot/dts/mediatek/mt8192.dtsi | 134 +++
 1 file changed, 134 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi 
b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index e12e024..dcf9fdf 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -15,6 +15,11 @@
#address-cells = <2>;
#size-cells = <2>;
 
+   aliases {
+   ovl2-2l2 = _2l2;
+   rdma4 = 
+   };
+
clk26m: oscillator0 {
compatible = "fixed-clock";
#clock-cells = <0>;
@@ -508,5 +513,134 @@
#size-cells = <0>;
status = "disabled";
};
+   
+   mmsys: syscon@1400 {
+   compatible = "mediatek,mt8192-mmsys", "syscon";
+   reg = <0 0x1400 0 0x1000>;
+   //mboxes = < 0 CMDQ_THR_PRIO_HIGHEST 1>,
+   //   < 1 CMDQ_THR_PRIO_HIGHEST 1>;
+   //mediatek,gce-client-reg = < SUBSYS_1400 0 
0x1000>;
+   #clock-cells = <1>;
+   };
+
+mutex: mutex@14001000 {
+   compatible = "mediatek,mt8192-disp-mutex";
+   reg = <0 0x14001000 0 0x1000>;
+   interrupts = ;
+   //clocks = < CLK_MM_DISP_MUTEX0>;
+   //mediatek,gce-events = 
,
+   //
;
+   };
+
+   ovl0: ovl@14005000 {
+   compatible = "mediatek,mt8192-disp-ovl";
+   reg = <0 0x14005000 0 0x1000>;
+   interrupts = ;
+   //clocks = < CLK_MM_DISP_OVL0>;
+   //iommus = < M4U_PORT_L0_OVL_RDMA0>;
+   //power-domains = < MT8192_POWER_DOMAIN_DISP>;
+   //mediatek,gce-client-reg = < SUBSYS_1400 
0x5000 0x1000>;
+   };
+
+   ovl_2l0: ovl@14006000 {
+   compatible = "mediatek,mt8192-disp-ovl-2l";
+   reg = <0 0x14006000 0 0x1000>;
+   interrupts = ;
+   //power-domains = < MT8192_POWER_DOMAIN_DISP>;
+   //clocks = < CLK_MM_DISP_OVL0_2L>;
+   //iommus = < M4U_PORT_L1_OVL_2L_RDMA0>;
+   //mediatek,gce-client-reg = < SUBSYS_1400 
0x6000 0x1000>;
+   };
+
+   rdma0: rdma@14007000 {
+   compatible = "mediatek,mt8192-disp-rdma";
+   reg = <0 0x14007000 0 0x1000>;
+   interrupts = ;
+   //clocks = < CLK_MM_DISP_RDMA0>;
+   //iommus = < M4U_PORT_L0_DISP_RDMA0>;
+   //mediatek,larb = <>;
+   //mediatek,rdma-fifo-size = <5120>;
+   //power-domains = < MT8192_POWER_DOMAIN_DISP>;
+   //mediatek,gce-client-reg = < SUBSYS_1400 
0x7000 0x1000>;
+   };
+
+   color0: color@14009000 {
+   compatible = "mediatek,mt8192-disp-color",
+"mediatek,mt8173-disp-color";
+   reg = <0 0x14009000 0 0x1000>;
+   interrupts = ;
+   //power-domains = < MT8192_POWER_DOMAIN_DISP>;
+   //clocks = < CLK_MM_DISP_COLOR0>;
+   //mediatek,gce-client-reg = < SUBSYS_1400 
0x9000 0x1000>;
+   };
+
+   ccorr0: ccorr@1400a000 {
+   compatible = "mediatek,mt8192-disp-ccorr";
+   reg = <0 0x1400a000 0 0x1000>;
+   interrupts = ;
+   //power-domains = < MT8192_POWER_DOMAIN_DISP>;
+   //clocks = < CLK_MM_DISP_CCORR0>;
+   //mediatek,gce-client-reg = < SUBSYS_1400 
0xa000 0x1000>;
+   };
+
+   aal0: aal@1400b000 {
+   compatible = "mediatek,mt8192-disp-aal";
+   reg = <0 0x1400b000 0 0x1000>;
+   interrupts = ;
+   //power-domains = < MT8192_POWER_DOMAIN_DISP>;
+   //clocks = < CLK_MM_DISP_AAL0>;
+   //mediatek,gce-client-reg = < SUBSYS_1400 
0xb000 0x1000>;
+   };
+
+   gamma0: gamma@1400c000 {
+   compatible = "mediatek,mt8183-disp-gamma",
+"mediatek,mt8192-disp-gamma";
+   reg = <0 0x1400c000 0 0x1000>;
+   interrupts = ;
+   //power-domains = < MT8192_POWER_DOMAIN_DISP>;
+   //clocks = <