Re: [PATCH v3 05/12] dt-bindings: display/msm: Add SM6375 MDSS

2023-05-15 Thread Konrad Dybcio 



On 7.05.2023 10:20, Krzysztof Kozlowski wrote:
> On 05/05/2023 23:40, Konrad Dybcio wrote:
>> Document the SM6375 MDSS.
>>
>> Signed-off-by: Konrad Dybcio 
>> ---
>>  .../bindings/display/msm/qcom,sm6375-mdss.yaml | 216 
>> +
>>  1 file changed, 216 insertions(+)
>>
> 
> Thank you for your patch. There is something to discuss/improve.
> 
>> +
>> +examples:
>> +  - |
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +
>> +display-subsystem@5e0 {
>> +compatible = "qcom,sm6375-mdss";
>> +reg = <0x05e0 0x1000>;
>> +reg-names = "mdss";
>> +
>> +power-domains = < MDSS_GDSC>;
>> +
>> +clocks = < GCC_DISP_AHB_CLK>,
>> + < DISP_CC_MDSS_AHB_CLK>,
>> + < DISP_CC_MDSS_MDP_CLK>;
>> +clock-names = "iface", "ahb", "core";
>> +
>> +interrupts = ;
>> +interrupt-controller;
>> +#interrupt-cells = <1>;
>> +
>> +iommus = <_smmu 0x820 0x2>;
>> +#address-cells = <1>;
>> +#size-cells = <1>;
>> +ranges;
>> +
>> +display-controller@5e01000 {
>> +compatible = "qcom,sm6375-dpu";
>> +reg = <0x05e01000 0x8e030>,
>> +  <0x05eb 0x2008>;
>> +reg-names = "mdp", "vbif";
>> +
>> +clocks = < DISP_CC_MDSS_AHB_CLK>,
>> + < GCC_DISP_HF_AXI_CLK>,
>> + < DISP_CC_MDSS_MDP_CLK>,
>> + < DISP_CC_MDSS_MDP_LUT_CLK>,
>> + < DISP_CC_MDSS_ROT_CLK>,
>> + < DISP_CC_MDSS_VSYNC_CLK>,
>> + < GCC_DISP_THROTTLE_CORE_CLK>;
>> +clock-names = "iface",
>> +  "bus",
>> +  "core",
>> +  "lut",
>> +  "rot",
>> +  "vsync",
>> +  "throttle";
> 
> Are you sure you have clocks in correct order? I see warnings...
Right, testing *both* the DTs and bindings after making changes sounds
like a good thing to stop forgetting..

Konrad
> 
> Best regards,
> Krzysztof
>

Re: [PATCH v3 05/12] dt-bindings: display/msm: Add SM6375 MDSS

2023-05-07 Thread Krzysztof Kozlowski 
On 05/05/2023 23:40, Konrad Dybcio wrote:
> Document the SM6375 MDSS.
> 
> Signed-off-by: Konrad Dybcio 
> ---
>  .../bindings/display/msm/qcom,sm6375-mdss.yaml | 216 
> +
>  1 file changed, 216 insertions(+)
> 

Thank you for your patch. There is something to discuss/improve.

> +
> +examples:
> +  - |
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +
> +display-subsystem@5e0 {
> +compatible = "qcom,sm6375-mdss";
> +reg = <0x05e0 0x1000>;
> +reg-names = "mdss";
> +
> +power-domains = < MDSS_GDSC>;
> +
> +clocks = < GCC_DISP_AHB_CLK>,
> + < DISP_CC_MDSS_AHB_CLK>,
> + < DISP_CC_MDSS_MDP_CLK>;
> +clock-names = "iface", "ahb", "core";
> +
> +interrupts = ;
> +interrupt-controller;
> +#interrupt-cells = <1>;
> +
> +iommus = <_smmu 0x820 0x2>;
> +#address-cells = <1>;
> +#size-cells = <1>;
> +ranges;
> +
> +display-controller@5e01000 {
> +compatible = "qcom,sm6375-dpu";
> +reg = <0x05e01000 0x8e030>,
> +  <0x05eb 0x2008>;
> +reg-names = "mdp", "vbif";
> +
> +clocks = < DISP_CC_MDSS_AHB_CLK>,
> + < GCC_DISP_HF_AXI_CLK>,
> + < DISP_CC_MDSS_MDP_CLK>,
> + < DISP_CC_MDSS_MDP_LUT_CLK>,
> + < DISP_CC_MDSS_ROT_CLK>,
> + < DISP_CC_MDSS_VSYNC_CLK>,
> + < GCC_DISP_THROTTLE_CORE_CLK>;
> +clock-names = "iface",
> +  "bus",
> +  "core",
> +  "lut",
> +  "rot",
> +  "vsync",
> +  "throttle";

Are you sure you have clocks in correct order? I see warnings...

Best regards,
Krzysztof

Re: [PATCH v3 05/12] dt-bindings: display/msm: Add SM6375 MDSS

2023-05-05 Thread Rob Herring 


On Fri, 05 May 2023 23:40:31 +0200, Konrad Dybcio wrote:
> Document the SM6375 MDSS.
> 
> Signed-off-by: Konrad Dybcio 
> ---
>  .../bindings/display/msm/qcom,sm6375-mdss.yaml | 216 
> +
>  1 file changed, 216 insertions(+)
> 

My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
on your patch (DT_CHECKER_FLAGS is new in v5.13):

yamllint warnings/errors:

dtschema/dtc warnings/errors:
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/display/msm/qcom,sm6375-mdss.example.dtb:
 dsi@5e94000: compatible: 'oneOf' conditional failed, one must be fixed:
'qcom,sm6375-dsi-ctrl' is not one of ['qcom,apq8064-dsi-ctrl', 
'qcom,msm8916-dsi-ctrl', 'qcom,msm8953-dsi-ctrl', 'qcom,msm8974-dsi-ctrl', 
'qcom,msm8996-dsi-ctrl', 'qcom,msm8998-dsi-ctrl', 'qcom,qcm2290-dsi-ctrl', 
'qcom,sc7180-dsi-ctrl', 'qcom,sc7280-dsi-ctrl', 'qcom,sdm660-dsi-ctrl', 
'qcom,sdm845-dsi-ctrl', 'qcom,sm8150-dsi-ctrl', 'qcom,sm8250-dsi-ctrl', 
'qcom,sm8350-dsi-ctrl', 'qcom,sm8450-dsi-ctrl', 'qcom,sm8550-dsi-ctrl']
'qcom,sm6375-dsi-ctrl' is not one of ['dsi-ctrl-6g-qcm2290']
From schema: 
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/display/msm/qcom,sm6375-mdss.example.dtb:
 dsi@5e94000: Unevaluated properties are not allowed ('compatible' was 
unexpected)
From schema: 
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml

doc reference errors (make refcheckdocs):

See 
https://patchwork.ozlabs.org/project/devicetree-bindings/patch/20230411-topic-straitlagoon_mdss-v3-5-9837d6b35...@linaro.org

The base for the series is generally the latest rc1. A different dependency
should be noted in *this* patch.

If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:

pip3 install dtschema --upgrade

Please check and re-submit after running the above command yourself. Note
that DT_SCHEMA_FILES can be set to your schema file to speed up checking
your schema. However, it must be unset to test all examples with your schema.

[PATCH v3 05/12] dt-bindings: display/msm: Add SM6375 MDSS

2023-05-05 Thread Konrad Dybcio 
Document the SM6375 MDSS.

Signed-off-by: Konrad Dybcio 
---
 .../bindings/display/msm/qcom,sm6375-mdss.yaml | 216 +
 1 file changed, 216 insertions(+)

diff --git 
a/Documentation/devicetree/bindings/display/msm/qcom,sm6375-mdss.yaml 
b/Documentation/devicetree/bindings/display/msm/qcom,sm6375-mdss.yaml
new file mode 100644
index ..fb56971ea2a1
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/msm/qcom,sm6375-mdss.yaml
@@ -0,0 +1,216 @@
+# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/msm/qcom,sm6375-mdss.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm SM6375 Display MDSS
+
+maintainers:
+  - Konrad Dybcio 
+
+description:
+  SM6375 MSM Mobile Display Subsystem (MDSS), which encapsulates sub-blocks
+  like DPU display controller, DSI and DP interfaces etc.
+
+$ref: /schemas/display/msm/mdss-common.yaml#
+
+properties:
+  compatible:
+items:
+  - const: qcom,sm6375-mdss
+
+  clocks:
+items:
+  - description: Display AHB clock from gcc
+  - description: Display AHB clock
+  - description: Display core clock
+
+  clock-names:
+items:
+  - const: iface
+  - const: ahb
+  - const: core
+
+  iommus:
+maxItems: 1
+
+  interconnects:
+maxItems: 2
+
+  interconnect-names:
+maxItems: 2
+
+patternProperties:
+  "^display-controller@[0-9a-f]+$":
+type: object
+properties:
+  compatible:
+const: qcom,sm6375-dpu
+
+  "^dsi@[0-9a-f]+$":
+type: object
+properties:
+  compatible:
+items:
+  - const: qcom,sm6375-dsi-ctrl
+  - const: qcom,mdss-dsi-ctrl
+
+  "^phy@[0-9a-f]+$":
+type: object
+properties:
+  compatible:
+const: qcom,sm6375-dsi-phy-7nm
+
+unevaluatedProperties: false
+
+examples:
+  - |
+#include 
+#include 
+#include 
+#include 
+#include 
+
+display-subsystem@5e0 {
+compatible = "qcom,sm6375-mdss";
+reg = <0x05e0 0x1000>;
+reg-names = "mdss";
+
+power-domains = < MDSS_GDSC>;
+
+clocks = < GCC_DISP_AHB_CLK>,
+ < DISP_CC_MDSS_AHB_CLK>,
+ < DISP_CC_MDSS_MDP_CLK>;
+clock-names = "iface", "ahb", "core";
+
+interrupts = ;
+interrupt-controller;
+#interrupt-cells = <1>;
+
+iommus = <_smmu 0x820 0x2>;
+#address-cells = <1>;
+#size-cells = <1>;
+ranges;
+
+display-controller@5e01000 {
+compatible = "qcom,sm6375-dpu";
+reg = <0x05e01000 0x8e030>,
+  <0x05eb 0x2008>;
+reg-names = "mdp", "vbif";
+
+clocks = < DISP_CC_MDSS_AHB_CLK>,
+ < GCC_DISP_HF_AXI_CLK>,
+ < DISP_CC_MDSS_MDP_CLK>,
+ < DISP_CC_MDSS_MDP_LUT_CLK>,
+ < DISP_CC_MDSS_ROT_CLK>,
+ < DISP_CC_MDSS_VSYNC_CLK>,
+ < GCC_DISP_THROTTLE_CORE_CLK>;
+clock-names = "iface",
+  "bus",
+  "core",
+  "lut",
+  "rot",
+  "vsync",
+  "throttle";
+
+assigned-clocks = < DISP_CC_MDSS_VSYNC_CLK>;
+assigned-clock-rates = <1920>;
+
+operating-points-v2 = <_opp_table>;
+power-domains = < SM6375_VDDCX>;
+
+interrupt-parent = <>;
+interrupts = <0>;
+
+ports {
+#address-cells = <1>;
+#size-cells = <0>;
+
+port@0 {
+reg = <0>;
+dpu_intf1_out: endpoint {
+remote-endpoint = <_in>;
+};
+};
+
+port@1 {
+reg = <1>;
+dpu_intf2_out: endpoint {
+remote-endpoint = <_in>;
+};
+};
+};
+};
+
+dsi@5e94000 {
+compatible = "qcom,sm6375-dsi-ctrl", "qcom,mdss-dsi-ctrl";
+reg = <0x05e94000 0x400>;
+reg-names = "dsi_ctrl";
+
+interrupt-parent = <>;
+interrupts = <4>;
+
+clocks = < DISP_CC_MDSS_BYTE0_CLK>,
+ < DISP_CC_MDSS_BYTE0_INTF_CLK>,
+ < DISP_CC_MDSS_PCLK0_CLK>,
+ < DISP_CC_MDSS_ESC0_CLK>,
+ < DISP_CC_MDSS_AHB_CLK>,
+ < GCC_DISP_HF_AXI_CLK>;
+clock-names = "byte",
+  "byte_intf",
+  "pixel",
+  "core",
+  "iface",
+  "bus";
+
+assigned-clocks = < DISP_CC_MDSS_BYTE0_CLK_SRC>,
+  <