Re: [PATCH v3 09/11] clk: sunxi-ng: add support for Allwinner A64 DE2 CCU

[Maxime Ripard]

On Fri, Dec 22, 2017 at 08:22:41PM +0800, Icenowy Zheng wrote:
> Allwinner A64's DE2 needs to claim a section of SRAM (SRAM C) to work.
> 
> Add support for it.

That's highly suspicious that the clocks need an SRAM to operate
properly.

Can you elaborate?

Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com


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Re: [PATCH v3 09/11] clk: sunxi-ng: add support for Allwinner A64 DE2 CCU

[Chen-Yu Tsai]

On Fri, Dec 22, 2017 at 8:22 PM, Icenowy Zheng  wrote:
> Allwinner A64's DE2 needs to claim a section of SRAM (SRAM C) to work.
>
> Add support for it.
>
> Signed-off-by: Icenowy Zheng 
> ---
>  drivers/clk/sunxi-ng/ccu-sun8i-de2.c | 32 
>  1 file changed, 24 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-de2.c 
> b/drivers/clk/sunxi-ng/ccu-sun8i-de2.c
> index 468d1abaf0ee..38b029b7bb5a 100644
> --- a/drivers/clk/sunxi-ng/ccu-sun8i-de2.c
> +++ b/drivers/clk/sunxi-ng/ccu-sun8i-de2.c
> @@ -17,6 +17,7 @@
>  #include 
>  #include 
>  #include 
> +#include 
>
>  #include "ccu_common.h"
>  #include "ccu_div.h"
> @@ -196,6 +197,11 @@ static const struct sunxi_ccu_desc 
> sun8i_v3s_de2_clk_desc = {
> .num_resets = ARRAY_SIZE(sun8i_a83t_de2_resets),
>  };
>
> +static bool sunxi_de2_clk_has_sram(const struct device_node *node)
> +{
> +   return of_device_is_compatible(node, "allwinner,sun50i-a64-de2-clk");

Having to maintain a separate list is not a great idea. Please consider
adding a de2 ccu specific structure that embeds a struct sunxi_ccu_desc,
and also includes whatever special quirks flags this needs.

ChenYu

> +}
> +
>  static int sunxi_de2_clk_probe(struct platform_device *pdev)
>  {
> struct resource *res;
> @@ -239,11 +245,20 @@ static int sunxi_de2_clk_probe(struct platform_device 
> *pdev)
> return ret;
> }
>
> +   if (sunxi_de2_clk_has_sram(pdev->dev.of_node)) {
> +   ret = sunxi_sram_claim(>dev);
> +   if (ret) {
> +   dev_err(>dev,
> +   "Error couldn't map SRAM to device\n");
> +   return ret;
> +   }
> +   }
> +
> /* The clocks need to be enabled for us to access the registers */
> ret = clk_prepare_enable(bus_clk);
> if (ret) {
> dev_err(>dev, "Couldn't enable bus clk: %d\n", ret);
> -   return ret;
> +   goto err_release_sram;
> }
>
> ret = clk_prepare_enable(mod_clk);
> @@ -272,6 +287,10 @@ static int sunxi_de2_clk_probe(struct platform_device 
> *pdev)
> clk_disable_unprepare(mod_clk);
>  err_disable_bus_clk:
> clk_disable_unprepare(bus_clk);
> +err_release_sram:
> +   if (sunxi_de2_clk_has_sram(pdev->dev.of_node))
> +   sunxi_sram_release(>dev);
> +
> return ret;
>  }
>
> @@ -288,17 +307,14 @@ static const struct of_device_id sunxi_de2_clk_ids[] = {
> .compatible = "allwinner,sun8i-v3s-de2-clk",
> .data = _v3s_de2_clk_desc,
> },
> +   {
> +   .compatible = "allwinner,sun50i-a64-de2-clk",
> +   .data = _a64_de2_clk_desc,
> +   },
> {
> .compatible = "allwinner,sun50i-h5-de2-clk",
> .data = _a64_de2_clk_desc,
> },
> -   /*
> -* The Allwinner A64 SoC needs some bit to be poke in syscon to make
> -* DE2 really working.
> -* So there's currently no A64 compatible here.
> -* H5 shares the same reset line with A64, so here H5 is using the
> -* clock description of A64.
> -*/
> { }
>  };
>
> --
> 2.14.2
>
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[PATCH v3 09/11] clk: sunxi-ng: add support for Allwinner A64 DE2 CCU

[Icenowy Zheng]

Allwinner A64's DE2 needs to claim a section of SRAM (SRAM C) to work.

Add support for it.

Signed-off-by: Icenowy Zheng 
---
 drivers/clk/sunxi-ng/ccu-sun8i-de2.c | 32 
 1 file changed, 24 insertions(+), 8 deletions(-)

diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-de2.c 
b/drivers/clk/sunxi-ng/ccu-sun8i-de2.c
index 468d1abaf0ee..38b029b7bb5a 100644
--- a/drivers/clk/sunxi-ng/ccu-sun8i-de2.c
+++ b/drivers/clk/sunxi-ng/ccu-sun8i-de2.c
@@ -17,6 +17,7 @@
 #include 
 #include 
 #include 
+#include 
 
 #include "ccu_common.h"
 #include "ccu_div.h"
@@ -196,6 +197,11 @@ static const struct sunxi_ccu_desc sun8i_v3s_de2_clk_desc 
= {
.num_resets = ARRAY_SIZE(sun8i_a83t_de2_resets),
 };
 
+static bool sunxi_de2_clk_has_sram(const struct device_node *node)
+{
+   return of_device_is_compatible(node, "allwinner,sun50i-a64-de2-clk");
+}
+
 static int sunxi_de2_clk_probe(struct platform_device *pdev)
 {
struct resource *res;
@@ -239,11 +245,20 @@ static int sunxi_de2_clk_probe(struct platform_device 
*pdev)
return ret;
}
 
+   if (sunxi_de2_clk_has_sram(pdev->dev.of_node)) {
+   ret = sunxi_sram_claim(>dev);
+   if (ret) {
+   dev_err(>dev,
+   "Error couldn't map SRAM to device\n");
+   return ret;
+   }
+   }
+
/* The clocks need to be enabled for us to access the registers */
ret = clk_prepare_enable(bus_clk);
if (ret) {
dev_err(>dev, "Couldn't enable bus clk: %d\n", ret);
-   return ret;
+   goto err_release_sram;
}
 
ret = clk_prepare_enable(mod_clk);
@@ -272,6 +287,10 @@ static int sunxi_de2_clk_probe(struct platform_device 
*pdev)
clk_disable_unprepare(mod_clk);
 err_disable_bus_clk:
clk_disable_unprepare(bus_clk);
+err_release_sram:
+   if (sunxi_de2_clk_has_sram(pdev->dev.of_node))
+   sunxi_sram_release(>dev);
+
return ret;
 }
 
@@ -288,17 +307,14 @@ static const struct of_device_id sunxi_de2_clk_ids[] = {
.compatible = "allwinner,sun8i-v3s-de2-clk",
.data = _v3s_de2_clk_desc,
},
+   {
+   .compatible = "allwinner,sun50i-a64-de2-clk",
+   .data = _a64_de2_clk_desc,
+   },
{
.compatible = "allwinner,sun50i-h5-de2-clk",
.data = _a64_de2_clk_desc,
},
-   /*
-* The Allwinner A64 SoC needs some bit to be poke in syscon to make
-* DE2 really working.
-* So there's currently no A64 compatible here.
-* H5 shares the same reset line with A64, so here H5 is using the
-* clock description of A64.
-*/
{ }
 };
 
-- 
2.14.2

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