Re: [PATCH v4 1/2] drm/i915/jsl: Split EHL/JSL platform info and PCI ids
On Mon, Oct 05, 2020 at 10:54:49PM +0530, Tejas Upadhyay wrote: > Split the basic platform definition, macros, and PCI IDs to > differentiate between EHL and JSL platforms. > > Changes since V3 : > - Changed IS_EHL_JSL to IS_JSL_EHL A grep of drm/i915 after applying this patch still shows instances of IS_ELKHARTLAKE in the driver that haven't been converted. Some of those are in the intel_ddi code that you'll be updating in the next patch, but we should still switch all instances over to the new macro name in this patch and leave the behavioral changes to vswing programming for the next patch, otherwise we'll have problems bisecting the driver properly. > - Renamed IS_EHL_REVID to IS_JSL_EHL_REVID > - Reverted removal of IS_ELKHARTLAKE and also > added IS_JASPERLAKE As I just mentioned on a different reply, I don't think we want this last change. The entire driver with the exception of the vswing code (and I guess drm_WARN()'s we have for PCH check) should always be using IS_JSL_EHL() everywhere. If we add these macros, it will just increase the chances that someone will accidentally use them elsewhere in the driver and introduce subtle bugs. > > Changes since V2 : > - Added IS_EHL_JSL to replace IS_ELKHARTLAKE > - EHL/JSL PCI ids split added > > Changes since V1 : > - IS_ELKHARTLAKE and IS_JASPERLAKE is replaced with > HAS_PCH_MCC(EHL) and HAS_PCH_JSP(JSL) respectively > - Reverted EHL/JSL PCI ids split change > > Signed-off-by: Tejas Upadhyay > --- > drivers/gpu/drm/i915/display/icl_dsi.c | 4 ++-- > drivers/gpu/drm/i915/display/intel_cdclk.c | 4 ++-- > drivers/gpu/drm/i915/display/intel_combo_phy.c | 6 +++--- > drivers/gpu/drm/i915/display/intel_display.c | 8 > drivers/gpu/drm/i915/display/intel_dp.c| 2 +- > drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 16 > drivers/gpu/drm/i915/gt/intel_sseu.c | 2 +- > drivers/gpu/drm/i915/gt/intel_workarounds.c| 4 ++-- > drivers/gpu/drm/i915/i915_drv.h| 9 ++--- > drivers/gpu/drm/i915/i915_pci.c| 9 + > drivers/gpu/drm/i915/intel_device_info.c | 1 + > drivers/gpu/drm/i915/intel_device_info.h | 1 + > drivers/gpu/drm/i915/intel_pch.c | 2 +- > include/drm/i915_pciids.h | 9 ++--- > 14 files changed, 47 insertions(+), 30 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c > b/drivers/gpu/drm/i915/display/icl_dsi.c > index fe946a2e2082..f7c3731f5a4b 100644 > --- a/drivers/gpu/drm/i915/display/icl_dsi.c > +++ b/drivers/gpu/drm/i915/display/icl_dsi.c > @@ -455,7 +455,7 @@ static void gen11_dsi_config_phy_lanes_sequence(struct > intel_encoder *encoder) > intel_de_write(dev_priv, ICL_PORT_TX_DW2_GRP(phy), tmp); > > /* For EHL, TGL, set latency optimization for PCS_DW1 lanes */ > - if (IS_ELKHARTLAKE(dev_priv) || (INTEL_GEN(dev_priv) >= 12)) { > + if (IS_JSL_EHL(dev_priv) || (INTEL_GEN(dev_priv) >= 12)) { > tmp = intel_de_read(dev_priv, > ICL_PORT_PCS_DW1_AUX(phy)); > tmp &= ~LATENCY_OPTIM_MASK; > @@ -612,7 +612,7 @@ gen11_dsi_setup_dphy_timings(struct intel_encoder > *encoder, > } > } > > - if (IS_ELKHARTLAKE(dev_priv)) { > + if (IS_JSL_EHL(dev_priv)) { > for_each_dsi_phy(phy, intel_dsi->phys) { > tmp = intel_de_read(dev_priv, ICL_DPHY_CHKN(phy)); > tmp |= ICL_DPHY_CHKN_AFE_OVER_PPI_STRAP; > diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c > b/drivers/gpu/drm/i915/display/intel_cdclk.c > index cb93f6cf6d37..c6e87569b3d6 100644 > --- a/drivers/gpu/drm/i915/display/intel_cdclk.c > +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c > @@ -2588,7 +2588,7 @@ static int intel_compute_max_dotclk(struct > drm_i915_private *dev_priv) > */ > void intel_update_max_cdclk(struct drm_i915_private *dev_priv) > { > - if (IS_ELKHARTLAKE(dev_priv)) { > + if (IS_JSL_EHL(dev_priv)) { > if (dev_priv->cdclk.hw.ref == 24000) > dev_priv->max_cdclk_freq = 552000; > else > @@ -2815,7 +2815,7 @@ void intel_init_cdclk_hooks(struct drm_i915_private > *dev_priv) > dev_priv->display.modeset_calc_cdclk = bxt_modeset_calc_cdclk; > dev_priv->display.calc_voltage_level = tgl_calc_voltage_level; > dev_priv->cdclk.table = icl_cdclk_table; > - } else if (IS_ELKHARTLAKE(dev_priv)) { > + } else if (IS_JSL_EHL(dev_priv)) { > dev_priv->display.set_cdclk = bxt_set_cdclk; > dev_priv->display.bw_calc_min_cdclk = skl_bw_calc_min_cdclk; > dev_priv->display.modeset_calc_cdclk = bxt_modeset_calc_cdclk; > diff --git
[PATCH v4 1/2] drm/i915/jsl: Split EHL/JSL platform info and PCI ids
Split the basic platform definition, macros, and PCI IDs to differentiate between EHL and JSL platforms. Changes since V3 : - Changed IS_EHL_JSL to IS_JSL_EHL - Renamed IS_EHL_REVID to IS_JSL_EHL_REVID - Reverted removal of IS_ELKHARTLAKE and also added IS_JASPERLAKE Changes since V2 : - Added IS_EHL_JSL to replace IS_ELKHARTLAKE - EHL/JSL PCI ids split added Changes since V1 : - IS_ELKHARTLAKE and IS_JASPERLAKE is replaced with HAS_PCH_MCC(EHL) and HAS_PCH_JSP(JSL) respectively - Reverted EHL/JSL PCI ids split change Signed-off-by: Tejas Upadhyay --- drivers/gpu/drm/i915/display/icl_dsi.c | 4 ++-- drivers/gpu/drm/i915/display/intel_cdclk.c | 4 ++-- drivers/gpu/drm/i915/display/intel_combo_phy.c | 6 +++--- drivers/gpu/drm/i915/display/intel_display.c | 8 drivers/gpu/drm/i915/display/intel_dp.c| 2 +- drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 16 drivers/gpu/drm/i915/gt/intel_sseu.c | 2 +- drivers/gpu/drm/i915/gt/intel_workarounds.c| 4 ++-- drivers/gpu/drm/i915/i915_drv.h| 9 ++--- drivers/gpu/drm/i915/i915_pci.c| 9 + drivers/gpu/drm/i915/intel_device_info.c | 1 + drivers/gpu/drm/i915/intel_device_info.h | 1 + drivers/gpu/drm/i915/intel_pch.c | 2 +- include/drm/i915_pciids.h | 9 ++--- 14 files changed, 47 insertions(+), 30 deletions(-) diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c index fe946a2e2082..f7c3731f5a4b 100644 --- a/drivers/gpu/drm/i915/display/icl_dsi.c +++ b/drivers/gpu/drm/i915/display/icl_dsi.c @@ -455,7 +455,7 @@ static void gen11_dsi_config_phy_lanes_sequence(struct intel_encoder *encoder) intel_de_write(dev_priv, ICL_PORT_TX_DW2_GRP(phy), tmp); /* For EHL, TGL, set latency optimization for PCS_DW1 lanes */ - if (IS_ELKHARTLAKE(dev_priv) || (INTEL_GEN(dev_priv) >= 12)) { + if (IS_JSL_EHL(dev_priv) || (INTEL_GEN(dev_priv) >= 12)) { tmp = intel_de_read(dev_priv, ICL_PORT_PCS_DW1_AUX(phy)); tmp &= ~LATENCY_OPTIM_MASK; @@ -612,7 +612,7 @@ gen11_dsi_setup_dphy_timings(struct intel_encoder *encoder, } } - if (IS_ELKHARTLAKE(dev_priv)) { + if (IS_JSL_EHL(dev_priv)) { for_each_dsi_phy(phy, intel_dsi->phys) { tmp = intel_de_read(dev_priv, ICL_DPHY_CHKN(phy)); tmp |= ICL_DPHY_CHKN_AFE_OVER_PPI_STRAP; diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c index cb93f6cf6d37..c6e87569b3d6 100644 --- a/drivers/gpu/drm/i915/display/intel_cdclk.c +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c @@ -2588,7 +2588,7 @@ static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv) */ void intel_update_max_cdclk(struct drm_i915_private *dev_priv) { - if (IS_ELKHARTLAKE(dev_priv)) { + if (IS_JSL_EHL(dev_priv)) { if (dev_priv->cdclk.hw.ref == 24000) dev_priv->max_cdclk_freq = 552000; else @@ -2815,7 +2815,7 @@ void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv) dev_priv->display.modeset_calc_cdclk = bxt_modeset_calc_cdclk; dev_priv->display.calc_voltage_level = tgl_calc_voltage_level; dev_priv->cdclk.table = icl_cdclk_table; - } else if (IS_ELKHARTLAKE(dev_priv)) { + } else if (IS_JSL_EHL(dev_priv)) { dev_priv->display.set_cdclk = bxt_set_cdclk; dev_priv->display.bw_calc_min_cdclk = skl_bw_calc_min_cdclk; dev_priv->display.modeset_calc_cdclk = bxt_modeset_calc_cdclk; diff --git a/drivers/gpu/drm/i915/display/intel_combo_phy.c b/drivers/gpu/drm/i915/display/intel_combo_phy.c index 157d8c8c605a..d59ceaa2916a 100644 --- a/drivers/gpu/drm/i915/display/intel_combo_phy.c +++ b/drivers/gpu/drm/i915/display/intel_combo_phy.c @@ -188,7 +188,7 @@ static bool has_phy_misc(struct drm_i915_private *i915, enum phy phy) * PHY-B and may not even have instances of the register for the * other combo PHY's. */ - if (IS_ELKHARTLAKE(i915) || + if (IS_JSL_EHL(i915) || IS_ROCKETLAKE(i915)) return phy < PHY_C; @@ -282,7 +282,7 @@ static bool icl_combo_phy_verify_state(struct drm_i915_private *dev_priv, ret &= check_phy_reg(dev_priv, phy, ICL_PORT_COMP_DW8(phy), IREFGEN, IREFGEN); - if (IS_ELKHARTLAKE(dev_priv)) { + if (IS_JSL_EHL(dev_priv)) { if (ehl_vbt_ddi_d_present(dev_priv)) expected_val = ICL_PHY_MISC_MUX_DDID;
[PATCH v4 1/2] drm/i915/jsl: Split EHL/JSL platform info and PCI ids
Split the basic platform definition, macros, and PCI IDs to differentiate between EHL and JSL platforms. Changes since V3 : - Changed IS_EHL_JSL to IS_JSL_EHL - Renamed IS_EHL_REVID to IS_JSL_EHL_REVID - Reverted removal of IS_ELKHARTLAKE and also added IS_JASPERLAKE Changes since V2 : - Added IS_EHL_JSL to replace IS_ELKHARTLAKE - EHL/JSL PCI ids split added Changes since V1 : - IS_ELKHARTLAKE and IS_JASPERLAKE is replaced with HAS_PCH_MCC(EHL) and HAS_PCH_JSP(JSL) respectively - Reverted EHL/JSL PCI ids split change Signed-off-by: Tejas Upadhyay --- drivers/gpu/drm/i915/display/icl_dsi.c | 4 ++-- drivers/gpu/drm/i915/display/intel_cdclk.c | 4 ++-- drivers/gpu/drm/i915/display/intel_combo_phy.c | 6 +++--- drivers/gpu/drm/i915/display/intel_display.c | 8 drivers/gpu/drm/i915/display/intel_dp.c| 2 +- drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 16 drivers/gpu/drm/i915/gt/intel_sseu.c | 2 +- drivers/gpu/drm/i915/gt/intel_workarounds.c| 4 ++-- drivers/gpu/drm/i915/i915_drv.h| 9 ++--- drivers/gpu/drm/i915/i915_pci.c| 9 + drivers/gpu/drm/i915/intel_device_info.c | 1 + drivers/gpu/drm/i915/intel_device_info.h | 1 + drivers/gpu/drm/i915/intel_pch.c | 2 +- include/drm/i915_pciids.h | 9 ++--- 14 files changed, 47 insertions(+), 30 deletions(-) diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c index fe946a2e2082..f7c3731f5a4b 100644 --- a/drivers/gpu/drm/i915/display/icl_dsi.c +++ b/drivers/gpu/drm/i915/display/icl_dsi.c @@ -455,7 +455,7 @@ static void gen11_dsi_config_phy_lanes_sequence(struct intel_encoder *encoder) intel_de_write(dev_priv, ICL_PORT_TX_DW2_GRP(phy), tmp); /* For EHL, TGL, set latency optimization for PCS_DW1 lanes */ - if (IS_ELKHARTLAKE(dev_priv) || (INTEL_GEN(dev_priv) >= 12)) { + if (IS_JSL_EHL(dev_priv) || (INTEL_GEN(dev_priv) >= 12)) { tmp = intel_de_read(dev_priv, ICL_PORT_PCS_DW1_AUX(phy)); tmp &= ~LATENCY_OPTIM_MASK; @@ -612,7 +612,7 @@ gen11_dsi_setup_dphy_timings(struct intel_encoder *encoder, } } - if (IS_ELKHARTLAKE(dev_priv)) { + if (IS_JSL_EHL(dev_priv)) { for_each_dsi_phy(phy, intel_dsi->phys) { tmp = intel_de_read(dev_priv, ICL_DPHY_CHKN(phy)); tmp |= ICL_DPHY_CHKN_AFE_OVER_PPI_STRAP; diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c index cb93f6cf6d37..c6e87569b3d6 100644 --- a/drivers/gpu/drm/i915/display/intel_cdclk.c +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c @@ -2588,7 +2588,7 @@ static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv) */ void intel_update_max_cdclk(struct drm_i915_private *dev_priv) { - if (IS_ELKHARTLAKE(dev_priv)) { + if (IS_JSL_EHL(dev_priv)) { if (dev_priv->cdclk.hw.ref == 24000) dev_priv->max_cdclk_freq = 552000; else @@ -2815,7 +2815,7 @@ void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv) dev_priv->display.modeset_calc_cdclk = bxt_modeset_calc_cdclk; dev_priv->display.calc_voltage_level = tgl_calc_voltage_level; dev_priv->cdclk.table = icl_cdclk_table; - } else if (IS_ELKHARTLAKE(dev_priv)) { + } else if (IS_JSL_EHL(dev_priv)) { dev_priv->display.set_cdclk = bxt_set_cdclk; dev_priv->display.bw_calc_min_cdclk = skl_bw_calc_min_cdclk; dev_priv->display.modeset_calc_cdclk = bxt_modeset_calc_cdclk; diff --git a/drivers/gpu/drm/i915/display/intel_combo_phy.c b/drivers/gpu/drm/i915/display/intel_combo_phy.c index 157d8c8c605a..d59ceaa2916a 100644 --- a/drivers/gpu/drm/i915/display/intel_combo_phy.c +++ b/drivers/gpu/drm/i915/display/intel_combo_phy.c @@ -188,7 +188,7 @@ static bool has_phy_misc(struct drm_i915_private *i915, enum phy phy) * PHY-B and may not even have instances of the register for the * other combo PHY's. */ - if (IS_ELKHARTLAKE(i915) || + if (IS_JSL_EHL(i915) || IS_ROCKETLAKE(i915)) return phy < PHY_C; @@ -282,7 +282,7 @@ static bool icl_combo_phy_verify_state(struct drm_i915_private *dev_priv, ret &= check_phy_reg(dev_priv, phy, ICL_PORT_COMP_DW8(phy), IREFGEN, IREFGEN); - if (IS_ELKHARTLAKE(dev_priv)) { + if (IS_JSL_EHL(dev_priv)) { if (ehl_vbt_ddi_d_present(dev_priv)) expected_val = ICL_PHY_MISC_MUX_DDID;