Hi Maxime
On Wed, 8 Jul 2020 at 18:43, Maxime Ripard wrote:
>
> In order to clear our intermediate FIFOs that might end up with a stale
> pixel, let's make sure our FIFO channel is reset everytime our channel is
> setup.
Minor nit pick: s/everytime/every time
> Signed-off-by: Maxime Ripard
Reviewed-by: Dave Stevenson
> ---
> drivers/gpu/drm/vc4/vc4_hvs.c | 4
> 1 file changed, 4 insertions(+)
>
> diff --git a/drivers/gpu/drm/vc4/vc4_hvs.c b/drivers/gpu/drm/vc4/vc4_hvs.c
> index c7de77afbf0a..64b9d72471ef 100644
> --- a/drivers/gpu/drm/vc4/vc4_hvs.c
> +++ b/drivers/gpu/drm/vc4/vc4_hvs.c
> @@ -205,6 +205,10 @@ static int vc4_hvs_init_channel(struct vc4_dev *vc4,
> struct drm_crtc *crtc,
> u32 dispbkgndx;
> u32 dispctrl;
>
> + HVS_WRITE(SCALER_DISPCTRLX(chan), 0);
> + HVS_WRITE(SCALER_DISPCTRLX(chan), SCALER_DISPCTRLX_RESET);
> + HVS_WRITE(SCALER_DISPCTRLX(chan), 0);
> +
> /* Turn on the scaler, which will wait for vstart to start
> * compositing.
> * When feeding the transposer, we should operate in oneshot
> --
> git-series 0.9.1
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