Re: [PATCH v4 3/3] arm64: dts: qcom: sc7180: Add A618 gpu dt blob
On Wed 05 Feb 11:24 PST 2020, Doug Anderson wrote: > Hi, > > On Tue, Feb 4, 2020 at 11:02 PM Sharat Masetty > wrote: > > > > + power-domains = <&gpucc CX_GDSC>, <&gpucc GX_GDSC>; > > I should note that this is going to be a PITA to land because the > patch adding "GX_GDSC" should technically land in the "clk" tree. > Without extra work that's going to mean waiting for a full Linux > release before Bjorn and Andy can land. It might be worth sticking > the hardcoded "1" in for now instead of "GX_GDSC". That's what we > often do in cases like this. > I'm fine with the patches using the GX_GDSC define and I will replace it if necessary when applying the patch - but either way we this is dependent on the clock tree picking up the patch that defines the value. Regards, Bjorn ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: [PATCH v4 3/3] arm64: dts: qcom: sc7180: Add A618 gpu dt blob
Hi, On Tue, Feb 4, 2020 at 11:02 PM Sharat Masetty wrote: > > + power-domains = <&gpucc CX_GDSC>, <&gpucc GX_GDSC>; I should note that this is going to be a PITA to land because the patch adding "GX_GDSC" should technically land in the "clk" tree. Without extra work that's going to mean waiting for a full Linux release before Bjorn and Andy can land. It might be worth sticking the hardcoded "1" in for now instead of "GX_GDSC". That's what we often do in cases like this. -Doug ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: [PATCH v4 3/3] arm64: dts: qcom: sc7180: Add A618 gpu dt blob
Hi, On Tue, Feb 4, 2020 at 11:02 PM Sharat Masetty wrote: > > This patch adds the required dt nodes and properties > to enabled A618 GPU. > > Signed-off-by: Sharat Masetty > --- > arch/arm64/boot/dts/qcom/sc7180.dtsi | 102 > +++ > 1 file changed, 102 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi > b/arch/arm64/boot/dts/qcom/sc7180.dtsi > index f3fcc5c..63fff15 100644 > --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi > +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi > @@ -1043,6 +1043,108 @@ > }; > }; > > + gpu: gpu@500 { > + compatible = "qcom,adreno-618.0", "qcom,adreno"; > + #stream-id-cells = <16>; > + reg = <0 0x0500 0 0x4>, <0 0x0509e000 0 > 0x1000>, > + <0 0x05061000 0 0x800>; > + reg-names = "kgsl_3d0_reg_memory", "cx_mem", > "cx_dbgc"; > + interrupts = ; > + iommus = <&adreno_smmu 0>; > + operating-points-v2 = <&gpu_opp_table>; > + qcom,gmu = <&gmu>; > + > + gpu_opp_table: opp-table { > + compatible = "operating-points-v2"; > + > + opp-8 { > + opp-hz = /bits/ 64 <8>; > + opp-level = > ; > + }; > + > + opp-65000 { > + opp-hz = /bits/ 64 <65000>; > + opp-level = > ; > + }; > + > + opp-56500 { > + opp-hz = /bits/ 64 <56500>; > + opp-level = > ; > + }; > + > + opp-43000 { > + opp-hz = /bits/ 64 <43000>; > + opp-level = > ; > + }; > + > + opp-35500 { > + opp-hz = /bits/ 64 <35500>; > + opp-level = > ; > + }; > + > + opp-26700 { > + opp-hz = /bits/ 64 <26700>; > + opp-level = > ; > + }; > + > + opp-18000 { > + opp-hz = /bits/ 64 <18000>; > + opp-level = > ; > + }; > + }; > + }; > + > + adreno_smmu: iommu@504 { > + compatible = "qcom,sc7180-smmu-v2", "qcom,smmu-v2"; As per prior discussion "qcom,sc7180-smmu-v2" needs to be added to the bindings. > + reg = <0 0x0504 0 0x1>; > + #iommu-cells = <1>; > + #global-interrupts = <2>; > + interrupts = , > + , > + , > + , > + , > + , > + , > + , > + , > + ; > + clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, > + <&gcc GCC_GPU_CFG_AHB_CLK>, > + <&gcc GCC_DDRSS_GPU_AXI_CLK>; > + > + clock-names = "bus", "iface", "mem_iface_clk"; As per discussion in v3 [1], "mem_iface_clk" is new and needs to be added to the bindings. Presumably that patch should be posted / Acked by Rob before we land this dts. Other than relying on un-posted bindings, this looks sane to me and this patch lets me bring the GPU up on my sc7180-based board. Reviewed-by: Douglas Anderson Tested-by: Douglas Anderson -Doug [1] https://lore.kernel.org/r/1e29097cc1cdf18671379f6420f87...@codeaurora.org ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH v4 3/3] arm64: dts: qcom: sc7180: Add A618 gpu dt blob
This patch adds the required dt nodes and properties to enabled A618 GPU. Signed-off-by: Sharat Masetty --- arch/arm64/boot/dts/qcom/sc7180.dtsi | 102 +++ 1 file changed, 102 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi index f3fcc5c..63fff15 100644 --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi @@ -1043,6 +1043,108 @@ }; }; + gpu: gpu@500 { + compatible = "qcom,adreno-618.0", "qcom,adreno"; + #stream-id-cells = <16>; + reg = <0 0x0500 0 0x4>, <0 0x0509e000 0 0x1000>, + <0 0x05061000 0 0x800>; + reg-names = "kgsl_3d0_reg_memory", "cx_mem", "cx_dbgc"; + interrupts = ; + iommus = <&adreno_smmu 0>; + operating-points-v2 = <&gpu_opp_table>; + qcom,gmu = <&gmu>; + + gpu_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-8 { + opp-hz = /bits/ 64 <8>; + opp-level = ; + }; + + opp-65000 { + opp-hz = /bits/ 64 <65000>; + opp-level = ; + }; + + opp-56500 { + opp-hz = /bits/ 64 <56500>; + opp-level = ; + }; + + opp-43000 { + opp-hz = /bits/ 64 <43000>; + opp-level = ; + }; + + opp-35500 { + opp-hz = /bits/ 64 <35500>; + opp-level = ; + }; + + opp-26700 { + opp-hz = /bits/ 64 <26700>; + opp-level = ; + }; + + opp-18000 { + opp-hz = /bits/ 64 <18000>; + opp-level = ; + }; + }; + }; + + adreno_smmu: iommu@504 { + compatible = "qcom,sc7180-smmu-v2", "qcom,smmu-v2"; + reg = <0 0x0504 0 0x1>; + #iommu-cells = <1>; + #global-interrupts = <2>; + interrupts = , + , + , + , + , + , + , + , + , + ; + clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, + <&gcc GCC_GPU_CFG_AHB_CLK>, + <&gcc GCC_DDRSS_GPU_AXI_CLK>; + + clock-names = "bus", "iface", "mem_iface_clk"; + power-domains = <&gpucc CX_GDSC>; + }; + + gmu: gmu@506a000 { + compatible="qcom,adreno-gmu-618.0", "qcom,adreno-gmu"; + reg = <0 0x0506a000 0 0x31000>, <0 0x0b29 0 0x1>, + <0 0x0b49 0 0x1>; + reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq"; + interrupts = , + ; + interrupt-names = "hfi", "gmu"; + clocks = <&gpucc GPU_CC_CX_GMU_CLK>, + <&gpucc GPU_CC_CXO_CLK>, + <&gcc GCC_DDRSS_GPU_AXI_CLK>, + <&gcc GCC_GPU_MEMNOC_GFX_CLK>; + clock-names = "gmu", "cxo", "axi", "memnoc"; + power-domains = <&gpucc CX_GDSC>, <&gpucc GX_GDSC>; + power-domain-names = "cx", "gx"; + iommus = <&adreno_smmu 5>; + operating-points-v2 = <&gmu_opp_table>; + + gmu_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-2 { + opp-hz = /bits/ 64 <200