Add dt-schema yaml bindig for AM65x DSS, AM65x version TI Keystone
Display SubSystem.
Version history:
v2: no change
v3: - Add ports node
- use allOf in ti,am65x-oldi-io-ctrl to add both $ref and maxItems
- Add includes to dts example
- reindent dts example
v4: - Add descriptions to reg and clocks properties
- Remove minItems when its value is the same as maxItems value
v5: - itemize reg and clocks properties' descriptions
Signed-off-by: Jyri Sarha
---
.../bindings/display/ti/ti,am65x-dss.yaml | 152 ++
1 file changed, 152 insertions(+)
create mode 100644
Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml
diff --git a/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml
b/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml
new file mode 100644
index ..cac61a998203
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml
@@ -0,0 +1,152 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+# Copyright 2019 Texas Instruments Incorporated
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/display/ti/ti,am65x-dss.yaml#;
+$schema: "http://devicetree.org/meta-schemas/core.yaml#;
+
+title: Texas Instruments AM65x Display Subsystem
+
+maintainers:
+ - Jyri Sarha
+ - Tomi Valkeinen
+
+description: |
+ The AM65x TI Keystone Display SubSystem with two output ports and
+ two video planes. The first video port supports OLDI and the second
+ supports DPI format. The fist plane is full video plane with all
+ features and the second is a "lite plane" without scaling support.
+
+properties:
+ compatible:
+const: ti,am65x-dss
+
+ reg:
+description:
+ Addresses to each DSS memory region described in the SoC's TRM.
+items:
+ - description: common DSS register area
+ - description: VIDL1 light video plane
+ - description: VID video plane
+ - description: OVR1 overlay manager for vp1
+ - description: OVR2 overlay manager for vp2
+ - description: VP1 video port 1
+ - description: VP2 video port 2
+
+ reg-names:
+items:
+ - const: common
+ - const: vidl1
+ - const: vid
+ - const: ovr1
+ - const: ovr2
+ - const: vp1
+ - const: vp2
+
+ clocks:
+items:
+ - description: fck DSS functional clock
+ - description: vp1 Video Port 1 pixel clock
+ - description: vp2 Video Port 2 pixel clock
+
+ clock-names:
+items:
+ - const: fck
+ - const: vp1
+ - const: vp2
+
+ interrupts:
+maxItems: 1
+
+ power-domains:
+maxItems: 1
+description: phandle to the associated power domain
+
+ ports:
+type: object
+description:
+ Ports as described in Documentation/devictree/bindings/graph.txt
+properties:
+ "#address-cells":
+const: 1
+
+ "#size-cells":
+const: 0
+
+ port@0:
+type: object
+description:
+ The DSS OLDI output port node form video port 1
+
+ port@1:
+type: object
+description:
+ The DSS DPI output port node from video port 2
+
+required:
+ - "#address-cells"
+ - "#size-cells"
+
+ ti,am65x-oldi-io-ctrl:
+allOf:
+ - $ref: "/schemas/types.yaml#/definitions/phandle-array"
+ - maxItems: 1
+description:
+ phandle to syscon device node mapping OLDI IO_CTRL registers.
+ The mapped range should point to OLDI_DAT0_IO_CTRL, map it and
+ following OLDI_DAT1_IO_CTRL, OLDI_DAT2_IO_CTRL, OLDI_DAT3_IO_CTRL,
+ and OLDI_CLK_IO_CTRL registers. This property is needed for OLDI
+ interface to work.
+
+ max-memory-bandwidth:
+$ref: /schemas/types.yaml#/definitions/uint32
+description:
+ Input memory (from main memory to dispc) bandwidth limit in
+ bytes per second
+
+required:
+ - compatible
+ - reg
+ - reg-names
+ - clocks
+ - clock-names
+ - interrupts
+ - ports
+
+additionalProperties: false
+
+examples:
+ - |
+#include
+#include
+#include
+
+dss: dss@04a0 {
+compatible = "ti,am65x-dss";
+reg = <0x0 0x04a0 0x0 0x1000>, /* common */
+<0x0 0x04a02000 0x0 0x1000>, /* vidl1 */
+<0x0 0x04a06000 0x0 0x1000>, /* vid */
+<0x0 0x04a07000 0x0 0x1000>, /* ovr1 */
+<0x0 0x04a08000 0x0 0x1000>, /* ovr2 */
+<0x0 0x04a0a000 0x0 0x1000>, /* vp1 */
+<0x0 0x04a0b000 0x0 0x1000>; /* vp2 */
+reg-names = "common", "vidl1", "vid",
+"ovr1", "ovr2", "vp1", "vp2";
+ti,am65x-oldi-io-ctrl = <_oldi_io_ctrl>;
+power-domains = <_pds 67 TI_SCI_PD_EXCLUSIVE>;
+clocks =<_clks 67 1>,
+<_clks 216 1>,
+<_clks 67 2>;
+clock-names = "fck", "vp1", "vp2";
+interrupts = ;
+ports {
+
