Re: [PATCH v5 3/5] drm: bridge: synopsis: add dsi v1.01 support
Hello Adrian,
Here i get a compile error:
On Mon, Mar 30, 2020 at 2:36 PM Adrian Ratiu wrote:
>
> The Synopsis MIPI DSI v1.01 host controller is quite widely used
> on platforms like i.mx6 and is not very different from the other
> versions like the 1.31/1.30 used on rockchip/stm. The protocols
> appear to be the same, only the register layout is different and
> the newer versions have new features symbolized by new registers
> so adding support for it is just a matter of defining the new
> layout and adding a couple of dsi version checks.
>
> Signed-off-by: Adrian Ratiu
> ---
> New in v5.
> ---
> drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c | 125 +-
> 1 file changed, 119 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
> b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
> index 5b78ff925af0..fb9dbc4fd0f5 100644
> --- a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
> +++ b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
> @@ -32,6 +32,7 @@
>
> #define HWVER_131 0x31333100 /* IP version 1.31 */
> #define HWVER_130 0x31333000 /* IP version 1.30 */
> +#define HWVER_101 0x31303000 /* IP version 1.01 */
>
> #define DSI_VERSION0x00
> #define VERSIONGENMASK(31, 8)
> @@ -100,6 +101,25 @@
> #define DSI_EDPI_CMD_SIZE 0x64
>
> #define DSI_CMD_MODE_CFG 0x68
> +
> +#define DSI_DPI_CFG0x0c
> +#define DSI_TMR_LINE_CFG 0x28
> +#define DSI_VTIMING_CFG0x2c
> +#define DSI_PHY_TMR_CFG_V101 0x30
> +#define DSI_PHY_IF_CFG_V1010x58
> +#define DSI_PHY_IF_CTRL0x5c
> +#define DSI_PHY_RSTZ_V101 0x54
> +#define DSI_PHY_STATUS_V1010x60
> +#define DSI_PHY_TST_CTRL0_V101 0x64
> +#define DSI_GEN_HDR_V101 0x34
> +#define DSI_GEN_PLD_DATA_V101 0x38
> +#define DSI_CMD_MODE_CFG_V101 0x24
> +#define DSI_CMD_PKT_STATUS_V1010x3c
> +#define DSI_VID_PKT_CFG0x20
> +#define DSI_VID_MODE_CFG_V101 0x1c
> +#define DSI_TO_CNT_CFG_V1010x40
> +#define DSI_PCKHDL_CFG_V1010x18
> +
> #define MAX_RD_PKT_SIZE_LP BIT(24)
> #define DCS_LW_TX_LP BIT(19)
> #define DCS_SR_0P_TX_LPBIT(18)
> @@ -127,6 +147,33 @@
> GEN_SW_1P_TX_LP | \
> GEN_SW_0P_TX_LP)
>
> +#define EN_TEAR_FX_V101BIT(14)
> +#define DCS_LW_TX_LP_V101 BIT(12)
> +#define GEN_LW_TX_LP_V101 BIT(11)
> +#define MAX_RD_PKT_SIZE_LP_V101BIT(10)
> +#define DCS_SW_2P_TX_LP_V101 BIT(9)
> +#define DCS_SW_1P_TX_LP_V101 BIT(8)
> +#define DCS_SW_0P_TX_LP_V101 BIT(7)
> +#define GEN_SR_2P_TX_LP_V101 BIT(6)
> +#define GEN_SR_1P_TX_LP_V101 BIT(5)
> +#define GEN_SR_0P_TX_LP_V101 BIT(4)
> +#define GEN_SW_2P_TX_LP_V101 BIT(3)
> +#define GEN_SW_1P_TX_LP_V101 BIT(2)
> +#define GEN_SW_0P_TX_LP_V101 BIT(1)
> +
> +#define CMD_MODE_ALL_LP_V101 (DCS_LW_TX_LP_V101 | \
> +GEN_LW_TX_LP_V101 | \
> +MAX_RD_PKT_SIZE_LP_V101 | \
> +DCS_SW_2P_TX_LP_V101 | \
> +DCS_SW_1P_TX_LP_V101 | \
> +DCS_SW_0P_TX_LP_V101 | \
> +GEN_SR_2P_TX_LP_V101 | \
> +GEN_SR_1P_TX_LP_V101 | \
> +GEN_SR_0P_TX_LP_V101 | \
> +GEN_SW_2P_TX_LP_V101 | \
> +GEN_SW_1P_TX_LP_V101 | \
> +GEN_SW_0P_TX_LP_V101)
> +
> #define DSI_GEN_HDR0x6c
> #define DSI_GEN_PLD_DATA 0x70
>
> @@ -165,6 +212,11 @@
> #define DSI_INT_MSK0 0xc4
> #define DSI_INT_MSK1 0xc8
>
> +#define DSI_ERROR_ST0_V101 0x44
> +#define DSI_ERROR_ST1_V101 0x48
> +#define DSI_ERROR_MSK0_V1010x4c
> +#define DSI_ERROR_MSK1_V1010x50
> +
> #define DSI_PHY_TMR_RD_CFG 0xf4
>
> #define PHY_STATUS_TIMEOUT_US 1
> @@ -359,6 +411,49 @@ static const struct dw_mipi_dsi_variant
> dw_mipi_dsi_v130_v131_layout = {
> .cfg_gen_payload = REG_FIELD(DSI_GEN_PLD_DATA, 0, 31),
> };
>
> +static const struct dw_mipi_dsi_variant dw_mipi_dsi_v101_layout = {
> + .cfg_dpi_vid = REG_FIELD(DSI_DPI_CFG, 0, 1),
> + .cfg_dpi_color_coding = REG_FIELD(DS
Re: [PATCH v5 3/5] drm: bridge: synopsis: add dsi v1.01 support
On Mon, 30 Mar 2020, adrian61 wrote:
Hello Adrian,
Here i get a compile error:
I neglected to test with CONFIG_DEBUG_FS, oops!
Will fix in v6, thanks!
On Mon, Mar 30, 2020 at 2:36 PM Adrian Ratiu wrote:
The Synopsis MIPI DSI v1.01 host controller is quite widely used
on platforms like i.mx6 and is not very different from the other
versions like the 1.31/1.30 used on rockchip/stm. The protocols
appear to be the same, only the register layout is different and
the newer versions have new features symbolized by new registers
so adding support for it is just a matter of defining the new
layout and adding a couple of dsi version checks.
Signed-off-by: Adrian Ratiu
---
New in v5.
---
drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c | 125 +-
1 file changed, 119 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
index 5b78ff925af0..fb9dbc4fd0f5 100644
--- a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
+++ b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
@@ -32,6 +32,7 @@
#define HWVER_131 0x31333100 /* IP version 1.31 */
#define HWVER_130 0x31333000 /* IP version 1.30 */
+#define HWVER_101 0x31303000 /* IP version 1.01 */
#define DSI_VERSION0x00
#define VERSIONGENMASK(31, 8)
@@ -100,6 +101,25 @@
#define DSI_EDPI_CMD_SIZE 0x64
#define DSI_CMD_MODE_CFG 0x68
+
+#define DSI_DPI_CFG0x0c
+#define DSI_TMR_LINE_CFG 0x28
+#define DSI_VTIMING_CFG0x2c
+#define DSI_PHY_TMR_CFG_V101 0x30
+#define DSI_PHY_IF_CFG_V1010x58
+#define DSI_PHY_IF_CTRL0x5c
+#define DSI_PHY_RSTZ_V101 0x54
+#define DSI_PHY_STATUS_V1010x60
+#define DSI_PHY_TST_CTRL0_V101 0x64
+#define DSI_GEN_HDR_V101 0x34
+#define DSI_GEN_PLD_DATA_V101 0x38
+#define DSI_CMD_MODE_CFG_V101 0x24
+#define DSI_CMD_PKT_STATUS_V1010x3c
+#define DSI_VID_PKT_CFG0x20
+#define DSI_VID_MODE_CFG_V101 0x1c
+#define DSI_TO_CNT_CFG_V1010x40
+#define DSI_PCKHDL_CFG_V1010x18
+
#define MAX_RD_PKT_SIZE_LP BIT(24)
#define DCS_LW_TX_LP BIT(19)
#define DCS_SR_0P_TX_LPBIT(18)
@@ -127,6 +147,33 @@
GEN_SW_1P_TX_LP | \
GEN_SW_0P_TX_LP)
+#define EN_TEAR_FX_V101BIT(14)
+#define DCS_LW_TX_LP_V101 BIT(12)
+#define GEN_LW_TX_LP_V101 BIT(11)
+#define MAX_RD_PKT_SIZE_LP_V101BIT(10)
+#define DCS_SW_2P_TX_LP_V101 BIT(9)
+#define DCS_SW_1P_TX_LP_V101 BIT(8)
+#define DCS_SW_0P_TX_LP_V101 BIT(7)
+#define GEN_SR_2P_TX_LP_V101 BIT(6)
+#define GEN_SR_1P_TX_LP_V101 BIT(5)
+#define GEN_SR_0P_TX_LP_V101 BIT(4)
+#define GEN_SW_2P_TX_LP_V101 BIT(3)
+#define GEN_SW_1P_TX_LP_V101 BIT(2)
+#define GEN_SW_0P_TX_LP_V101 BIT(1)
+
+#define CMD_MODE_ALL_LP_V101 (DCS_LW_TX_LP_V101 | \
+GEN_LW_TX_LP_V101 | \
+MAX_RD_PKT_SIZE_LP_V101 | \
+DCS_SW_2P_TX_LP_V101 | \
+DCS_SW_1P_TX_LP_V101 | \
+DCS_SW_0P_TX_LP_V101 | \
+GEN_SR_2P_TX_LP_V101 | \
+GEN_SR_1P_TX_LP_V101 | \
+GEN_SR_0P_TX_LP_V101 | \
+GEN_SW_2P_TX_LP_V101 | \
+GEN_SW_1P_TX_LP_V101 | \
+GEN_SW_0P_TX_LP_V101)
+
#define DSI_GEN_HDR0x6c
#define DSI_GEN_PLD_DATA 0x70
@@ -165,6 +212,11 @@
#define DSI_INT_MSK0 0xc4
#define DSI_INT_MSK1 0xc8
+#define DSI_ERROR_ST0_V101 0x44
+#define DSI_ERROR_ST1_V101 0x48
+#define DSI_ERROR_MSK0_V1010x4c
+#define DSI_ERROR_MSK1_V1010x50
+
#define DSI_PHY_TMR_RD_CFG 0xf4
#define PHY_STATUS_TIMEOUT_US 1
@@ -359,6 +411,49 @@ static const struct dw_mipi_dsi_variant
dw_mipi_dsi_v130_v131_layout = {
.cfg_gen_payload = REG_FIELD(DSI_GEN_PLD_DATA, 0, 31),
};
+static const struct dw_mipi_dsi_variant dw_mipi_dsi_v101_layout = {
+ .cfg_dpi_vid = REG_FIELD(DSI_DPI_CFG, 0, 1),
+ .cfg_dpi_color_coding = REG_FIELD(DSI_DPI_CFG, 2, 4),
+ .cfg_dpi_18loosely_en = REG_FIELD(DSI_DPI_CFG, 10, 10)
[PATCH v5 3/5] drm: bridge: synopsis: add dsi v1.01 support
The Synopsis MIPI DSI v1.01 host controller is quite widely used
on platforms like i.mx6 and is not very different from the other
versions like the 1.31/1.30 used on rockchip/stm. The protocols
appear to be the same, only the register layout is different and
the newer versions have new features symbolized by new registers
so adding support for it is just a matter of defining the new
layout and adding a couple of dsi version checks.
Signed-off-by: Adrian Ratiu
---
New in v5.
---
drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c | 125 +-
1 file changed, 119 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
index 5b78ff925af0..fb9dbc4fd0f5 100644
--- a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
+++ b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
@@ -32,6 +32,7 @@
#define HWVER_131 0x31333100 /* IP version 1.31 */
#define HWVER_130 0x31333000 /* IP version 1.30 */
+#define HWVER_101 0x31303000 /* IP version 1.01 */
#define DSI_VERSION0x00
#define VERSIONGENMASK(31, 8)
@@ -100,6 +101,25 @@
#define DSI_EDPI_CMD_SIZE 0x64
#define DSI_CMD_MODE_CFG 0x68
+
+#define DSI_DPI_CFG0x0c
+#define DSI_TMR_LINE_CFG 0x28
+#define DSI_VTIMING_CFG0x2c
+#define DSI_PHY_TMR_CFG_V101 0x30
+#define DSI_PHY_IF_CFG_V1010x58
+#define DSI_PHY_IF_CTRL0x5c
+#define DSI_PHY_RSTZ_V101 0x54
+#define DSI_PHY_STATUS_V1010x60
+#define DSI_PHY_TST_CTRL0_V101 0x64
+#define DSI_GEN_HDR_V101 0x34
+#define DSI_GEN_PLD_DATA_V101 0x38
+#define DSI_CMD_MODE_CFG_V101 0x24
+#define DSI_CMD_PKT_STATUS_V1010x3c
+#define DSI_VID_PKT_CFG0x20
+#define DSI_VID_MODE_CFG_V101 0x1c
+#define DSI_TO_CNT_CFG_V1010x40
+#define DSI_PCKHDL_CFG_V1010x18
+
#define MAX_RD_PKT_SIZE_LP BIT(24)
#define DCS_LW_TX_LP BIT(19)
#define DCS_SR_0P_TX_LPBIT(18)
@@ -127,6 +147,33 @@
GEN_SW_1P_TX_LP | \
GEN_SW_0P_TX_LP)
+#define EN_TEAR_FX_V101BIT(14)
+#define DCS_LW_TX_LP_V101 BIT(12)
+#define GEN_LW_TX_LP_V101 BIT(11)
+#define MAX_RD_PKT_SIZE_LP_V101BIT(10)
+#define DCS_SW_2P_TX_LP_V101 BIT(9)
+#define DCS_SW_1P_TX_LP_V101 BIT(8)
+#define DCS_SW_0P_TX_LP_V101 BIT(7)
+#define GEN_SR_2P_TX_LP_V101 BIT(6)
+#define GEN_SR_1P_TX_LP_V101 BIT(5)
+#define GEN_SR_0P_TX_LP_V101 BIT(4)
+#define GEN_SW_2P_TX_LP_V101 BIT(3)
+#define GEN_SW_1P_TX_LP_V101 BIT(2)
+#define GEN_SW_0P_TX_LP_V101 BIT(1)
+
+#define CMD_MODE_ALL_LP_V101 (DCS_LW_TX_LP_V101 | \
+GEN_LW_TX_LP_V101 | \
+MAX_RD_PKT_SIZE_LP_V101 | \
+DCS_SW_2P_TX_LP_V101 | \
+DCS_SW_1P_TX_LP_V101 | \
+DCS_SW_0P_TX_LP_V101 | \
+GEN_SR_2P_TX_LP_V101 | \
+GEN_SR_1P_TX_LP_V101 | \
+GEN_SR_0P_TX_LP_V101 | \
+GEN_SW_2P_TX_LP_V101 | \
+GEN_SW_1P_TX_LP_V101 | \
+GEN_SW_0P_TX_LP_V101)
+
#define DSI_GEN_HDR0x6c
#define DSI_GEN_PLD_DATA 0x70
@@ -165,6 +212,11 @@
#define DSI_INT_MSK0 0xc4
#define DSI_INT_MSK1 0xc8
+#define DSI_ERROR_ST0_V101 0x44
+#define DSI_ERROR_ST1_V101 0x48
+#define DSI_ERROR_MSK0_V1010x4c
+#define DSI_ERROR_MSK1_V1010x50
+
#define DSI_PHY_TMR_RD_CFG 0xf4
#define PHY_STATUS_TIMEOUT_US 1
@@ -359,6 +411,49 @@ static const struct dw_mipi_dsi_variant
dw_mipi_dsi_v130_v131_layout = {
.cfg_gen_payload = REG_FIELD(DSI_GEN_PLD_DATA, 0, 31),
};
+static const struct dw_mipi_dsi_variant dw_mipi_dsi_v101_layout = {
+ .cfg_dpi_vid = REG_FIELD(DSI_DPI_CFG, 0, 1),
+ .cfg_dpi_color_coding = REG_FIELD(DSI_DPI_CFG, 2, 4),
+ .cfg_dpi_18loosely_en = REG_FIELD(DSI_DPI_CFG, 10, 10),
+ .cfg_dpi_vsync_active_low = REG_FIELD(DSI_DPI_CFG, 6, 6),
+ .cfg_dpi_hsync_active_low = REG_FIELD(DSI_DPI_CFG, 7, 7),
+ .cfg_cmd_mode_en = REG_FIELD(DSI_CMD_MODE_CFG_
