Add dt-schema yaml bindig for J721E DSS, J721E version TI Keystone
Display SubSystem.
Version history:
v2: no change
v3: - reg-names: "wp" -> "wb"
- Add ports node
- Add includes to dts example
- reindent dts example
v4: - Add descriptions to reg, clocks, and interrups properties
- Remove minItems when its value is the same as maxItems value
v5: - itemize reg, clocks and interrupts properties' descriptions
- there is no "vp" reg-name, only "wb" for write back
Signed-off-by: Jyri Sarha
---
.../bindings/display/ti/ti,j721e-dss.yaml | 208 ++
1 file changed, 208 insertions(+)
create mode 100644
Documentation/devicetree/bindings/display/ti/ti,j721e-dss.yaml
diff --git a/Documentation/devicetree/bindings/display/ti/ti,j721e-dss.yaml
b/Documentation/devicetree/bindings/display/ti/ti,j721e-dss.yaml
new file mode 100644
index ..ade9b2f513f5
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/ti/ti,j721e-dss.yaml
@@ -0,0 +1,208 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+# Copyright 2019 Texas Instruments Incorporated
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/display/ti/ti,j721e-dss.yaml#;
+$schema: "http://devicetree.org/meta-schemas/core.yaml#;
+
+title: Texas Instruments J721E Display Subsystem
+
+maintainers:
+ - Jyri Sarha
+ - Tomi Valkeinen
+
+description: |
+ The J721E TI Keystone Display SubSystem with four output ports and
+ four video planes. There is two full video planes and two "lite
+ planes" without scaling support. The video ports can be connected to
+ the SoC's DPI pins or to integrated display bridges on the SoC.
+
+properties:
+ compatible:
+const: ti,j721e-dss
+
+ reg:
+items:
+ - description: common_m DSS Master common
+ - description: common_s0 DSS Shared common 0
+ - description: common_s1 DSS Shared common 1
+ - description: common_s2 DSS Shared common 2
+ - description: VIDL1 light video plane 1
+ - description: VIDL2 light video plane 2
+ - description: VID1 video plane 1
+ - description: VID1 video plane 2
+ - description: OVR1 overlay manager for vp1
+ - description: OVR2 overlay manager for vp2
+ - description: OVR3 overlay manager for vp3
+ - description: OVR4 overlay manager for vp4
+ - description: VP1 video port 1
+ - description: VP2 video port 2
+ - description: VP3 video port 3
+ - description: VP4 video port 4
+ - description: WB Write Back
+
+ reg-names:
+items:
+ - const: common_m
+ - const: common_s0
+ - const: common_s1
+ - const: common_s2
+ - const: vidl1
+ - const: vidl2
+ - const: vid1
+ - const: vid2
+ - const: ovr1
+ - const: ovr2
+ - const: ovr3
+ - const: ovr4
+ - const: vp1
+ - const: vp2
+ - const: vp3
+ - const: vp4
+ - const: wb
+
+ clocks:
+items:
+ - description: fck DSS functional clock
+ - description: vp1 Video Port 1 pixel clock
+ - description: vp2 Video Port 2 pixel clock
+ - description: vp3 Video Port 3 pixel clock
+ - description: vp4 Video Port 4 pixel clock
+
+ clock-names:
+items:
+ - const: fck
+ - const: vp1
+ - const: vp2
+ - const: vp3
+ - const: vp4
+
+ interrupts:
+ items:
+ - description: common_m DSS Master common
+ - description: common_s0 DSS Shared common 0
+ - description: common_s1 DSS Shared common 1
+ - description: common_s2 DSS Shared common 2
+
+ interrupt-names:
+items:
+ - const: common_m
+ - const: common_s0
+ - const: common_s1
+ - const: common_s2
+
+ power-domains:
+maxItems: 1
+description: phandle to the associated power domain
+
+ ports:
+type: object
+description:
+ Ports as described in Documentation/devictree/bindings/graph.txt
+properties:
+ "#address-cells":
+const: 1
+
+ "#size-cells":
+const: 0
+
+ port@0:
+type: object
+description:
+ The output port node form video port 1
+
+ port@1:
+type: object
+description:
+ The output port node from video port 2
+
+ port@2:
+type: object
+description:
+ The output port node from video port 3
+
+ port@3:
+type: object
+description:
+ The output port node from video port 4
+
+required:
+ - "#address-cells"
+ - "#size-cells"
+
+ max-memory-bandwidth:
+$ref: /schemas/types.yaml#/definitions/uint32
+description:
+ Input memory (from main memory to dispc) bandwidth limit in
+ bytes per second
+
+required:
+ - compatible
+ - reg
+ - reg-names
+ - clocks
+ - clock-names
+ - interrupts
+ - interrupt-names
+ - ports
+
+additionalProperties: false
+
+examples:
+ - |
+#include
+#include
+#include
+
+dss: dss@04a0 {
+compatible = "ti,j721e-dss";
+
