Re: [PATCH v6 03/14] dt-bindings: display: bridge: Add i.MX8qm/qxp pixel combiner binding
On Wed, 2021-03-17 at 11:42 +0800, Liu Ying wrote:
> This patch adds bindings for i.MX8qm/qxp pixel combiner.
>
> Reviewed-by: Rob Herring
> Signed-off-by: Liu Ying
> ---
> v5->v6:
> * No change.
>
> v4->v5:
> * No change.
>
> v3->v4:
> * No change.
>
> v2->v3:
> * Add Rob's R-b tag.
>
> v1->v2:
> * Use graph schema. (Laurent)
> * Use enum instead of oneOf + const for the reg property of pixel combiner
> channels. (Rob)
>
> .../display/bridge/fsl,imx8qxp-pixel-combiner.yaml | 144
> +
> 1 file changed, 144 insertions(+)
> create mode 100644
> Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-pixel-combiner.yaml
>
> diff --git
> a/Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-pixel-combiner.yaml
> b/Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-pixel-combiner.yaml
> new file mode 100644
> index ..50bae21
> --- /dev/null
> +++
> b/Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-pixel-combiner.yaml
> @@ -0,0 +1,144 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id:
> http://devicetree.org/schemas/display/bridge/fsl,imx8qxp-pixel-combiner.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Freescale i.MX8qm/qxp Pixel Combiner
> +
> +maintainers:
> + - Liu Ying
> +
> +description: |
> + The Freescale i.MX8qm/qxp Pixel Combiner takes two output streams from a
> + single display controller and manipulates the two streams to support a
> number
> + of modes(bypass, pixel combine, YUV444 to YUV422, split_RGB) configured as
> + either one screen, two screens, or virtual screens. The pixel combiner is
> + also responsible for generating some of the control signals for the pixel
> link
> + output channel.
> +
> +properties:
> + compatible:
> + enum:
> + - fsl,imx8qm-pixel-combiner
> + - fsl,imx8qxp-pixel-combiner
> +
> + "#address-cells":
> + const: 1
> +
> + "#size-cells":
> + const: 0
> +
> + reg:
> + maxItems: 1
> +
> + clocks:
> + maxItems: 1
> +
> + clock-names:
> + const: apb
> +
> + power-domains:
> + maxItems: 1
> +
> +patternProperties:
> + "^channel@[0-1]$":
> + type: object
> + description: Represents a display stream of pixel combiner.
> +
> + properties:
> + "#address-cells":
> + const: 1
> +
> + "#size-cells":
> + const: 0
> +
> + reg:
> + description: The display stream index.
> + enum: [ 0, 1 ]
> +
> + port@0:
> + $ref: /schemas/graph.yaml#/properties/port
> + description: Input endpoint of the display stream.
> +
> + port@1:
> + $ref: /schemas/graph.yaml#/properties/port
> + description: Output endpoint of the display stream.
> +
> + required:
> + - "#address-cells"
> + - "#size-cells"
> + - reg
> + - port@0
> + - port@1
> +
> + additionalProperties: false
> +
> +required:
> + - compatible
> + - "#address-cells"
> + - "#size-cells"
> + - reg
> + - clocks
> + - clock-names
> + - power-domains
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include
> + #include
> + pixel-combiner@5602 {
> + compatible = "fsl,imx8qxp-pixel-combiner";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <0x5602 0x1>;
> + clocks = <_pixel_combiner_lpcg IMX_LPCG_CLK_4>;
> + clock-names = "apb";
> + power-domains = < IMX_SC_R_DC_0>;
> +
> + channel@0 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <0>;
> +
> + port@0 {
> + reg = <0>;
> +
> + dc0_pixel_combiner_ch0_dc0_dpu_disp0: endpoint {
> + remote-endpoint =
> <_dpu_disp0_dc0_pixel_combiner_ch0>;
While I acknowledge this just being an example you seem to call these as
follows elsewhere:
Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-pixel-combiner.yaml
dc0_dpu_disp0_dc0_pixel_combiner_ch0
pixel_combiner0_ch0_dpu0_disp0
Or am I just missing something?
> + };
> + };
> +
> + port@1 {
> + reg = <1>;
> +
> + dc0_pixel_combiner_ch0_dc0_pixel_link0: endpoint {
> + remote-endpoint =
> <_pixel_link0_dc0_pixel_combiner_ch0>;
> + };
> + };
> + };
> +
> + channel@1 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <1>;
> +
> + port@0 {
> + reg = <0>;
> +
> + dc0_pixel_combiner_ch1_dc0_dpu_disp1: endpoint {
> + remote-endpoint =
> <_dpu_disp1_dc0_pixel_combiner_ch1>;
ditto
> + };
> + };
> +
> + port@1 {
> + reg = <1>;
> +
> + dc0_pixel_combiner_ch1_dc0_pixel_link1: endpoint {
> + remote-endpoint =
>
Re: [PATCH v6 03/14] dt-bindings: display: bridge: Add i.MX8qm/qxp pixel combiner binding
Hi Marcel,
On Tue, 2021-03-23 at 00:34 +, Marcel Ziswiler wrote:
> On Wed, 2021-03-17 at 11:42 +0800, Liu Ying wrote:
> > This patch adds bindings for i.MX8qm/qxp pixel combiner.
> >
> > Reviewed-by: Rob Herring
> > Signed-off-by: Liu Ying
> > ---
> > v5->v6:
> > * No change.
> >
> > v4->v5:
> > * No change.
> >
> > v3->v4:
> > * No change.
> >
> > v2->v3:
> > * Add Rob's R-b tag.
> >
> > v1->v2:
> > * Use graph schema. (Laurent)
> > * Use enum instead of oneOf + const for the reg property of pixel combiner
> > channels. (Rob)
> >
> > .../display/bridge/fsl,imx8qxp-pixel-combiner.yaml | 144
> > +
> > 1 file changed, 144 insertions(+)
> > create mode 100644
> > Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-pixel-combiner.yaml
> >
> > diff --git
> > a/Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-pixel-combiner.yaml
> > b/Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-pixel-combiner.yaml
> > new file mode 100644
> > index ..50bae21
> > --- /dev/null
> > +++
> > b/Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-pixel-combiner.yaml
> > @@ -0,0 +1,144 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id:
> > https://eur01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fdevicetree.org%2Fschemas%2Fdisplay%2Fbridge%2Ffsl%2Cimx8qxp-pixel-combiner.yaml%23data=04%7C01%7Cvictor.liu%40nxp.com%7Cb83106f0261d4f715b4208d8ed936cb1%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0%7C637520564736692120%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000sdata=%2B4sZ3C9r3cewzQ01YHOvGk%2FCZaqQgg3ALftZ1dPLKIE%3Dreserved=0
> > +$schema:
> > https://eur01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fdevicetree.org%2Fmeta-schemas%2Fcore.yaml%23data=04%7C01%7Cvictor.liu%40nxp.com%7Cb83106f0261d4f715b4208d8ed936cb1%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0%7C637520564736692120%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000sdata=sP82pZYZXLKhzRRoYPR4C%2FFsDLUka1Fj0%2FA9InuWuvg%3Dreserved=0
> > +
> > +title: Freescale i.MX8qm/qxp Pixel Combiner
> > +
> > +maintainers:
> > + - Liu Ying
> > +
> > +description: |
> > + The Freescale i.MX8qm/qxp Pixel Combiner takes two output streams from a
> > + single display controller and manipulates the two streams to support a
> > number
> > + of modes(bypass, pixel combine, YUV444 to YUV422, split_RGB) configured
> > as
> > + either one screen, two screens, or virtual screens. The pixel combiner
> > is
> > + also responsible for generating some of the control signals for the
> > pixel link
> > + output channel.
> > +
> > +properties:
> > + compatible:
> > +enum:
> > + - fsl,imx8qm-pixel-combiner
> > + - fsl,imx8qxp-pixel-combiner
> > +
> > + "#address-cells":
> > +const: 1
> > +
> > + "#size-cells":
> > +const: 0
> > +
> > + reg:
> > +maxItems: 1
> > +
> > + clocks:
> > +maxItems: 1
> > +
> > + clock-names:
> > +const: apb
> > +
> > + power-domains:
> > +maxItems: 1
> > +
> > +patternProperties:
> > + "^channel@[0-1]$":
> > +type: object
> > +description: Represents a display stream of pixel combiner.
> > +
> > +properties:
> > + "#address-cells":
> > +const: 1
> > +
> > + "#size-cells":
> > +const: 0
> > +
> > + reg:
> > +description: The display stream index.
> > +enum: [ 0, 1 ]
> > +
> > + port@0:
> > +$ref: /schemas/graph.yaml#/properties/port
> > +description: Input endpoint of the display stream.
> > +
> > + port@1:
> > +$ref: /schemas/graph.yaml#/properties/port
> > +description: Output endpoint of the display stream.
> > +
> > +required:
> > + - "#address-cells"
> > + - "#size-cells"
> > + - reg
> > + - port@0
> > + - port@1
> > +
> > +additionalProperties: false
> > +
> > +required:
> > + - compatible
> > + - "#address-cells"
> > + - "#size-cells"
> > + - reg
> > + - clocks
> > + - clock-names
> > + - power-domains
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > + - |
> > +#include
> > +#include
> > +pixel-combiner@5602 {
> > +compatible = "fsl,imx8qxp-pixel-combiner";
> > +#address-cells = <1>;
> > +#size-cells = <0>;
> > +reg = <0x5602 0x1>;
> > +clocks = <_pixel_combiner_lpcg IMX_LPCG_CLK_4>;
> > +clock-names = "apb";
> > +power-domains = < IMX_SC_R_DC_0>;
> > +
> > +channel@0 {
> > +#address-cells = <1>;
> > +#size-cells = <0>;
> > +reg = <0>;
> > +
> > +port@0 {
> > +reg = <0>;
> > +
> > +dc0_pixel_combiner_ch0_dc0_dpu_disp0: endpoint {
> > +remote-endpoint =
> > <_dpu_disp0_dc0_pixel_combiner_ch0>;
>
> While I acknowledge this just
[PATCH v6 03/14] dt-bindings: display: bridge: Add i.MX8qm/qxp pixel combiner binding
This patch adds bindings for i.MX8qm/qxp pixel combiner.
Reviewed-by: Rob Herring
Signed-off-by: Liu Ying
---
v5->v6:
* No change.
v4->v5:
* No change.
v3->v4:
* No change.
v2->v3:
* Add Rob's R-b tag.
v1->v2:
* Use graph schema. (Laurent)
* Use enum instead of oneOf + const for the reg property of pixel combiner
channels. (Rob)
.../display/bridge/fsl,imx8qxp-pixel-combiner.yaml | 144 +
1 file changed, 144 insertions(+)
create mode 100644
Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-pixel-combiner.yaml
diff --git
a/Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-pixel-combiner.yaml
b/Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-pixel-combiner.yaml
new file mode 100644
index ..50bae21
--- /dev/null
+++
b/Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-pixel-combiner.yaml
@@ -0,0 +1,144 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id:
http://devicetree.org/schemas/display/bridge/fsl,imx8qxp-pixel-combiner.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Freescale i.MX8qm/qxp Pixel Combiner
+
+maintainers:
+ - Liu Ying
+
+description: |
+ The Freescale i.MX8qm/qxp Pixel Combiner takes two output streams from a
+ single display controller and manipulates the two streams to support a number
+ of modes(bypass, pixel combine, YUV444 to YUV422, split_RGB) configured as
+ either one screen, two screens, or virtual screens. The pixel combiner is
+ also responsible for generating some of the control signals for the pixel
link
+ output channel.
+
+properties:
+ compatible:
+enum:
+ - fsl,imx8qm-pixel-combiner
+ - fsl,imx8qxp-pixel-combiner
+
+ "#address-cells":
+const: 1
+
+ "#size-cells":
+const: 0
+
+ reg:
+maxItems: 1
+
+ clocks:
+maxItems: 1
+
+ clock-names:
+const: apb
+
+ power-domains:
+maxItems: 1
+
+patternProperties:
+ "^channel@[0-1]$":
+type: object
+description: Represents a display stream of pixel combiner.
+
+properties:
+ "#address-cells":
+const: 1
+
+ "#size-cells":
+const: 0
+
+ reg:
+description: The display stream index.
+enum: [ 0, 1 ]
+
+ port@0:
+$ref: /schemas/graph.yaml#/properties/port
+description: Input endpoint of the display stream.
+
+ port@1:
+$ref: /schemas/graph.yaml#/properties/port
+description: Output endpoint of the display stream.
+
+required:
+ - "#address-cells"
+ - "#size-cells"
+ - reg
+ - port@0
+ - port@1
+
+additionalProperties: false
+
+required:
+ - compatible
+ - "#address-cells"
+ - "#size-cells"
+ - reg
+ - clocks
+ - clock-names
+ - power-domains
+
+additionalProperties: false
+
+examples:
+ - |
+#include
+#include
+pixel-combiner@5602 {
+compatible = "fsl,imx8qxp-pixel-combiner";
+#address-cells = <1>;
+#size-cells = <0>;
+reg = <0x5602 0x1>;
+clocks = <_pixel_combiner_lpcg IMX_LPCG_CLK_4>;
+clock-names = "apb";
+power-domains = < IMX_SC_R_DC_0>;
+
+channel@0 {
+#address-cells = <1>;
+#size-cells = <0>;
+reg = <0>;
+
+port@0 {
+reg = <0>;
+
+dc0_pixel_combiner_ch0_dc0_dpu_disp0: endpoint {
+remote-endpoint = <_dpu_disp0_dc0_pixel_combiner_ch0>;
+};
+};
+
+port@1 {
+reg = <1>;
+
+dc0_pixel_combiner_ch0_dc0_pixel_link0: endpoint {
+remote-endpoint =
<_pixel_link0_dc0_pixel_combiner_ch0>;
+};
+};
+};
+
+channel@1 {
+#address-cells = <1>;
+#size-cells = <0>;
+reg = <1>;
+
+port@0 {
+reg = <0>;
+
+dc0_pixel_combiner_ch1_dc0_dpu_disp1: endpoint {
+remote-endpoint = <_dpu_disp1_dc0_pixel_combiner_ch1>;
+};
+};
+
+port@1 {
+reg = <1>;
+
+dc0_pixel_combiner_ch1_dc0_pixel_link1: endpoint {
+remote-endpoint =
<_pixel_link1_dc0_pixel_combiner_ch1>;
+};
+};
+};
+};
--
2.7.4
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