[PATCH v6 07/11] drm/hisilicon: Add designware dsi encoder driver
On 1 March 2016 at 20:45, Archit Taneja wrote:
>
>
> On 3/1/2016 4:03 PM, Xinliang Liu wrote:
>>
>> Hi,
>>
>> On 1 March 2016 at 02:49, Archit Taneja wrote:
>>>
>>>
>>>
>>> On 2/26/2016 2:10 PM, Xinliang Liu wrote:
Add DesignWare MIPI DSI Host Controller v1.02 encoder driver
for hi6220 SoC.
v6:
- Change "pclk_dsi" to "pclk".
v5: None.
v4: None.
v3:
- Rename file name to dw_drm_dsi.c
- Make encoder type as DRM_MODE_ENCODER_DSI.
- A few cleanup.
v2:
- Remove abtraction layer.
Signed-off-by: Xinliang Liu
Signed-off-by: Xinwei Kong
Signed-off-by: Andy Green
---
drivers/gpu/drm/hisilicon/kirin/Kconfig | 1 +
drivers/gpu/drm/hisilicon/kirin/Makefile | 3 +-
drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c | 743
+++
drivers/gpu/drm/hisilicon/kirin/dw_dsi_reg.h | 83 +++
4 files changed, 829 insertions(+), 1 deletion(-)
create mode 100644 drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c
create mode 100644 drivers/gpu/drm/hisilicon/kirin/dw_dsi_reg.h
diff --git a/drivers/gpu/drm/hisilicon/kirin/Kconfig
b/drivers/gpu/drm/hisilicon/kirin/Kconfig
index 3ac4b8edeac1..de0d454c5c13 100644
--- a/drivers/gpu/drm/hisilicon/kirin/Kconfig
+++ b/drivers/gpu/drm/hisilicon/kirin/Kconfig
@@ -4,6 +4,7 @@ config DRM_HISI_KIRIN
select DRM_KMS_HELPER
select DRM_GEM_CMA_HELPER
select DRM_KMS_CMA_HELPER
+ select DRM_MIPI_DSI
help
Choose this option if you have a hisilicon Kirin
chipsets(hi6220).
If M is selected the module will be called kirin-drm.
diff --git a/drivers/gpu/drm/hisilicon/kirin/Makefile
b/drivers/gpu/drm/hisilicon/kirin/Makefile
index 2a61ab006ddb..5dcd0d4328b6 100644
--- a/drivers/gpu/drm/hisilicon/kirin/Makefile
+++ b/drivers/gpu/drm/hisilicon/kirin/Makefile
@@ -1,4 +1,5 @@
kirin-drm-y := kirin_drm_drv.o \
- kirin_drm_ade.o
+ kirin_drm_ade.o \
+ dw_drm_dsi.o
obj-$(CONFIG_DRM_HISI_KIRIN) += kirin-drm.o
diff --git a/drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c
b/drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c
new file mode 100644
index ..8329148cc89d
--- /dev/null
+++ b/drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c
@@ -0,0 +1,743 @@
+/*
+ * DesignWare MIPI DSI Host Controller v1.02 driver
+ *
+ * Copyright (c) 2016 Linaro Limited.
+ * Copyright (c) 2014-2016 Hisilicon Limited.
+ *
+ * Author:
+ * Xinliang Liu
+ * Xinliang Liu
+ * Xinwei Kong
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#include
+#include
+#include
+
+#include
+#include
+#include
+#include
+#include
+
+#include "dw_dsi_reg.h"
+
+#define MAX_TX_ESC_CLK(10)
+#define ROUND(x, y) ((x) / (y) + ((x) % (y) * 10 / (y) >= 5 ? 1 : 0))
+#define PHY_REF_CLK_RATE 1920
+#define PHY_REF_CLK_PERIOD_PS (10 / (PHY_REF_CLK_RATE / 1000))
+
+#define encoder_to_dsi(encoder) \
+ container_of(encoder, struct dw_dsi, encoder)
+#define host_to_dsi(host) \
+ container_of(host, struct dw_dsi, host)
+
+struct mipi_phy_params {
+ u32 clk_t_lpx;
+ u32 clk_t_hs_prepare;
+ u32 clk_t_hs_zero;
+ u32 clk_t_hs_trial;
+ u32 clk_t_wakeup;
+ u32 data_t_lpx;
+ u32 data_t_hs_prepare;
+ u32 data_t_hs_zero;
+ u32 data_t_hs_trial;
+ u32 data_t_ta_go;
+ u32 data_t_ta_get;
+ u32 data_t_wakeup;
+ u32 hstx_ckg_sel;
+ u32 pll_fbd_div5f;
+ u32 pll_fbd_div1f;
+ u32 pll_fbd_2p;
+ u32 pll_enbwt;
+ u32 pll_fbd_p;
+ u32 pll_fbd_s;
+ u32 pll_pre_div1p;
+ u32 pll_pre_p;
+ u32 pll_vco_750M;
+ u32 pll_lpf_rs;
+ u32 pll_lpf_cs;
+ u32 clklp2hs_time;
+ u32 clkhs2lp_time;
+ u32 lp2hs_time;
+ u32 hs2lp_time;
+ u32 clk_to_data_delay;
+ u32 data_to_clk_delay;
+ u32 lane_byte_clk_kHz;
+ u32 clk_division;
+};
+
+struct dsi_hw_ctx {
+ void __iomem *base;
+ struct clk *pclk;
+};
+
+struct dw_dsi {
+ struct drm_encoder encoder;
+ struct drm_display_mode cur_mode;
+ struct dsi_hw_ctx *ctx;
+ struct
[PATCH v6 07/11] drm/hisilicon: Add designware dsi encoder driver
Hi,
On 1 March 2016 at 02:49, Archit Taneja wrote:
>
>
> On 2/26/2016 2:10 PM, Xinliang Liu wrote:
>>
>> Add DesignWare MIPI DSI Host Controller v1.02 encoder driver
>> for hi6220 SoC.
>>
>> v6:
>> - Change "pclk_dsi" to "pclk".
>> v5: None.
>> v4: None.
>> v3:
>> - Rename file name to dw_drm_dsi.c
>> - Make encoder type as DRM_MODE_ENCODER_DSI.
>> - A few cleanup.
>> v2:
>> - Remove abtraction layer.
>>
>> Signed-off-by: Xinliang Liu
>> Signed-off-by: Xinwei Kong
>> Signed-off-by: Andy Green
>> ---
>> drivers/gpu/drm/hisilicon/kirin/Kconfig | 1 +
>> drivers/gpu/drm/hisilicon/kirin/Makefile | 3 +-
>> drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c | 743
>> +++
>> drivers/gpu/drm/hisilicon/kirin/dw_dsi_reg.h | 83 +++
>> 4 files changed, 829 insertions(+), 1 deletion(-)
>> create mode 100644 drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c
>> create mode 100644 drivers/gpu/drm/hisilicon/kirin/dw_dsi_reg.h
>>
>> diff --git a/drivers/gpu/drm/hisilicon/kirin/Kconfig
>> b/drivers/gpu/drm/hisilicon/kirin/Kconfig
>> index 3ac4b8edeac1..de0d454c5c13 100644
>> --- a/drivers/gpu/drm/hisilicon/kirin/Kconfig
>> +++ b/drivers/gpu/drm/hisilicon/kirin/Kconfig
>> @@ -4,6 +4,7 @@ config DRM_HISI_KIRIN
>> select DRM_KMS_HELPER
>> select DRM_GEM_CMA_HELPER
>> select DRM_KMS_CMA_HELPER
>> + select DRM_MIPI_DSI
>> help
>> Choose this option if you have a hisilicon Kirin
>> chipsets(hi6220).
>> If M is selected the module will be called kirin-drm.
>> diff --git a/drivers/gpu/drm/hisilicon/kirin/Makefile
>> b/drivers/gpu/drm/hisilicon/kirin/Makefile
>> index 2a61ab006ddb..5dcd0d4328b6 100644
>> --- a/drivers/gpu/drm/hisilicon/kirin/Makefile
>> +++ b/drivers/gpu/drm/hisilicon/kirin/Makefile
>> @@ -1,4 +1,5 @@
>> kirin-drm-y := kirin_drm_drv.o \
>> - kirin_drm_ade.o
>> + kirin_drm_ade.o \
>> + dw_drm_dsi.o
>>
>> obj-$(CONFIG_DRM_HISI_KIRIN) += kirin-drm.o
>> diff --git a/drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c
>> b/drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c
>> new file mode 100644
>> index ..8329148cc89d
>> --- /dev/null
>> +++ b/drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c
>> @@ -0,0 +1,743 @@
>> +/*
>> + * DesignWare MIPI DSI Host Controller v1.02 driver
>> + *
>> + * Copyright (c) 2016 Linaro Limited.
>> + * Copyright (c) 2014-2016 Hisilicon Limited.
>> + *
>> + * Author:
>> + * Xinliang Liu
>> + * Xinliang Liu
>> + * Xinwei Kong
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License version 2 as
>> + * published by the Free Software Foundation.
>> + *
>> + */
>> +
>> +#include
>> +#include
>> +#include
>> +
>> +#include
>> +#include
>> +#include
>> +#include
>> +#include
>> +
>> +#include "dw_dsi_reg.h"
>> +
>> +#define MAX_TX_ESC_CLK(10)
>> +#define ROUND(x, y) ((x) / (y) + ((x) % (y) * 10 / (y) >= 5 ? 1 : 0))
>> +#define PHY_REF_CLK_RATE 1920
>> +#define PHY_REF_CLK_PERIOD_PS (10 / (PHY_REF_CLK_RATE / 1000))
>> +
>> +#define encoder_to_dsi(encoder) \
>> + container_of(encoder, struct dw_dsi, encoder)
>> +#define host_to_dsi(host) \
>> + container_of(host, struct dw_dsi, host)
>> +
>> +struct mipi_phy_params {
>> + u32 clk_t_lpx;
>> + u32 clk_t_hs_prepare;
>> + u32 clk_t_hs_zero;
>> + u32 clk_t_hs_trial;
>> + u32 clk_t_wakeup;
>> + u32 data_t_lpx;
>> + u32 data_t_hs_prepare;
>> + u32 data_t_hs_zero;
>> + u32 data_t_hs_trial;
>> + u32 data_t_ta_go;
>> + u32 data_t_ta_get;
>> + u32 data_t_wakeup;
>> + u32 hstx_ckg_sel;
>> + u32 pll_fbd_div5f;
>> + u32 pll_fbd_div1f;
>> + u32 pll_fbd_2p;
>> + u32 pll_enbwt;
>> + u32 pll_fbd_p;
>> + u32 pll_fbd_s;
>> + u32 pll_pre_div1p;
>> + u32 pll_pre_p;
>> + u32 pll_vco_750M;
>> + u32 pll_lpf_rs;
>> + u32 pll_lpf_cs;
>> + u32 clklp2hs_time;
>> + u32 clkhs2lp_time;
>> + u32 lp2hs_time;
>> + u32 hs2lp_time;
>> + u32 clk_to_data_delay;
>> + u32 data_to_clk_delay;
>> + u32 lane_byte_clk_kHz;
>> + u32 clk_division;
>> +};
>> +
>> +struct dsi_hw_ctx {
>> + void __iomem *base;
>> + struct clk *pclk;
>> +};
>> +
>> +struct dw_dsi {
>> + struct drm_encoder encoder;
>> + struct drm_display_mode cur_mode;
>> + struct dsi_hw_ctx *ctx;
>> + struct mipi_phy_params phy;
>> +
>> + u32 lanes;
>> + enum mipi_dsi_pixel_format format;
>> + unsigned long mode_flags;
>> + bool enable;
>> +};
>> +
>> +struct dsi_data {
>> + struct dw_dsi dsi;
>> + struct dsi_hw_ctx ctx;
>> +};
>> +
>> +struct dsi_phy_range {
>> + u32 min_range_kHz;
>> + u32 max_range_kHz;
>> + u32 pll_vco_750M;
>> + u32 hstx_ckg_sel;
>> +};
>> +
>>
[PATCH v6 07/11] drm/hisilicon: Add designware dsi encoder driver
On 3/1/2016 4:03 PM, Xinliang Liu wrote:
> Hi,
>
> On 1 March 2016 at 02:49, Archit Taneja wrote:
>>
>>
>> On 2/26/2016 2:10 PM, Xinliang Liu wrote:
>>>
>>> Add DesignWare MIPI DSI Host Controller v1.02 encoder driver
>>> for hi6220 SoC.
>>>
>>> v6:
>>> - Change "pclk_dsi" to "pclk".
>>> v5: None.
>>> v4: None.
>>> v3:
>>> - Rename file name to dw_drm_dsi.c
>>> - Make encoder type as DRM_MODE_ENCODER_DSI.
>>> - A few cleanup.
>>> v2:
>>> - Remove abtraction layer.
>>>
>>> Signed-off-by: Xinliang Liu
>>> Signed-off-by: Xinwei Kong
>>> Signed-off-by: Andy Green
>>> ---
>>>drivers/gpu/drm/hisilicon/kirin/Kconfig | 1 +
>>>drivers/gpu/drm/hisilicon/kirin/Makefile | 3 +-
>>>drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c | 743
>>> +++
>>>drivers/gpu/drm/hisilicon/kirin/dw_dsi_reg.h | 83 +++
>>>4 files changed, 829 insertions(+), 1 deletion(-)
>>>create mode 100644 drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c
>>>create mode 100644 drivers/gpu/drm/hisilicon/kirin/dw_dsi_reg.h
>>>
>>> diff --git a/drivers/gpu/drm/hisilicon/kirin/Kconfig
>>> b/drivers/gpu/drm/hisilicon/kirin/Kconfig
>>> index 3ac4b8edeac1..de0d454c5c13 100644
>>> --- a/drivers/gpu/drm/hisilicon/kirin/Kconfig
>>> +++ b/drivers/gpu/drm/hisilicon/kirin/Kconfig
>>> @@ -4,6 +4,7 @@ config DRM_HISI_KIRIN
>>> select DRM_KMS_HELPER
>>> select DRM_GEM_CMA_HELPER
>>> select DRM_KMS_CMA_HELPER
>>> + select DRM_MIPI_DSI
>>> help
>>>Choose this option if you have a hisilicon Kirin
>>> chipsets(hi6220).
>>>If M is selected the module will be called kirin-drm.
>>> diff --git a/drivers/gpu/drm/hisilicon/kirin/Makefile
>>> b/drivers/gpu/drm/hisilicon/kirin/Makefile
>>> index 2a61ab006ddb..5dcd0d4328b6 100644
>>> --- a/drivers/gpu/drm/hisilicon/kirin/Makefile
>>> +++ b/drivers/gpu/drm/hisilicon/kirin/Makefile
>>> @@ -1,4 +1,5 @@
>>>kirin-drm-y := kirin_drm_drv.o \
>>> - kirin_drm_ade.o
>>> + kirin_drm_ade.o \
>>> + dw_drm_dsi.o
>>>
>>>obj-$(CONFIG_DRM_HISI_KIRIN) += kirin-drm.o
>>> diff --git a/drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c
>>> b/drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c
>>> new file mode 100644
>>> index ..8329148cc89d
>>> --- /dev/null
>>> +++ b/drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c
>>> @@ -0,0 +1,743 @@
>>> +/*
>>> + * DesignWare MIPI DSI Host Controller v1.02 driver
>>> + *
>>> + * Copyright (c) 2016 Linaro Limited.
>>> + * Copyright (c) 2014-2016 Hisilicon Limited.
>>> + *
>>> + * Author:
>>> + * Xinliang Liu
>>> + * Xinliang Liu
>>> + * Xinwei Kong
>>> + *
>>> + * This program is free software; you can redistribute it and/or modify
>>> + * it under the terms of the GNU General Public License version 2 as
>>> + * published by the Free Software Foundation.
>>> + *
>>> + */
>>> +
>>> +#include
>>> +#include
>>> +#include
>>> +
>>> +#include
>>> +#include
>>> +#include
>>> +#include
>>> +#include
>>> +
>>> +#include "dw_dsi_reg.h"
>>> +
>>> +#define MAX_TX_ESC_CLK(10)
>>> +#define ROUND(x, y) ((x) / (y) + ((x) % (y) * 10 / (y) >= 5 ? 1 : 0))
>>> +#define PHY_REF_CLK_RATE 1920
>>> +#define PHY_REF_CLK_PERIOD_PS (10 / (PHY_REF_CLK_RATE / 1000))
>>> +
>>> +#define encoder_to_dsi(encoder) \
>>> + container_of(encoder, struct dw_dsi, encoder)
>>> +#define host_to_dsi(host) \
>>> + container_of(host, struct dw_dsi, host)
>>> +
>>> +struct mipi_phy_params {
>>> + u32 clk_t_lpx;
>>> + u32 clk_t_hs_prepare;
>>> + u32 clk_t_hs_zero;
>>> + u32 clk_t_hs_trial;
>>> + u32 clk_t_wakeup;
>>> + u32 data_t_lpx;
>>> + u32 data_t_hs_prepare;
>>> + u32 data_t_hs_zero;
>>> + u32 data_t_hs_trial;
>>> + u32 data_t_ta_go;
>>> + u32 data_t_ta_get;
>>> + u32 data_t_wakeup;
>>> + u32 hstx_ckg_sel;
>>> + u32 pll_fbd_div5f;
>>> + u32 pll_fbd_div1f;
>>> + u32 pll_fbd_2p;
>>> + u32 pll_enbwt;
>>> + u32 pll_fbd_p;
>>> + u32 pll_fbd_s;
>>> + u32 pll_pre_div1p;
>>> + u32 pll_pre_p;
>>> + u32 pll_vco_750M;
>>> + u32 pll_lpf_rs;
>>> + u32 pll_lpf_cs;
>>> + u32 clklp2hs_time;
>>> + u32 clkhs2lp_time;
>>> + u32 lp2hs_time;
>>> + u32 hs2lp_time;
>>> + u32 clk_to_data_delay;
>>> + u32 data_to_clk_delay;
>>> + u32 lane_byte_clk_kHz;
>>> + u32 clk_division;
>>> +};
>>> +
>>> +struct dsi_hw_ctx {
>>> + void __iomem *base;
>>> + struct clk *pclk;
>>> +};
>>> +
>>> +struct dw_dsi {
>>> + struct drm_encoder encoder;
>>> + struct drm_display_mode cur_mode;
>>> + struct dsi_hw_ctx *ctx;
>>> + struct mipi_phy_params phy;
>>> +
>>> + u32 lanes;
>>> + enum mipi_dsi_pixel_format format;
>>> + unsigned long mode_flags;
>>> + bool enable;
>>> +};
>>> +
>>> +struct dsi_data {
>>> + struct
[PATCH v6 07/11] drm/hisilicon: Add designware dsi encoder driver
On 2/26/2016 2:10 PM, Xinliang Liu wrote:
> Add DesignWare MIPI DSI Host Controller v1.02 encoder driver
> for hi6220 SoC.
>
> v6:
> - Change "pclk_dsi" to "pclk".
> v5: None.
> v4: None.
> v3:
> - Rename file name to dw_drm_dsi.c
> - Make encoder type as DRM_MODE_ENCODER_DSI.
> - A few cleanup.
> v2:
> - Remove abtraction layer.
>
> Signed-off-by: Xinliang Liu
> Signed-off-by: Xinwei Kong
> Signed-off-by: Andy Green
> ---
> drivers/gpu/drm/hisilicon/kirin/Kconfig | 1 +
> drivers/gpu/drm/hisilicon/kirin/Makefile | 3 +-
> drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c | 743
> +++
> drivers/gpu/drm/hisilicon/kirin/dw_dsi_reg.h | 83 +++
> 4 files changed, 829 insertions(+), 1 deletion(-)
> create mode 100644 drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c
> create mode 100644 drivers/gpu/drm/hisilicon/kirin/dw_dsi_reg.h
>
> diff --git a/drivers/gpu/drm/hisilicon/kirin/Kconfig
> b/drivers/gpu/drm/hisilicon/kirin/Kconfig
> index 3ac4b8edeac1..de0d454c5c13 100644
> --- a/drivers/gpu/drm/hisilicon/kirin/Kconfig
> +++ b/drivers/gpu/drm/hisilicon/kirin/Kconfig
> @@ -4,6 +4,7 @@ config DRM_HISI_KIRIN
> select DRM_KMS_HELPER
> select DRM_GEM_CMA_HELPER
> select DRM_KMS_CMA_HELPER
> + select DRM_MIPI_DSI
> help
> Choose this option if you have a hisilicon Kirin chipsets(hi6220).
> If M is selected the module will be called kirin-drm.
> diff --git a/drivers/gpu/drm/hisilicon/kirin/Makefile
> b/drivers/gpu/drm/hisilicon/kirin/Makefile
> index 2a61ab006ddb..5dcd0d4328b6 100644
> --- a/drivers/gpu/drm/hisilicon/kirin/Makefile
> +++ b/drivers/gpu/drm/hisilicon/kirin/Makefile
> @@ -1,4 +1,5 @@
> kirin-drm-y := kirin_drm_drv.o \
> -kirin_drm_ade.o
> +kirin_drm_ade.o \
> +dw_drm_dsi.o
>
> obj-$(CONFIG_DRM_HISI_KIRIN) += kirin-drm.o
> diff --git a/drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c
> b/drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c
> new file mode 100644
> index ..8329148cc89d
> --- /dev/null
> +++ b/drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c
> @@ -0,0 +1,743 @@
> +/*
> + * DesignWare MIPI DSI Host Controller v1.02 driver
> + *
> + * Copyright (c) 2016 Linaro Limited.
> + * Copyright (c) 2014-2016 Hisilicon Limited.
> + *
> + * Author:
> + * Xinliang Liu
> + * Xinliang Liu
> + * Xinwei Kong
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + *
> + */
> +
> +#include
> +#include
> +#include
> +
> +#include
> +#include
> +#include
> +#include
> +#include
> +
> +#include "dw_dsi_reg.h"
> +
> +#define MAX_TX_ESC_CLK (10)
> +#define ROUND(x, y) ((x) / (y) + ((x) % (y) * 10 / (y) >= 5 ? 1 : 0))
> +#define PHY_REF_CLK_RATE 1920
> +#define PHY_REF_CLK_PERIOD_PS (10 / (PHY_REF_CLK_RATE / 1000))
> +
> +#define encoder_to_dsi(encoder) \
> + container_of(encoder, struct dw_dsi, encoder)
> +#define host_to_dsi(host) \
> + container_of(host, struct dw_dsi, host)
> +
> +struct mipi_phy_params {
> + u32 clk_t_lpx;
> + u32 clk_t_hs_prepare;
> + u32 clk_t_hs_zero;
> + u32 clk_t_hs_trial;
> + u32 clk_t_wakeup;
> + u32 data_t_lpx;
> + u32 data_t_hs_prepare;
> + u32 data_t_hs_zero;
> + u32 data_t_hs_trial;
> + u32 data_t_ta_go;
> + u32 data_t_ta_get;
> + u32 data_t_wakeup;
> + u32 hstx_ckg_sel;
> + u32 pll_fbd_div5f;
> + u32 pll_fbd_div1f;
> + u32 pll_fbd_2p;
> + u32 pll_enbwt;
> + u32 pll_fbd_p;
> + u32 pll_fbd_s;
> + u32 pll_pre_div1p;
> + u32 pll_pre_p;
> + u32 pll_vco_750M;
> + u32 pll_lpf_rs;
> + u32 pll_lpf_cs;
> + u32 clklp2hs_time;
> + u32 clkhs2lp_time;
> + u32 lp2hs_time;
> + u32 hs2lp_time;
> + u32 clk_to_data_delay;
> + u32 data_to_clk_delay;
> + u32 lane_byte_clk_kHz;
> + u32 clk_division;
> +};
> +
> +struct dsi_hw_ctx {
> + void __iomem *base;
> + struct clk *pclk;
> +};
> +
> +struct dw_dsi {
> + struct drm_encoder encoder;
> + struct drm_display_mode cur_mode;
> + struct dsi_hw_ctx *ctx;
> + struct mipi_phy_params phy;
> +
> + u32 lanes;
> + enum mipi_dsi_pixel_format format;
> + unsigned long mode_flags;
> + bool enable;
> +};
> +
> +struct dsi_data {
> + struct dw_dsi dsi;
> + struct dsi_hw_ctx ctx;
> +};
> +
> +struct dsi_phy_range {
> + u32 min_range_kHz;
> + u32 max_range_kHz;
> + u32 pll_vco_750M;
> + u32 hstx_ckg_sel;
> +};
> +
> +static const struct dsi_phy_range dphy_range_info[] = {
> + { 46875,62500, 1,7 },
> + { 62500,93750, 0,7 },
> + { 93750, 125000, 1,6 },
> + { 125000, 187500, 0,6 },
> + { 187500, 25, 1,5 },
> + { 25, 375000, 0,5 },
> + { 375000, 50, 1,
[PATCH v6 07/11] drm/hisilicon: Add designware dsi encoder driver
Add DesignWare MIPI DSI Host Controller v1.02 encoder driver
for hi6220 SoC.
v6:
- Change "pclk_dsi" to "pclk".
v5: None.
v4: None.
v3:
- Rename file name to dw_drm_dsi.c
- Make encoder type as DRM_MODE_ENCODER_DSI.
- A few cleanup.
v2:
- Remove abtraction layer.
Signed-off-by: Xinliang Liu
Signed-off-by: Xinwei Kong
Signed-off-by: Andy Green
---
drivers/gpu/drm/hisilicon/kirin/Kconfig | 1 +
drivers/gpu/drm/hisilicon/kirin/Makefile | 3 +-
drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c | 743 +++
drivers/gpu/drm/hisilicon/kirin/dw_dsi_reg.h | 83 +++
4 files changed, 829 insertions(+), 1 deletion(-)
create mode 100644 drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c
create mode 100644 drivers/gpu/drm/hisilicon/kirin/dw_dsi_reg.h
diff --git a/drivers/gpu/drm/hisilicon/kirin/Kconfig
b/drivers/gpu/drm/hisilicon/kirin/Kconfig
index 3ac4b8edeac1..de0d454c5c13 100644
--- a/drivers/gpu/drm/hisilicon/kirin/Kconfig
+++ b/drivers/gpu/drm/hisilicon/kirin/Kconfig
@@ -4,6 +4,7 @@ config DRM_HISI_KIRIN
select DRM_KMS_HELPER
select DRM_GEM_CMA_HELPER
select DRM_KMS_CMA_HELPER
+ select DRM_MIPI_DSI
help
Choose this option if you have a hisilicon Kirin chipsets(hi6220).
If M is selected the module will be called kirin-drm.
diff --git a/drivers/gpu/drm/hisilicon/kirin/Makefile
b/drivers/gpu/drm/hisilicon/kirin/Makefile
index 2a61ab006ddb..5dcd0d4328b6 100644
--- a/drivers/gpu/drm/hisilicon/kirin/Makefile
+++ b/drivers/gpu/drm/hisilicon/kirin/Makefile
@@ -1,4 +1,5 @@
kirin-drm-y := kirin_drm_drv.o \
- kirin_drm_ade.o
+ kirin_drm_ade.o \
+ dw_drm_dsi.o
obj-$(CONFIG_DRM_HISI_KIRIN) += kirin-drm.o
diff --git a/drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c
b/drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c
new file mode 100644
index ..8329148cc89d
--- /dev/null
+++ b/drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c
@@ -0,0 +1,743 @@
+/*
+ * DesignWare MIPI DSI Host Controller v1.02 driver
+ *
+ * Copyright (c) 2016 Linaro Limited.
+ * Copyright (c) 2014-2016 Hisilicon Limited.
+ *
+ * Author:
+ * Xinliang Liu
+ * Xinliang Liu
+ * Xinwei Kong
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#include
+#include
+#include
+
+#include
+#include
+#include
+#include
+#include
+
+#include "dw_dsi_reg.h"
+
+#define MAX_TX_ESC_CLK(10)
+#define ROUND(x, y) ((x) / (y) + ((x) % (y) * 10 / (y) >= 5 ? 1 : 0))
+#define PHY_REF_CLK_RATE 1920
+#define PHY_REF_CLK_PERIOD_PS (10 / (PHY_REF_CLK_RATE / 1000))
+
+#define encoder_to_dsi(encoder) \
+ container_of(encoder, struct dw_dsi, encoder)
+#define host_to_dsi(host) \
+ container_of(host, struct dw_dsi, host)
+
+struct mipi_phy_params {
+ u32 clk_t_lpx;
+ u32 clk_t_hs_prepare;
+ u32 clk_t_hs_zero;
+ u32 clk_t_hs_trial;
+ u32 clk_t_wakeup;
+ u32 data_t_lpx;
+ u32 data_t_hs_prepare;
+ u32 data_t_hs_zero;
+ u32 data_t_hs_trial;
+ u32 data_t_ta_go;
+ u32 data_t_ta_get;
+ u32 data_t_wakeup;
+ u32 hstx_ckg_sel;
+ u32 pll_fbd_div5f;
+ u32 pll_fbd_div1f;
+ u32 pll_fbd_2p;
+ u32 pll_enbwt;
+ u32 pll_fbd_p;
+ u32 pll_fbd_s;
+ u32 pll_pre_div1p;
+ u32 pll_pre_p;
+ u32 pll_vco_750M;
+ u32 pll_lpf_rs;
+ u32 pll_lpf_cs;
+ u32 clklp2hs_time;
+ u32 clkhs2lp_time;
+ u32 lp2hs_time;
+ u32 hs2lp_time;
+ u32 clk_to_data_delay;
+ u32 data_to_clk_delay;
+ u32 lane_byte_clk_kHz;
+ u32 clk_division;
+};
+
+struct dsi_hw_ctx {
+ void __iomem *base;
+ struct clk *pclk;
+};
+
+struct dw_dsi {
+ struct drm_encoder encoder;
+ struct drm_display_mode cur_mode;
+ struct dsi_hw_ctx *ctx;
+ struct mipi_phy_params phy;
+
+ u32 lanes;
+ enum mipi_dsi_pixel_format format;
+ unsigned long mode_flags;
+ bool enable;
+};
+
+struct dsi_data {
+ struct dw_dsi dsi;
+ struct dsi_hw_ctx ctx;
+};
+
+struct dsi_phy_range {
+ u32 min_range_kHz;
+ u32 max_range_kHz;
+ u32 pll_vco_750M;
+ u32 hstx_ckg_sel;
+};
+
+static const struct dsi_phy_range dphy_range_info[] = {
+ { 46875,62500, 1,7 },
+ { 62500,93750, 0,7 },
+ { 93750, 125000, 1,6 },
+ { 125000, 187500, 0,6 },
+ { 187500, 25, 1,5 },
+ { 25, 375000, 0,5 },
+ { 375000, 50, 1,4 },
+ { 50, 75, 0,4 },
+ { 75, 100, 1,0 },
+ { 100, 150, 0,0 }
+};
+
+static void dsi_get_phy_params(u32 phy_freq_kHz,
+ struct mipi_phy_params *phy)
+{
+
