[RFC 2/4] drm: exynos: add MDNIE post processor
Hi Ajay,
Thanks for the patch.
On 03/19/2014 03:22 PM, Ajay Kumar wrote:
> Add post processor ops for MDNIE and their support functions.
> Expose an interface for the FIMD to register MDNIE PP.
>
> Signed-off-by: Ajay Kumar
> Signed-off-by: Shirish S
> Signed-off-by: Rahul Sharma
> ---
> drivers/gpu/drm/exynos/Makefile| 2 +-
> drivers/gpu/drm/exynos/exynos_mdnie.c | 707
> +
> drivers/gpu/drm/exynos/exynos_mdnie_regs.h | 154 +++
> 3 files changed, 862 insertions(+), 1 deletion(-)
> create mode 100644 drivers/gpu/drm/exynos/exynos_mdnie.c
> create mode 100644 drivers/gpu/drm/exynos/exynos_mdnie_regs.h
>
> diff --git a/drivers/gpu/drm/exynos/Makefile b/drivers/gpu/drm/exynos/Makefile
> index 02dde22..653eab5 100644
> --- a/drivers/gpu/drm/exynos/Makefile
> +++ b/drivers/gpu/drm/exynos/Makefile
> @@ -10,7 +10,7 @@ exynosdrm-y := exynos_drm_drv.o exynos_drm_encoder.o \
>
> exynosdrm-$(CONFIG_DRM_EXYNOS_IOMMU) += exynos_drm_iommu.o
> exynosdrm-$(CONFIG_DRM_EXYNOS_DMABUF) += exynos_drm_dmabuf.o
> -exynosdrm-$(CONFIG_DRM_EXYNOS_FIMD) += exynos_drm_fimd.o
> +exynosdrm-$(CONFIG_DRM_EXYNOS_FIMD) += exynos_drm_fimd.o exynos_mdnie.o
Is there is a reason to not to create Kconfig entry?
> exynosdrm-$(CONFIG_DRM_EXYNOS_DSI) += exynos_drm_dsi.o
> exynosdrm-$(CONFIG_DRM_EXYNOS_DP)+= exynos_dp_core.o exynos_dp_reg.o
> exynosdrm-$(CONFIG_DRM_EXYNOS_HDMI) += exynos_hdmi.o exynos_mixer.o
> diff --git a/drivers/gpu/drm/exynos/exynos_mdnie.c
> b/drivers/gpu/drm/exynos/exynos_mdnie.c
> new file mode 100644
> index 000..a043853
> --- /dev/null
> +++ b/drivers/gpu/drm/exynos/exynos_mdnie.c
> @@ -0,0 +1,707 @@
> +/* drivers/gpu/drm/exynos/exynos_mdnie.c
> + *
> + * Samsung mDNIe driver
> + *
> + * Copyright (C) 2014 Samsung Electronics Co., Ltd.
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms of the GNU General Public License as published by the
> + * Free Software Foundation; either version 2 of the License, or (at your
> + * option) any later version.
> +*/
> +
> +#include
> +#include
> +#include
> +
> +#include
> +
> +#include
> +
> +#include "exynos_drm_drv.h"
> +#include "exynos_fimd_pp.h"
> +#include "exynos_mdnie_regs.h"
> +
> +#define GAMMA_RAMP_LENGTH17
> +#define COLOR_COMPONENTS 3
It is not used.
> +
> +#define MDNIE_ON 1
> +#define MDNIE_OFF0
You can drop these and use bool instead.
> +
> +#define PARAM_IN_RANGE(r, p, l, u) \
> + do {\
> + r = ((p >= l) && (p <= u)) ? 0 : 1; \
> + if (r) \
> + DRM_ERROR("Wrong param: %s:%llu\n", #p, (u64)p); \
> + } while (0)
I am not sure if it is applicable but you can try to replace it with clamp.
> +
> +struct exynos_mdnie_drm_gamma {
> + u8 gamma_r[GAMMA_RAMP_LENGTH];
> + u8 gamma_g[GAMMA_RAMP_LENGTH];
> + u8 gamma_b[GAMMA_RAMP_LENGTH];
> +};
> +
> +struct mdnie_conf_params {
> + u32 modules_enabled;
> + struct exynos_mdnie_drm_gamma gamma_params;
> + struct drm_exynos_mdnie_window win;
> + struct drm_mode_color_reproduction cr_params;
> + struct drm_mode_color_saturationcs_params;
> + struct drm_mode_edge_enhancementde_params;
> +};
> +
> +struct mdnie_context {
> + struct mdnie_conf_paramsparams;
> + struct clk *mdnie_mux_clk;
> + struct clk *mdnie_bus_clk;
> + struct clk *mdnie_src_clk;
> + struct clk *sclk_mout_fimd;
> + void __iomem*exynos_mdnie_base;
> + void __iomem*sysreg_disp1blk;
> + struct drm_display_mode mode;
> +};
> +
> +static void exynos_mdnie_unmask(struct mdnie_context *mdnie)
> +{
> + writel(!MDNIE_RELEASE_RFF_MASK_REGISTERS,
> + mdnie->exynos_mdnie_base +
> + MDNIE_RELEASE_RFF * sizeof(u32));
> +}
I see this function is called after many writes, why?
> +
> +static u32 mdnie_read(struct mdnie_context *mdnie, u32 reg)
> +{
> + return readl(mdnie->exynos_mdnie_base + reg * sizeof(u32)) &
> + MDNIE_REG_WIDTH;
> +}
By convention registers are addressed using byte offset.
> +
> +static void mdnie_write(struct mdnie_context *mdnie, u32 reg, u32 val)
> +{
> + writel(val & MDNIE_REG_WIDTH, mdnie->exynos_mdnie_base +
> + (reg & MDNIE_REG_OFFSET_LIMIT) * sizeof(u32));
> +
> + exynos_mdnie_unmask(mdnie);
> +}
> +
> +static void exynos_mdnie_bank_sel(struct mdnie_context *mdnie, int bank)
> +{
> + if (bank)
> + writel(MDNIE_TOP_R0_BANK1_SEL |
> + MDNIE_TOP_R0_SHADOW_SEL ,
> +
[RFC 2/4] drm: exynos: add MDNIE post processor
Hi Sachin,
On Wed, Mar 19, 2014 at 10:51 PM, Sachin Kamat wrote:
> Hi Ajay,
>
> On 19 March 2014 19:52, Ajay Kumar wrote:
> > Add post processor ops for MDNIE and their support functions.
> > Expose an interface for the FIMD to register MDNIE PP.
> >
> > Signed-off-by: Ajay Kumar
> > Signed-off-by: Shirish S
> > Signed-off-by: Rahul Sharma
> > ---
> > drivers/gpu/drm/exynos/Makefile| 2 +-
> > drivers/gpu/drm/exynos/exynos_mdnie.c | 707
> +
> > drivers/gpu/drm/exynos/exynos_mdnie_regs.h | 154 +++
> > 3 files changed, 862 insertions(+), 1 deletion(-)
> > create mode 100644 drivers/gpu/drm/exynos/exynos_mdnie.c
> > create mode 100644 drivers/gpu/drm/exynos/exynos_mdnie_regs.h
> >
> > diff --git a/drivers/gpu/drm/exynos/Makefile
> b/drivers/gpu/drm/exynos/Makefile
> > index 02dde22..653eab5 100644
> > --- a/drivers/gpu/drm/exynos/Makefile
> > +++ b/drivers/gpu/drm/exynos/Makefile
> > @@ -10,7 +10,7 @@ exynosdrm-y := exynos_drm_drv.o exynos_drm_encoder.o \
> >
> > exynosdrm-$(CONFIG_DRM_EXYNOS_IOMMU) += exynos_drm_iommu.o
> > exynosdrm-$(CONFIG_DRM_EXYNOS_DMABUF) += exynos_drm_dmabuf.o
> > -exynosdrm-$(CONFIG_DRM_EXYNOS_FIMD)+= exynos_drm_fimd.o
> > +exynosdrm-$(CONFIG_DRM_EXYNOS_FIMD)+= exynos_drm_fimd.o
> exynos_mdnie.o
> > exynosdrm-$(CONFIG_DRM_EXYNOS_DSI) += exynos_drm_dsi.o
> > exynosdrm-$(CONFIG_DRM_EXYNOS_DP) += exynos_dp_core.o
> exynos_dp_reg.o
> > exynosdrm-$(CONFIG_DRM_EXYNOS_HDMI)+= exynos_hdmi.o exynos_mixer.o
> > diff --git a/drivers/gpu/drm/exynos/exynos_mdnie.c
> b/drivers/gpu/drm/exynos/exynos_mdnie.c
> > new file mode 100644
> > index 000..a043853
> > --- /dev/null
> > +++ b/drivers/gpu/drm/exynos/exynos_mdnie.c
> > @@ -0,0 +1,707 @@
> > +/* drivers/gpu/drm/exynos/exynos_mdnie.c
> > + *
> > + * Samsung mDNIe driver
> > + *
> > + * Copyright (C) 2014 Samsung Electronics Co., Ltd.
> > + *
> > + * This program is free software; you can redistribute it and/or modify
> it
> > + * under the terms of the GNU General Public License as published by the
> > + * Free Software Foundation; either version 2 of the License, or (at
> your
> > + * option) any later version.
> > +*/
> > +
> > +#include
> > +#include
> > +#include
> > +
> > +#include
> > +
> > +#include
> > +
> > +#include "exynos_drm_drv.h"
> > +#include "exynos_fimd_pp.h"
> > +#include "exynos_mdnie_regs.h"
> > +
> > +#define GAMMA_RAMP_LENGTH 17
> > +#define COLOR_COMPONENTS 3
> > +
> > +#define MDNIE_ON 1
> > +#define MDNIE_OFF 0
> > +
> > +#define PARAM_IN_RANGE(r, p, l, u) \
> > + do {\
> > + r = ((p >= l) && (p <= u)) ? 0 : 1; \
> > + if (r) \
> > + DRM_ERROR("Wrong param: %s:%llu\n", #p, (u64)p);
> \
> > + } while (0)
> > +
>
> [snip]
>
> > +static int mdnie_set_color_saturation_params(
> > + struct mdnie_context *mdnie,
> > + const struct drm_mode_color_saturation *params)
> > +{
> > + int ret;
> > +
> > + PARAM_IN_RANGE(ret, params->hue_gain_red, HG_MIN, HG_MAX);
> > + PARAM_IN_RANGE(ret, params->hue_gain_green, HG_MIN, HG_MAX);
> > + PARAM_IN_RANGE(ret, params->hue_gain_blue, HG_MIN, HG_MAX);
> > + PARAM_IN_RANGE(ret, params->hue_gain_cyan, HG_MIN, HG_MAX);
> > + PARAM_IN_RANGE(ret, params->hue_gain_magenta, HG_MIN, HG_MAX);
> > + PARAM_IN_RANGE(ret, params->hue_gain_yellow, HG_MIN, HG_MAX);
> > + PARAM_IN_RANGE(ret, params->hue_gain_overall, HG_MIN, HG_MAX);
> > +
> > + if (ret)
> > + return -EINVAL;
>
> This would be applicable only for the last macro call as ret would get
> overwritten after
> each call.
>
> Nice catch. I will fix it.
>
> > + memcpy(>params.cs_params, params, sizeof(*params));
> > +
> > + return 0;
> > +}
> > +
> > +static int mdnie_set_color_reproduction_params(
> > + struct mdnie_context *mdnie,
> > + const struct drm_mode_color_reproduction *params)
> > +{
> > + int ret;
> > +
> > + PARAM_IN_RANGE(ret, params->red_rgb[0], CC_MIN, CC_MAX);
> > + PARAM_IN_RANGE(ret, params->red_rgb[1], CC_MIN, CC_MAX);
> > + PARAM_IN_RANGE(ret, params->red_rgb[2], CC_MIN, CC_MAX);
> > + PARAM_IN_RANGE(ret, params->green_rgb[0], CC_MIN, CC_MAX);
> > + PARAM_IN_RANGE(ret, params->green_rgb[1], CC_MIN, CC_MAX);
> > + PARAM_IN_RANGE(ret, params->green_rgb[2], CC_MIN, CC_MAX);
> > + PARAM_IN_RANGE(ret, params->blue_rgb[0], CC_MIN, CC_MAX);
> > + PARAM_IN_RANGE(ret, params->blue_rgb[1], CC_MIN, CC_MAX);
> > + PARAM_IN_RANGE(ret, params->blue_rgb[2], CC_MIN, CC_MAX);
> > + PARAM_IN_RANGE(ret, params->cyan_rgb[0], CC_MIN, CC_MAX);
> > + PARAM_IN_RANGE(ret, params->cyan_rgb[1], CC_MIN, CC_MAX);
> > + PARAM_IN_RANGE(ret, params->cyan_rgb[2], CC_MIN,
[RFC 2/4] drm: exynos: add MDNIE post processor
Hi Ajay,
On 19 March 2014 19:52, Ajay Kumar wrote:
> Add post processor ops for MDNIE and their support functions.
> Expose an interface for the FIMD to register MDNIE PP.
>
> Signed-off-by: Ajay Kumar
> Signed-off-by: Shirish S
> Signed-off-by: Rahul Sharma
> ---
> drivers/gpu/drm/exynos/Makefile| 2 +-
> drivers/gpu/drm/exynos/exynos_mdnie.c | 707
> +
> drivers/gpu/drm/exynos/exynos_mdnie_regs.h | 154 +++
> 3 files changed, 862 insertions(+), 1 deletion(-)
> create mode 100644 drivers/gpu/drm/exynos/exynos_mdnie.c
> create mode 100644 drivers/gpu/drm/exynos/exynos_mdnie_regs.h
>
> diff --git a/drivers/gpu/drm/exynos/Makefile b/drivers/gpu/drm/exynos/Makefile
> index 02dde22..653eab5 100644
> --- a/drivers/gpu/drm/exynos/Makefile
> +++ b/drivers/gpu/drm/exynos/Makefile
> @@ -10,7 +10,7 @@ exynosdrm-y := exynos_drm_drv.o exynos_drm_encoder.o \
>
> exynosdrm-$(CONFIG_DRM_EXYNOS_IOMMU) += exynos_drm_iommu.o
> exynosdrm-$(CONFIG_DRM_EXYNOS_DMABUF) += exynos_drm_dmabuf.o
> -exynosdrm-$(CONFIG_DRM_EXYNOS_FIMD)+= exynos_drm_fimd.o
> +exynosdrm-$(CONFIG_DRM_EXYNOS_FIMD)+= exynos_drm_fimd.o exynos_mdnie.o
> exynosdrm-$(CONFIG_DRM_EXYNOS_DSI) += exynos_drm_dsi.o
> exynosdrm-$(CONFIG_DRM_EXYNOS_DP) += exynos_dp_core.o exynos_dp_reg.o
> exynosdrm-$(CONFIG_DRM_EXYNOS_HDMI)+= exynos_hdmi.o exynos_mixer.o
> diff --git a/drivers/gpu/drm/exynos/exynos_mdnie.c
> b/drivers/gpu/drm/exynos/exynos_mdnie.c
> new file mode 100644
> index 000..a043853
> --- /dev/null
> +++ b/drivers/gpu/drm/exynos/exynos_mdnie.c
> @@ -0,0 +1,707 @@
> +/* drivers/gpu/drm/exynos/exynos_mdnie.c
> + *
> + * Samsung mDNIe driver
> + *
> + * Copyright (C) 2014 Samsung Electronics Co., Ltd.
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms of the GNU General Public License as published by the
> + * Free Software Foundation; either version 2 of the License, or (at your
> + * option) any later version.
> +*/
> +
> +#include
> +#include
> +#include
> +
> +#include
> +
> +#include
> +
> +#include "exynos_drm_drv.h"
> +#include "exynos_fimd_pp.h"
> +#include "exynos_mdnie_regs.h"
> +
> +#define GAMMA_RAMP_LENGTH 17
> +#define COLOR_COMPONENTS 3
> +
> +#define MDNIE_ON 1
> +#define MDNIE_OFF 0
> +
> +#define PARAM_IN_RANGE(r, p, l, u) \
> + do {\
> + r = ((p >= l) && (p <= u)) ? 0 : 1; \
> + if (r) \
> + DRM_ERROR("Wrong param: %s:%llu\n", #p, (u64)p); \
> + } while (0)
> +
[snip]
> +static int mdnie_set_color_saturation_params(
> + struct mdnie_context *mdnie,
> + const struct drm_mode_color_saturation *params)
> +{
> + int ret;
> +
> + PARAM_IN_RANGE(ret, params->hue_gain_red, HG_MIN, HG_MAX);
> + PARAM_IN_RANGE(ret, params->hue_gain_green, HG_MIN, HG_MAX);
> + PARAM_IN_RANGE(ret, params->hue_gain_blue, HG_MIN, HG_MAX);
> + PARAM_IN_RANGE(ret, params->hue_gain_cyan, HG_MIN, HG_MAX);
> + PARAM_IN_RANGE(ret, params->hue_gain_magenta, HG_MIN, HG_MAX);
> + PARAM_IN_RANGE(ret, params->hue_gain_yellow, HG_MIN, HG_MAX);
> + PARAM_IN_RANGE(ret, params->hue_gain_overall, HG_MIN, HG_MAX);
> +
> + if (ret)
> + return -EINVAL;
This would be applicable only for the last macro call as ret would get
overwritten after
each call.
> + memcpy(>params.cs_params, params, sizeof(*params));
> +
> + return 0;
> +}
> +
> +static int mdnie_set_color_reproduction_params(
> + struct mdnie_context *mdnie,
> + const struct drm_mode_color_reproduction *params)
> +{
> + int ret;
> +
> + PARAM_IN_RANGE(ret, params->red_rgb[0], CC_MIN, CC_MAX);
> + PARAM_IN_RANGE(ret, params->red_rgb[1], CC_MIN, CC_MAX);
> + PARAM_IN_RANGE(ret, params->red_rgb[2], CC_MIN, CC_MAX);
> + PARAM_IN_RANGE(ret, params->green_rgb[0], CC_MIN, CC_MAX);
> + PARAM_IN_RANGE(ret, params->green_rgb[1], CC_MIN, CC_MAX);
> + PARAM_IN_RANGE(ret, params->green_rgb[2], CC_MIN, CC_MAX);
> + PARAM_IN_RANGE(ret, params->blue_rgb[0], CC_MIN, CC_MAX);
> + PARAM_IN_RANGE(ret, params->blue_rgb[1], CC_MIN, CC_MAX);
> + PARAM_IN_RANGE(ret, params->blue_rgb[2], CC_MIN, CC_MAX);
> + PARAM_IN_RANGE(ret, params->cyan_rgb[0], CC_MIN, CC_MAX);
> + PARAM_IN_RANGE(ret, params->cyan_rgb[1], CC_MIN, CC_MAX);
> + PARAM_IN_RANGE(ret, params->cyan_rgb[2], CC_MIN, CC_MAX);
> + PARAM_IN_RANGE(ret, params->magenta_rgb[0], CC_MIN, CC_MAX);
> + PARAM_IN_RANGE(ret, params->magenta_rgb[1], CC_MIN, CC_MAX);
> + PARAM_IN_RANGE(ret, params->magenta_rgb[2], CC_MIN, CC_MAX);
> + PARAM_IN_RANGE(ret, params->yellow_rgb[0], CC_MIN, CC_MAX);
> + PARAM_IN_RANGE(ret, params->yellow_rgb[1],
[RFC 2/4] drm: exynos: add MDNIE post processor
Add post processor ops for MDNIE and their support functions.
Expose an interface for the FIMD to register MDNIE PP.
Signed-off-by: Ajay Kumar
Signed-off-by: Shirish S
Signed-off-by: Rahul Sharma
---
drivers/gpu/drm/exynos/Makefile| 2 +-
drivers/gpu/drm/exynos/exynos_mdnie.c | 707 +
drivers/gpu/drm/exynos/exynos_mdnie_regs.h | 154 +++
3 files changed, 862 insertions(+), 1 deletion(-)
create mode 100644 drivers/gpu/drm/exynos/exynos_mdnie.c
create mode 100644 drivers/gpu/drm/exynos/exynos_mdnie_regs.h
diff --git a/drivers/gpu/drm/exynos/Makefile b/drivers/gpu/drm/exynos/Makefile
index 02dde22..653eab5 100644
--- a/drivers/gpu/drm/exynos/Makefile
+++ b/drivers/gpu/drm/exynos/Makefile
@@ -10,7 +10,7 @@ exynosdrm-y := exynos_drm_drv.o exynos_drm_encoder.o \
exynosdrm-$(CONFIG_DRM_EXYNOS_IOMMU) += exynos_drm_iommu.o
exynosdrm-$(CONFIG_DRM_EXYNOS_DMABUF) += exynos_drm_dmabuf.o
-exynosdrm-$(CONFIG_DRM_EXYNOS_FIMD)+= exynos_drm_fimd.o
+exynosdrm-$(CONFIG_DRM_EXYNOS_FIMD)+= exynos_drm_fimd.o exynos_mdnie.o
exynosdrm-$(CONFIG_DRM_EXYNOS_DSI) += exynos_drm_dsi.o
exynosdrm-$(CONFIG_DRM_EXYNOS_DP) += exynos_dp_core.o exynos_dp_reg.o
exynosdrm-$(CONFIG_DRM_EXYNOS_HDMI)+= exynos_hdmi.o exynos_mixer.o
diff --git a/drivers/gpu/drm/exynos/exynos_mdnie.c
b/drivers/gpu/drm/exynos/exynos_mdnie.c
new file mode 100644
index 000..a043853
--- /dev/null
+++ b/drivers/gpu/drm/exynos/exynos_mdnie.c
@@ -0,0 +1,707 @@
+/* drivers/gpu/drm/exynos/exynos_mdnie.c
+ *
+ * Samsung mDNIe driver
+ *
+ * Copyright (C) 2014 Samsung Electronics Co., Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+*/
+
+#include
+#include
+#include
+
+#include
+
+#include
+
+#include "exynos_drm_drv.h"
+#include "exynos_fimd_pp.h"
+#include "exynos_mdnie_regs.h"
+
+#define GAMMA_RAMP_LENGTH 17
+#define COLOR_COMPONENTS 3
+
+#define MDNIE_ON 1
+#define MDNIE_OFF 0
+
+#define PARAM_IN_RANGE(r, p, l, u) \
+ do {\
+ r = ((p >= l) && (p <= u)) ? 0 : 1; \
+ if (r) \
+ DRM_ERROR("Wrong param: %s:%llu\n", #p, (u64)p); \
+ } while (0)
+
+struct exynos_mdnie_drm_gamma {
+ u8 gamma_r[GAMMA_RAMP_LENGTH];
+ u8 gamma_g[GAMMA_RAMP_LENGTH];
+ u8 gamma_b[GAMMA_RAMP_LENGTH];
+};
+
+struct mdnie_conf_params {
+ u32 modules_enabled;
+ struct exynos_mdnie_drm_gamma gamma_params;
+ struct drm_exynos_mdnie_window win;
+ struct drm_mode_color_reproduction cr_params;
+ struct drm_mode_color_saturationcs_params;
+ struct drm_mode_edge_enhancementde_params;
+};
+
+struct mdnie_context {
+ struct mdnie_conf_paramsparams;
+ struct clk *mdnie_mux_clk;
+ struct clk *mdnie_bus_clk;
+ struct clk *mdnie_src_clk;
+ struct clk *sclk_mout_fimd;
+ void __iomem*exynos_mdnie_base;
+ void __iomem*sysreg_disp1blk;
+ struct drm_display_mode mode;
+};
+
+static void exynos_mdnie_unmask(struct mdnie_context *mdnie)
+{
+ writel(!MDNIE_RELEASE_RFF_MASK_REGISTERS,
+ mdnie->exynos_mdnie_base +
+ MDNIE_RELEASE_RFF * sizeof(u32));
+}
+
+static u32 mdnie_read(struct mdnie_context *mdnie, u32 reg)
+{
+ return readl(mdnie->exynos_mdnie_base + reg * sizeof(u32)) &
+ MDNIE_REG_WIDTH;
+}
+
+static void mdnie_write(struct mdnie_context *mdnie, u32 reg, u32 val)
+{
+ writel(val & MDNIE_REG_WIDTH, mdnie->exynos_mdnie_base +
+ (reg & MDNIE_REG_OFFSET_LIMIT) * sizeof(u32));
+
+ exynos_mdnie_unmask(mdnie);
+}
+
+static void exynos_mdnie_bank_sel(struct mdnie_context *mdnie, int bank)
+{
+ if (bank)
+ writel(MDNIE_TOP_R0_BANK1_SEL |
+ MDNIE_TOP_R0_SHADOW_SEL ,
+ mdnie->exynos_mdnie_base);
+ else
+ writel(MDNIE_TOP_R0_BANK0_SEL |
+ MDNIE_TOP_R0_SHADOW_SEL ,
+ mdnie->exynos_mdnie_base);
+
+ exynos_mdnie_unmask(mdnie);
+}
+
+static int exynos_mdnie_set_size(struct mdnie_context *mdnie)
+{
+ unsigned int cfg;
+
+ if ((mdnie->mode.crtc_hdisplay > MDNIE_TOP_RSIZE_MAX) ||
+ (mdnie->mode.crtc_vdisplay > MDNIE_TOP_RSIZE_MAX))
+ return -EINVAL;
+
+
