[RFC PATCH 02/14] drm/exynos: dsi: delay setting clocks after reset
Hi Andrzej Thank you for comments. On 04/18/2014 09:15 PM, Andrzej Hajda wrote: > Hi YoungJun, > > Thanks for the whole patchset. > > On 04/15/2014 07:47 AM, YoungJun Cho wrote: >> Some phy control registers are not kept after software reset. >> So this patch makes the clocks containing phy control to be set >> after software reset. >> >> Signed-off-by: YoungJun Cho >> Signed-off-by: Inki Dae >> Signed-off-by: Kyungmin Park >> --- >> drivers/gpu/drm/exynos/exynos_drm_dsi.c |2 +- >> 1 file changed, 1 insertion(+), 1 deletion(-) >> >> diff --git a/drivers/gpu/drm/exynos/exynos_drm_dsi.c >> b/drivers/gpu/drm/exynos/exynos_drm_dsi.c >> index 956e5f3..2cf1f0b 100644 >> --- a/drivers/gpu/drm/exynos/exynos_drm_dsi.c >> +++ b/drivers/gpu/drm/exynos/exynos_drm_dsi.c >> @@ -946,10 +946,10 @@ static irqreturn_t exynos_dsi_irq(int irq, void >> *dev_id) >> >> static int exynos_dsi_init(struct exynos_dsi *dsi) >> { >> -exynos_dsi_enable_clock(dsi); >> exynos_dsi_reset(dsi); >> enable_irq(dsi->irq); >> exynos_dsi_wait_for_reset(dsi); >> +exynos_dsi_enable_clock(dsi); >> exynos_dsi_init_link(dsi); >> >> return 0; > Are you sure this sequence is OK? I have observed that sequence: > > dsi power off > dsi power on > dsi_reset > > on 4210 or 4412 resulted in lack of irq after reset, only enabling > clocks helped. > And according to documentation reset do not touch registers set by > exynos_dsi_enable_clock, > so the current solution should work. As I mentioned in description, it came from phy control registers. Fortunately Exynos4 SoCs are safe, but the DSIM_PHYCTRL_REG, DSIM_PHYTIMING_REG, DSIM_PHYTIMING1_REG and DSIM_PHYTIMING2_REG are affected which are used in exynos_dsi_set_pll() for Exynos5 SoCs. So this patch is required for Exynos5 SoCs. Thank you best regards YJ > > Regards > Andrzej >
[RFC PATCH 02/14] drm/exynos: dsi: delay setting clocks after reset
Hi YoungJun, Thanks for the whole patchset. On 04/15/2014 07:47 AM, YoungJun Cho wrote: > Some phy control registers are not kept after software reset. > So this patch makes the clocks containing phy control to be set > after software reset. > > Signed-off-by: YoungJun Cho > Signed-off-by: Inki Dae > Signed-off-by: Kyungmin Park > --- > drivers/gpu/drm/exynos/exynos_drm_dsi.c |2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/exynos/exynos_drm_dsi.c > b/drivers/gpu/drm/exynos/exynos_drm_dsi.c > index 956e5f3..2cf1f0b 100644 > --- a/drivers/gpu/drm/exynos/exynos_drm_dsi.c > +++ b/drivers/gpu/drm/exynos/exynos_drm_dsi.c > @@ -946,10 +946,10 @@ static irqreturn_t exynos_dsi_irq(int irq, void *dev_id) > > static int exynos_dsi_init(struct exynos_dsi *dsi) > { > - exynos_dsi_enable_clock(dsi); > exynos_dsi_reset(dsi); > enable_irq(dsi->irq); > exynos_dsi_wait_for_reset(dsi); > + exynos_dsi_enable_clock(dsi); > exynos_dsi_init_link(dsi); > > return 0; Are you sure this sequence is OK? I have observed that sequence: dsi power off dsi power on dsi_reset on 4210 or 4412 resulted in lack of irq after reset, only enabling clocks helped. And according to documentation reset do not touch registers set by exynos_dsi_enable_clock, so the current solution should work. Regards Andrzej
[RFC PATCH 02/14] drm/exynos: dsi: delay setting clocks after reset
Some phy control registers are not kept after software reset. So this patch makes the clocks containing phy control to be set after software reset. Signed-off-by: YoungJun Cho Signed-off-by: Inki Dae Signed-off-by: Kyungmin Park --- drivers/gpu/drm/exynos/exynos_drm_dsi.c |2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/exynos/exynos_drm_dsi.c b/drivers/gpu/drm/exynos/exynos_drm_dsi.c index 956e5f3..2cf1f0b 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_dsi.c +++ b/drivers/gpu/drm/exynos/exynos_drm_dsi.c @@ -946,10 +946,10 @@ static irqreturn_t exynos_dsi_irq(int irq, void *dev_id) static int exynos_dsi_init(struct exynos_dsi *dsi) { - exynos_dsi_enable_clock(dsi); exynos_dsi_reset(dsi); enable_irq(dsi->irq); exynos_dsi_wait_for_reset(dsi); + exynos_dsi_enable_clock(dsi); exynos_dsi_init_link(dsi); return 0; -- 1.7.9.5