Re: [RFC PATCH 1/8] drm/panel: nv3052c: Document known register names

2023-09-18 Thread John Watts 
On Wed, Sep 13, 2023 at 02:43:43PM -0700, Jessica Zhang wrote:
> Hi John,
> 
> Just curious, what do you mean by these registers being mostly unknown?
> 
> I do see them specified in the online specs -- some even seem to map to
> existing MIPI_DCS_* enums (ex. 0x01 to MIPI_DCS_SOFT_RESET, and 0x04 to
> MIPI_DCS_GET_DISPLAY_ID).
> 
> Thanks,
> 
> Jessica Zhang

Hi Jessica,

Unfortunately these registers are not MIPI ones, but on a separate page of
registers. So page 2 register 1 isn't MIPI_DCS_SOFT_RESET, that is page 0
register 1.

John.

Re: [RFC PATCH 1/8] drm/panel: nv3052c: Document known register names

2023-09-14 Thread Jessica Zhang 




On 9/13/2023 9:12 PM, John Watts wrote:

On Wed, Sep 13, 2023 at 02:43:43PM -0700, Jessica Zhang wrote:

Hi John,

Just curious, what do you mean by these registers being mostly unknown?

I do see them specified in the online specs -- some even seem to map to
existing MIPI_DCS_* enums (ex. 0x01 to MIPI_DCS_SOFT_RESET, and 0x04 to
MIPI_DCS_GET_DISPLAY_ID).

Thanks,

Jessica Zhang


Hi Jessica,

Unfortunately these registers are not MIPI ones, but on a separate page of
registers. So page 2 register 1 isn't MIPI_DCS_SOFT_RESET, that is page 0
register 1.


Got it -- thanks for the explanation.

In that case,

Reviewed-by: Jessica Zhang 

Thanks,

Jessica Zhang



John.

Re: [RFC PATCH 1/8] drm/panel: nv3052c: Document known register names

2023-09-13 Thread Jessica Zhang 




On 9/11/2023 2:01 AM, John Watts wrote:

Many of these registers have a known name in the public datasheet.
Document them as comments for reference.

Signed-off-by: John Watts 
---
  .../gpu/drm/panel/panel-newvision-nv3052c.c   | 261 +-
  1 file changed, 132 insertions(+), 129 deletions(-)

diff --git a/drivers/gpu/drm/panel/panel-newvision-nv3052c.c 
b/drivers/gpu/drm/panel/panel-newvision-nv3052c.c
index 71e57de6d8b2..589431523ce7 100644
--- a/drivers/gpu/drm/panel/panel-newvision-nv3052c.c
+++ b/drivers/gpu/drm/panel/panel-newvision-nv3052c.c
@@ -42,9 +42,9 @@ struct nv3052c_reg {
  };
  
  static const struct nv3052c_reg nv3052c_panel_regs[] = {

-   { 0xff, 0x30 },
-   { 0xff, 0x52 },
-   { 0xff, 0x01 },
+   // EXTC Command set enable, select page 1
+   { 0xff, 0x30 }, { 0xff, 0x52 }, { 0xff, 0x01 },
+   // Mostly unknown registers


Hi John,

Just curious, what do you mean by these registers being mostly unknown?

I do see them specified in the online specs -- some even seem to map to 
existing MIPI_DCS_* enums (ex. 0x01 to MIPI_DCS_SOFT_RESET, and 0x04 to 
MIPI_DCS_GET_DISPLAY_ID).


Thanks,

Jessica Zhang


{ 0xe3, 0x00 },
{ 0x40, 0x00 },
{ 0x03, 0x40 },
@@ -62,15 +62,15 @@ static const struct nv3052c_reg nv3052c_panel_regs[] = {
{ 0x25, 0x06 },
{ 0x26, 0x14 },
{ 0x27, 0x14 },
-   { 0x38, 0xcc },
-   { 0x39, 0xd7 },
-   { 0x3a, 0x4a },
+   { 0x38, 0xcc }, // VCOM_ADJ1
+   { 0x39, 0xd7 }, // VCOM_ADJ2
+   { 0x3a, 0x4a }, // VCOM_ADJ3
{ 0x28, 0x40 },
{ 0x29, 0x01 },
{ 0x2a, 0xdf },
{ 0x49, 0x3c },
-   { 0x91, 0x77 },
-   { 0x92, 0x77 },
+   { 0x91, 0x77 }, // EXTPW_CTRL2
+   { 0x92, 0x77 }, // EXTPW_CTRL3
{ 0xa0, 0x55 },
{ 0xa1, 0x50 },
{ 0xa4, 0x9c },
@@ -94,123 +94,126 @@ static const struct nv3052c_reg nv3052c_panel_regs[] = {
{ 0xb8, 0x26 },
{ 0xf0, 0x00 },
{ 0xf6, 0xc0 },
-   { 0xff, 0x30 },
-   { 0xff, 0x52 },
-   { 0xff, 0x02 },
-   { 0xb0, 0x0b },
-   { 0xb1, 0x16 },
-   { 0xb2, 0x17 },
-   { 0xb3, 0x2c },
-   { 0xb4, 0x32 },
-   { 0xb5, 0x3b },
-   { 0xb6, 0x29 },
-   { 0xb7, 0x40 },
-   { 0xb8, 0x0d },
-   { 0xb9, 0x05 },
-   { 0xba, 0x12 },
-   { 0xbb, 0x10 },
-   { 0xbc, 0x12 },
-   { 0xbd, 0x15 },
-   { 0xbe, 0x19 },
-   { 0xbf, 0x0e },
-   { 0xc0, 0x16 },
-   { 0xc1, 0x0a },
-   { 0xd0, 0x0c },
-   { 0xd1, 0x17 },
-   { 0xd2, 0x14 },
-   { 0xd3, 0x2e },
-   { 0xd4, 0x32 },
-   { 0xd5, 0x3c },
-   { 0xd6, 0x22 },
-   { 0xd7, 0x3d },
-   { 0xd8, 0x0d },
-   { 0xd9, 0x07 },
-   { 0xda, 0x13 },
-   { 0xdb, 0x13 },
-   { 0xdc, 0x11 },
-   { 0xdd, 0x15 },
-   { 0xde, 0x19 },
-   { 0xdf, 0x10 },
-   { 0xe0, 0x17 },
-   { 0xe1, 0x0a },
-   { 0xff, 0x30 },
-   { 0xff, 0x52 },
-   { 0xff, 0x03 },
-   { 0x00, 0x2a },
-   { 0x01, 0x2a },
-   { 0x02, 0x2a },
-   { 0x03, 0x2a },
-   { 0x04, 0x61 },
-   { 0x05, 0x80 },
-   { 0x06, 0xc7 },
-   { 0x07, 0x01 },
-   { 0x08, 0x03 },
-   { 0x09, 0x04 },
-   { 0x70, 0x22 },
-   { 0x71, 0x80 },
-   { 0x30, 0x2a },
-   { 0x31, 0x2a },
-   { 0x32, 0x2a },
-   { 0x33, 0x2a },
-   { 0x34, 0x61 },
-   { 0x35, 0xc5 },
-   { 0x36, 0x80 },
-   { 0x37, 0x23 },
-   { 0x40, 0x03 },
-   { 0x41, 0x04 },
-   { 0x42, 0x05 },
-   { 0x43, 0x06 },
-   { 0x44, 0x11 },
-   { 0x45, 0xe8 },
-   { 0x46, 0xe9 },
-   { 0x47, 0x11 },
-   { 0x48, 0xea },
-   { 0x49, 0xeb },
-   { 0x50, 0x07 },
-   { 0x51, 0x08 },
-   { 0x52, 0x09 },
-   { 0x53, 0x0a },
-   { 0x54, 0x11 },
-   { 0x55, 0xec },
-   { 0x56, 0xed },
-   { 0x57, 0x11 },
-   { 0x58, 0xef },
-   { 0x59, 0xf0 },
-   { 0xb1, 0x01 },
-   { 0xb4, 0x15 },
-   { 0xb5, 0x16 },
-   { 0xb6, 0x09 },
-   { 0xb7, 0x0f },
-   { 0xb8, 0x0d },
-   { 0xb9, 0x0b },
-   { 0xba, 0x00 },
-   { 0xc7, 0x02 },
-   { 0xca, 0x17 },
-   { 0xcb, 0x18 },
-   { 0xcc, 0x0a },
-   { 0xcd, 0x10 },
-   { 0xce, 0x0e },
-   { 0xcf, 0x0c },
-   { 0xd0, 0x00 },
-   { 0x81, 0x00 },
-   { 0x84, 0x15 },
-   { 0x85, 0x16 },
-   { 0x86, 0x10 },
-   { 0x87, 0x0a },
-   { 0x88, 0x0c },
-   { 0x89, 0x0e },
-   { 0x8a, 0x02 },
-   { 0x97, 0x00 },
-   { 0x9a, 0x17 },
-   { 0x9b, 0x18 },
-   { 0x9c, 0x0f },
-   { 0x9d, 0x09 },
-   { 0x9e, 0x0b },
-   { 0x9f, 0x0d },
-   { 0xa0, 0x01 },
-   { 0xff, 0x30 },
-   { 0xff, 0x52 },
-   { 0xff, 0x02 },
+   // EXTC Command set enable, select page 2
+   { 0xff, 0x30 }, { 0xff, 0x52 }, { 0xff, 0x02 },
+   // Set gray scale voltage to adjust gamma
+

[RFC PATCH 1/8] drm/panel: nv3052c: Document known register names

2023-09-12 Thread John Watts 
Many of these registers have a known name in the public datasheet.
Document them as comments for reference.

Signed-off-by: John Watts 
---
 .../gpu/drm/panel/panel-newvision-nv3052c.c   | 261 +-
 1 file changed, 132 insertions(+), 129 deletions(-)

diff --git a/drivers/gpu/drm/panel/panel-newvision-nv3052c.c 
b/drivers/gpu/drm/panel/panel-newvision-nv3052c.c
index 71e57de6d8b2..589431523ce7 100644
--- a/drivers/gpu/drm/panel/panel-newvision-nv3052c.c
+++ b/drivers/gpu/drm/panel/panel-newvision-nv3052c.c
@@ -42,9 +42,9 @@ struct nv3052c_reg {
 };
 
 static const struct nv3052c_reg nv3052c_panel_regs[] = {
-   { 0xff, 0x30 },
-   { 0xff, 0x52 },
-   { 0xff, 0x01 },
+   // EXTC Command set enable, select page 1
+   { 0xff, 0x30 }, { 0xff, 0x52 }, { 0xff, 0x01 },
+   // Mostly unknown registers
{ 0xe3, 0x00 },
{ 0x40, 0x00 },
{ 0x03, 0x40 },
@@ -62,15 +62,15 @@ static const struct nv3052c_reg nv3052c_panel_regs[] = {
{ 0x25, 0x06 },
{ 0x26, 0x14 },
{ 0x27, 0x14 },
-   { 0x38, 0xcc },
-   { 0x39, 0xd7 },
-   { 0x3a, 0x4a },
+   { 0x38, 0xcc }, // VCOM_ADJ1
+   { 0x39, 0xd7 }, // VCOM_ADJ2
+   { 0x3a, 0x4a }, // VCOM_ADJ3
{ 0x28, 0x40 },
{ 0x29, 0x01 },
{ 0x2a, 0xdf },
{ 0x49, 0x3c },
-   { 0x91, 0x77 },
-   { 0x92, 0x77 },
+   { 0x91, 0x77 }, // EXTPW_CTRL2
+   { 0x92, 0x77 }, // EXTPW_CTRL3
{ 0xa0, 0x55 },
{ 0xa1, 0x50 },
{ 0xa4, 0x9c },
@@ -94,123 +94,126 @@ static const struct nv3052c_reg nv3052c_panel_regs[] = {
{ 0xb8, 0x26 },
{ 0xf0, 0x00 },
{ 0xf6, 0xc0 },
-   { 0xff, 0x30 },
-   { 0xff, 0x52 },
-   { 0xff, 0x02 },
-   { 0xb0, 0x0b },
-   { 0xb1, 0x16 },
-   { 0xb2, 0x17 },
-   { 0xb3, 0x2c },
-   { 0xb4, 0x32 },
-   { 0xb5, 0x3b },
-   { 0xb6, 0x29 },
-   { 0xb7, 0x40 },
-   { 0xb8, 0x0d },
-   { 0xb9, 0x05 },
-   { 0xba, 0x12 },
-   { 0xbb, 0x10 },
-   { 0xbc, 0x12 },
-   { 0xbd, 0x15 },
-   { 0xbe, 0x19 },
-   { 0xbf, 0x0e },
-   { 0xc0, 0x16 },
-   { 0xc1, 0x0a },
-   { 0xd0, 0x0c },
-   { 0xd1, 0x17 },
-   { 0xd2, 0x14 },
-   { 0xd3, 0x2e },
-   { 0xd4, 0x32 },
-   { 0xd5, 0x3c },
-   { 0xd6, 0x22 },
-   { 0xd7, 0x3d },
-   { 0xd8, 0x0d },
-   { 0xd9, 0x07 },
-   { 0xda, 0x13 },
-   { 0xdb, 0x13 },
-   { 0xdc, 0x11 },
-   { 0xdd, 0x15 },
-   { 0xde, 0x19 },
-   { 0xdf, 0x10 },
-   { 0xe0, 0x17 },
-   { 0xe1, 0x0a },
-   { 0xff, 0x30 },
-   { 0xff, 0x52 },
-   { 0xff, 0x03 },
-   { 0x00, 0x2a },
-   { 0x01, 0x2a },
-   { 0x02, 0x2a },
-   { 0x03, 0x2a },
-   { 0x04, 0x61 },
-   { 0x05, 0x80 },
-   { 0x06, 0xc7 },
-   { 0x07, 0x01 },
-   { 0x08, 0x03 },
-   { 0x09, 0x04 },
-   { 0x70, 0x22 },
-   { 0x71, 0x80 },
-   { 0x30, 0x2a },
-   { 0x31, 0x2a },
-   { 0x32, 0x2a },
-   { 0x33, 0x2a },
-   { 0x34, 0x61 },
-   { 0x35, 0xc5 },
-   { 0x36, 0x80 },
-   { 0x37, 0x23 },
-   { 0x40, 0x03 },
-   { 0x41, 0x04 },
-   { 0x42, 0x05 },
-   { 0x43, 0x06 },
-   { 0x44, 0x11 },
-   { 0x45, 0xe8 },
-   { 0x46, 0xe9 },
-   { 0x47, 0x11 },
-   { 0x48, 0xea },
-   { 0x49, 0xeb },
-   { 0x50, 0x07 },
-   { 0x51, 0x08 },
-   { 0x52, 0x09 },
-   { 0x53, 0x0a },
-   { 0x54, 0x11 },
-   { 0x55, 0xec },
-   { 0x56, 0xed },
-   { 0x57, 0x11 },
-   { 0x58, 0xef },
-   { 0x59, 0xf0 },
-   { 0xb1, 0x01 },
-   { 0xb4, 0x15 },
-   { 0xb5, 0x16 },
-   { 0xb6, 0x09 },
-   { 0xb7, 0x0f },
-   { 0xb8, 0x0d },
-   { 0xb9, 0x0b },
-   { 0xba, 0x00 },
-   { 0xc7, 0x02 },
-   { 0xca, 0x17 },
-   { 0xcb, 0x18 },
-   { 0xcc, 0x0a },
-   { 0xcd, 0x10 },
-   { 0xce, 0x0e },
-   { 0xcf, 0x0c },
-   { 0xd0, 0x00 },
-   { 0x81, 0x00 },
-   { 0x84, 0x15 },
-   { 0x85, 0x16 },
-   { 0x86, 0x10 },
-   { 0x87, 0x0a },
-   { 0x88, 0x0c },
-   { 0x89, 0x0e },
-   { 0x8a, 0x02 },
-   { 0x97, 0x00 },
-   { 0x9a, 0x17 },
-   { 0x9b, 0x18 },
-   { 0x9c, 0x0f },
-   { 0x9d, 0x09 },
-   { 0x9e, 0x0b },
-   { 0x9f, 0x0d },
-   { 0xa0, 0x01 },
-   { 0xff, 0x30 },
-   { 0xff, 0x52 },
-   { 0xff, 0x02 },
+   // EXTC Command set enable, select page 2
+   { 0xff, 0x30 }, { 0xff, 0x52 }, { 0xff, 0x02 },
+   // Set gray scale voltage to adjust gamma
+   { 0xb0, 0x0b }, // PGAMVR0
+   { 0xb1, 0x16 }, // PGAMVR1
+   { 0xb2, 0x17 }, // PGAMVR2
+   { 0xb3, 0x2c }, // PGAMVR3
+   { 0xb4, 0x32 }, // PGAMVR4
+   { 0xb5, 0x3b }, // PGAMVR5
+   { 0xb6, 0x29 }, // PGAMPR0
+   { 0xb7, 0x40 }, // PGAMPR1
+   { 0xb8, 0x0d }, // PGAMPK0
+   { 0xb9, 0x05 }, //