On Thu, 2016-01-14 at 16:24 +0100, Maxime Ripard wrote:
> The Allwinner A10 and subsequent SoCs share the same display pipeline, with
> variations in the number of controllers (1 or 2), or the presence or not of
> some output (HDMI, TV, VGA) or not.
>Â
> Add a driver with a limited set of features for now, and we will hopefully
> support all of them eventually
>Â
[..]
> diff --git a/drivers/gpu/drm/sun4i/sun4i_backend.h
> b/drivers/gpu/drm/sun4i/sun4i_backend.h
> new file mode 100644
> index ..60f6a200fa73
> --- /dev/null
> +++ b/drivers/gpu/drm/sun4i/sun4i_backend.h
> @@ -0,0 +1,160 @@
> +/*
> + * Copyright (C) 2015 Free Electrons
> + * Copyright (C) 2015 NextThing Co
> + *
> + * Maxime Ripard
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + */
> +
> +#ifndef _SUN4I_BACKEND_H_
> +#define _SUN4I_BACKEND_H_
> +
> +#include
> +#include
> +
> +#define SUN4I_BACKEND_MODCTL_REG 0x800
> +#define SUN4I_BACKEND_MODCTL_LINE_SELBIT(29)
> +#define SUN4I_BACKEND_MODCTL_ITLMOD_EN BIT(28
> )
> +#define SUN4I_BACKEND_MODCTL_OUT_SEL GENMASK(
> 22, 20)
> +#define SUN4I_BACKEND_MODCTL_OUT_LCD
> (0 << 20)
> +#define SUN4I_BACKEND_MODCTL_OUT_FE0
> (6 << 20)
> +#define SUN4I_BACKEND_MODCTL_OUT_FE1
> (7 << 20)
> +#define SUN4I_BACKEND_MODCTL_HWC_EN BIT(16)
> +#define SUN4I_BACKEND_MODCTL_LAY_EN(l) BIT(8
> + l)
> +#define SUN4I_BACKEND_MODCTL_OCSC_EN BIT(5)
> +#define SUN4I_BACKEND_MODCTL_DFLK_EN BIT(4)
> +#define SUN4I_BACKEND_MODCTL_DLP_START_CTL BIT(2)
> +#define SUN4I_BACKEND_MODCTL_START_CTL BIT(1)
> +#define SUN4I_BACKEND_MODCTL_DEBE_EN BIT(0)
> +
> +#define SUN4I_BACKEND_BACKCOLOR_REG 0x804
> +#define SUN4I_BACKEND_BACKCOLOR(r, g, b) (((r) << 16)
> | ((g) << 8) | (b))
> +
> +#define SUN4I_BACKEND_DISSIZE_REG0x808
> +#define SUN4I_BACKEND_DISSIZE(w, h) (h) -
> 1) & 0x) << 16) | \
> + Â (((w) - 1)
> & 0x))
> +
> +#define SUN4I_BACKEND_LAYSIZE_REG(l) (0x810 + (0x4 *
> (l)))
> +#define SUN4I_BACKEND_LAYSIZE(w, h) (h) -
> 1) & 0x1fff) << 16) | \
> + Â (((w) - 1)
> & 0x1fff))
> +
> +#define SUN4I_BACKEND_LAYCOOR_REG(l) (0x820 + (0x4 *
> (l)))
> +#define SUN4I_BACKEND_LAYCOOR(x, y) u32)(
> y) & 0x) << 16) | \
> + Â ((u32)(x) &
> 0x))
> +
> +#define SUN4I_BACKEND_LAYLINEWIDTH_REG(l)(0x840 + (0x4 *
> (l)))
> +
> +#define SUN4I_BACKEND_LAYFB_L32ADD_REG(l)(0x850 + (0x4 *
> (l)))
> +
> +#define SUN4I_BACKEND_LAYFB_H4ADD_REG0x860
> +#define SUN4I_BACKEND_LAYFB_H4ADD_MSK(l) GENMASK(3 +
> ((l) * 8), 0)
> +#define SUN4I_BACKEND_LAYFB_H4ADD(l, val)((v
> al) << ((l) * 8))
> +
> +#define SUN4I_BACKEND_REGBUFFCTL_REG 0x870
> +#define SUN4I_BACKEND_REGBUFFCTL_AUTOLOAD_DISBIT(1)
> +#define SUN4I_BACKEND_REGBUFFCTL_LOADCTL BIT(0)
> +
> +#define SUN4I_BACKEND_CKMAX_REG 0x880
> +#define SUN4I_BACKEND_CKMIN_REG 0x884
> +#define SUN4I_BACKEND_CKCFG_REG 0x888
> +#define SUN4I_BACKEND_ATTCTL_REG0(l) (0x890 + (0x4 *
> (l)))
> +#define SUN4I_BACKEND_ATTCTL_REG0_LAY_PIPESEL_MASK BIT(15)
> +#define SUN4I_BACKEND_ATTCTL_REG0_LAY_PIPESEL(x) ((x)
> << 15)
> +#define SUN4I_BACKEND_ATTCTL_REG0_LAY_PRISEL_MASKGENMASK(11,
> 10)
> +#define SUN4I_BACKEND_ATTCTL_REG0_LAY_PRISEL(x)
> ((x) << 10)
> +
> +#define SUN4I_BACKEND_ATTCTL_REG1(l) (0x8a0 + (0x4 *
> (l)))
> +#define SUN4I_BACKEND_ATTCTL_REG1_LAY_HSCAFCTGENMASK
> (15, 14)
> +#define SUN4I_BACKEND_ATTCTL_REG1_LAY_WSCAFCTGENMASK
> (13, 12)
> +#define SUN4I_BACKEND_ATTCTL_REG1_LAY_FBFMT GENMASK(1
> 1, 8)
> +#define SUN4I_BACKEND_LAY_FBFMT_1BPP
> (0 << 8)
> +#define SUN4I_BACKEND_LAY_FBFMT_2BPP
> (1 << 8)
> +#define SUN4I_BACKEND_LAY_FBFMT_4BPP
> (2 << 8)
> +#define SUN4I_BACKEND_LAY_FBFMT_8BPP
> (3 << 8)
> +#define SUN4I_BACKEND_LAY_FBFMT_RGB655
> (4 << 8)
> +#define SUN4I_BACKEND_LAY_FBFMT_RGB565
> (5 << 8)
> +#define SUN4I_BACKEND_LAY_FBFMT_RGB556
> (6 << 8)
> +#define SUN4I_BACKEND_LAY_FBFMT_
