Re: [v4 3/3] drm/mediatek: add mipi_tx driver for mt8183
Hi, Jitao:
On Sat, 2019-06-01 at 17:52 +0800, Jitao Shi wrote:
> This patch add mt8183 mipi_tx driver.
> And also support other chips that use the same binding and driver.
>
> Signed-off-by: Jitao Shi
> ---
> drivers/gpu/drm/mediatek/Makefile | 1 +
> drivers/gpu/drm/mediatek/mtk_mipi_tx.c| 2 +
> drivers/gpu/drm/mediatek/mtk_mipi_tx.h| 1 +
> drivers/gpu/drm/mediatek/mtk_mt8183_mipi_tx.c | 162
> ++
> 4 files changed, 166 insertions(+)
> create mode 100644 drivers/gpu/drm/mediatek/mtk_mt8183_mipi_tx.c
>
> diff --git a/drivers/gpu/drm/mediatek/Makefile
> b/drivers/gpu/drm/mediatek/Makefile
> index 2c8de1f5a5ee..8067a4be8311 100644
> --- a/drivers/gpu/drm/mediatek/Makefile
> +++ b/drivers/gpu/drm/mediatek/Makefile
> @@ -13,6 +13,7 @@ mediatek-drm-y := mtk_disp_color.o \
> mtk_dsi.o \
> mtk_mipi_tx.o \
> mtk_mt8173_mipi_tx.o \
> + mtk_mt8183_mipi_tx.o \
> mtk_dpi.o
>
> obj-$(CONFIG_DRM_MEDIATEK) += mediatek-drm.o
> diff --git a/drivers/gpu/drm/mediatek/mtk_mipi_tx.c
> b/drivers/gpu/drm/mediatek/mtk_mipi_tx.c
> index cdc68b88cefd..ab0fbfba5572 100644
> --- a/drivers/gpu/drm/mediatek/mtk_mipi_tx.c
> +++ b/drivers/gpu/drm/mediatek/mtk_mipi_tx.c
> @@ -182,6 +182,8 @@ static const struct of_device_id mtk_mipi_tx_match[] = {
> .data = _mipitx_data },
> { .compatible = "mediatek,mt8173-mipi-tx",
> .data = _mipitx_data },
> + { .compatible = "mediatek,mt8183-mipi-tx",
> + .data = _mipitx_data },
> { },
> };
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_mipi_tx.h
> b/drivers/gpu/drm/mediatek/mtk_mipi_tx.h
> index 660726924992..3fd24563952e 100644
> --- a/drivers/gpu/drm/mediatek/mtk_mipi_tx.h
> +++ b/drivers/gpu/drm/mediatek/mtk_mipi_tx.h
> @@ -45,5 +45,6 @@ unsigned long mtk_mipi_tx_pll_recalc_rate(struct clk_hw *hw,
>
> extern const struct mtk_mipitx_data mt2701_mipitx_data;
> extern const struct mtk_mipitx_data mt8173_mipitx_data;
> +extern const struct mtk_mipitx_data mt8183_mipitx_data;
>
> #endif
> diff --git a/drivers/gpu/drm/mediatek/mtk_mt8183_mipi_tx.c
> b/drivers/gpu/drm/mediatek/mtk_mt8183_mipi_tx.c
> new file mode 100644
> index ..a9f893d8e409
> --- /dev/null
> +++ b/drivers/gpu/drm/mediatek/mtk_mt8183_mipi_tx.c
> @@ -0,0 +1,162 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (c) 2019 MediaTek Inc.
> + * Author: jitao.shi
> + */
> +
> +#include "mtk_mipi_tx.h"
> +
> +#define MIPITX_LANE_CON 0x000c
> +#define RG_DSI_CPHY_T1DRV_EN BIT(0)
> +#define RG_DSI_ANA_CK_SELBIT(1)
> +#define RG_DSI_PHY_CK_SELBIT(2)
> +#define RG_DSI_CPHY_EN BIT(3)
> +#define RG_DSI_PHYCK_INV_EN BIT(4)
> +#define RG_DSI_PWR04_EN BIT(5)
> +#define RG_DSI_BG_LPF_EN BIT(6)
> +#define RG_DSI_BG_CORE_ENBIT(7)
> +#define RG_DSI_PAD_TIEL_SEL BIT(8)
> +
> +#define MIPITX_PLL_PWR 0x0028
> +#define MIPITX_PLL_CON0 0x002c
> +#define MIPITX_PLL_CON1 0x0030
> +#define MIPITX_PLL_CON2 0x0034
> +#define MIPITX_PLL_CON3 0x0038
> +#define MIPITX_PLL_CON4 0x003c
> +#define RG_DSI_PLL_IBIAS (3 << 10)
> +
> +#define MIPITX_D2_SW_CTL_EN 0x0144
> +#define MIPITX_D0_SW_CTL_EN 0x0244
> +#define MIPITX_CK_CKMODE_EN 0x0328
> +#define DSI_CK_CKMODE_EN BIT(0)
> +#define MIPITX_CK_SW_CTL_EN 0x0344
> +#define MIPITX_D1_SW_CTL_EN 0x0444
> +#define MIPITX_D3_SW_CTL_EN 0x0544
> +#define DSI_SW_CTL_ENBIT(0)
> +#define AD_DSI_PLL_SDM_PWR_ONBIT(0)
> +#define AD_DSI_PLL_SDM_ISO_ENBIT(1)
> +
> +#define RG_DSI_PLL_ENBIT(4)
> +#define RG_DSI_PLL_POSDIV(0x7 << 8)
> +
> +static int mtk_mipi_tx_pll_prepare(struct clk_hw *hw)
> +{
> + struct mtk_mipi_tx *mipi_tx = mtk_mipi_tx_from_clk_hw(hw);
> + unsigned int txdiv, txdiv0;
> + u64 pcw;
> + int ret;
> +
> + dev_dbg(mipi_tx->dev, "prepare: %u bps\n", mipi_tx->data_rate);
> +
> + if (mipi_tx->data_rate >= 20) {
> + txdiv = 1;
> + txdiv0 = 0;
> + } else if (mipi_tx->data_rate >= 10) {
> + txdiv = 2;
> + txdiv0 = 1;
> + } else if (mipi_tx->data_rate >= 5) {
> + txdiv = 4;
> + txdiv0 = 2;
> + } else if (mipi_tx->data_rate > 25000) {
> + txdiv = 8;
> + txdiv0 = 3;
> + } else if (mipi_tx->data_rate >= 12500) {
> + txdiv = 16;
> + txdiv0 = 4;
> + } else {
> + return -EINVAL;
> + }
> +
> + ret = clk_prepare_enable(mipi_tx->ref_clk);
My last comment is in [1].
[1]
http://lists.infradead.org/pipermail/linux-mediatek/2019-May/019851.html
Regards,
CK
> + if (ret < 0) {
> + dev_err(mipi_tx->dev,
> +
[v4 3/3] drm/mediatek: add mipi_tx driver for mt8183
This patch add mt8183 mipi_tx driver.
And also support other chips that use the same binding and driver.
Signed-off-by: Jitao Shi
---
drivers/gpu/drm/mediatek/Makefile | 1 +
drivers/gpu/drm/mediatek/mtk_mipi_tx.c| 2 +
drivers/gpu/drm/mediatek/mtk_mipi_tx.h| 1 +
drivers/gpu/drm/mediatek/mtk_mt8183_mipi_tx.c | 162 ++
4 files changed, 166 insertions(+)
create mode 100644 drivers/gpu/drm/mediatek/mtk_mt8183_mipi_tx.c
diff --git a/drivers/gpu/drm/mediatek/Makefile
b/drivers/gpu/drm/mediatek/Makefile
index 2c8de1f5a5ee..8067a4be8311 100644
--- a/drivers/gpu/drm/mediatek/Makefile
+++ b/drivers/gpu/drm/mediatek/Makefile
@@ -13,6 +13,7 @@ mediatek-drm-y := mtk_disp_color.o \
mtk_dsi.o \
mtk_mipi_tx.o \
mtk_mt8173_mipi_tx.o \
+ mtk_mt8183_mipi_tx.o \
mtk_dpi.o
obj-$(CONFIG_DRM_MEDIATEK) += mediatek-drm.o
diff --git a/drivers/gpu/drm/mediatek/mtk_mipi_tx.c
b/drivers/gpu/drm/mediatek/mtk_mipi_tx.c
index cdc68b88cefd..ab0fbfba5572 100644
--- a/drivers/gpu/drm/mediatek/mtk_mipi_tx.c
+++ b/drivers/gpu/drm/mediatek/mtk_mipi_tx.c
@@ -182,6 +182,8 @@ static const struct of_device_id mtk_mipi_tx_match[] = {
.data = _mipitx_data },
{ .compatible = "mediatek,mt8173-mipi-tx",
.data = _mipitx_data },
+ { .compatible = "mediatek,mt8183-mipi-tx",
+ .data = _mipitx_data },
{ },
};
diff --git a/drivers/gpu/drm/mediatek/mtk_mipi_tx.h
b/drivers/gpu/drm/mediatek/mtk_mipi_tx.h
index 660726924992..3fd24563952e 100644
--- a/drivers/gpu/drm/mediatek/mtk_mipi_tx.h
+++ b/drivers/gpu/drm/mediatek/mtk_mipi_tx.h
@@ -45,5 +45,6 @@ unsigned long mtk_mipi_tx_pll_recalc_rate(struct clk_hw *hw,
extern const struct mtk_mipitx_data mt2701_mipitx_data;
extern const struct mtk_mipitx_data mt8173_mipitx_data;
+extern const struct mtk_mipitx_data mt8183_mipitx_data;
#endif
diff --git a/drivers/gpu/drm/mediatek/mtk_mt8183_mipi_tx.c
b/drivers/gpu/drm/mediatek/mtk_mt8183_mipi_tx.c
new file mode 100644
index ..a9f893d8e409
--- /dev/null
+++ b/drivers/gpu/drm/mediatek/mtk_mt8183_mipi_tx.c
@@ -0,0 +1,162 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2019 MediaTek Inc.
+ * Author: jitao.shi
+ */
+
+#include "mtk_mipi_tx.h"
+
+#define MIPITX_LANE_CON0x000c
+#define RG_DSI_CPHY_T1DRV_EN BIT(0)
+#define RG_DSI_ANA_CK_SEL BIT(1)
+#define RG_DSI_PHY_CK_SEL BIT(2)
+#define RG_DSI_CPHY_EN BIT(3)
+#define RG_DSI_PHYCK_INV_ENBIT(4)
+#define RG_DSI_PWR04_ENBIT(5)
+#define RG_DSI_BG_LPF_EN BIT(6)
+#define RG_DSI_BG_CORE_EN BIT(7)
+#define RG_DSI_PAD_TIEL_SELBIT(8)
+
+#define MIPITX_PLL_PWR 0x0028
+#define MIPITX_PLL_CON00x002c
+#define MIPITX_PLL_CON10x0030
+#define MIPITX_PLL_CON20x0034
+#define MIPITX_PLL_CON30x0038
+#define MIPITX_PLL_CON40x003c
+#define RG_DSI_PLL_IBIAS (3 << 10)
+
+#define MIPITX_D2_SW_CTL_EN0x0144
+#define MIPITX_D0_SW_CTL_EN0x0244
+#define MIPITX_CK_CKMODE_EN0x0328
+#define DSI_CK_CKMODE_EN BIT(0)
+#define MIPITX_CK_SW_CTL_EN0x0344
+#define MIPITX_D1_SW_CTL_EN0x0444
+#define MIPITX_D3_SW_CTL_EN0x0544
+#define DSI_SW_CTL_EN BIT(0)
+#define AD_DSI_PLL_SDM_PWR_ON BIT(0)
+#define AD_DSI_PLL_SDM_ISO_EN BIT(1)
+
+#define RG_DSI_PLL_EN BIT(4)
+#define RG_DSI_PLL_POSDIV (0x7 << 8)
+
+static int mtk_mipi_tx_pll_prepare(struct clk_hw *hw)
+{
+ struct mtk_mipi_tx *mipi_tx = mtk_mipi_tx_from_clk_hw(hw);
+ unsigned int txdiv, txdiv0;
+ u64 pcw;
+ int ret;
+
+ dev_dbg(mipi_tx->dev, "prepare: %u bps\n", mipi_tx->data_rate);
+
+ if (mipi_tx->data_rate >= 20) {
+ txdiv = 1;
+ txdiv0 = 0;
+ } else if (mipi_tx->data_rate >= 10) {
+ txdiv = 2;
+ txdiv0 = 1;
+ } else if (mipi_tx->data_rate >= 5) {
+ txdiv = 4;
+ txdiv0 = 2;
+ } else if (mipi_tx->data_rate > 25000) {
+ txdiv = 8;
+ txdiv0 = 3;
+ } else if (mipi_tx->data_rate >= 12500) {
+ txdiv = 16;
+ txdiv0 = 4;
+ } else {
+ return -EINVAL;
+ }
+
+ ret = clk_prepare_enable(mipi_tx->ref_clk);
+ if (ret < 0) {
+ dev_err(mipi_tx->dev,
+ "can't prepare and enable mipi_tx ref_clk %d\n", ret);
+ return ret;
+ }
+
+ mtk_mipi_tx_clear_bits(mipi_tx, MIPITX_PLL_CON4, RG_DSI_PLL_IBIAS);
+
+ mtk_mipi_tx_set_bits(mipi_tx, MIPITX_PLL_PWR, AD_DSI_PLL_SDM_PWR_ON);
+ usleep_range(30, 100);
+ mtk_mipi_tx_clear_bits(mipi_tx, MIPITX_PLL_PWR,
