Re: [PATCH v14 RESEND 1/6] dt-bindings: display: imx: Add i.MX8qxp/qm DPU binding
On Tue, Sep 05, 2023 at 03:44:23AM +, Ying Liu wrote: > On Thursday, August 24, 2023 5:48 PM, Maxime Ripard > wrote: > > On Wed, Aug 23, 2023 at 08:47:51AM +, Ying Liu wrote: > > > > > This dt-binding just follows generic dt-binding rule to describe the > > > > > DPU > > IP > > > > > hardware, not the software implementation. DPU internal units do not > > > > > constitute separate devices. > > > > > > > > I mean, your driver does split them into separate devices so surely it > > > > constitutes separate devices. > > > > > > My driver treats them as DPU internal units, especially not Linux devices. > > > > > > Let's avoid Linuxisms when implementing this dt-binding and just be simple > > > to describe necessary stuff exposing to DPU's embodying system/SoC, like > > > reg, interrupts, clocks and power-domains. > > > > Let's focus the conversation here, because it's redundant with the rest. > > > > Your driver registers two additional devices, that have a different > > register space, different clocks, different interrupts, different power > > domains, etc. That has nothing to do with Linux, it's hardware > > properties. > > > > That alone is a very good indication to me that these devices should be > > modeled as such. And your driver agrees. > > > > Whether or not the other internal units need to be described as separate > > devices, I can't really tell, I don't have the datasheet. > > i.MX8qxp and i.MX8qm SoC reference manuals can be found at(I think > registration is needed first): > https://www.nxp.com/webapp/Download?colCode=IMX8DQXPRM > https://www.nxp.com/webapp/Download?colCode=IMX8QMRM I tried, but the registration is buggy. The email takes longer than the timeout to be sent. > Sorry for putting this in a short way, but the DPU is one IP, so one > dt-binding. > > > > > But at least the CRTC and the interrupt controller should be split away, > > or explained and detailed far better than "well it's just convenient". > > CRTC is Linuxisms, which cannot be referenced to determine dt-binding. > > DPU as Display Controller is listed as a standalone module/IP in RM. > This is how the IP is designed in the first place, not for any convenient > purpose. Sure, but pushing that argument further, the entire SoC has been designed as a single entity. Every vendor out there designs its display pipeline in its entirety and not block by block. This doesn't mean that it isn't composed of several mostly discrete components. If it has a separate address space, clock and interrupt, it's a different device, no matter how it was designed or what the intent was. Maxime signature.asc Description: PGP signature
RE: [PATCH v14 RESEND 1/6] dt-bindings: display: imx: Add i.MX8qxp/qm DPU binding
On Thursday, August 24, 2023 5:48 PM, Maxime Ripard wrote: > On Wed, Aug 23, 2023 at 08:47:51AM +, Ying Liu wrote: > > > > This dt-binding just follows generic dt-binding rule to describe the DPU > IP > > > > hardware, not the software implementation. DPU internal units do not > > > > constitute separate devices. > > > > > > I mean, your driver does split them into separate devices so surely it > > > constitutes separate devices. > > > > My driver treats them as DPU internal units, especially not Linux devices. > > > > Let's avoid Linuxisms when implementing this dt-binding and just be simple > > to describe necessary stuff exposing to DPU's embodying system/SoC, like > > reg, interrupts, clocks and power-domains. > > Let's focus the conversation here, because it's redundant with the rest. > > Your driver registers two additional devices, that have a different > register space, different clocks, different interrupts, different power > domains, etc. That has nothing to do with Linux, it's hardware > properties. > > That alone is a very good indication to me that these devices should be > modeled as such. And your driver agrees. > > Whether or not the other internal units need to be described as separate > devices, I can't really tell, I don't have the datasheet. i.MX8qxp and i.MX8qm SoC reference manuals can be found at(I think registration is needed first): https://www.nxp.com/webapp/Download?colCode=IMX8DQXPRM https://www.nxp.com/webapp/Download?colCode=IMX8QMRM Sorry for putting this in a short way, but the DPU is one IP, so one dt-binding. > > But at least the CRTC and the interrupt controller should be split away, > or explained and detailed far better than "well it's just convenient". CRTC is Linuxisms, which cannot be referenced to determine dt-binding. DPU as Display Controller is listed as a standalone module/IP in RM. This is how the IP is designed in the first place, not for any convenient purpose. Regards, Liu Ying > > Maxime
Re: [PATCH v14 RESEND 1/6] dt-bindings: display: imx: Add i.MX8qxp/qm DPU binding
On Wed, Aug 23, 2023 at 08:47:51AM +, Ying Liu wrote: > > > This dt-binding just follows generic dt-binding rule to describe the DPU > > > IP > > > hardware, not the software implementation. DPU internal units do not > > > constitute separate devices. > > > > I mean, your driver does split them into separate devices so surely it > > constitutes separate devices. > > My driver treats them as DPU internal units, especially not Linux devices. > > Let's avoid Linuxisms when implementing this dt-binding and just be simple > to describe necessary stuff exposing to DPU's embodying system/SoC, like > reg, interrupts, clocks and power-domains. Let's focus the conversation here, because it's redundant with the rest. Your driver registers two additional devices, that have a different register space, different clocks, different interrupts, different power domains, etc. That has nothing to do with Linux, it's hardware properties. That alone is a very good indication to me that these devices should be modeled as such. And your driver agrees. Whether or not the other internal units need to be described as separate devices, I can't really tell, I don't have the datasheet. But at least the CRTC and the interrupt controller should be split away, or explained and detailed far better than "well it's just convenient". Maxime signature.asc Description: PGP signature
RE: [PATCH v14 RESEND 1/6] dt-bindings: display: imx: Add i.MX8qxp/qm DPU binding
On Wednesday, August 23, 2023 3:32 PM Maxime Ripard wrote: > > On Wed, Aug 23, 2023 at 02:45:53AM +, Ying Liu wrote: > > On Tuesday, August 22, 2023 7:47 PM Maxime Ripard > wrote: > > > > > > Hi, > > > > Hi Maxime, > > > > Thanks for your review. > > > > > > > > On Tue, Aug 22, 2023 at 04:59:44PM +0800, Liu Ying wrote: > > > > This patch adds bindings for i.MX8qxp/qm Display Processing Unit. > > > > > > > > Reviewed-by: Rob Herring > > > > Signed-off-by: Liu Ying > > > > --- > > > > v7->v14: > > > > * No change. > > > > > > > > v6->v7: > > > > * Add Rob's R-b tag back. > > > > > > > > v5->v6: > > > > * Use graph schema. So, drop Rob's R-b tag as review is needed. > > > > > > > > v4->v5: > > > > * No change. > > > > > > > > v3->v4: > > > > * Improve compatible property by using enum instead of oneOf+const. > > > (Rob) > > > > * Add Rob's R-b tag. > > > > > > > > v2->v3: > > > > * No change. > > > > > > > > v1->v2: > > > > * Fix yamllint warnings. > > > > * Require bypass0 and bypass1 clocks for both i.MX8qxp and i.MX8qm, > as > > > the > > > > display controller subsystem spec does say that they exist. > > > > * Use new dt binding way to add clocks in the example. > > > > * Trivial tweaks for the example. > > > > > > > > .../bindings/display/imx/fsl,imx8qxp-dpu.yaml | 387 > ++ > > > > 1 file changed, 387 insertions(+) > > > > create mode 100644 > > > Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dpu.yaml > > > > > > > > diff --git > a/Documentation/devicetree/bindings/display/imx/fsl,imx8qxp- > > > dpu.yaml > b/Documentation/devicetree/bindings/display/imx/fsl,imx8qxp- > > > dpu.yaml > > > > new file mode 100644 > > > > index ..6b05c586cd9d > > > > --- /dev/null > > > > +++ b/Documentation/devicetree/bindings/display/imx/fsl,imx8qxp- > > > dpu.yaml > > > > @@ -0,0 +1,387 @@ > > > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > > > > +%YAML 1.2 > > > > +--- > > > > +$id: http://devicetree.org/schemas/display/imx/fsl,imx8qxp- > dpu.yaml# > > > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > > > + > > > > +title: Freescale i.MX8qm/qxp Display Processing Unit > > > > + > > > > +maintainers: > > > > + - Liu Ying > > > > + > > > > +description: | > > > > + The Freescale i.MX8qm/qxp Display Processing Unit(DPU) is > comprised of > > > two > > > > + main components that include a blit engine for 2D graphics > accelerations > > > > + and a display controller for display output processing, as well as a > > > command > > > > + sequencer. > > > > + > > > > +properties: > > > > + compatible: > > > > +enum: > > > > + - fsl,imx8qxp-dpu > > > > + - fsl,imx8qm-dpu > > > > + > > > > + reg: > > > > +maxItems: 1 > > > > + > > > > + interrupts: > > > > +items: > > > > + - description: | > > > > + store9 shadow load interrupt(blit engine) > > > > + - description: | > > > > + store9 frame complete interrupt(blit engine) > > > > + - description: | > > > > + store9 sequence complete interrupt(blit engine) > > > > + - description: | > > > > + extdst0 shadow load interrupt > > > > + (display controller, content stream 0) > > > > + - description: | > > > > + extdst0 frame complete interrupt > > > > + (display controller, content stream 0) > > > > + - description: | > > > > + extdst0 sequence complete interrupt > > > > + (display controller, content stream 0) > > > > + - description: | > > > > + extdst4 shadow load interrupt > > > > + (display controller, safety stream 0) > > > > + - description: | > > > > + extdst4 frame complete interrupt > > > > + (display controller, safety stream 0) > > > > + - description: | > > > > + extdst4 sequence complete interrupt > > > > + (display controller, safety stream 0) > > > > + - description: | > > > > + extdst1 shadow load interrupt > > > > + (display controller, content stream 1) > > > > + - description: | > > > > + extdst1 frame complete interrupt > > > > + (display controller, content stream 1) > > > > + - description: | > > > > + extdst1 sequence complete interrupt > > > > + (display controller, content stream 1) > > > > + - description: | > > > > + extdst5 shadow load interrupt > > > > + (display controller, safety stream 1) > > > > + - description: | > > > > + extdst5 frame complete interrupt > > > > + (display controller, safety stream 1) > > > > + - description: | > > > > + extdst5 sequence complete interrupt > > > > + (display controller, safety stream 1) > > > > + - description: | > > > > + disengcfg0 shadow load interrupt > > > > + (display controller, display stream 0) > > > > + - description: | > > > > + disengcfg0
Re: [PATCH v14 RESEND 1/6] dt-bindings: display: imx: Add i.MX8qxp/qm DPU binding
On Wed, Aug 23, 2023 at 02:45:53AM +, Ying Liu wrote: > On Tuesday, August 22, 2023 7:47 PM Maxime Ripard wrote: > > > > Hi, > > Hi Maxime, > > Thanks for your review. > > > > > On Tue, Aug 22, 2023 at 04:59:44PM +0800, Liu Ying wrote: > > > This patch adds bindings for i.MX8qxp/qm Display Processing Unit. > > > > > > Reviewed-by: Rob Herring > > > Signed-off-by: Liu Ying > > > --- > > > v7->v14: > > > * No change. > > > > > > v6->v7: > > > * Add Rob's R-b tag back. > > > > > > v5->v6: > > > * Use graph schema. So, drop Rob's R-b tag as review is needed. > > > > > > v4->v5: > > > * No change. > > > > > > v3->v4: > > > * Improve compatible property by using enum instead of oneOf+const. > > (Rob) > > > * Add Rob's R-b tag. > > > > > > v2->v3: > > > * No change. > > > > > > v1->v2: > > > * Fix yamllint warnings. > > > * Require bypass0 and bypass1 clocks for both i.MX8qxp and i.MX8qm, as > > the > > > display controller subsystem spec does say that they exist. > > > * Use new dt binding way to add clocks in the example. > > > * Trivial tweaks for the example. > > > > > > .../bindings/display/imx/fsl,imx8qxp-dpu.yaml | 387 ++ > > > 1 file changed, 387 insertions(+) > > > create mode 100644 > > Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dpu.yaml > > > > > > diff --git a/Documentation/devicetree/bindings/display/imx/fsl,imx8qxp- > > dpu.yaml b/Documentation/devicetree/bindings/display/imx/fsl,imx8qxp- > > dpu.yaml > > > new file mode 100644 > > > index ..6b05c586cd9d > > > --- /dev/null > > > +++ b/Documentation/devicetree/bindings/display/imx/fsl,imx8qxp- > > dpu.yaml > > > @@ -0,0 +1,387 @@ > > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > > > +%YAML 1.2 > > > +--- > > > +$id: http://devicetree.org/schemas/display/imx/fsl,imx8qxp-dpu.yaml# > > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > > + > > > +title: Freescale i.MX8qm/qxp Display Processing Unit > > > + > > > +maintainers: > > > + - Liu Ying > > > + > > > +description: | > > > + The Freescale i.MX8qm/qxp Display Processing Unit(DPU) is comprised of > > two > > > + main components that include a blit engine for 2D graphics > > > accelerations > > > + and a display controller for display output processing, as well as a > > command > > > + sequencer. > > > + > > > +properties: > > > + compatible: > > > +enum: > > > + - fsl,imx8qxp-dpu > > > + - fsl,imx8qm-dpu > > > + > > > + reg: > > > +maxItems: 1 > > > + > > > + interrupts: > > > +items: > > > + - description: | > > > + store9 shadow load interrupt(blit engine) > > > + - description: | > > > + store9 frame complete interrupt(blit engine) > > > + - description: | > > > + store9 sequence complete interrupt(blit engine) > > > + - description: | > > > + extdst0 shadow load interrupt > > > + (display controller, content stream 0) > > > + - description: | > > > + extdst0 frame complete interrupt > > > + (display controller, content stream 0) > > > + - description: | > > > + extdst0 sequence complete interrupt > > > + (display controller, content stream 0) > > > + - description: | > > > + extdst4 shadow load interrupt > > > + (display controller, safety stream 0) > > > + - description: | > > > + extdst4 frame complete interrupt > > > + (display controller, safety stream 0) > > > + - description: | > > > + extdst4 sequence complete interrupt > > > + (display controller, safety stream 0) > > > + - description: | > > > + extdst1 shadow load interrupt > > > + (display controller, content stream 1) > > > + - description: | > > > + extdst1 frame complete interrupt > > > + (display controller, content stream 1) > > > + - description: | > > > + extdst1 sequence complete interrupt > > > + (display controller, content stream 1) > > > + - description: | > > > + extdst5 shadow load interrupt > > > + (display controller, safety stream 1) > > > + - description: | > > > + extdst5 frame complete interrupt > > > + (display controller, safety stream 1) > > > + - description: | > > > + extdst5 sequence complete interrupt > > > + (display controller, safety stream 1) > > > + - description: | > > > + disengcfg0 shadow load interrupt > > > + (display controller, display stream 0) > > > + - description: | > > > + disengcfg0 frame complete interrupt > > > + (display controller, display stream 0) > > > + - description: | > > > + disengcfg0 sequence complete interrupt > > > + (display controller, display stream 0) > > > + - description: | > > > + framegen0 programmable interrupt0 > > > + (display controller,
RE: [PATCH v14 RESEND 1/6] dt-bindings: display: imx: Add i.MX8qxp/qm DPU binding
On Tuesday, August 22, 2023 7:47 PM Maxime Ripard wrote: > > Hi, Hi Maxime, Thanks for your review. > > On Tue, Aug 22, 2023 at 04:59:44PM +0800, Liu Ying wrote: > > This patch adds bindings for i.MX8qxp/qm Display Processing Unit. > > > > Reviewed-by: Rob Herring > > Signed-off-by: Liu Ying > > --- > > v7->v14: > > * No change. > > > > v6->v7: > > * Add Rob's R-b tag back. > > > > v5->v6: > > * Use graph schema. So, drop Rob's R-b tag as review is needed. > > > > v4->v5: > > * No change. > > > > v3->v4: > > * Improve compatible property by using enum instead of oneOf+const. > (Rob) > > * Add Rob's R-b tag. > > > > v2->v3: > > * No change. > > > > v1->v2: > > * Fix yamllint warnings. > > * Require bypass0 and bypass1 clocks for both i.MX8qxp and i.MX8qm, as > the > > display controller subsystem spec does say that they exist. > > * Use new dt binding way to add clocks in the example. > > * Trivial tweaks for the example. > > > > .../bindings/display/imx/fsl,imx8qxp-dpu.yaml | 387 ++ > > 1 file changed, 387 insertions(+) > > create mode 100644 > Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dpu.yaml > > > > diff --git a/Documentation/devicetree/bindings/display/imx/fsl,imx8qxp- > dpu.yaml b/Documentation/devicetree/bindings/display/imx/fsl,imx8qxp- > dpu.yaml > > new file mode 100644 > > index ..6b05c586cd9d > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/display/imx/fsl,imx8qxp- > dpu.yaml > > @@ -0,0 +1,387 @@ > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > > +%YAML 1.2 > > +--- > > +$id: http://devicetree.org/schemas/display/imx/fsl,imx8qxp-dpu.yaml# > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > + > > +title: Freescale i.MX8qm/qxp Display Processing Unit > > + > > +maintainers: > > + - Liu Ying > > + > > +description: | > > + The Freescale i.MX8qm/qxp Display Processing Unit(DPU) is comprised of > two > > + main components that include a blit engine for 2D graphics accelerations > > + and a display controller for display output processing, as well as a > command > > + sequencer. > > + > > +properties: > > + compatible: > > +enum: > > + - fsl,imx8qxp-dpu > > + - fsl,imx8qm-dpu > > + > > + reg: > > +maxItems: 1 > > + > > + interrupts: > > +items: > > + - description: | > > + store9 shadow load interrupt(blit engine) > > + - description: | > > + store9 frame complete interrupt(blit engine) > > + - description: | > > + store9 sequence complete interrupt(blit engine) > > + - description: | > > + extdst0 shadow load interrupt > > + (display controller, content stream 0) > > + - description: | > > + extdst0 frame complete interrupt > > + (display controller, content stream 0) > > + - description: | > > + extdst0 sequence complete interrupt > > + (display controller, content stream 0) > > + - description: | > > + extdst4 shadow load interrupt > > + (display controller, safety stream 0) > > + - description: | > > + extdst4 frame complete interrupt > > + (display controller, safety stream 0) > > + - description: | > > + extdst4 sequence complete interrupt > > + (display controller, safety stream 0) > > + - description: | > > + extdst1 shadow load interrupt > > + (display controller, content stream 1) > > + - description: | > > + extdst1 frame complete interrupt > > + (display controller, content stream 1) > > + - description: | > > + extdst1 sequence complete interrupt > > + (display controller, content stream 1) > > + - description: | > > + extdst5 shadow load interrupt > > + (display controller, safety stream 1) > > + - description: | > > + extdst5 frame complete interrupt > > + (display controller, safety stream 1) > > + - description: | > > + extdst5 sequence complete interrupt > > + (display controller, safety stream 1) > > + - description: | > > + disengcfg0 shadow load interrupt > > + (display controller, display stream 0) > > + - description: | > > + disengcfg0 frame complete interrupt > > + (display controller, display stream 0) > > + - description: | > > + disengcfg0 sequence complete interrupt > > + (display controller, display stream 0) > > + - description: | > > + framegen0 programmable interrupt0 > > + (display controller, display stream 0) > > + - description: | > > + framegen0 programmable interrupt1 > > + (display controller, display stream 0) > > + - description: | > > + framegen0 programmable interrupt2 > > + (display controller, display stream 0) > > + - description: | > > + framegen0 programmable
Re: [PATCH v14 RESEND 1/6] dt-bindings: display: imx: Add i.MX8qxp/qm DPU binding
Hi, On Tue, Aug 22, 2023 at 04:59:44PM +0800, Liu Ying wrote: > This patch adds bindings for i.MX8qxp/qm Display Processing Unit. > > Reviewed-by: Rob Herring > Signed-off-by: Liu Ying > --- > v7->v14: > * No change. > > v6->v7: > * Add Rob's R-b tag back. > > v5->v6: > * Use graph schema. So, drop Rob's R-b tag as review is needed. > > v4->v5: > * No change. > > v3->v4: > * Improve compatible property by using enum instead of oneOf+const. (Rob) > * Add Rob's R-b tag. > > v2->v3: > * No change. > > v1->v2: > * Fix yamllint warnings. > * Require bypass0 and bypass1 clocks for both i.MX8qxp and i.MX8qm, as the > display controller subsystem spec does say that they exist. > * Use new dt binding way to add clocks in the example. > * Trivial tweaks for the example. > > .../bindings/display/imx/fsl,imx8qxp-dpu.yaml | 387 ++ > 1 file changed, 387 insertions(+) > create mode 100644 > Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dpu.yaml > > diff --git > a/Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dpu.yaml > b/Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dpu.yaml > new file mode 100644 > index ..6b05c586cd9d > --- /dev/null > +++ b/Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dpu.yaml > @@ -0,0 +1,387 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/display/imx/fsl,imx8qxp-dpu.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Freescale i.MX8qm/qxp Display Processing Unit > + > +maintainers: > + - Liu Ying > + > +description: | > + The Freescale i.MX8qm/qxp Display Processing Unit(DPU) is comprised of two > + main components that include a blit engine for 2D graphics accelerations > + and a display controller for display output processing, as well as a > command > + sequencer. > + > +properties: > + compatible: > +enum: > + - fsl,imx8qxp-dpu > + - fsl,imx8qm-dpu > + > + reg: > +maxItems: 1 > + > + interrupts: > +items: > + - description: | > + store9 shadow load interrupt(blit engine) > + - description: | > + store9 frame complete interrupt(blit engine) > + - description: | > + store9 sequence complete interrupt(blit engine) > + - description: | > + extdst0 shadow load interrupt > + (display controller, content stream 0) > + - description: | > + extdst0 frame complete interrupt > + (display controller, content stream 0) > + - description: | > + extdst0 sequence complete interrupt > + (display controller, content stream 0) > + - description: | > + extdst4 shadow load interrupt > + (display controller, safety stream 0) > + - description: | > + extdst4 frame complete interrupt > + (display controller, safety stream 0) > + - description: | > + extdst4 sequence complete interrupt > + (display controller, safety stream 0) > + - description: | > + extdst1 shadow load interrupt > + (display controller, content stream 1) > + - description: | > + extdst1 frame complete interrupt > + (display controller, content stream 1) > + - description: | > + extdst1 sequence complete interrupt > + (display controller, content stream 1) > + - description: | > + extdst5 shadow load interrupt > + (display controller, safety stream 1) > + - description: | > + extdst5 frame complete interrupt > + (display controller, safety stream 1) > + - description: | > + extdst5 sequence complete interrupt > + (display controller, safety stream 1) > + - description: | > + disengcfg0 shadow load interrupt > + (display controller, display stream 0) > + - description: | > + disengcfg0 frame complete interrupt > + (display controller, display stream 0) > + - description: | > + disengcfg0 sequence complete interrupt > + (display controller, display stream 0) > + - description: | > + framegen0 programmable interrupt0 > + (display controller, display stream 0) > + - description: | > + framegen0 programmable interrupt1 > + (display controller, display stream 0) > + - description: | > + framegen0 programmable interrupt2 > + (display controller, display stream 0) > + - description: | > + framegen0 programmable interrupt3 > + (display controller, display stream 0) > + - description: | > + signature0 shadow load interrupt > + (display controller, display stream 0) > + - description: | > + signature0 measurement valid interrupt > + (display controller, display stream 0) > + - description: | > + signature0
