Re: [PATCH v8 07/19] drm/i915/dp: Compute DSC pipe config in atomic check
On Tue, Nov 06, 2018 at 02:41:01PM -0800, Srivatsa, Anusha wrote: > > > >-Original Message- > >From: Ville Syrjälä [mailto:ville.syrj...@linux.intel.com] > >Sent: Tuesday, November 6, 2018 6:43 AM > >To: Navare, Manasi D > >Cc: intel-...@lists.freedesktop.org; dri-devel@lists.freedesktop.org; Jani > >Nikula > >; Srivatsa, Anusha ; > >Singh, Gaurav K > >Subject: Re: [PATCH v8 07/19] drm/i915/dp: Compute DSC pipe config in atomic > >check > > > >On Fri, Nov 02, 2018 at 07:09:03PM -0700, Manasi Navare wrote: > >> On Fri, Nov 02, 2018 at 02:31:26PM -0700, Manasi Navare wrote: > >> > DSC params like the enable, compressed bpp, slice count and > >> > dsc_split are added to the intel_crtc_state. These parameters are > >> > set based on the requested mode and available link parameters during > >> > the pipe configuration in atomic check phase. > >> > These values are then later used to populate the remaining DSC and > >> > RC parameters before enbaling DSC in atomic commit. > >> > > >> > v11: > >> > * Const crtc_state, reject DSC on DP without FEC (Ville) > >> > * Dont set dsc_split to false (Ville) > >> > v10: > >> > * Add a helper for dp_dsc support (Ville) > >> > * Set pipe_config to max bpp, link params for DSC for now (Ville) > >> > * Compute bpp - use dp dsc support helper (Ville) > >> > v9: > >> > * Rebase on top of drm-tip that now uses fast_narrow config for edp > >> > (Manasi) > >> > v8: > >> > * Check for DSC bpc not 0 (manasi) > >> > > >> > v7: > >> > * Fix indentation in compute_m_n (Manasi) > >> > > >> > v6 (From Gaurav): > >> > * Remove function call of intel_dp_compute_dsc_params() and invoke > >> > intel_dp_compute_dsc_params() in the patch where it is defined to > >> > fix compilation warning (Gaurav) > >> > > >> > v5: > >> > Add drm_dsc_cfg in intel_crtc_state (Manasi) > >> > > >> > v4: > >> > * Rebase on refactoring of intel_dp_compute_config on tip (Manasi) > >> > * Add a comment why we need to check PSR while enabling DSC (Gaurav) > >> > > >> > v3: > >> > * Check PPR > max_cdclock to use 2 VDSC instances (Ville) > >> > > >> > v2: > >> > * Add if-else for eDP/DP (Gaurav) > >> > > >> > Cc: Jani Nikula > >> > Cc: Ville Syrjala > >> > Cc: Anusha Srivatsa > >> > Cc: Gaurav K Singh > >> > Signed-off-by: Manasi Navare > >> > Reviewed-by: Anusha Srivatsa > >> > Acked-by: Jani Nikula > >> > --- > >> > drivers/gpu/drm/i915/intel_display.c | 20 +++- > >> > drivers/gpu/drm/i915/intel_display.h | 3 +- > >> > drivers/gpu/drm/i915/intel_dp.c | 167 --- > >> > drivers/gpu/drm/i915/intel_dp_mst.c | 2 +- > >> > 4 files changed, 166 insertions(+), 26 deletions(-) > >> > > >> > diff --git a/drivers/gpu/drm/i915/intel_display.c > >> > b/drivers/gpu/drm/i915/intel_display.c > >> > index b219d5858160..477e53c37353 100644 > >> > --- a/drivers/gpu/drm/i915/intel_display.c > >> > +++ b/drivers/gpu/drm/i915/intel_display.c > >> > @@ -6442,7 +6442,7 @@ static int ironlake_fdi_compute_config(struct > >> > intel_crtc *intel_crtc, > >> > > >> > pipe_config->fdi_lanes = lane; > >> > > >> > -intel_link_compute_m_n(pipe_config->pipe_bpp, lane, > >> > fdi_dotclock, > >> > +intel_link_compute_m_n(pipe_config->pipe_bpp, 0, lane, > >> > +fdi_dotclock, > >> > link_bw, &pipe_config->fdi_m_n, false); > >> > > >> > ret = ironlake_check_fdi_lanes(dev, intel_crtc->pipe, > >> > pipe_config); @@ -6679,17 +6679,25 @@ static void > >> > compute_m_n(unsigned int m, unsigned int n, } > >> > > >> > void > >> > -intel_link_compute_m_n(int bits_per_pixel, int nlanes, > >> > +intel_link_compute_m_n(int bits_per_pixel, uint16_t compressed_bpp, > >> > + int nlanes, > >> > int pixel_clock, int link_clock, > >> > struct intel_link_m_n *m_n, > >> > bool c
RE: [PATCH v8 07/19] drm/i915/dp: Compute DSC pipe config in atomic check
>-Original Message-
>From: Ville Syrjälä [mailto:ville.syrj...@linux.intel.com]
>Sent: Tuesday, November 6, 2018 6:43 AM
>To: Navare, Manasi D
>Cc: intel-...@lists.freedesktop.org; dri-devel@lists.freedesktop.org; Jani
>Nikula
>; Srivatsa, Anusha ;
>Singh, Gaurav K
>Subject: Re: [PATCH v8 07/19] drm/i915/dp: Compute DSC pipe config in atomic
>check
>
>On Fri, Nov 02, 2018 at 07:09:03PM -0700, Manasi Navare wrote:
>> On Fri, Nov 02, 2018 at 02:31:26PM -0700, Manasi Navare wrote:
>> > DSC params like the enable, compressed bpp, slice count and
>> > dsc_split are added to the intel_crtc_state. These parameters are
>> > set based on the requested mode and available link parameters during
>> > the pipe configuration in atomic check phase.
>> > These values are then later used to populate the remaining DSC and
>> > RC parameters before enbaling DSC in atomic commit.
>> >
>> > v11:
>> > * Const crtc_state, reject DSC on DP without FEC (Ville)
>> > * Dont set dsc_split to false (Ville)
>> > v10:
>> > * Add a helper for dp_dsc support (Ville)
>> > * Set pipe_config to max bpp, link params for DSC for now (Ville)
>> > * Compute bpp - use dp dsc support helper (Ville)
>> > v9:
>> > * Rebase on top of drm-tip that now uses fast_narrow config for edp
>> > (Manasi)
>> > v8:
>> > * Check for DSC bpc not 0 (manasi)
>> >
>> > v7:
>> > * Fix indentation in compute_m_n (Manasi)
>> >
>> > v6 (From Gaurav):
>> > * Remove function call of intel_dp_compute_dsc_params() and invoke
>> > intel_dp_compute_dsc_params() in the patch where it is defined to
>> > fix compilation warning (Gaurav)
>> >
>> > v5:
>> > Add drm_dsc_cfg in intel_crtc_state (Manasi)
>> >
>> > v4:
>> > * Rebase on refactoring of intel_dp_compute_config on tip (Manasi)
>> > * Add a comment why we need to check PSR while enabling DSC (Gaurav)
>> >
>> > v3:
>> > * Check PPR > max_cdclock to use 2 VDSC instances (Ville)
>> >
>> > v2:
>> > * Add if-else for eDP/DP (Gaurav)
>> >
>> > Cc: Jani Nikula
>> > Cc: Ville Syrjala
>> > Cc: Anusha Srivatsa
>> > Cc: Gaurav K Singh
>> > Signed-off-by: Manasi Navare
>> > Reviewed-by: Anusha Srivatsa
>> > Acked-by: Jani Nikula
>> > ---
>> > drivers/gpu/drm/i915/intel_display.c | 20 +++-
>> > drivers/gpu/drm/i915/intel_display.h | 3 +-
>> > drivers/gpu/drm/i915/intel_dp.c | 167 ---
>> > drivers/gpu/drm/i915/intel_dp_mst.c | 2 +-
>> > 4 files changed, 166 insertions(+), 26 deletions(-)
>> >
>> > diff --git a/drivers/gpu/drm/i915/intel_display.c
>> > b/drivers/gpu/drm/i915/intel_display.c
>> > index b219d5858160..477e53c37353 100644
>> > --- a/drivers/gpu/drm/i915/intel_display.c
>> > +++ b/drivers/gpu/drm/i915/intel_display.c
>> > @@ -6442,7 +6442,7 @@ static int ironlake_fdi_compute_config(struct
>> > intel_crtc *intel_crtc,
>> >
>> >pipe_config->fdi_lanes = lane;
>> >
>> > - intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
>> > + intel_link_compute_m_n(pipe_config->pipe_bpp, 0, lane,
>> > +fdi_dotclock,
>> > link_bw, &pipe_config->fdi_m_n, false);
>> >
>> >ret = ironlake_check_fdi_lanes(dev, intel_crtc->pipe,
>> > pipe_config); @@ -6679,17 +6679,25 @@ static void
>> > compute_m_n(unsigned int m, unsigned int n, }
>> >
>> > void
>> > -intel_link_compute_m_n(int bits_per_pixel, int nlanes,
>> > +intel_link_compute_m_n(int bits_per_pixel, uint16_t compressed_bpp,
>> > + int nlanes,
>> > int pixel_clock, int link_clock,
>> > struct intel_link_m_n *m_n,
>> > bool constant_n)
>> > {
>> >m_n->tu = 64;
>> >
>> > - compute_m_n(bits_per_pixel * pixel_clock,
>> > - link_clock * nlanes * 8,
>> > - &m_n->gmch_m, &m_n->gmch_n,
>> > - constant_n);
>> > + /* For DSC, Data M/N calculation uses compressed BPP */
>> > + if (compressed_bpp)
>> > + compute_m_n(compressed_bpp * pixel_clock,
>> > + link_clock * nlanes * 8,
>> > + &m_n->gmch_m, &m_n->gmch_n,
>
Re: [PATCH v8 07/19] drm/i915/dp: Compute DSC pipe config in atomic check
On Tue, Nov 06, 2018 at 04:42:56PM +0200, Ville Syrjälä wrote:
> On Fri, Nov 02, 2018 at 07:09:03PM -0700, Manasi Navare wrote:
> > On Fri, Nov 02, 2018 at 02:31:26PM -0700, Manasi Navare wrote:
> > > DSC params like the enable, compressed bpp, slice count and
> > > dsc_split are added to the intel_crtc_state. These parameters
> > > are set based on the requested mode and available link parameters
> > > during the pipe configuration in atomic check phase.
> > > These values are then later used to populate the remaining DSC
> > > and RC parameters before enbaling DSC in atomic commit.
> > >
> > > v11:
> > > * Const crtc_state, reject DSC on DP without FEC (Ville)
> > > * Dont set dsc_split to false (Ville)
> > > v10:
> > > * Add a helper for dp_dsc support (Ville)
> > > * Set pipe_config to max bpp, link params for DSC for now (Ville)
> > > * Compute bpp - use dp dsc support helper (Ville)
> > > v9:
> > > * Rebase on top of drm-tip that now uses fast_narrow config
> > > for edp (Manasi)
> > > v8:
> > > * Check for DSC bpc not 0 (manasi)
> > >
> > > v7:
> > > * Fix indentation in compute_m_n (Manasi)
> > >
> > > v6 (From Gaurav):
> > > * Remove function call of intel_dp_compute_dsc_params() and
> > > invoke intel_dp_compute_dsc_params() in the patch where
> > > it is defined to fix compilation warning (Gaurav)
> > >
> > > v5:
> > > Add drm_dsc_cfg in intel_crtc_state (Manasi)
> > >
> > > v4:
> > > * Rebase on refactoring of intel_dp_compute_config on tip (Manasi)
> > > * Add a comment why we need to check PSR while enabling DSC (Gaurav)
> > >
> > > v3:
> > > * Check PPR > max_cdclock to use 2 VDSC instances (Ville)
> > >
> > > v2:
> > > * Add if-else for eDP/DP (Gaurav)
> > >
> > > Cc: Jani Nikula
> > > Cc: Ville Syrjala
> > > Cc: Anusha Srivatsa
> > > Cc: Gaurav K Singh
> > > Signed-off-by: Manasi Navare
> > > Reviewed-by: Anusha Srivatsa
> > > Acked-by: Jani Nikula
> > > ---
> > > drivers/gpu/drm/i915/intel_display.c | 20 +++-
> > > drivers/gpu/drm/i915/intel_display.h | 3 +-
> > > drivers/gpu/drm/i915/intel_dp.c | 167 ---
> > > drivers/gpu/drm/i915/intel_dp_mst.c | 2 +-
> > > 4 files changed, 166 insertions(+), 26 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/intel_display.c
> > > b/drivers/gpu/drm/i915/intel_display.c
> > > index b219d5858160..477e53c37353 100644
> > > --- a/drivers/gpu/drm/i915/intel_display.c
> > > +++ b/drivers/gpu/drm/i915/intel_display.c
> > > @@ -6442,7 +6442,7 @@ static int ironlake_fdi_compute_config(struct
> > > intel_crtc *intel_crtc,
> > >
> > > pipe_config->fdi_lanes = lane;
> > >
> > > - intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
> > > + intel_link_compute_m_n(pipe_config->pipe_bpp, 0, lane, fdi_dotclock,
> > > link_bw, &pipe_config->fdi_m_n, false);
> > >
> > > ret = ironlake_check_fdi_lanes(dev, intel_crtc->pipe, pipe_config);
> > > @@ -6679,17 +6679,25 @@ static void compute_m_n(unsigned int m, unsigned
> > > int n,
> > > }
> > >
> > > void
> > > -intel_link_compute_m_n(int bits_per_pixel, int nlanes,
> > > +intel_link_compute_m_n(int bits_per_pixel, uint16_t compressed_bpp,
> > > +int nlanes,
> > > int pixel_clock, int link_clock,
> > > struct intel_link_m_n *m_n,
> > > bool constant_n)
> > > {
> > > m_n->tu = 64;
> > >
> > > - compute_m_n(bits_per_pixel * pixel_clock,
> > > - link_clock * nlanes * 8,
> > > - &m_n->gmch_m, &m_n->gmch_n,
> > > - constant_n);
> > > + /* For DSC, Data M/N calculation uses compressed BPP */
> > > + if (compressed_bpp)
> > > + compute_m_n(compressed_bpp * pixel_clock,
> > > + link_clock * nlanes * 8,
> > > + &m_n->gmch_m, &m_n->gmch_n,
> > > + constant_n);
> > > + else
> > > + compute_m_n(bits_per_pixel * pixel_clock,
> > > + link_clock * nlanes * 8,
> > > + &m_n->gmch_m, &m_n->gmch_n,
> > > + constant_n);
> > >
> > > compute_m_n(pixel_clock, link_clock,
> > > &m_n->link_m, &m_n->link_n,
> > > diff --git a/drivers/gpu/drm/i915/intel_display.h
> > > b/drivers/gpu/drm/i915/intel_display.h
> > > index 5d50decbcbb5..b0b23e1e9392 100644
> > > --- a/drivers/gpu/drm/i915/intel_display.h
> > > +++ b/drivers/gpu/drm/i915/intel_display.h
> > > @@ -407,7 +407,8 @@ struct intel_link_m_n {
> > >(__i)++) \
> > > for_each_if(plane)
> > >
> > > -void intel_link_compute_m_n(int bpp, int nlanes,
> > > +void intel_link_compute_m_n(int bpp, uint16_t compressed_bpp,
> > > + int nlanes,
> > > int pixel_clock, int link_clock,
> > > struct intel_link_m_n *m_n,
> > > bool constant_n);
> > > diff --git a/drivers/gpu/drm/i915/intel_dp.c
> > > b/drivers/gpu/drm/i915/intel_dp.
Re: [PATCH v8 07/19] drm/i915/dp: Compute DSC pipe config in atomic check
On Fri, Nov 02, 2018 at 07:09:03PM -0700, Manasi Navare wrote:
> On Fri, Nov 02, 2018 at 02:31:26PM -0700, Manasi Navare wrote:
> > DSC params like the enable, compressed bpp, slice count and
> > dsc_split are added to the intel_crtc_state. These parameters
> > are set based on the requested mode and available link parameters
> > during the pipe configuration in atomic check phase.
> > These values are then later used to populate the remaining DSC
> > and RC parameters before enbaling DSC in atomic commit.
> >
> > v11:
> > * Const crtc_state, reject DSC on DP without FEC (Ville)
> > * Dont set dsc_split to false (Ville)
> > v10:
> > * Add a helper for dp_dsc support (Ville)
> > * Set pipe_config to max bpp, link params for DSC for now (Ville)
> > * Compute bpp - use dp dsc support helper (Ville)
> > v9:
> > * Rebase on top of drm-tip that now uses fast_narrow config
> > for edp (Manasi)
> > v8:
> > * Check for DSC bpc not 0 (manasi)
> >
> > v7:
> > * Fix indentation in compute_m_n (Manasi)
> >
> > v6 (From Gaurav):
> > * Remove function call of intel_dp_compute_dsc_params() and
> > invoke intel_dp_compute_dsc_params() in the patch where
> > it is defined to fix compilation warning (Gaurav)
> >
> > v5:
> > Add drm_dsc_cfg in intel_crtc_state (Manasi)
> >
> > v4:
> > * Rebase on refactoring of intel_dp_compute_config on tip (Manasi)
> > * Add a comment why we need to check PSR while enabling DSC (Gaurav)
> >
> > v3:
> > * Check PPR > max_cdclock to use 2 VDSC instances (Ville)
> >
> > v2:
> > * Add if-else for eDP/DP (Gaurav)
> >
> > Cc: Jani Nikula
> > Cc: Ville Syrjala
> > Cc: Anusha Srivatsa
> > Cc: Gaurav K Singh
> > Signed-off-by: Manasi Navare
> > Reviewed-by: Anusha Srivatsa
> > Acked-by: Jani Nikula
> > ---
> > drivers/gpu/drm/i915/intel_display.c | 20 +++-
> > drivers/gpu/drm/i915/intel_display.h | 3 +-
> > drivers/gpu/drm/i915/intel_dp.c | 167 ---
> > drivers/gpu/drm/i915/intel_dp_mst.c | 2 +-
> > 4 files changed, 166 insertions(+), 26 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_display.c
> > b/drivers/gpu/drm/i915/intel_display.c
> > index b219d5858160..477e53c37353 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -6442,7 +6442,7 @@ static int ironlake_fdi_compute_config(struct
> > intel_crtc *intel_crtc,
> >
> > pipe_config->fdi_lanes = lane;
> >
> > - intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
> > + intel_link_compute_m_n(pipe_config->pipe_bpp, 0, lane, fdi_dotclock,
> >link_bw, &pipe_config->fdi_m_n, false);
> >
> > ret = ironlake_check_fdi_lanes(dev, intel_crtc->pipe, pipe_config);
> > @@ -6679,17 +6679,25 @@ static void compute_m_n(unsigned int m, unsigned
> > int n,
> > }
> >
> > void
> > -intel_link_compute_m_n(int bits_per_pixel, int nlanes,
> > +intel_link_compute_m_n(int bits_per_pixel, uint16_t compressed_bpp,
> > + int nlanes,
> >int pixel_clock, int link_clock,
> >struct intel_link_m_n *m_n,
> >bool constant_n)
> > {
> > m_n->tu = 64;
> >
> > - compute_m_n(bits_per_pixel * pixel_clock,
> > - link_clock * nlanes * 8,
> > - &m_n->gmch_m, &m_n->gmch_n,
> > - constant_n);
> > + /* For DSC, Data M/N calculation uses compressed BPP */
> > + if (compressed_bpp)
> > + compute_m_n(compressed_bpp * pixel_clock,
> > + link_clock * nlanes * 8,
> > + &m_n->gmch_m, &m_n->gmch_n,
> > + constant_n);
> > + else
> > + compute_m_n(bits_per_pixel * pixel_clock,
> > + link_clock * nlanes * 8,
> > + &m_n->gmch_m, &m_n->gmch_n,
> > + constant_n);
> >
> > compute_m_n(pixel_clock, link_clock,
> > &m_n->link_m, &m_n->link_n,
> > diff --git a/drivers/gpu/drm/i915/intel_display.h
> > b/drivers/gpu/drm/i915/intel_display.h
> > index 5d50decbcbb5..b0b23e1e9392 100644
> > --- a/drivers/gpu/drm/i915/intel_display.h
> > +++ b/drivers/gpu/drm/i915/intel_display.h
> > @@ -407,7 +407,8 @@ struct intel_link_m_n {
> > (__i)++) \
> > for_each_if(plane)
> >
> > -void intel_link_compute_m_n(int bpp, int nlanes,
> > +void intel_link_compute_m_n(int bpp, uint16_t compressed_bpp,
> > + int nlanes,
> > int pixel_clock, int link_clock,
> > struct intel_link_m_n *m_n,
> > bool constant_n);
> > diff --git a/drivers/gpu/drm/i915/intel_dp.c
> > b/drivers/gpu/drm/i915/intel_dp.c
> > index b39b4bda8e40..58326fc9d935 100644
> > --- a/drivers/gpu/drm/i915/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/intel_dp.c
> > @@ -47,6 +47,8 @@
> >
> > /* DP DSC small joiner has 2 FIFOs each of 640 x 6 bytes */
> > #define DP_
Re: [PATCH v8 07/19] drm/i915/dp: Compute DSC pipe config in atomic check
On Fri, Nov 02, 2018 at 02:31:26PM -0700, Manasi Navare wrote:
> DSC params like the enable, compressed bpp, slice count and
> dsc_split are added to the intel_crtc_state. These parameters
> are set based on the requested mode and available link parameters
> during the pipe configuration in atomic check phase.
> These values are then later used to populate the remaining DSC
> and RC parameters before enbaling DSC in atomic commit.
>
> v11:
> * Const crtc_state, reject DSC on DP without FEC (Ville)
> * Dont set dsc_split to false (Ville)
> v10:
> * Add a helper for dp_dsc support (Ville)
> * Set pipe_config to max bpp, link params for DSC for now (Ville)
> * Compute bpp - use dp dsc support helper (Ville)
> v9:
> * Rebase on top of drm-tip that now uses fast_narrow config
> for edp (Manasi)
> v8:
> * Check for DSC bpc not 0 (manasi)
>
> v7:
> * Fix indentation in compute_m_n (Manasi)
>
> v6 (From Gaurav):
> * Remove function call of intel_dp_compute_dsc_params() and
> invoke intel_dp_compute_dsc_params() in the patch where
> it is defined to fix compilation warning (Gaurav)
>
> v5:
> Add drm_dsc_cfg in intel_crtc_state (Manasi)
>
> v4:
> * Rebase on refactoring of intel_dp_compute_config on tip (Manasi)
> * Add a comment why we need to check PSR while enabling DSC (Gaurav)
>
> v3:
> * Check PPR > max_cdclock to use 2 VDSC instances (Ville)
>
> v2:
> * Add if-else for eDP/DP (Gaurav)
>
> Cc: Jani Nikula
> Cc: Ville Syrjala
> Cc: Anusha Srivatsa
> Cc: Gaurav K Singh
> Signed-off-by: Manasi Navare
> Reviewed-by: Anusha Srivatsa
> Acked-by: Jani Nikula
> ---
> drivers/gpu/drm/i915/intel_display.c | 20 +++-
> drivers/gpu/drm/i915/intel_display.h | 3 +-
> drivers/gpu/drm/i915/intel_dp.c | 167 ---
> drivers/gpu/drm/i915/intel_dp_mst.c | 2 +-
> 4 files changed, 166 insertions(+), 26 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c
> index b219d5858160..477e53c37353 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -6442,7 +6442,7 @@ static int ironlake_fdi_compute_config(struct
> intel_crtc *intel_crtc,
>
> pipe_config->fdi_lanes = lane;
>
> - intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
> + intel_link_compute_m_n(pipe_config->pipe_bpp, 0, lane, fdi_dotclock,
> link_bw, &pipe_config->fdi_m_n, false);
>
> ret = ironlake_check_fdi_lanes(dev, intel_crtc->pipe, pipe_config);
> @@ -6679,17 +6679,25 @@ static void compute_m_n(unsigned int m, unsigned int
> n,
> }
>
> void
> -intel_link_compute_m_n(int bits_per_pixel, int nlanes,
> +intel_link_compute_m_n(int bits_per_pixel, uint16_t compressed_bpp,
> +int nlanes,
> int pixel_clock, int link_clock,
> struct intel_link_m_n *m_n,
> bool constant_n)
> {
> m_n->tu = 64;
>
> - compute_m_n(bits_per_pixel * pixel_clock,
> - link_clock * nlanes * 8,
> - &m_n->gmch_m, &m_n->gmch_n,
> - constant_n);
> + /* For DSC, Data M/N calculation uses compressed BPP */
> + if (compressed_bpp)
> + compute_m_n(compressed_bpp * pixel_clock,
> + link_clock * nlanes * 8,
> + &m_n->gmch_m, &m_n->gmch_n,
> + constant_n);
> + else
> + compute_m_n(bits_per_pixel * pixel_clock,
> + link_clock * nlanes * 8,
> + &m_n->gmch_m, &m_n->gmch_n,
> + constant_n);
>
> compute_m_n(pixel_clock, link_clock,
> &m_n->link_m, &m_n->link_n,
> diff --git a/drivers/gpu/drm/i915/intel_display.h
> b/drivers/gpu/drm/i915/intel_display.h
> index 5d50decbcbb5..b0b23e1e9392 100644
> --- a/drivers/gpu/drm/i915/intel_display.h
> +++ b/drivers/gpu/drm/i915/intel_display.h
> @@ -407,7 +407,8 @@ struct intel_link_m_n {
>(__i)++) \
> for_each_if(plane)
>
> -void intel_link_compute_m_n(int bpp, int nlanes,
> +void intel_link_compute_m_n(int bpp, uint16_t compressed_bpp,
> + int nlanes,
> int pixel_clock, int link_clock,
> struct intel_link_m_n *m_n,
> bool constant_n);
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index b39b4bda8e40..58326fc9d935 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -47,6 +47,8 @@
>
> /* DP DSC small joiner has 2 FIFOs each of 640 x 6 bytes */
> #define DP_DSC_MAX_SMALL_JOINER_RAM_BUFFER 61440
> +#define DP_DSC_MIN_SUPPORTED_BPC 8
> +#define DP_DSC_MAX_SUPPORTED_BPC 10
>
> /* DP DSC throughput values used for slice count calculations KPixels/s */
> #define DP_DSC_PEAK_PIXEL_RA
