last git xf86-video-intel have problem with video out xv

2007-07-29 Thread Sergio Monteiro Basto
Hi , I done a bisect the git xf86-video-intel 
and here is the results:
--
drv-intel
bad vo xv:
HEAD is now at 04130ac... Fix i915 rendering for tiled buffer
version 1

bad vo xv:
88f8b688e2316ae4a1f7485f0010ce90de54783a
HEAD is now at 88f8b68... Fix some physical address handling for >4GB
addresses
verison 2

bad vo xv:
HEAD is now at 4359df9... Fix tiling and fb compression defaults for 965
(not yet fully supported).
version 5

bad vo xv:
HEAD is now at ca593a5... FBC and tiling changes
version 6

good:
8798ef11321ee6957919279076758d47ad956cf3
HEAD is now at 8798ef1... Merge branch 'master' into fbc
version 4

good:
HEAD is now at 8919b22... Re-add tiling kludge, but only for 965
version 3

good:
3c552af65d28fafec1d09484a8914b690b961349
Update documentation and bump driver version to 2.1.0.

and xorg diff of last good and first bad Xorg.log

-- 
Sérgio M. B.
15c15
< (==) Log file: "/var/log/Xorg.0.log.good", Time: Sun Jul 29 19:19:26 2007
---
> (==) Log file: "/var/log/Xorg.0.log.bad", Time: Sun Jul 29 19:15:14 2007
462a463
> (II) intel(0): fbc disabled
658a660,662
> (II) intel(0): Framebuffer compression enabled, forcing tiling on.
> (**) intel(0): Framebuffer compression enabled
> (**) intel(0): Tiling enabled
660a665
> (II) intel(0): Framebuffer compression enabled
665,668c670,675
< (II) intel(0): 0x0002-0x00029fff: HW cursors (40 kB, 0x1f82 physical)
< (II) intel(0): 0x0002a000-0x00031fff: logical 3D context (32 kB)
< (II) intel(0): 0x00032000-0x00032fff: overlay registers (4 kB, 0x1f832000 physical)
< (II) intel(0): 0x0004-0x01837fff: front buffer (24544 kB)
---
> (II) intel(0): 0x0002-0x0061: compressed frame buffer (6144 kB, 0x1f82 physical)
> (II) intel(0): 0x0062-0x00620fff: compressed ll buffer (4 kB, 0x1fe2 physical)
> (II) intel(0): 0x00621000-0x0062afff: HW cursors (40 kB, 0x1fe21000 physical)
> (II) intel(0): 0x0062b000-0x00632fff: logical 3D context (32 kB)
> (II) intel(0): 0x00633000-0x00633fff: overlay registers (4 kB, 0x1fe33000 physical)
> (II) intel(0): 0x00634000-0x00643fff: xaa scratch (64 kB)
670,673c677,680
< (II) intel(0): 0x01838000-0x01847fff: xaa scratch (64 kB)
< (II) intel(0): 0x01c0-0x01ff: back buffer (4096 kB)
< (II) intel(0): 0x0200-0x023f: depth buffer (4096 kB)
< (II) intel(0): 0x0240-0x043f: DRI memory manager (32768 kB)
---
> (II) intel(0): 0x0080-0x00bf: back buffer (4096 kB)
> (II) intel(0): 0x00c0-0x00ff: depth buffer (4096 kB)
> (II) intel(0): 0x0200-0x03ff: front buffer (24544 kB)
> (II) intel(0): 0x0400-0x05ff: DRI memory manager (32768 kB)
675c682
< (II) intel(0): front buffer is not tiled
---
> (II) intel(0): front buffer is tiled
689,691c696,698
< (II) intel(0): [drm] added 8192 byte SAREA at 0xe03ea000
< (II) intel(0): [drm] mapped SAREA 0xe03ea000 to 0xb7f6b000
< (II) intel(0): [drm] framebuffer handle = 0xc004
---
> (II) intel(0): [drm] added 8192 byte SAREA at 0xe0105000
> (II) intel(0): [drm] mapped SAREA 0xe0105000 to 0xb7f6d000
> (II) intel(0): [drm] framebuffer handle = 0xc200
697,699c704,706
< (II) intel(0): [drm] Front Buffer = 0x28008000
< (II) intel(0): [drm] Back Buffer = 0xc1c0
< (II) intel(0): [drm] Depth Buffer = 0xc200
---
> (II) intel(0): [drm] Front Buffer = 0x2840
> (II) intel(0): [drm] Back Buffer = 0xc080
> (II) intel(0): [drm] Depth Buffer = 0xc0c0
718,721c725,727
< (II) intel(0): xf86BindGARTMemory: bind key 0 at 0x007bf000 (pgoffset 1983)
< (II) intel(0): xf86BindGARTMemory: bind key 1 at 0x01838000 (pgoffset 6200)
< (II) intel(0): xf86BindGARTMemory: bind key 2 at 0x01c0 (pgoffset 7168)
< (II) intel(0): xf86BindGARTMemory: bind key 3 at 0x0200 (pgoffset 8192)
---
> (II) intel(0): xf86BindGARTMemory: bind key 1 at 0x0080 (pgoffset 2048)
> (II) intel(0): xf86BindGARTMemory: bind key 2 at 0x00c0 (pgoffset 3072)
> (II) intel(0): xf86BindGARTMemory: bind key 0 at 0x0200 (pgoffset 8192)
723a730
> (II) intel(0): fbc disabled
825a833,841
> Synaptics DeviceOff called
> (II) intel(0): [drm] removed 1 reserved context for kernel
> (II) intel(0): [drm] unmapping 8192 bytes of SAREA 0xe0105000 at 0xb7f6d000
> (EE) intel(0): I830 Vblank Pipe Setup Failed 0
> (EE) intel(0): I830 Vblank Pipe Setup Failed 0
> (EE) intel(0): I830 Vblank Pipe Setup Failed 0
> (II) intel(0): xf86UnbindGARTMemory: unbind key 1
> (II) intel(0): xf86UnbindGARTMemory: unbind key 2
> (II) intel(0): xf86UnbindGARTMemory: unbind key 0


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[Bug 11609] SIN and COS do not support angles outside of -PI to PI.

2007-07-29 Thread bugzilla-daemon
http://bugs.freedesktop.org/show_bug.cgi?id=11609


[EMAIL PROTECTED] changed:

   What|Removed |Added

 Status|NEW |RESOLVED
 Resolution||FIXED




--- Comment #3 from [EMAIL PROTECTED]  2007-07-29 10:46 PST ---
(In reply to comment #2)
> I've got a proposed fix up but I doubt it's optimal - it looks as if the
> beginning of the COS/SIN generators (MUL/MOD/MUL) was an attempt to normalize
> the angles, and I can run the routines fine without those three 
> instructions...
> I can't quite figure out what the MOD is doing since it's not used anywhere
> else in the driver and it's not part of the GL spec.

Yes, those 3 instructions are for range reduction. The header file says A0_MOD
is dst = src0 fmod 1.0, so looks like a float modulo 1.0 to me...
Not sure why the code wouldn't work correctly, seems ok at first look (not sure
if the MULs you can use instead of the MADs  with the MOD is actually faster,
but it saves some constants at least).
Actually, looks not ok at second look... Should be fixed in git. If not reopen.


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[Bug 11131] Mesa 6.5.2 implementation error: i915_program_error: Exceeded max nr indirect texture lookups

2007-07-29 Thread bugzilla-daemon
http://bugs.freedesktop.org/show_bug.cgi?id=11131





--- Comment #3 from [EMAIL PROTECTED]  2007-07-29 09:40 PST ---
The crashes should be fixed in git.
However, the driver will still complain, and you're going to be short lived if
you play half life with swrast fallback...


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[2.6 patch] radeon_driver_vblank_do_wait() static

2007-07-29 Thread Adrian Bunk
radeon_driver_vblank_do_wait() can become static.

Signed-off-by: Adrian Bunk <[EMAIL PROTECTED]>

---
--- linux-2.6.23-rc1-mm1/drivers/char/drm/radeon_irq.c.old  2007-07-26 
08:49:12.0 +0200
+++ linux-2.6.23-rc1-mm1/drivers/char/drm/radeon_irq.c  2007-07-26 
08:49:46.0 +0200
@@ -144,8 +144,8 @@
return ret;
 }
 
-int radeon_driver_vblank_do_wait(struct drm_device * dev, unsigned int 
*sequence,
-int crtc)
+static int radeon_driver_vblank_do_wait(struct drm_device * dev,
+   unsigned int *sequence, int crtc)
 {
drm_radeon_private_t *dev_priv =
(drm_radeon_private_t *) dev->dev_private;


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[Bug 11762] VIA CN700 openchrome dri alignment error

2007-07-29 Thread bugzilla-daemon
http://bugs.freedesktop.org/show_bug.cgi?id=11762





--- Comment #1 from [EMAIL PROTECTED]  2007-07-29 06:31 PST ---
Sounds like a duplicate of bug #9965.  Should be fixed in Mesa-6.5.3 and up. 
What version are you using?  See `glxgears -info | grep VERSION`.

By the way: it's better to post Unichrome bugs to the openchrome mailing list
first.


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[Bug 11762] New: VIA CN700 openchrome dri alignment error

2007-07-29 Thread bugzilla-daemon
http://bugs.freedesktop.org/show_bug.cgi?id=11762

   Summary: VIA CN700 openchrome dri alignment error
   Product: DRI
   Version: DRI CVS
  Platform: x86 (IA32)
OS/Version: Linux (All)
Status: NEW
  Severity: normal
  Priority: medium
 Component: General
AssignedTo: dri-devel@lists.sourceforge.net
ReportedBy: [EMAIL PROTECTED]


dri windows are in the wrong places. for example glxgear windowless in the
upperleft corner shows the gears in the right place. When moving the window to
the right or bottom, the gearswindow moves 3/2 as fast as the window itself. To
make things worse, the gears in the gearwindow are not alligned to the window
itself.

The kde screen saver preview window, behaves the same with opengl screensavers.

The flightgear main window is split in two when x is in 1280x1024. The left
part is on the left, the right on the totaly right part of the window.


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