Re: last git xf86-video-intel have problem with video out xv
On Tue, 2007-07-31 at 07:51 +0200, Michel Dänzer wrote: On Mon, 2007-07-30 at 22:01 +0100, Sergio Monteiro Basto wrote: (WW) intel(0): Option Legacy3D is not used (II) AIGLX: Loaded and initialized /usr/lib/dri/i915_dri.so Did the build time configure check for DRI_MM succeed? I just found the problem, my fault, I forget update libdrm to git 2.3.(1) since this commits 37652b6... intel: oops I commited pixman local workaround - undo it 1e169be... intel: don't try and use TTM memory manager with old libdrm interface It is need it ! Thanks, -- Sérgio M. B. smime.p7s Description: S/MIME cryptographic signature - This SF.net email is sponsored by: Splunk Inc. Still grepping through log files to find problems? Stop. Now Search log events and configuration files using AJAX and a browser. Download your FREE copy of Splunk now http://get.splunk.com/-- ___ Dri-devel mailing list Dri-devel@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/dri-devel
Re: last git xf86-video-intel have problem with video out xv
On 2007.07.30 11:43:00 +, Eric Anholt wrote: On Mon, 2007-07-30 at 09:09 -0700, Jesse Barnes wrote: What hardware do you have? Does Xv based video work again if you add Option tiling false to the Intel device section of your xorg.conf? I thought Wang's fix would have taken care of this problem, but it sounds like we still have a bug here... His last fix I saw land was for render acceleration. We're still getting the xv fix sorted out. yep, the reason for xv failure (XAA) is that we trys to get memory in i830_video.c using xfree86 linear allocation from a _tiling_ buffer. So yuv surface got distorted copies. I have patch to use new mem for xv linear allocation, but in while Eric's TTM rework will land soon, I won't push it and want to fit in future mem manager code. Tiling is not well sorted out now, so I think now we might investigate any hw relate issues, and make it work right with ttm later. - This SF.net email is sponsored by: Splunk Inc. Still grepping through log files to find problems? Stop. Now Search log events and configuration files using AJAX and a browser. Download your FREE copy of Splunk now http://get.splunk.com/ -- ___ Dri-devel mailing list Dri-devel@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/dri-devel
Re: last git xf86-video-intel have problem with video out xv
What hardware do you have? Does Xv based video work again if you add Option tiling false to the Intel device section of your xorg.conf? I thought Wang's fix would have taken care of this problem, but it sounds like we still have a bug here... Jesse On Sunday, July 29, 2007 11:29 am Sergio Monteiro Basto wrote: Hi , I done a bisect the git xf86-video-intel and here is the results: -- drv-intel bad vo xv: HEAD is now at 04130ac... Fix i915 rendering for tiled buffer version 1 bad vo xv: 88f8b688e2316ae4a1f7485f0010ce90de54783a HEAD is now at 88f8b68... Fix some physical address handling for 4GB addresses verison 2 bad vo xv: HEAD is now at 4359df9... Fix tiling and fb compression defaults for 965 (not yet fully supported). version 5 bad vo xv: HEAD is now at ca593a5... FBC and tiling changes version 6 good: 8798ef11321ee6957919279076758d47ad956cf3 HEAD is now at 8798ef1... Merge branch 'master' into fbc version 4 good: HEAD is now at 8919b22... Re-add tiling kludge, but only for 965 version 3 good: 3c552af65d28fafec1d09484a8914b690b961349 Update documentation and bump driver version to 2.1.0. and xorg diff of last good and first bad Xorg.log - This SF.net email is sponsored by: Splunk Inc. Still grepping through log files to find problems? Stop. Now Search log events and configuration files using AJAX and a browser. Download your FREE copy of Splunk now http://get.splunk.com/ -- ___ Dri-devel mailing list Dri-devel@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/dri-devel
Re: last git xf86-video-intel have problem with video out xv
On Mon, 2007-07-30 at 09:09 -0700, Jesse Barnes wrote: What hardware do you have? 00:00.0 Host bridge: Intel Corporation Mobile 915GM/PM/GMS/910GML Express Processor to DRAM Controller (rev 03) Subsystem: Hewlett-Packard Company NX6110/NC6120 Latency: 0 Capabilities: [e0] Vendor Specific Information 00:02.0 VGA compatible controller: Intel Corporation Mobile 915GM/GMS/910GML Express Graphics Controller (rev 03) (prog-if 00 [VGA]) Subsystem: Hewlett-Packard Company NX6110/NC6120 Latency: 0 Interrupt: pin A routed to IRQ 18 Region 0: Memory at d010 (32-bit, non-prefetchable) [size=512K] Region 1: I/O ports at 2000 [size=8] Region 2: Memory at c000 (32-bit, prefetchable) [size=256M] Region 3: Memory at d018 (32-bit, non-prefetchable) [size=256K] Capabilities: [d0] Power Management version 2 Flags: PMEClk- DSI+ D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) Status: D0 PME-Enable- DSel=0 DScale=0 PME- 00:02.1 Display controller: Intel Corporation Mobile 915GM/GMS/910GML Express Graphics Controller (rev 03) Subsystem: Hewlett-Packard Company NX6110/NC6120 Latency: 0 Region 0: Memory at d020 (32-bit, non-prefetchable) [size=512K] Capabilities: [d0] Power Management version 2 Flags: PMEClk- DSI+ D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) Status: D0 PME-Enable- DSel=0 DScale=0 PME- lspci -n 00:00.0 0600: 8086:2590 (rev 03) 00:02.0 0300: 8086:2592 (rev 03) 00:02.1 0380: 8086:2792 (rev 03) 00:1d.0 0c03: 8086:2658 (rev 03) 00:1d.1 0c03: 8086:2659 (rev 03) 00:1d.2 0c03: 8086:265a (rev 03) 00:1d.3 0c03: 8086:265b (rev 03) 00:1d.7 0c03: 8086:265c (rev 03) 00:1e.0 0604: 8086:2448 (rev d3) 00:1e.2 0401: 8086:266e (rev 03) 00:1e.3 0703: 8086:266d (rev 03) 00:1f.0 0601: 8086:2641 (rev 03) 00:1f.1 0101: 8086:266f (rev 03) 02:04.0 0280: 8086:4220 (rev 05) (WW) intel: No matching Device section for instance (BusID PCI:0:2:1) found (--) Chipset 915GM found Does Xv based video work again if you add Option tiling false to the Intel device section of your xorg.conf? no , seems that not obey to Option tiling false I try latest git and here is the xorg diff in attach Thanks, I thought Wang's fix would have taken care of this problem, but it sounds like we still have a bug here... Jesse On Sunday, July 29, 2007 11:29 am Sergio Monteiro Basto wrote: Hi , I done a bisect the git xf86-video-intel and here is the results: -- drv-intel bad vo xv: HEAD is now at 04130ac... Fix i915 rendering for tiled buffer version 1 bad vo xv: 88f8b688e2316ae4a1f7485f0010ce90de54783a HEAD is now at 88f8b68... Fix some physical address handling for 4GB addresses verison 2 bad vo xv: HEAD is now at 4359df9... Fix tiling and fb compression defaults for 965 (not yet fully supported). version 5 bad vo xv: HEAD is now at ca593a5... FBC and tiling changes version 6 good: 8798ef11321ee6957919279076758d47ad956cf3 HEAD is now at 8798ef1... Merge branch 'master' into fbc version 4 good: HEAD is now at 8919b22... Re-add tiling kludge, but only for 965 version 3 good: 3c552af65d28fafec1d09484a8914b690b961349 Update documentation and bump driver version to 2.1.0. and xorg diff of last good and first bad Xorg.log -- Sérgio M. B. 15c15 (==) Log file: /var/log/Xorg.0.log.bad, Time: Mon Jul 30 21:18:37 2007 --- (==) Log file: /var/log/Xorg.0.log.good, Time: Sun Jul 29 19:19:26 2007 390c390 (**) intel(0): Option Tiling false --- (**) intel(0): Option Legacy3D false 397c397,399 (--) intel(0): Will try to allocate texture pool for old Mesa 3D driver. --- (**) intel(0): Will not try to allocate texture pool for old Mesa 3D driver. (II) intel(0): Will try to reserve 32768 kiB of AGP aperture space for the DRM memory manager. 608,637c610,612 (WW) intel(0): Register 0x68000 (TV_CTL) changed from 0x3000 to 0x000c0c00 (WW) intel(0): Register 0x68010 (TV_CSC_Y) changed from 0x to 0x0332012d (WW) intel(0): Register 0x68014 (TV_CSC_Y2) changed from 0x to 0x07d30104 (WW) intel(0): Register 0x68018 (TV_CSC_U) changed from 0x to 0x0733052d (WW) intel(0): Register 0x6801c (TV_CSC_U2) changed from 0x to 0x05c70200 (WW) intel(0): Register 0x68020 (TV_CSC_V) changed from 0x to 0x0340030c (WW) intel(0): Register 0x68024 (TV_CSC_V2) changed from 0x to 0x06d00200 (WW) intel(0): Register 0x68028 (TV_CLR_KNOBS) changed from 0x to 0x10606000 (WW) intel(0): Register 0x6802c (TV_CLR_LEVEL) changed from 0x to 0x010b00e1 (WW) intel(0): Register 0x68030 (TV_H_CTL_1) changed from 0x to 0x00400359 (WW) intel(0): Register 0x68034 (TV_H_CTL_2) changed from 0x to 0x80480022 (WW) intel(0): Register 0x68038 (TV_H_CTL_3) changed from 0x to 0x007c0344 (WW)
Re: last git xf86-video-intel have problem with video out xv
Does Xv based video work again if you add Option tiling false to the Intel device section of your xorg.conf? no , seems that not obey to Option tiling false I try latest git and here is the xorg diff in attach Oh, you should also add Option FramebufferCompression false for that configuration... Jesse - This SF.net email is sponsored by: Splunk Inc. Still grepping through log files to find problems? Stop. Now Search log events and configuration files using AJAX and a browser. Download your FREE copy of Splunk now http://get.splunk.com/ -- ___ Dri-devel mailing list Dri-devel@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/dri-devel
Re: last git xf86-video-intel have problem with video out xv
On Mon, 2007-07-30 at 13:37 -0700, Jesse Barnes wrote: Does Xv based video work again if you add Option tiling false to the Intel device section of your xorg.conf? no , seems that not obey to Option tiling false I try latest git and here is the xorg diff in attach Oh, you should also add Option FramebufferCompression false for that configuration... ok now with Option FramebufferCompression false vo(video output) xv working correctly but other strange thing continue (WW) intel(0): Option Legacy3D is not used (II) AIGLX: Loaded and initialized /usr/lib/dri/i915_dri.so xorg diff in attach Thanks , Jesse -- Sérgio M. B. 15c15 (==) Log file: /var/log/Xorg.0.log.good, Time: Mon Jul 30 21:55:27 2007 --- (==) Log file: /var/log/Xorg.0.log.bad, Time: Mon Jul 30 21:24:42 2007 390d389 (**) intel(0): Option FramebufferCompression false 661,662c660,662 (**) intel(0): Framebuffer compression disabled (**) intel(0): Tiling disabled --- (II) intel(0): Framebuffer compression enabled, forcing tiling on. (**) intel(0): Framebuffer compression enabled (**) intel(0): Tiling enabled 663a664 (II) intel(0): Framebuffer compression enabled 668,671c669,674 (II) intel(0): 0x0002-0x00029fff: HW cursors (40 kB, 0x1f82 physical) (II) intel(0): 0x0002a000-0x00031fff: logical 3D context (32 kB) (II) intel(0): 0x00032000-0x00032fff: overlay registers (4 kB, 0x1f832000 physical) (II) intel(0): 0x0004-0x01837fff: front buffer (24544 kB) --- (II) intel(0): 0x0002-0x0061: compressed frame buffer (6144 kB, 0x1f82 physical) (II) intel(0): 0x0062-0x00620fff: compressed ll buffer (4 kB, 0x1fe2 physical) (II) intel(0): 0x00621000-0x0062afff: HW cursors (40 kB, 0x1fe21000 physical) (II) intel(0): 0x0062b000-0x00632fff: logical 3D context (32 kB) (II) intel(0): 0x00633000-0x00633fff: overlay registers (4 kB, 0x1fe33000 physical) (II) intel(0): 0x00634000-0x00643fff: xaa scratch (64 kB) 673,676c676,679 (II) intel(0): 0x01838000-0x01847fff: xaa scratch (64 kB) (II) intel(0): 0x01848000-0x01c47fff: back buffer (4096 kB) (II) intel(0): 0x01c48000-0x02047fff: depth buffer (4096 kB) (II) intel(0): 0x02048000-0x04047fff: textures (32768 kB) --- (II) intel(0): 0x0080-0x00bf: back buffer (4096 kB) (II) intel(0): 0x00c0-0x00ff: depth buffer (4096 kB) (II) intel(0): 0x0200-0x03ff: front buffer (24544 kB) (II) intel(0): 0x0400-0x05ff: textures (32768 kB) 678,680c681,683 (II) intel(0): front buffer is not tiled (II) intel(0): back buffer is not tiled (II) intel(0): depth buffer is not tiled --- (II) intel(0): front buffer is tiled (II) intel(0): back buffer is tiled (II) intel(0): depth buffer is tiled 692,694c695,697 (II) intel(0): [drm] added 8192 byte SAREA at 0xe03ea000 (II) intel(0): [drm] mapped SAREA 0xe03ea000 to 0xb7f6e000 (II) intel(0): [drm] framebuffer handle = 0xc004 --- (II) intel(0): [drm] added 8192 byte SAREA at 0xe0105000 (II) intel(0): [drm] mapped SAREA 0xe0105000 to 0xb7f0c000 (II) intel(0): [drm] framebuffer handle = 0xc200 700,703c703,706 (II) intel(0): [drm] Front Buffer = 0x28008000 (II) intel(0): [drm] Back Buffer = 0xc1848000 (II) intel(0): [drm] Depth Buffer = 0xc1c48000 (II) intel(0): [drm] textures = 0xc2048000 --- (II) intel(0): [drm] Front Buffer = 0x2840 (II) intel(0): [drm] Back Buffer = 0xc080 (II) intel(0): [drm] Depth Buffer = 0xc0c0 (II) intel(0): [drm] textures = 0xc400 723,727c726,729 (II) intel(0): xf86BindGARTMemory: bind key 0 at 0x007bf000 (pgoffset 1983) (II) intel(0): xf86BindGARTMemory: bind key 1 at 0x01838000 (pgoffset 6200) (II) intel(0): xf86BindGARTMemory: bind key 2 at 0x01848000 (pgoffset 6216) (II) intel(0): xf86BindGARTMemory: bind key 3 at 0x01c48000 (pgoffset 7240) (II) intel(0): xf86BindGARTMemory: bind key 4 at 0x02048000 (pgoffset 8264) --- (II) intel(0): xf86BindGARTMemory: bind key 1 at 0x0080 (pgoffset 2048) (II) intel(0): xf86BindGARTMemory: bind key 2 at 0x00c0 (pgoffset 3072) (II) intel(0): xf86BindGARTMemory: bind key 0 at 0x0200 (pgoffset 8192) (II) intel(0): xf86BindGARTMemory: bind key 3 at 0x0400 (pgoffset 16384) 830a833,842 Synaptics DeviceOff called (II) intel(0): [drm] removed 1 reserved context for kernel (II) intel(0): [drm] unmapping 8192 bytes of SAREA 0xe0105000 at 0xb7f0c000 (EE) intel(0): I830 Vblank Pipe Setup Failed 0 (EE) intel(0): I830 Vblank Pipe Setup Failed 0 (EE) intel(0): I830 Vblank Pipe Setup Failed 0 (II) intel(0): xf86UnbindGARTMemory: unbind key 1 (II) intel(0): xf86UnbindGARTMemory: unbind key 2 (II) intel(0): xf86UnbindGARTMemory: unbind key 0 (II) intel(0): xf86UnbindGARTMemory: unbind key 3 smime.p7s Description: S/MIME cryptographic signature - This SF.net email is sponsored by: Splunk Inc. Still grepping through log files to find
Re: last git xf86-video-intel have problem with video out xv
On Monday, July 30, 2007 2:01 pm Sergio Monteiro Basto wrote: On Mon, 2007-07-30 at 13:37 -0700, Jesse Barnes wrote: Does Xv based video work again if you add Option tiling false to the Intel device section of your xorg.conf? no , seems that not obey to Option tiling false I try latest git and here is the xorg diff in attach Oh, you should also add Option FramebufferCompression false for that configuration... ok now with Option FramebufferCompression false vo(video output) xv working correctly Ok good, that means it's just a tiling bug. I'm still working to track the rest of these down. but other strange thing continue (WW) intel(0): Option Legacy3D is not used I'm not sure about this option, it may be obsolete now... (II) AIGLX: Loaded and initialized /usr/lib/dri/i915_dri.so This is generally a good message since it means your 3D accel module was loaded correctly. Thanks, Jesse - This SF.net email is sponsored by: Splunk Inc. Still grepping through log files to find problems? Stop. Now Search log events and configuration files using AJAX and a browser. Download your FREE copy of Splunk now http://get.splunk.com/ -- ___ Dri-devel mailing list Dri-devel@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/dri-devel
Re: last git xf86-video-intel have problem with video out xv
On Mon, 2007-07-30 at 14:02 -0700, Jesse Barnes wrote: but other strange thing continue (WW) intel(0): Option Legacy3D is not used I will check this problem better I'm not sure about this option, it may be obsolete now... (II) AIGLX: Loaded and initialized /usr/lib/dri/i915_dri.so This is generally a good message since it means your 3D accel module was loaded correctly. yes but I use to have (II) AIGLX: Loaded and initialized /usr/lib/dri/i915tex_dri.so :) Thanks, -- Sérgio M. B. smime.p7s Description: S/MIME cryptographic signature - This SF.net email is sponsored by: Splunk Inc. Still grepping through log files to find problems? Stop. Now Search log events and configuration files using AJAX and a browser. Download your FREE copy of Splunk now http://get.splunk.com/-- ___ Dri-devel mailing list Dri-devel@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/dri-devel
Re: last git xf86-video-intel have problem with video out xv
On Mon, 2007-07-30 at 09:09 -0700, Jesse Barnes wrote: What hardware do you have? Does Xv based video work again if you add Option tiling false to the Intel device section of your xorg.conf? I thought Wang's fix would have taken care of this problem, but it sounds like we still have a bug here... His last fix I saw land was for render acceleration. We're still getting the xv fix sorted out. On Sunday, July 29, 2007 11:29 am Sergio Monteiro Basto wrote: Hi , I done a bisect the git xf86-video-intel and here is the results: -- drv-intel bad vo xv: HEAD is now at 04130ac... Fix i915 rendering for tiled buffer version 1 bad vo xv: 88f8b688e2316ae4a1f7485f0010ce90de54783a HEAD is now at 88f8b68... Fix some physical address handling for 4GB addresses verison 2 bad vo xv: HEAD is now at 4359df9... Fix tiling and fb compression defaults for 965 (not yet fully supported). version 5 bad vo xv: HEAD is now at ca593a5... FBC and tiling changes version 6 good: 8798ef11321ee6957919279076758d47ad956cf3 HEAD is now at 8798ef1... Merge branch 'master' into fbc version 4 good: HEAD is now at 8919b22... Re-add tiling kludge, but only for 965 version 3 good: 3c552af65d28fafec1d09484a8914b690b961349 Update documentation and bump driver version to 2.1.0. and xorg diff of last good and first bad Xorg.log - This SF.net email is sponsored by: Splunk Inc. Still grepping through log files to find problems? Stop. Now Search log events and configuration files using AJAX and a browser. Download your FREE copy of Splunk now http://get.splunk.com/ -- ___ Dri-devel mailing list Dri-devel@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/dri-devel -- Eric Anholt [EMAIL PROTECTED] [EMAIL PROTECTED] [EMAIL PROTECTED] signature.asc Description: This is a digitally signed message part - This SF.net email is sponsored by: Splunk Inc. Still grepping through log files to find problems? Stop. Now Search log events and configuration files using AJAX and a browser. Download your FREE copy of Splunk now http://get.splunk.com/-- ___ Dri-devel mailing list Dri-devel@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/dri-devel
Re: last git xf86-video-intel have problem with video out xv
On Mon, 2007-07-30 at 22:01 +0100, Sergio Monteiro Basto wrote: (WW) intel(0): Option Legacy3D is not used (II) AIGLX: Loaded and initialized /usr/lib/dri/i915_dri.so Did the build time configure check for DRI_MM succeed? -- Earthling Michel Dänzer | http://tungstengraphics.com Libre software enthusiast | Debian, X and DRI developer - This SF.net email is sponsored by: Splunk Inc. Still grepping through log files to find problems? Stop. Now Search log events and configuration files using AJAX and a browser. Download your FREE copy of Splunk now http://get.splunk.com/ -- ___ Dri-devel mailing list Dri-devel@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/dri-devel
last git xf86-video-intel have problem with video out xv
Hi , I done a bisect the git xf86-video-intel and here is the results: -- drv-intel bad vo xv: HEAD is now at 04130ac... Fix i915 rendering for tiled buffer version 1 bad vo xv: 88f8b688e2316ae4a1f7485f0010ce90de54783a HEAD is now at 88f8b68... Fix some physical address handling for 4GB addresses verison 2 bad vo xv: HEAD is now at 4359df9... Fix tiling and fb compression defaults for 965 (not yet fully supported). version 5 bad vo xv: HEAD is now at ca593a5... FBC and tiling changes version 6 good: 8798ef11321ee6957919279076758d47ad956cf3 HEAD is now at 8798ef1... Merge branch 'master' into fbc version 4 good: HEAD is now at 8919b22... Re-add tiling kludge, but only for 965 version 3 good: 3c552af65d28fafec1d09484a8914b690b961349 Update documentation and bump driver version to 2.1.0. and xorg diff of last good and first bad Xorg.log -- Sérgio M. B. 15c15 (==) Log file: /var/log/Xorg.0.log.good, Time: Sun Jul 29 19:19:26 2007 --- (==) Log file: /var/log/Xorg.0.log.bad, Time: Sun Jul 29 19:15:14 2007 462a463 (II) intel(0): fbc disabled 658a660,662 (II) intel(0): Framebuffer compression enabled, forcing tiling on. (**) intel(0): Framebuffer compression enabled (**) intel(0): Tiling enabled 660a665 (II) intel(0): Framebuffer compression enabled 665,668c670,675 (II) intel(0): 0x0002-0x00029fff: HW cursors (40 kB, 0x1f82 physical) (II) intel(0): 0x0002a000-0x00031fff: logical 3D context (32 kB) (II) intel(0): 0x00032000-0x00032fff: overlay registers (4 kB, 0x1f832000 physical) (II) intel(0): 0x0004-0x01837fff: front buffer (24544 kB) --- (II) intel(0): 0x0002-0x0061: compressed frame buffer (6144 kB, 0x1f82 physical) (II) intel(0): 0x0062-0x00620fff: compressed ll buffer (4 kB, 0x1fe2 physical) (II) intel(0): 0x00621000-0x0062afff: HW cursors (40 kB, 0x1fe21000 physical) (II) intel(0): 0x0062b000-0x00632fff: logical 3D context (32 kB) (II) intel(0): 0x00633000-0x00633fff: overlay registers (4 kB, 0x1fe33000 physical) (II) intel(0): 0x00634000-0x00643fff: xaa scratch (64 kB) 670,673c677,680 (II) intel(0): 0x01838000-0x01847fff: xaa scratch (64 kB) (II) intel(0): 0x01c0-0x01ff: back buffer (4096 kB) (II) intel(0): 0x0200-0x023f: depth buffer (4096 kB) (II) intel(0): 0x0240-0x043f: DRI memory manager (32768 kB) --- (II) intel(0): 0x0080-0x00bf: back buffer (4096 kB) (II) intel(0): 0x00c0-0x00ff: depth buffer (4096 kB) (II) intel(0): 0x0200-0x03ff: front buffer (24544 kB) (II) intel(0): 0x0400-0x05ff: DRI memory manager (32768 kB) 675c682 (II) intel(0): front buffer is not tiled --- (II) intel(0): front buffer is tiled 689,691c696,698 (II) intel(0): [drm] added 8192 byte SAREA at 0xe03ea000 (II) intel(0): [drm] mapped SAREA 0xe03ea000 to 0xb7f6b000 (II) intel(0): [drm] framebuffer handle = 0xc004 --- (II) intel(0): [drm] added 8192 byte SAREA at 0xe0105000 (II) intel(0): [drm] mapped SAREA 0xe0105000 to 0xb7f6d000 (II) intel(0): [drm] framebuffer handle = 0xc200 697,699c704,706 (II) intel(0): [drm] Front Buffer = 0x28008000 (II) intel(0): [drm] Back Buffer = 0xc1c0 (II) intel(0): [drm] Depth Buffer = 0xc200 --- (II) intel(0): [drm] Front Buffer = 0x2840 (II) intel(0): [drm] Back Buffer = 0xc080 (II) intel(0): [drm] Depth Buffer = 0xc0c0 718,721c725,727 (II) intel(0): xf86BindGARTMemory: bind key 0 at 0x007bf000 (pgoffset 1983) (II) intel(0): xf86BindGARTMemory: bind key 1 at 0x01838000 (pgoffset 6200) (II) intel(0): xf86BindGARTMemory: bind key 2 at 0x01c0 (pgoffset 7168) (II) intel(0): xf86BindGARTMemory: bind key 3 at 0x0200 (pgoffset 8192) --- (II) intel(0): xf86BindGARTMemory: bind key 1 at 0x0080 (pgoffset 2048) (II) intel(0): xf86BindGARTMemory: bind key 2 at 0x00c0 (pgoffset 3072) (II) intel(0): xf86BindGARTMemory: bind key 0 at 0x0200 (pgoffset 8192) 723a730 (II) intel(0): fbc disabled 825a833,841 Synaptics DeviceOff called (II) intel(0): [drm] removed 1 reserved context for kernel (II) intel(0): [drm] unmapping 8192 bytes of SAREA 0xe0105000 at 0xb7f6d000 (EE) intel(0): I830 Vblank Pipe Setup Failed 0 (EE) intel(0): I830 Vblank Pipe Setup Failed 0 (EE) intel(0): I830 Vblank Pipe Setup Failed 0 (II) intel(0): xf86UnbindGARTMemory: unbind key 1 (II) intel(0): xf86UnbindGARTMemory: unbind key 2 (II) intel(0): xf86UnbindGARTMemory: unbind key 0 smime.p7s Description: S/MIME cryptographic signature - This SF.net email is sponsored by: Splunk Inc. Still grepping through log files to find problems? Stop. Now Search log events and configuration files using AJAX and a browser. Download your FREE copy of Splunk now http://get.splunk.com/-- ___ Dri-devel mailing list Dri-devel@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/dri-devel
