Ok, so I've got everything built and the sample server starts (after applying
the attached patch):
[EMAIL PROTECTED] miniglx]# ./sample_server
[miniglx] probed chipset 0x4e4b
got MMIOAddress 0x20001090 offset 268435456
[drm] added 65536 byte SAREA at 0xa00204fa
[drm] mapped SAREA 0xa00204fa to 0x20001120, size 65536
[drm] framebuffer handle = 0xc041c800
[drm] register handle = 0xc041c010
[pci] 8192 kB allocated with handle 0x0551c000
[pci] ring handle = 0xa0020551c000
[pci] ring read ptr handle = 0xa0020562
[pci] vertex/indirect buffers handle = 0xa00205624000
[pci] GART texture map handle = 0xa00205824000
Using 8 MB AGP aperture
Using 1 MB for the ring buffer
Using 2 MB for vertex/indirect buffers
Using 1 MB for AGP textures
Will use back buffer at offset 0x60
Will use depth buffer at offset 0xb0
Will use 245760 kb for textures at offset 0x100
[drm] Added 32 65536 byte vertex/indirect buffers
[drm] dma control initialized, using IRQ 67
[drm] Initialized kernel gart heap manager, 5111808
page flipping disabled
[miniglx] Setting mode: visible 1280x1024 virtual 1280x1024x32
[miniglx] Readback mode: visible 1280x1024 virtual 1280x1024x32
RADEONEngineRestore
[1]+ Stopped ./sample_server
[EMAIL PROTECTED] miniglx]# bg
then I start up the sample test app:
[EMAIL PROTECTED] miniglx]# ./miniglxtest
[miniglx] probed chipset 0x4e4b
CreateNotify
Authorize - magic 1
Unknown device ID 4E4B, please report. Assuming plain R300.
Using 8 maximum texture units..
sizeof(drm_r300_cmd_header_t)=4
sizeof(drm_radeon_cmd_buffer_t)=32
Allocating 284420 bytes command buffer (max state is 11140 bytes)
*WARN_ONCE*
File r300_state.c function r300Enable line 516
Don't know how to enable polygon offset point/line. Help me !
***
DestroyNotify
Segmentation fault
Any ideas? Is this because I'm using the radeon server/ directory (at least
it looks like the r300 dir's server/ dir has items symlinked back to
radeon/)?
FYI for the unknown id issue, lspci reports this for my device:
17:00.0 VGA compatible controller: ATI Technologies Inc R350 NK [Fire GL X2]
(rev 80) (prog-if 00 [VGA])
Subsystem: ATI Technologies Inc: Unknown device 0152
Flags: bus master, stepping, 66Mhz, medium devsel, latency 0, IRQ 67
Memory at c041c800 (32-bit, prefetchable) [size=128M]
I/O ports at c04023001000 [size=256]
Memory at c041c010 (32-bit, non-prefetchable) [size=64K]
Expansion ROM at c041c012 [disabled] [size=128K]
Capabilities: [58] AGP version 3.0
Capabilities: [50] Power Management version 2
17:00.1 Display controller: ATI Technologies Inc: Unknown device 4e6b (rev 80)
Subsystem: ATI Technologies Inc: Unknown device 0153
Flags: bus master, stepping, 66Mhz, medium devsel, latency 0
Memory at c041d000 (32-bit, prefetchable) [size=128M]
Memory at c041c011 (32-bit, non-prefetchable) [size=64K]
[virtual] Expansion ROM at c041c000 [disabled] [size=1]
Capabilities: [50] Power Management version 2
Thanks,
Jesse
Index: server/radeon_dri.c
===
RCS file: /cvs/mesa/Mesa/src/mesa/drivers/dri/radeon/server/radeon_dri.c,v
retrieving revision 1.15
diff -u -r1.15 radeon_dri.c
--- server/radeon_dri.c 9 Dec 2004 00:18:59 - 1.15
+++ server/radeon_dri.c 4 Mar 2005 21:48:30 -
@@ -14,6 +14,8 @@
#include
#include
+#include "glheader.h"
+
#include "driver.h"
#include "drm.h"
@@ -976,7 +978,7 @@
pSAREAPriv->pfState = info->page_flip_enable;
}
-
+#if !defined(__ia64_) && !defined(__powerpc__)
/* Quick hack to clear the front & back buffers. Could also use
* the clear ioctl to do this, but would need to setup hw state
* first.
@@ -988,6 +990,7 @@
memset((char *)ctx->FBAddress + info->backOffset,
0,
info->backPitch * ctx->cpp * ctx->shared.virtualHeight );
+#endif
/* This is the struct passed to radeon_dri.so for its initialization */
