Re: [PATCH resend] rt5208: Fix a sleep-in-atomic bug in xd_copy_page

2017-06-04 Thread Greg KH 
On Mon, Jun 05, 2017 at 09:26:35AM +0800, Jia-Ju Bai wrote:
> Last patch lacks code explanation, and it is included in this patch.

That should go below the --- line, as a 'v2' patch.  Please fix it up so
I don't have to hand-edit this and resend.

Please read Documentation/SubmittingPatches for how to properly version
your patches.  And also, please put the subsystem in your subject line,
otherwise it's hard for me to find them at times.  Look at how other
patches subject lines are for these same drivers (i.e. you need
'staging' in it...)

thanks,

greg k-h
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ks7010 firmware upload fail

2017-06-04 Thread Tobin C. Harding 
Hi,

I am attempting to test the ks7010 SIDO Wi-Fi driver (drivers/staging/ks7010/).

Currently probing the driver fails because of a firmware upload error.

I am seeking ideas on where to continue troubleshooting this issue.

Test setup:
- Spectec SDW-823 WIFI card (micro SD).
- Raspberry Pi B 1 (kernel 4.9.29) breakout board connected via GPIO pins.
- Driver code from current mainline (commit 
453e102db531ac1ffa55f3e03c4907c063125859)
  (with additional debugging output calls).

Debugging thus far:

- define DEBUG in ks7010 and mmc makefiles (core, card, host).

kernel messages from time of fail:

[ 3746.903972] mmc1: starting CMD53 arg 94002004 flags 01b5
[ 3746.903985] mmc1: blksz 4 blocks 1 flags 0100 tsac 1000 ms nsac 0
[ 3746.904077] mmc1: req done (CMD53): 0: 1000   
[ 3746.904090] mmc1: 4 bytes transferred: 0
[ 3746.904114] mmc1: starting CMD53 arg 94000804 flags 01b5
[ 3746.904126] mmc1: blksz 4 blocks 1 flags 0100 tsac 1000 ms nsac 0
[ 3746.904180] mmc1: req done (CMD53): 0: 1000   
[ 3746.904189] mmc1: 4 bytes transferred: 0
[ 3746.912784] ks7010_upload_firmware: updated index to: 600
[ 3746.912816] mmc1: starting CMD53 arg 9e80 flags 01b5
[ 3746.912831] mmc1: blksz 512 blocks 128 flags 0100 tsac 1000 ms nsac 0
[ 3746.916336] mmc1: req done (CMD53): 0: 1000   
[ 3746.916353] mmc1: 65536 bytes transferred: 0
[ 3746.916420] ks7010_upload_firmware: wrote to address 1 (DATA_WINDOW) 
65536 bytes
[ 3746.916429] ks7010_sdio_data_compare: read 65536 bytes from address 1
[ 3746.916436] debug messages from mmc/core are enabled
[ 3746.916459] mmc1: starting CMD53 arg 1e80 flags 01b5
[ 3746.916472] mmc1: blksz 512 blocks 128 flags 0200 tsac 1000 ms nsac 0
[ 3746.916575] mmc1: req done (CMD53): 0: 1000   
[ 3746.916588] mmc1: 0 bytes transferred: -84
[ 3746.920029] ks7010_sdio_read: sdio_memcpy_fromio() failed: -84
[ 3746.920100] ks7010: ERROR firmware load failed: 9

Briefly, firmware is uploaded to the card in chunks. Each chunk is
read back from the card to verify the transfer.

CMD53 can be seen to succeed when writing the first chunk to the
card. ks7010_sdio_data_compare() is then called which calls
ks7010_sdio_read() to read back the data written to the card. It is
this call that fails.

(CMD52 appears to be successful as well as CMD53 write).

All function calls (including memory addresses on the card, and kernel
buffer addresses) appear to be correct.

Removing the call to ks7010_sdio_data_compare() leads to an MMC read
error for each successive read (via CMD53) by the driver.

My question is should I be digging further into the MMC code or be doing
something else with the driver code?

Any suggestions, no matter how simple, most appreciated. This is my
first time digging into MMC and my first time really trying to trouble
shoot a kernel issue.

thanks,
Tobin.
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[PATCH] Drivers: ccree - style fix, spaces and tabs

2017-06-04 Thread Derek Robson 
Changed code indent to be tabs across whole driver
Found using checkpatch

Signed-off-by: Derek Robson 
---
 drivers/staging/ccree/ssi_cipher.c | 45 +-
 drivers/staging/ccree/ssi_driver.c |  6 ++---
 drivers/staging/ccree/ssi_driver.h |  6 ++---
 drivers/staging/ccree/ssi_fips.h   |  8 +++---
 drivers/staging/ccree/ssi_fips_ext.c   |  4 +--
 drivers/staging/ccree/ssi_fips_ll.c| 40 +++---
 drivers/staging/ccree/ssi_fips_local.c | 28 ++---
 drivers/staging/ccree/ssi_fips_local.h | 12 -
 8 files changed, 75 insertions(+), 74 deletions(-)

diff --git a/drivers/staging/ccree/ssi_cipher.c 
b/drivers/staging/ccree/ssi_cipher.c
index 2dfc6a3bd4c1..34450a5e6573 100644
--- a/drivers/staging/ccree/ssi_cipher.c
+++ b/drivers/staging/ccree/ssi_cipher.c
@@ -258,45 +258,45 @@ static void ssi_blkcipher_exit(struct crypto_tfm *tfm)
 
 
 typedef struct tdes_keys{
-u8  key1[DES_KEY_SIZE];
-u8  key2[DES_KEY_SIZE];
-u8  key3[DES_KEY_SIZE];
+   u8  key1[DES_KEY_SIZE];
+   u8  key2[DES_KEY_SIZE];
+   u8  key3[DES_KEY_SIZE];
 }tdes_keys_t;
 
-static const u8 zero_buff[] = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
-   0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
-   0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
-   0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0};
+static const u8 zero_buff[] = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
+   0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
+   0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
+   0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0};
 
 /* The function verifies that tdes keys are not weak.*/
 static int ssi_fips_verify_3des_keys(const u8 *key, unsigned int keylen)
 {
 #ifdef CCREE_FIPS_SUPPORT
-tdes_keys_t *tdes_key = (tdes_keys_t*)key;
+   tdes_keys_t *tdes_key = (tdes_keys_t*)key;
 
/* verify key1 != key2 and key3 != key2*/
-if (unlikely( (memcmp((u8*)tdes_key->key1, (u8*)tdes_key->key2, 
sizeof(tdes_key->key1)) == 0) ||
+   if (unlikely( (memcmp((u8*)tdes_key->key1, (u8*)tdes_key->key2, 
sizeof(tdes_key->key1)) == 0) ||
  (memcmp((u8*)tdes_key->key3, (u8*)tdes_key->key2, 
sizeof(tdes_key->key3)) == 0) )) {
-return -ENOEXEC;
-}
+   return -ENOEXEC;
+   }
 #endif /* CCREE_FIPS_SUPPORT */
 
-return 0;
+   return 0;
 }
 
 /* The function verifies that xts keys are not weak.*/
 static int ssi_fips_verify_xts_keys(const u8 *key, unsigned int keylen)
 {
 #ifdef CCREE_FIPS_SUPPORT
-/* Weak key is define as key that its first half (128/256 lsb) equals 
its second half (128/256 msb) */
-int singleKeySize = keylen >> 1;
+   /* Weak key is define as key that its first half (128/256 lsb) equals 
its second half (128/256 msb) */
+   int singleKeySize = keylen >> 1;
 
if (unlikely(memcmp(key, &key[singleKeySize], singleKeySize) == 0)) {
return -ENOEXEC;
}
 #endif /* CCREE_FIPS_SUPPORT */
 
-return 0;
+   return 0;
 }
 
 static enum cc_hw_crypto_key hw_key_to_cc_hw_key(int slot_num)
@@ -720,12 +720,13 @@ ssi_blkcipher_create_data_desc(
 }
 
 static int ssi_blkcipher_complete(struct device *dev,
-  struct ssi_ablkcipher_ctx *ctx_p,
-  struct blkcipher_req_ctx *req_ctx,
-  struct scatterlist *dst, struct scatterlist 
*src,
-  unsigned int ivsize,
-  void *areq,
-  void __iomem *cc_base)
+   struct ssi_ablkcipher_ctx *ctx_p,
+   struct blkcipher_req_ctx *req_ctx,
+   struct scatterlist *dst,
+   struct scatterlist *src,
+   unsigned int ivsize,
+   void *areq,
+   void __iomem *cc_base)
 {
int completion_error = 0;
u32 inflight_counter;
@@ -779,7 +780,7 @@ static int ssi_blkcipher_process(
/* No data to process is valid */
return 0;
}
-/*For CTS in case of data size aligned to 16 use CBC mode*/
+   /*For CTS in case of data size aligned to 16 use CBC mode*/
if (((nbytes % AES_BLOCK_SIZE) == 0) && (ctx_p->cipher_mode == 
DRV_CIPHER_CBC_CTS)){
 
ctx_p->cipher_mode = DRV_CIPHER_CBC;
diff --git a/drivers/staging/ccree/ssi_driver.c 
b/drivers/staging/ccree/ssi_driver.c
index 190922970bf0..b9d0dd27e853 100644
--- a/drivers/staging/ccree/ssi_driver.c
+++ b/drivers/staging/ccree/ssi_driver.c
@@ -437,9 +437,9 @@ static void cleanup_cc_resources(struct platform_device 
*plat_d

[BUG] rts5208: Sleeping under a spin lock in free_zone

2017-06-04 Thread Jia-Ju Bai 

According to rtsx_chip.c and xd.c, the driver may sleep under a spin lock.
The function call path is:
rtsx_exclusive_enter_ss (acquire the lock by spin_lock)
  rtsx_enter_ss
rtsx_power_off_card
  xd_cleanup_work
xd_delay_write
  xd_finish_write
xd_set_unused_block
  free_zone
vfree --> may sleep

This bug is found by my static analysis tool and my code review.
I hope to fix it, but I do not have a good solution.

Thanks,
Jia-Ju Bai

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[BUG] rts5208: Sleeping under a spin lock in xd_build_l2p_tbl

2017-06-04 Thread Jia-Ju Bai 

According to rtsx_chip.c and xd.c, the driver may sleep under a spin lock.
The function call path is:
rtsx_exclusive_enter_ss (acquire the lock by spin_lock)
  rtsx_enter_ss
rtsx_power_off_card
  xd_cleanup_work
xd_delay_write
  xd_finish_write
xd_set_unused_block
  xd_build_l2p_tbl
vmalloc --> may sleep

This bug is found by my static analysis tool and my code review.
I hope to fix it, but I do not have a good solution.

Thanks,
Jia-Ju Bai

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[BUG] rts5208: Sleeping under a spin lock in xd_init_l2p_tbl

2017-06-04 Thread Jia-Ju Bai 

According to rtsx_chip.c and xd.c, the driver may sleep under a spin lock.
The function call path is:
rtsx_exclusive_enter_ss (acquire the lock by spin_lock)
  rtsx_enter_ss
rtsx_power_off_card
  xd_cleanup_work
xd_delay_write
  xd_finish_write
xd_set_unused_block
  xd_build_l2p_tbl
xd_init_l2p_tbl
  vmalloc --> may sleep

This bug is found by my static analysis tool and my code review.
I hope to fix it, but I do not have a good solution.

Thanks,
Jia-Ju Bai

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[PATCH] rts5208: Fix a sleep-in-atomic bug in sd_send_cmd_get_rsp

2017-06-04 Thread Jia-Ju Bai 
The driver may sleep under a spin lock, and the function call path is:
rtsx_exclusive_enter_ss (acquire the lock by spin_lock)
  rtsx_enter_ss
rtsx_power_off_card
  sd_cleanup_work
sd_stop_seq_mode
  sd_switch_clock
sd_ddr_tuning
  sd_ddr_pre_tuning_tx
sd_send_cmd_get_rsp
  wait_timeout
schedule_timeout --> may sleep

To fix it, "wait_timeout" is replaced with mdelay in sd_send_cmd_get_rsp.

Signed-off-by: Jia-Ju Bai 
---
 drivers/staging/rts5208/sd.c |2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/staging/rts5208/sd.c b/drivers/staging/rts5208/sd.c
index bdd35b6..fed17ff 100644
--- a/drivers/staging/rts5208/sd.c
+++ b/drivers/staging/rts5208/sd.c
@@ -226,7 +226,7 @@ static int sd_send_cmd_get_rsp(struct rtsx_chip *chip, u8 
cmd_idx,
return STATUS_FAIL;
}
if (rty_cnt < SD_MAX_RETRY_COUNT) {
-   wait_timeout(20);
+   mdelay(20);
rty_cnt++;
goto RTY_SEND_CMD;
} else {
-- 
1.7.9.5


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[PATCH resend] rt5208: Fix a sleep-in-atomic bug in xd_copy_page

2017-06-04 Thread Jia-Ju Bai 
Last patch lacks code explanation, and it is included in this patch.

The driver may sleep under a spin lock, and the function call path is:
rtsx_exclusive_enter_ss (acquire the lock by spin_lock)
  rtsx_enter_ss
rtsx_power_off_card
  xd_cleanup_work
xd_delay_write
  xd_finish_write
xd_copy_page
  wait_timeout
schedule_timeout --> may sleep

To fix it, "wait_timeout" is replaced with mdelay in xd_copy_page.

Signed-off-by: Jia-Ju Bai 
---
 drivers/staging/rts5208/xd.c |2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/staging/rts5208/xd.c b/drivers/staging/rts5208/xd.c
index 85aba05..74d36f9 100644
--- a/drivers/staging/rts5208/xd.c
+++ b/drivers/staging/rts5208/xd.c
@@ -1268,7 +1268,7 @@ static int xd_copy_page(struct rtsx_chip *chip, u32 
old_blk, u32 new_blk,
reg = 0;
rtsx_read_register(chip, XD_CTL, ®);
if (reg & (XD_ECC1_ERROR | XD_ECC2_ERROR)) {
-   wait_timeout(100);
+   mdelay(100);
 
if (detect_card_cd(chip,
   XD_CARD) != STATUS_SUCCESS) {
-- 
1.7.9.5


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[PATCH] rt5208: Fix a sleep-in-atomic bug in xd_copy_page

2017-06-04 Thread Jia-Ju Bai 
Signed-off-by: Jia-Ju Bai 
---
 drivers/staging/rts5208/xd.c |2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/staging/rts5208/xd.c b/drivers/staging/rts5208/xd.c
index 85aba05..74d36f9 100644
--- a/drivers/staging/rts5208/xd.c
+++ b/drivers/staging/rts5208/xd.c
@@ -1268,7 +1268,7 @@ static int xd_copy_page(struct rtsx_chip *chip, u32 
old_blk, u32 new_blk,
reg = 0;
rtsx_read_register(chip, XD_CTL, ®);
if (reg & (XD_ECC1_ERROR | XD_ECC2_ERROR)) {
-   wait_timeout(100);
+   mdelay(100);
 
if (detect_card_cd(chip,
   XD_CARD) != STATUS_SUCCESS) {
-- 
1.7.9.5


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Re: [PATCH] rts5208: Fix a sleep-in-atomic bug in rtsx_exclusive_enter_ss

2017-06-04 Thread Jia-Ju Bai 

On 06/03/2017 04:52 PM, Greg KH wrote:

On Thu, Jun 01, 2017 at 11:43:35AM +0800, Jia-Ju Bai wrote:

The driver may sleep under a spin lock, and the function call path is:
rtsx_exclusive_enter_ss (acquire the lock by spin_lock)
   rtsx_enter_ss
 rtsx_power_off_card
   sd_cleanup_work
 sd_stop_seq_mode
   sd_switch_clock
 sd_ddr_tuning
   sd_ddr_pre_tuning_tx
 sd_change_phase
   wait_timeout
 schedule_timeout -->  may sleep

To fix it, "wait_timeout" is replaced with mdelay in sd_change_phase.

Nice work, how are you finding these bugs?  What tools gives you this
kind of analysis?

thanks,

greg k-h

Hi,

I am very glad to get your praise on my work :)
I recently write a static analysis tool for detecting sleep-in-atomic 
bugs, instead of using existing tools. One reason is that I have 
encountered these bugs for some times when I writing drivers.
I am still improving my tool and detecting other similar bugs in Linux 
kernel. If you have suggestions or comments on my work, please feel free 
to contact me :)


Thanks,
Jia-Ju Bai

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[PATCH] staging: sm750fb: change default screen resolution

2017-06-04 Thread Sudip Mukherjee 
Update the default screen resolution and also use 24bpp for a better
screen performance.

Tested-by: Teddy Wang 
Signed-off-by: Sudip Mukherjee 
---
 drivers/staging/sm750fb/sm750.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/staging/sm750fb/sm750.c b/drivers/staging/sm750fb/sm750.c
index a7f722a..d5934f3 100644
--- a/drivers/staging/sm750fb/sm750.c
+++ b/drivers/staging/sm750fb/sm750.c
@@ -33,7 +33,7 @@
 static int g_noaccel;
 static int g_nomtrr;
 static const char *g_fbmode[] = {NULL, NULL};
-static const char *g_def_fbmode = "800x600-16@60";
+static const char *g_def_fbmode = "1024x768-24@60";
 static char *g_settings;
 static int g_dualview;
 static char *g_option;
-- 
1.9.1

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Re: [PATCH v7 16/34] [media] add Omnivision OV5640 sensor driver

2017-06-04 Thread Steve Longerbeam 



On 06/03/2017 11:02 AM, Steve Longerbeam wrote:

Hi Sakari,


On 05/29/2017 11:56 PM, Sakari Ailus wrote:

Hi Steve,

On Mon, May 29, 2017 at 02:50:34PM -0700, Steve Longerbeam wrote:




+
+static int ov5640_s_ctrl(struct v4l2_ctrl *ctrl)
+{
+struct v4l2_subdev *sd = ctrl_to_sd(ctrl);
+struct ov5640_dev *sensor = to_ov5640_dev(sd);
+int ret = 0;
+
+mutex_lock(&sensor->lock);
Could you use the same lock for the controls as you use for the 
rest? Just

setting handler->lock after handler init does the trick.


Can you please rephrase, I don't follow. "same lock for the controls as
you use for the rest" - there's only one device lock owned by this 
driver

and I am already using that same lock.


There's another in the control handler. You could use your own lock 
for the

control handler as well.


I still don't understand.



Hi Sakari, sorry I see what you are referring to now. The lock
in 'struct v4l2_ctrl_handler' can be overridden by a caller's own
lock. Yes that's a good idea, I'll do that.

Steve

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[PATCH] staging: comedi: ni_labpc_isadma: fixed a comment coding style issue

2017-06-04 Thread Adrian Stanciu 
Fixed a BLOCK_COMMENT_STYLE warning reported by checkpatch.pl script.

Signed-off-by: Adrian Stanciu 
---
 drivers/staging/comedi/drivers/ni_labpc_isadma.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/staging/comedi/drivers/ni_labpc_isadma.h 
b/drivers/staging/comedi/drivers/ni_labpc_isadma.h
index b8a1b0e..e93f790 100644
--- a/drivers/staging/comedi/drivers/ni_labpc_isadma.h
+++ b/drivers/staging/comedi/drivers/ni_labpc_isadma.h
@@ -1,6 +1,6 @@
 /*
  * ni_labpc ISA DMA support.
-*/
+ */
 
 #ifndef _NI_LABPC_ISADMA_H
 #define _NI_LABPC_ISADMA_H
-- 
2.7.4

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[PATCH] staging: ks7010: use le16_to_cpu() to access __le16 field

2017-06-04 Thread dick 
From: Richard Porter 

Fixes sparse warning:
drivers/staging/ks7010/ks_hostif.c:959:24: warning: restricted __le16
degrades to integer

Signed-off-by: Richard Porter 
---
Every access of struct association_request_t.req_ies_size is wrapped with
le16_to_cpu(), except the one at ks_hostif.c:959.

 drivers/staging/ks7010/ks_hostif.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/staging/ks7010/ks_hostif.c 
b/drivers/staging/ks7010/ks_hostif.c
index 79634be..697347b 100644
--- a/drivers/staging/ks7010/ks_hostif.c
+++ b/drivers/staging/ks7010/ks_hostif.c
@@ -956,7 +956,7 @@ void hostif_associate_indication(struct ks_wlan_private 
*priv)
wrqu.data.length += sizeof(associnfo_leader1) - 1;
pbuf += sizeof(associnfo_leader1) - 1;

-   pb += assoc_req->req_ies_size;
+   pb += le16_to_cpu(assoc_req->req_ies_size);
for (i = 0; i < le16_to_cpu(assoc_resp->resp_ies_size); i++)
pbuf += sprintf(pbuf, "%02x", *(pb + i));
wrqu.data.length += (le16_to_cpu(assoc_resp->resp_ies_size)) * 2;
--
2.7.4

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Re: [PATCH] staging: ks7010: define ether_hdr.h_proto to be big-endian

2017-06-04 Thread Dick Porter 
On Sat, Jun 03, 2017 at 05:38:12PM +0900, Greg KH wrote:
> On Sun, May 21, 2017 at 10:15:11AM +0100, d...@acm.org wrote:
> > From: Richard Porter 
> > 
> > Fixes sparse warnings:
> > drivers/staging/ks7010/ks_hostif.c:339:21: warning: cast to restricted 
> > __be16
> > drivers/staging/ks7010/ks_hostif.c:430:21: warning: cast to restricted 
> > __be16
> > drivers/staging/ks7010/ks_hostif.c:1226:21: warning: cast to restricted 
> > __be16
> > 
> > Signed-off-by: Richard Porter 
> > ---
> >  drivers/staging/ks7010/eap_packet.h | 2 +-
> >  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> Does not apply to my tree at all :(

Looks like someone beat me to it :(

- Dick

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Re: [PATCH 1/4] Staging: ccree: cc_crypto_ctx.h: Added * on subsequent lines of a comment block.

2017-06-04 Thread Greg KH 
On Sun, Jun 04, 2017 at 05:02:08AM +0530, srishti sharma wrote:
> Added * on subsequent lines of a comment block.
> 
> Signed-off-by: srishti sharma 
> ---
>  drivers/staging/ccree/cc_crypto_ctx.h | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)

This whole series also does not apply.  Note, this driver is under
active development, you are probably running into the problem that lots
of people are working on it at the same time.

sorry,

greg k-h
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Re: [PATCH] Staging: ccree: ssi_aead.h: Fixed a comment coding style issue.

2017-06-04 Thread Greg KH 
On Sat, Jun 03, 2017 at 06:04:59PM +0530, srishti sharma wrote:
> Fixed a comment coding style issue , block comments use * on subsequent lines.
> 
> Signed-off-by: srishti sharma 
> ---
>  drivers/staging/ccree/ssi_aead.h | 5 +++--
>  1 file changed, 3 insertions(+), 2 deletions(-)

Patch does not apply to my staging-testing branch, sorry :(
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[PATCH v3 18/18] staging: ccree: remove descriptor context definitions

2017-06-04 Thread Gilad Ben-Yossef 
Remove definitions of descriptor context which are not used
in the driver.

Signed-off-by: Gilad Ben-Yossef 
---
 drivers/staging/ccree/cc_crypto_ctx.h | 86 ---
 1 file changed, 86 deletions(-)

diff --git a/drivers/staging/ccree/cc_crypto_ctx.h 
b/drivers/staging/ccree/cc_crypto_ctx.h
index 20f3f9f..591f6fd 100644
--- a/drivers/staging/ccree/cc_crypto_ctx.h
+++ b/drivers/staging/ccree/cc_crypto_ctx.h
@@ -196,91 +196,5 @@ enum drv_crypto_padding_type {
DRV_PADDING_RESERVE32B = S32_MAX
 };
 
-/***/
-/* DESCRIPTOR BASED CONTEXTS ***/
-/***/
-
- /* Generic context ("super-class") */
-struct drv_ctx_generic {
-   enum drv_crypto_alg alg;
-} __attribute__((__may_alias__));
-
-struct drv_ctx_hash {
-   enum drv_crypto_alg alg; /* DRV_CRYPTO_ALG_HASH */
-   enum drv_hash_mode mode;
-   u8 digest[CC_DIGEST_SIZE_MAX];
-   /* reserve to end of allocated context size */
-   u8 reserved[CC_CTX_SIZE - 2 * sizeof(u32) -
-   CC_DIGEST_SIZE_MAX];
-};
-
-/* NOTE! drv_ctx_hmac should have the same structure as drv_ctx_hash except
- * k0, k0_size fields
- */
-struct drv_ctx_hmac {
-   enum drv_crypto_alg alg; /* DRV_CRYPTO_ALG_HMAC */
-   enum drv_hash_mode mode;
-   u8 digest[CC_DIGEST_SIZE_MAX];
-   u32 k0[CC_HMAC_BLOCK_SIZE_MAX / sizeof(u32)];
-   u32 k0_size;
-   /* reserve to end of allocated context size */
-   u8 reserved[CC_CTX_SIZE - 3 * sizeof(u32) -
-   CC_DIGEST_SIZE_MAX - CC_HMAC_BLOCK_SIZE_MAX];
-};
-
-struct drv_ctx_cipher {
-   enum drv_crypto_alg alg; /* DRV_CRYPTO_ALG_AES */
-   enum drv_cipher_mode mode;
-   enum drv_crypto_direction direction;
-   enum drv_crypto_key_type crypto_key_type;
-   enum drv_crypto_padding_type padding_type;
-   u32 key_size; /* numeric value in bytes   */
-   u32 data_unit_size; /* required for XTS */
-   /* block_state is the AES engine block state.
-* It is used by the host to pass IV or counter at initialization.
-* It is used by SeP for intermediate block chaining state and for
-* returning MAC algorithms results.
-*/
-   u8 block_state[CC_AES_BLOCK_SIZE];
-   u8 key[CC_AES_KEY_SIZE_MAX];
-   u8 xex_key[CC_AES_KEY_SIZE_MAX];
-   /* reserve to end of allocated context size */
-   u32 reserved[CC_DRV_CTX_SIZE_WORDS - 7 -
-   CC_AES_BLOCK_SIZE / sizeof(u32) - 2 *
-   (CC_AES_KEY_SIZE_MAX / sizeof(u32))];
-};
-
-/* authentication and encryption with associated data class */
-struct drv_ctx_aead {
-   enum drv_crypto_alg alg; /* DRV_CRYPTO_ALG_AES */
-   enum drv_cipher_mode mode;
-   enum drv_crypto_direction direction;
-   u32 key_size; /* numeric value in bytes   */
-   u32 nonce_size; /* nonce size (octets) */
-   u32 header_size; /* finit additional data size (octets) */
-   u32 text_size; /* finit text data size (octets) */
-   u32 tag_size; /* mac size, element of {4, 6, 8, 10, 12, 14, 16} */
-   /* block_state1/2 is the AES engine block state */
-   u8 block_state[CC_AES_BLOCK_SIZE];
-   u8 mac_state[CC_AES_BLOCK_SIZE]; /* MAC result */
-   u8 nonce[CC_AES_BLOCK_SIZE]; /* nonce buffer */
-   u8 key[CC_AES_KEY_SIZE_MAX];
-   /* reserve to end of allocated context size */
-   u32 reserved[CC_DRV_CTX_SIZE_WORDS - 8 -
-   3 * (CC_AES_BLOCK_SIZE / sizeof(u32)) -
-   CC_AES_KEY_SIZE_MAX / sizeof(u32)];
-};
-
-/***/
-/* MESSAGE BASED CONTEXTS **/
-/***/
-
-/* Get the address of a @member within a given @ctx address
- * @ctx: The context address
- * @type: Type of context structure
- * @member: Associated context field
- */
-#define GET_CTX_FIELD_ADDR(ctx, type, member) ((ctx) + offsetof(type, member))
-
 #endif /* _CC_CRYPTO_CTX_H_ */
 
-- 
2.1.4

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[PATCH v3 17/18] staging: ccree: remove last remnants of sblkcipher

2017-06-04 Thread Gilad Ben-Yossef 
The cipher code had some left overs of an attempt to support
synch. cipher API with the HW. Remove the code handling this.

Signed-off-by: Gilad Ben-Yossef 
---
 drivers/staging/ccree/ssi_cipher.c | 102 +++--
 drivers/staging/ccree/ssi_driver.h |   1 -
 2 files changed, 6 insertions(+), 97 deletions(-)

diff --git a/drivers/staging/ccree/ssi_cipher.c 
b/drivers/staging/ccree/ssi_cipher.c
index e16fd36..2dfc6a3 100644
--- a/drivers/staging/ccree/ssi_cipher.c
+++ b/drivers/staging/ccree/ssi_cipher.c
@@ -36,7 +36,6 @@
 #define MAX_ABLKCIPHER_SEQ_LEN 6
 
 #define template_ablkciphertemplate_u.ablkcipher
-#define template_sblkciphertemplate_u.blkcipher
 
 #define SSI_MIN_AES_XTS_SIZE 0x10
 #define SSI_MAX_AES_XTS_SIZE 0x2000
@@ -886,69 +885,6 @@ static void ssi_ablkcipher_complete(struct device *dev, 
void *ssi_req, void __io
   ivsize, areq, cc_base);
 }
 
-
-
-static int ssi_sblkcipher_init(struct crypto_tfm *tfm)
-{
-   struct ssi_ablkcipher_ctx *ctx_p = crypto_tfm_ctx(tfm);
-
-   /* Allocate sync ctx buffer */
-   ctx_p->sync_ctx = kmalloc(sizeof(struct blkcipher_req_ctx), 
GFP_KERNEL|GFP_DMA);
-   if (!ctx_p->sync_ctx) {
-   SSI_LOG_ERR("Allocating sync ctx buffer in context failed\n");
-   return -ENOMEM;
-   }
-   SSI_LOG_DEBUG("Allocated sync ctx buffer in context 
ctx_p->sync_ctx=@%p\n",
-   
ctx_p->sync_ctx);
-
-   return ssi_blkcipher_init(tfm);
-}
-
-
-static void ssi_sblkcipher_exit(struct crypto_tfm *tfm)
-{
-   struct ssi_ablkcipher_ctx *ctx_p = crypto_tfm_ctx(tfm);
-
-   kfree(ctx_p->sync_ctx);
-   SSI_LOG_DEBUG("Free sync ctx buffer in context ctx_p->sync_ctx=@%p\n", 
ctx_p->sync_ctx);
-
-   ssi_blkcipher_exit(tfm);
-}
-
-#ifdef SYNC_ALGS
-static int ssi_sblkcipher_encrypt(struct blkcipher_desc *desc,
-struct scatterlist *dst, struct scatterlist *src,
-unsigned int nbytes)
-{
-   struct crypto_blkcipher *blk_tfm = desc->tfm;
-   struct crypto_tfm *tfm = crypto_blkcipher_tfm(blk_tfm);
-   struct ssi_ablkcipher_ctx *ctx_p = crypto_tfm_ctx(tfm);
-   struct blkcipher_req_ctx *req_ctx = ctx_p->sync_ctx;
-   unsigned int ivsize = crypto_blkcipher_ivsize(blk_tfm);
-
-   req_ctx->backup_info = desc->info;
-   req_ctx->is_giv = false;
-
-   return ssi_blkcipher_process(tfm, req_ctx, dst, src, nbytes, 
desc->info, ivsize, NULL, DRV_CRYPTO_DIRECTION_ENCRYPT);
-}
-
-static int ssi_sblkcipher_decrypt(struct blkcipher_desc *desc,
-struct scatterlist *dst, struct scatterlist *src,
-unsigned int nbytes)
-{
-   struct crypto_blkcipher *blk_tfm = desc->tfm;
-   struct crypto_tfm *tfm = crypto_blkcipher_tfm(blk_tfm);
-   struct ssi_ablkcipher_ctx *ctx_p = crypto_tfm_ctx(tfm);
-   struct blkcipher_req_ctx *req_ctx = ctx_p->sync_ctx;
-   unsigned int ivsize = crypto_blkcipher_ivsize(blk_tfm);
-
-   req_ctx->backup_info = desc->info;
-   req_ctx->is_giv = false;
-
-   return ssi_blkcipher_process(tfm, req_ctx, dst, src, nbytes, 
desc->info, ivsize, NULL, DRV_CRYPTO_DIRECTION_DECRYPT);
-}
-#endif
-
 /* Async wrap functions */
 
 static int ssi_ablkcipher_init(struct crypto_tfm *tfm)
@@ -1014,7 +950,6 @@ static struct ssi_alg_template blkcipher_algs[] = {
},
.cipher_mode = DRV_CIPHER_XTS,
.flow_mode = S_DIN_to_AES,
-.synchronous = false,
},
{
.name = "xts(aes)",
@@ -1031,7 +966,6 @@ static struct ssi_alg_template blkcipher_algs[] = {
},
.cipher_mode = DRV_CIPHER_XTS,
.flow_mode = S_DIN_to_AES,
-   .synchronous = false,
},
{
.name = "xts(aes)",
@@ -1048,7 +982,6 @@ static struct ssi_alg_template blkcipher_algs[] = {
},
.cipher_mode = DRV_CIPHER_XTS,
.flow_mode = S_DIN_to_AES,
-   .synchronous = false,
},
 #endif /*SSI_CC_HAS_AES_XTS*/
 #if SSI_CC_HAS_AES_ESSIV
@@ -1067,7 +1000,6 @@ static struct ssi_alg_template blkcipher_algs[] = {
},
.cipher_mode = DRV_CIPHER_ESSIV,
.flow_mode = S_DIN_to_AES,
-   .synchronous = false,
},
{
.name = "essiv(aes)",
@@ -1084,7 +1016,6 @@ static struct ssi_alg_template blkcipher_algs[] = {
},
.cipher_mode = DRV_CIPHER_ESSIV,
.flow_mode = S_DIN_to_AES,
-   .synchronous = false,
},
{
.name = "essiv(aes)",
@@ -1101,7 +1032,6 @@ static struct ssi_alg_template blkcipher_algs[] = {
},
.cipher_mode = DRV_CIPHER_ESSIV,
.flow_mode = S_DIN_to_AES,

[PATCH v3 15/18] staging: ccree: fix wrong whitespace usage

2017-06-04 Thread Gilad Ben-Yossef 
Some of the register definition files had none
kernel coding style usage of tabs vs. spaces in macro
definitions. This patch fixes them.

Signed-off-by: Gilad Ben-Yossef 
---
 drivers/staging/ccree/dx_crys_kernel.h | 308 -
 drivers/staging/ccree/dx_host.h| 256 +--
 2 files changed, 282 insertions(+), 282 deletions(-)

diff --git a/drivers/staging/ccree/dx_crys_kernel.h 
b/drivers/staging/ccree/dx_crys_kernel.h
index a776e24..2196030 100644
--- a/drivers/staging/ccree/dx_crys_kernel.h
+++ b/drivers/staging/ccree/dx_crys_kernel.h
@@ -20,161 +20,161 @@
 // --
 // BLOCK: DSCRPTR
 // --
-#define DX_DSCRPTR_COMPLETION_COUNTER_REG_OFFSET   0xE00UL
-#define DX_DSCRPTR_COMPLETION_COUNTER_COMPLETION_COUNTER_BIT_SHIFT 0x0UL
-#define DX_DSCRPTR_COMPLETION_COUNTER_COMPLETION_COUNTER_BIT_SIZE  0x6UL
-#define DX_DSCRPTR_COMPLETION_COUNTER_OVERFLOW_COUNTER_BIT_SHIFT   0x6UL
-#define DX_DSCRPTR_COMPLETION_COUNTER_OVERFLOW_COUNTER_BIT_SIZE0x1UL
-#define DX_DSCRPTR_SW_RESET_REG_OFFSET 0xE40UL
-#define DX_DSCRPTR_SW_RESET_VALUE_BIT_SHIFT0x0UL
-#define DX_DSCRPTR_SW_RESET_VALUE_BIT_SIZE 0x1UL
-#define DX_DSCRPTR_QUEUE_SRAM_SIZE_REG_OFFSET  0xE60UL
-#define DX_DSCRPTR_QUEUE_SRAM_SIZE_NUM_OF_DSCRPTR_BIT_SHIFT0x0UL
-#define DX_DSCRPTR_QUEUE_SRAM_SIZE_NUM_OF_DSCRPTR_BIT_SIZE 0xAUL
-#define DX_DSCRPTR_QUEUE_SRAM_SIZE_DSCRPTR_SRAM_SIZE_BIT_SHIFT 0xAUL
-#define DX_DSCRPTR_QUEUE_SRAM_SIZE_DSCRPTR_SRAM_SIZE_BIT_SIZE  0xCUL
-#define DX_DSCRPTR_QUEUE_SRAM_SIZE_SRAM_SIZE_BIT_SHIFT 0x16UL
-#define DX_DSCRPTR_QUEUE_SRAM_SIZE_SRAM_SIZE_BIT_SIZE  0x3UL
-#define DX_DSCRPTR_SINGLE_ADDR_EN_REG_OFFSET   0xE64UL
-#define DX_DSCRPTR_SINGLE_ADDR_EN_VALUE_BIT_SHIFT  0x0UL
-#define DX_DSCRPTR_SINGLE_ADDR_EN_VALUE_BIT_SIZE   0x1UL
-#define DX_DSCRPTR_MEASURE_CNTR_REG_OFFSET 0xE68UL
-#define DX_DSCRPTR_MEASURE_CNTR_VALUE_BIT_SHIFT0x0UL
-#define DX_DSCRPTR_MEASURE_CNTR_VALUE_BIT_SIZE 0x20UL
-#define DX_DSCRPTR_QUEUE_WORD0_REG_OFFSET  0xE80UL
-#define DX_DSCRPTR_QUEUE_WORD0_VALUE_BIT_SHIFT 0x0UL
-#define DX_DSCRPTR_QUEUE_WORD0_VALUE_BIT_SIZE  0x20UL
-#define DX_DSCRPTR_QUEUE_WORD1_REG_OFFSET  0xE84UL
-#define DX_DSCRPTR_QUEUE_WORD1_DIN_DMA_MODE_BIT_SHIFT  0x0UL
-#define DX_DSCRPTR_QUEUE_WORD1_DIN_DMA_MODE_BIT_SIZE   0x2UL
-#define DX_DSCRPTR_QUEUE_WORD1_DIN_SIZE_BIT_SHIFT  0x2UL
-#define DX_DSCRPTR_QUEUE_WORD1_DIN_SIZE_BIT_SIZE   0x18UL
-#define DX_DSCRPTR_QUEUE_WORD1_NS_BIT_BIT_SHIFT0x1AUL
-#define DX_DSCRPTR_QUEUE_WORD1_NS_BIT_BIT_SIZE 0x1UL
-#define DX_DSCRPTR_QUEUE_WORD1_DIN_CONST_VALUE_BIT_SHIFT   0x1BUL
-#define DX_DSCRPTR_QUEUE_WORD1_DIN_CONST_VALUE_BIT_SIZE0x1UL
-#define DX_DSCRPTR_QUEUE_WORD1_NOT_LAST_BIT_SHIFT  0x1CUL
-#define DX_DSCRPTR_QUEUE_WORD1_NOT_LAST_BIT_SIZE   0x1UL
-#define DX_DSCRPTR_QUEUE_WORD1_LOCK_QUEUE_BIT_SHIFT0x1DUL
-#define DX_DSCRPTR_QUEUE_WORD1_LOCK_QUEUE_BIT_SIZE 0x1UL
-#define DX_DSCRPTR_QUEUE_WORD1_NOT_USED_BIT_SHIFT  0x1EUL
-#define DX_DSCRPTR_QUEUE_WORD1_NOT_USED_BIT_SIZE   0x2UL
-#define DX_DSCRPTR_QUEUE_WORD2_REG_OFFSET  0xE88UL
-#define DX_DSCRPTR_QUEUE_WORD2_VALUE_BIT_SHIFT 0x0UL
-#define DX_DSCRPTR_QUEUE_WORD2_VALUE_BIT_SIZE  0x20UL
-#define DX_DSCRPTR_QUEUE_WORD3_REG_OFFSET  0xE8CUL
-#define DX_DSCRPTR_QUEUE_WORD3_DOUT_DMA_MODE_BIT_SHIFT 0x0UL
-#define DX_DSCRPTR_QUEUE_WORD3_DOUT_DMA_MODE_BIT_SIZE  0x2UL
-#define DX_DSCRPTR_QUEUE_WORD3_DOUT_SIZE_BIT_SHIFT 0x2UL
-#define DX_DSCRPTR_QUEUE_WORD3_DOUT_SIZE_BIT_SIZE  0x18UL
-#define DX_DSCRPTR_QUEUE_WORD3_NS_BIT_BIT_SHIFT0x1AUL
-#define DX_DSCRPTR_QUEUE_WORD3_NS_BIT_BIT_SIZE 0x1UL
-#define DX_DSCRPTR_QUEUE_WORD3_DOUT_LAST_IND_BIT_SHIFT 0x1BUL
-#define DX_DSCRPTR_QUEUE_WORD3_DOUT_LAST_IND_BIT_SIZE  0x1UL
-#define DX_DSCRPTR_QUEUE_WORD3_HASH_XOR_BIT_BIT_SHIFT  0x1DUL
-#define DX_DSCRPTR_QUEUE_WORD3_HASH_XOR_BIT_BIT_SIZE   0x1UL
-#define DX_DSCRPTR_QUEUE_WORD3_NOT_USED_BIT_SHIFT  0x1EUL
-#define DX_DSCRPTR_QUEUE_WORD3_NOT_USED_BIT_SIZE   0x1UL
-#define DX_DSCRPTR_QUEUE_WORD3_QUEUE_LAST_IND_BIT_SHIFT0x1FUL
-#define DX_DSCRPTR_QUEUE_WORD3_QUEUE_LAST_IND_BIT_SIZE 0x1UL
-#define DX_DSCRPTR_QUEUE_WORD4_REG_OFFSET  0xE90UL
-#define DX_DSCRPTR_QUEUE_WORD4_DATA_FLOW_MODE_BIT_SHIFT0x0UL
-#define DX_DSCRPTR_QUEUE_WORD4_DATA_FLOW_MODE_BIT_SIZE 0x6UL
-#define DX_DSCRPTR_QUEUE_WORD4_AES_SEL_N_HASH_BIT_SHIFT0x6UL
-#define DX_DSCRPTR_QUEUE_WORD4_AES_SEL_N_HASH_BIT_SIZE 0x1UL
-#define DX_DSCRPTR_QUEUE_WORD4_AES_XOR_CRYPTO_KEY_BIT_SHIFT0x7UL
-#define DX_DSCRPTR_QUEUE_WORD4_AES_XOR_CRYPTO_KEY_BIT_SIZE 0x1UL
-#define DX_DSCRPTR_QUEUE_WORD4_ACK_NEEDED_BIT_SHIFT0x8UL
-#define DX_DSCRPTR_QUEUE_WORD4_ACK_NEEDED_BIT_SIZE 0x2UL
-#define DX_DSCRPTR_QUEUE_WORD4_CIPHER_MOD

[PATCH v3 16/18] staging: ccree: remove last remnants of sash algo

2017-06-04 Thread Gilad Ben-Yossef 
The hash code had some left overs from a misguided attempt
to support shash API with the HW. Remove the code handling
this.

Signed-off-by: Gilad Ben-Yossef 
---
 drivers/staging/ccree/ssi_hash.c | 448 +++
 1 file changed, 127 insertions(+), 321 deletions(-)

diff --git a/drivers/staging/ccree/ssi_hash.c b/drivers/staging/ccree/ssi_hash.c
index 47bc496..ed1c672 100644
--- a/drivers/staging/ccree/ssi_hash.c
+++ b/drivers/staging/ccree/ssi_hash.c
@@ -76,15 +76,11 @@ static void ssi_hash_create_cmac_setup(struct ahash_request 
*areq,
 
 struct ssi_hash_alg {
struct list_head entry;
-   bool synchronize;
int hash_mode;
int hw_mode;
int inter_digestsize;
struct ssi_drvdata *drvdata;
-   union {
-   struct ahash_alg ahash_alg;
-   struct shash_alg shash_alg;
-   };
+   struct ahash_alg ahash_alg;
 };
 
 
@@ -112,8 +108,6 @@ struct ssi_hash_ctx {
bool is_hmac;
 };
 
-static const struct crypto_type crypto_shash_type;
-
 static void ssi_hash_create_data_desc(
struct ahash_req_ctx *areq_ctx,
struct ssi_hash_ctx *ctx,
@@ -1015,15 +1009,9 @@ static int ssi_hash_setkey(void *hash,
 SSI_LOG_DEBUG("ssi_hash_setkey: start keylen: %d", keylen);
 
CHECK_AND_RETURN_UPON_FIPS_ERROR();
-   if (synchronize) {
-   ctx = crypto_shash_ctx(((struct crypto_shash *)hash));
-   blocksize = crypto_tfm_alg_blocksize(&((struct crypto_shash 
*)hash)->base);
-   digestsize = crypto_shash_digestsize(((struct crypto_shash 
*)hash));
-   } else {
-   ctx = crypto_ahash_ctx(((struct crypto_ahash *)hash));
-   blocksize = crypto_tfm_alg_blocksize(&((struct crypto_ahash 
*)hash)->base);
-   digestsize = crypto_ahash_digestsize(((struct crypto_ahash 
*)hash));
-   }
+   ctx = crypto_ahash_ctx(((struct crypto_ahash *)hash));
+   blocksize = crypto_tfm_alg_blocksize(&((struct crypto_ahash 
*)hash)->base);
+   digestsize = crypto_ahash_digestsize(((struct crypto_ahash *)hash));
 
larval_addr = ssi_ahash_get_larval_digest_sram_addr(
ctx->drvdata, ctx->hash_mode);
@@ -1184,13 +1172,8 @@ static int ssi_hash_setkey(void *hash,
rc = send_request(ctx->drvdata, &ssi_req, desc, idx, 0);
 
 out:
-   if (rc != 0) {
-   if (synchronize) {
-   crypto_shash_set_flags((struct crypto_shash *)hash, 
CRYPTO_TFM_RES_BAD_KEY_LEN);
-   } else {
-   crypto_ahash_set_flags((struct crypto_ahash *)hash, 
CRYPTO_TFM_RES_BAD_KEY_LEN);
-   }
-   }
+   if (rc)
+   crypto_ahash_set_flags((struct crypto_ahash *)hash, 
CRYPTO_TFM_RES_BAD_KEY_LEN);
 
if (ctx->key_params.key_dma_addr) {
dma_unmap_single(&ctx->drvdata->plat_dev->dev,
@@ -1395,23 +1378,6 @@ static int ssi_hash_alloc_ctx(struct ssi_hash_ctx *ctx)
return -ENOMEM;
 }
 
-static int ssi_shash_cra_init(struct crypto_tfm *tfm)
-{
-   struct ssi_hash_ctx *ctx = crypto_tfm_ctx(tfm);
-   struct shash_alg * shash_alg =
-   container_of(tfm->__crt_alg, struct shash_alg, base);
-   struct ssi_hash_alg *ssi_alg =
-   container_of(shash_alg, struct ssi_hash_alg, shash_alg);
-
-   CHECK_AND_RETURN_UPON_FIPS_ERROR();
-   ctx->hash_mode = ssi_alg->hash_mode;
-   ctx->hw_mode = ssi_alg->hw_mode;
-   ctx->inter_digestsize = ssi_alg->inter_digestsize;
-   ctx->drvdata = ssi_alg->drvdata;
-
-   return ssi_hash_alloc_ctx(ctx);
-}
-
 static int ssi_ahash_cra_init(struct crypto_tfm *tfm)
 {
struct ssi_hash_ctx *ctx = crypto_tfm_ctx(tfm);
@@ -1764,100 +1730,6 @@ static int ssi_mac_digest(struct ahash_request *req)
return rc;
 }
 
-//shash wrap functions
-#ifdef SYNC_ALGS
-static int ssi_shash_digest(struct shash_desc *desc,
-   const u8 *data, unsigned int len, u8 *out)
-{
-   struct ahash_req_ctx *state = shash_desc_ctx(desc);
-   struct crypto_shash *tfm = desc->tfm;
-   struct ssi_hash_ctx *ctx = crypto_shash_ctx(tfm);
-   u32 digestsize = crypto_shash_digestsize(tfm);
-   struct scatterlist src;
-
-   if (len == 0) {
-   return ssi_hash_digest(state, ctx, digestsize, NULL, 0, out, 
NULL);
-   }
-
-   /* sg_init_one may crash when len is 0 (depends on kernel 
configuration) */
-   sg_init_one(&src, (const void *)data, len);
-
-   return ssi_hash_digest(state, ctx, digestsize, &src, len, out, NULL);
-}
-
-static int ssi_shash_update(struct shash_desc *desc,
-   const u8 *data, unsigned int 
len)
-{
-   struct ahash_req_ctx *state = shash_desc_ctx(desc);
-   struct crypto_shash *tfm = desc->tfm;
-   struct ssi_hash_ctx *ctx = crypto_shash_ctx(tfm);
-   u32 blocksize = crypto_tfm_alg_blocksize(

[PATCH v3 14/18] staging: ccree: remove spurious blank line

2017-06-04 Thread Gilad Ben-Yossef 
Remove spurious blank line from cc_regs.h

Signed-off-by: Gilad Ben-Yossef 
---
 drivers/staging/ccree/cc_regs.h | 1 -
 1 file changed, 1 deletion(-)

diff --git a/drivers/staging/ccree/cc_regs.h b/drivers/staging/ccree/cc_regs.h
index 53675e3..4a893a6 100644
--- a/drivers/staging/ccree/cc_regs.h
+++ b/drivers/staging/ccree/cc_regs.h
@@ -14,7 +14,6 @@
  * along with this program; if not, see .
  */
 
-
 /*!
  * @file
  * @brief This file contains macro definitions for accessing ARM TrustZone
-- 
2.1.4

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[PATCH v3 13/18] staging: ccree: remove dead code

2017-06-04 Thread Gilad Ben-Yossef 
Remove some unused macro definitions from hash definitions.

Signed-off-by: Gilad Ben-Yossef 
---
 drivers/staging/ccree/hash_defs.h | 31 +++
 1 file changed, 3 insertions(+), 28 deletions(-)

diff --git a/drivers/staging/ccree/hash_defs.h 
b/drivers/staging/ccree/hash_defs.h
index 872ed97..f52656f 100644
--- a/drivers/staging/ccree/hash_defs.h
+++ b/drivers/staging/ccree/hash_defs.h
@@ -14,36 +14,11 @@
  * along with this program; if not, see .
  */
 
-#ifndef  _HASH_DEFS_H__
-#define  _HASH_DEFS_H__
+#ifndef _HASH_DEFS_H_
+#define _HASH_DEFS_H_
 
 #include "cc_crypto_ctx.h"
 
-/* this files provides definitions required for hash engine drivers */
-#ifndef CC_CONFIG_HASH_SHA_512_SUPPORTED
-#define SEP_HASH_LENGTH_WORDS  2
-#else
-#define SEP_HASH_LENGTH_WORDS  4
-#endif
-
-#ifdef BIG__ENDIAN
-#define OPAD_CURRENT_LENGTH 0x4000, 0x , 0x, 0x
-#define HASH_LARVAL_MD5  0x76543210, 0xFEDCBA98, 0x89ABCDEF, 0x01234567
-#define HASH_LARVAL_SHA1 0xF0E1D2C3, 0x76543210, 0xFEDCBA98, 0x89ABCDEF, 
0x01234567
-#define HASH_LARVAL_SHA224 0XA44FFABE, 0XA78FF964, 0X11155868, 0X310BC0FF, 
0X39590EF7, 0X17DD7030, 0X07D57C36, 0XD89E05C1
-#define HASH_LARVAL_SHA256 0X19CDE05B, 0XABD9831F, 0X8C68059B, 0X7F520E51, 
0X3AF54FA5, 0X72F36E3C, 0X85AE67BB, 0X67E6096A
-#define HASH_LARVAL_SHA384 0X1D48B547, 0XA44FFABE, 0X0D2E0CDB, 0XA78FF964, 
0X874AB48E, 0X11155868, 0X67263367, 0X310BC0FF, 0XD8EC2F15, 0X39590EF7, 
0X5A015991, 0X17DD7030, 0X2A299A62, 0X07D57C36, 0X5D9DBBCB, 0XD89E05C1
-#define HASH_LARVAL_SHA512 0X19CDE05B, 0X79217E13, 0XABD9831F, 0X6BBD41FB, 
0X8C68059B, 0X1F6C3E2B, 0X7F520E51, 0XD182E6AD, 0X3AF54FA5, 0XF1361D5F, 
0X72F36E3C, 0X2BF894FE, 0X85AE67BB, 0X3BA7CA84, 0X67E6096A, 0X08C9BCF3
-#else
-#define OPAD_CURRENT_LENGTH 0x0040, 0x, 0x, 0x
-#define HASH_LARVAL_MD5  0x10325476, 0x98BADCFE, 0xEFCDAB89, 0x67452301
-#define HASH_LARVAL_SHA1 0xC3D2E1F0, 0x10325476, 0x98BADCFE, 0xEFCDAB89, 
0x67452301
-#define HASH_LARVAL_SHA224 0xbefa4fa4, 0x64f98fa7, 0x68581511, 0xffc00b31, 
0xf70e5939, 0x3070dd17, 0x367cd507, 0xc1059ed8
-#define HASH_LARVAL_SHA256 0x5be0cd19, 0x1f83d9ab, 0x9b05688c, 0x510e527f, 
0xa54ff53a, 0x3c6ef372, 0xbb67ae85, 0x6a09e667
-#define HASH_LARVAL_SHA384 0X47B5481D, 0XBEFA4FA4, 0XDB0C2E0D, 0X64F98FA7, 
0X8EB44A87, 0X68581511, 0X67332667, 0XFFC00B31, 0X152FECD8, 0XF70E5939, 
0X9159015A, 0X3070DD17, 0X629A292A, 0X367CD507, 0XCBBB9D5D, 0XC1059ED8
-#define HASH_LARVAL_SHA512 0x5be0cd19, 0x137e2179, 0x1f83d9ab, 0xfb41bd6b, 
0x9b05688c, 0x2b3e6c1f, 0x510e527f, 0xade682d1, 0xa54ff53a, 0x5f1d36f1, 
0x3c6ef372, 0xfe94f82b, 0xbb67ae85, 0x84caa73b, 0x6a09e667, 0xf3bcc908
-#endif
-
 enum cc_hash_conf_pad {
HASH_PADDING_DISABLED = 0,
HASH_PADDING_ENABLED = 1,
@@ -57,5 +32,5 @@ enum cc_hash_cipher_pad {
HASH_CIPHER_DO_PADDING_RESERVE32 = S32_MAX,
 };
 
-#endif /*_HASH_DEFS_H__*/
+#endif /*_HASH_DEFS_H_*/
 
-- 
2.1.4

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[PATCH v3 09/18] staging: ccree: remove custom bitfield macros

2017-06-04 Thread Gilad Ben-Yossef 
With all users removed or re-factored to use the standard
kernel bit fields ops we can now drop the custom
bit field macros.

Signed-off-by: Gilad Ben-Yossef 
---
 drivers/staging/ccree/cc_bitops.h| 39 --
 drivers/staging/ccree/cc_hw_queue_defs.h |  2 +-
 drivers/staging/ccree/cc_lli_defs.h  |  2 -
 drivers/staging/ccree/cc_regs.h  | 71 +++-
 drivers/staging/ccree/ssi_driver.h   |  1 -
 5 files changed, 7 insertions(+), 108 deletions(-)
 delete mode 100644 drivers/staging/ccree/cc_bitops.h

diff --git a/drivers/staging/ccree/cc_bitops.h 
b/drivers/staging/ccree/cc_bitops.h
deleted file mode 100644
index cbdc1ab..000
--- a/drivers/staging/ccree/cc_bitops.h
+++ /dev/null
@@ -1,39 +0,0 @@
-/*
- * Copyright (C) 2012-2017 ARM Limited or its affiliates.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, see .
- */
-
-/*!
- * \file cc_bitops.h
- * Bit fields operations macros.
- */
-#ifndef _CC_BITOPS_H_
-#define _CC_BITOPS_H_
-
-#include 
-#include 
-
-#define BITMASK(mask_size) (((mask_size) < 32) ?   \
-   ((1UL << (mask_size)) - 1) : 0xUL)
-
-#define BITMASK_AT(mask_size, mask_offset) (BITMASK(mask_size) << 
(mask_offset))
-
-#define BITFIELD_GET(word, bit_offset, bit_size) \
-   (((word) >> (bit_offset)) & BITMASK(bit_size))
-#define BITFIELD_SET(word, bit_offset, bit_size, new_val)   do {\
-   word = ((word) & ~BITMASK_AT(bit_size, bit_offset)) |   \
-   (((new_val) & BITMASK(bit_size)) << (bit_offset));  \
-} while (0)
-
-#endif /*_CC_BITOPS_H_*/
diff --git a/drivers/staging/ccree/cc_hw_queue_defs.h 
b/drivers/staging/ccree/cc_hw_queue_defs.h
index e750817..8dc9b6e 100644
--- a/drivers/staging/ccree/cc_hw_queue_defs.h
+++ b/drivers/staging/ccree/cc_hw_queue_defs.h
@@ -19,8 +19,8 @@
 
 #include 
 
-#include "cc_regs.h"
 #include "dx_crys_kernel.h"
+#include 
 
 /**
 *  DEFINITIONS
diff --git a/drivers/staging/ccree/cc_lli_defs.h 
b/drivers/staging/ccree/cc_lli_defs.h
index 78811aa..851d390 100644
--- a/drivers/staging/ccree/cc_lli_defs.h
+++ b/drivers/staging/ccree/cc_lli_defs.h
@@ -19,8 +19,6 @@
 
 #include 
 
-#include "cc_bitops.h"
-
 /* Max DLLI size
  *  AKA DX_DSCRPTR_QUEUE_WORD1_DIN_SIZE_BIT_SIZE
  */
diff --git a/drivers/staging/ccree/cc_regs.h b/drivers/staging/ccree/cc_regs.h
index 6abb6ff..53675e3 100644
--- a/drivers/staging/ccree/cc_regs.h
+++ b/drivers/staging/ccree/cc_regs.h
@@ -24,7 +24,12 @@
 #ifndef _CC_REGS_H_
 #define _CC_REGS_H_
 
-#include "cc_bitops.h"
+#include 
+
+#define AXIM_MON_BASE_OFFSET CC_REG_OFFSET(CRY_KERNEL, AXIM_MON_COMP)
+#define AXIM_MON_COMP_VALUE GENMASK(DX_AXIM_MON_COMP_VALUE_BIT_SIZE + \
+   DX_AXIM_MON_COMP_VALUE_BIT_SHIFT, \
+   DX_AXIM_MON_COMP_VALUE_BIT_SHIFT)
 
 #define AXIM_MON_BASE_OFFSET CC_REG_OFFSET(CRY_KERNEL, AXIM_MON_COMP)
 #define AXIM_MON_COMP_VALUE GENMASK(DX_AXIM_MON_COMP_VALUE_BIT_SIZE + \
@@ -35,68 +40,4 @@
 #define CC_REG_OFFSET(unit_name, reg_name)   \
(DX_BASE_ ## unit_name + DX_ ## reg_name ## _REG_OFFSET)
 
-#define CC_REG_BIT_SHIFT(reg_name, field_name)   \
-   (DX_ ## reg_name ## _ ## field_name ## _BIT_SHIFT)
-
-/* Read-Modify-Write a field of a register */
-#define MODIFY_REGISTER_FLD(unitName, regName, fldName, fldVal) \
-do {   \
-   u32 regVal; \
-   regVal = READ_REGISTER(CC_REG_ADDR(unitName, regName));   \
-   CC_REG_FLD_SET(unitName, regName, fldName, regVal, fldVal); \
-   WRITE_REGISTER(CC_REG_ADDR(unitName, regName), regVal);   \
-} while (0)
-
-/*! Bit fields get */
-#define CC_REG_FLD_GET(unit_name, reg_name, fld_name, reg_val)   \
-   (DX_ ## reg_name ## _ ## fld_name ## _BIT_SIZE == 0x20 ?  \
-   reg_val /*!< \internal Optimization for 32b fields */ : 
  \
-   BITFIELD_GET(reg_val, DX_ ## reg_name ## _ ## fld_name ## _BIT_SHIFT, \
-DX_ ## reg_name ## _ ## fld_name ## _BIT_SIZE))
-
-/*! Bit fields access */
-#define CC_REG_FLD_GET2(unit_name, reg_name, fld_name, reg_val)  \
-   (CC_ ## reg_name ## _ ## fld_name ## _BIT_SIZE == 0x20 ?  \
-   reg_val /*!< \internal Optimization for

[PATCH v3 12/18] staging: ccree: drop no longer used macro

2017-06-04 Thread Gilad Ben-Yossef 
MSB64 macro is no longer used or needed. Drop it.

Signed-off-by: Gilad Ben-Yossef 
---
 drivers/staging/ccree/cc_hw_queue_defs.h | 2 --
 1 file changed, 2 deletions(-)

diff --git a/drivers/staging/ccree/cc_hw_queue_defs.h 
b/drivers/staging/ccree/cc_hw_queue_defs.h
index 1cbd2e1..aaa56c8 100644
--- a/drivers/staging/ccree/cc_hw_queue_defs.h
+++ b/drivers/staging/ccree/cc_hw_queue_defs.h
@@ -237,8 +237,6 @@ static inline void set_ack_last(struct cc_hw_desc *pdesc)
pdesc->word[4] |= FIELD_PREP(WORD4_ACK_NEEDED, 1);
 }
 
-#define MSB64(_addr) (sizeof(_addr) == 4 ? 0 : ((_addr) >> 32) & U16_MAX)
-
 /*
  * Set the DIN field of a HW descriptors
  *
-- 
2.1.4

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[PATCH v3 08/18] staging: ccree: move request_mgr to generic bitfield ops

2017-06-04 Thread Gilad Ben-Yossef 
request_mgr was using custom bit field macros. move over to
standard kernel bitfield ops.

Signed-off-by: Gilad Ben-Yossef 
---
 drivers/staging/ccree/cc_regs.h |  5 +
 drivers/staging/ccree/ssi_request_mgr.c | 27 +--
 2 files changed, 22 insertions(+), 10 deletions(-)

diff --git a/drivers/staging/ccree/cc_regs.h b/drivers/staging/ccree/cc_regs.h
index 1513412..6abb6ff 100644
--- a/drivers/staging/ccree/cc_regs.h
+++ b/drivers/staging/ccree/cc_regs.h
@@ -26,6 +26,11 @@
 
 #include "cc_bitops.h"
 
+#define AXIM_MON_BASE_OFFSET CC_REG_OFFSET(CRY_KERNEL, AXIM_MON_COMP)
+#define AXIM_MON_COMP_VALUE GENMASK(DX_AXIM_MON_COMP_VALUE_BIT_SIZE + \
+   DX_AXIM_MON_COMP_VALUE_BIT_SHIFT, \
+   DX_AXIM_MON_COMP_VALUE_BIT_SHIFT)
+
 /* Register Offset macro */
 #define CC_REG_OFFSET(unit_name, reg_name)   \
(DX_BASE_ ## unit_name + DX_ ## reg_name ## _REG_OFFSET)
diff --git a/drivers/staging/ccree/ssi_request_mgr.c 
b/drivers/staging/ccree/ssi_request_mgr.c
index 2382f32..7c2d88a 100644
--- a/drivers/staging/ccree/ssi_request_mgr.c
+++ b/drivers/staging/ccree/ssi_request_mgr.c
@@ -35,8 +35,6 @@
 
 #define SSI_MAX_POLL_ITER  10
 
-#define AXIM_MON_BASE_OFFSET CC_REG_OFFSET(CRY_KERNEL, AXIM_MON_COMP)
-
 struct ssi_request_mgr_handle {
/* Request manager resources */
unsigned int hw_queue_size; /* HW capability */
@@ -502,6 +500,15 @@ static void proc_completions(struct ssi_drvdata *drvdata)
}
 }
 
+static inline u32 cc_axi_comp_count(void __iomem *cc_base)
+{
+   /* The CC_HAL_READ_REGISTER macro implictly requires and uses
+* a base MMIO register address variable named cc_base.
+*/
+   return FIELD_GET(AXIM_MON_COMP_VALUE,
+CC_HAL_READ_REGISTER(AXIM_MON_BASE_OFFSET));
+}
+
 /* Deferred service handler, run as interrupt-fired tasklet */
 static void comp_handler(unsigned long devarg)
 {
@@ -521,25 +528,25 @@ static void comp_handler(unsigned long devarg)
CC_HAL_WRITE_REGISTER(CC_REG_OFFSET(HOST_RGF, HOST_ICR), 
SSI_COMP_IRQ_MASK);
 
/* Avoid race with above clear: Test completion counter once 
more */
-   request_mgr_handle->axi_completed += CC_REG_FLD_GET(CRY_KERNEL, 
AXIM_MON_COMP, VALUE,
-   CC_HAL_READ_REGISTER(AXIM_MON_BASE_OFFSET));
+   request_mgr_handle->axi_completed +=
+   cc_axi_comp_count(cc_base);
 
while (request_mgr_handle->axi_completed) {
do {
proc_completions(drvdata);
-   /* At this point (after proc_completions()), 
request_mgr_handle->axi_completed is always 0.
-* The following assignment was changed to = 
(previously was +=) to conform KW restrictions.
+   /* At this point (after proc_completions()),
+* request_mgr_handle->axi_completed is 0.
 */
-   request_mgr_handle->axi_completed = 
CC_REG_FLD_GET(CRY_KERNEL, AXIM_MON_COMP, VALUE,
-   
CC_HAL_READ_REGISTER(AXIM_MON_BASE_OFFSET));
+   request_mgr_handle->axi_completed =
+   cc_axi_comp_count(cc_base);
} while (request_mgr_handle->axi_completed > 0);
 
/* To avoid the interrupt from firing as we unmask it, 
we clear it now */
CC_HAL_WRITE_REGISTER(CC_REG_OFFSET(HOST_RGF, 
HOST_ICR), SSI_COMP_IRQ_MASK);
 
/* Avoid race with above clear: Test completion counter 
once more */
-   request_mgr_handle->axi_completed += 
CC_REG_FLD_GET(CRY_KERNEL, AXIM_MON_COMP, VALUE,
-   CC_HAL_READ_REGISTER(AXIM_MON_BASE_OFFSET));
+   request_mgr_handle->axi_completed +=
+   cc_axi_comp_count(cc_base);
}
 
}
-- 
2.1.4

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[PATCH v3 10/18] staging: ccree: remove unused struct

2017-06-04 Thread Gilad Ben-Yossef 
struct SepHashPrivateContext is not used anywhere in the code.
Remove it.

Signed-off-by: Gilad Ben-Yossef 
---
 drivers/staging/ccree/hash_defs.h | 18 --
 1 file changed, 18 deletions(-)

diff --git a/drivers/staging/ccree/hash_defs.h 
b/drivers/staging/ccree/hash_defs.h
index 3f2b2d1..9e01219 100644
--- a/drivers/staging/ccree/hash_defs.h
+++ b/drivers/staging/ccree/hash_defs.h
@@ -57,23 +57,5 @@ enum HashCipherDoPadding {
HASH_CIPHER_DO_PADDING_RESERVE32 = S32_MAX,
 };
 
-typedef struct SepHashPrivateContext {
-   /* The current length is placed at the end of the context buffer 
because the hash
-*  context is used for all HMAC operations as well. HMAC context 
includes a 64 bytes
-*  K0 field.  The size of struct drv_ctx_hash reserved field is  
88/184 bytes depend if t
-*  he SHA512 is supported ( in this case teh context size is 256 
bytes).
-*  The size of struct drv_ctx_hash reseved field is 20 or 52 depend if 
the SHA512 is supported.
-*  This means that this structure size (without the reserved field can 
be up to 20 bytes ,
-*  in case sha512 is not suppported it is 20 bytes 
(SEP_HASH_LENGTH_WORDS define to 2 ) and in the other
-* case it is 28 (SEP_HASH_LENGTH_WORDS define to 4)
-*/
-   u32 reserved[(sizeof(struct drv_ctx_hash)/sizeof(u32)) - 
SEP_HASH_LENGTH_WORDS - 3];
-   u32 CurrentDigestedLength[SEP_HASH_LENGTH_WORDS];
-   u32 KeyType;
-   u32 dataCompleted;
-   u32 hmacFinalization;
-   /* no space left */
-} SepHashPrivateContext_s;
-
 #endif /*_HASH_DEFS_H__*/
 
-- 
2.1.4

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[PATCH v3 11/18] staging: ccree: use snake_case for hash enums

2017-06-04 Thread Gilad Ben-Yossef 
Hash enum were named using CamelCase, move over to snake_case.

Signed-off-by: Gilad Ben-Yossef 
---
 drivers/staging/ccree/cc_hw_queue_defs.h | 4 ++--
 drivers/staging/ccree/hash_defs.h| 4 ++--
 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/staging/ccree/cc_hw_queue_defs.h 
b/drivers/staging/ccree/cc_hw_queue_defs.h
index 8dc9b6e..1cbd2e1 100644
--- a/drivers/staging/ccree/cc_hw_queue_defs.h
+++ b/drivers/staging/ccree/cc_hw_queue_defs.h
@@ -505,7 +505,7 @@ static inline void set_cipher_config0(struct cc_hw_desc 
*pdesc,
  * @config: Any one of the modes defined in [CC7x-DESC]
  */
 static inline void set_cipher_config1(struct cc_hw_desc *pdesc,
- enum HashConfig1Padding config)
+ enum cc_hash_conf_pad config)
 {
pdesc->word[4] |= FIELD_PREP(WORD4_CIPHER_CONF1, config);
 }
@@ -598,7 +598,7 @@ static inline void set_setup_mode(struct cc_hw_desc *pdesc,
  * @config: Any one of the cipher do defined in [CC7x-DESC]
  */
 static inline void set_cipher_do(struct cc_hw_desc *pdesc,
-enum HashCipherDoPadding config)
+enum cc_hash_cipher_pad config)
 {
pdesc->word[4] |= FIELD_PREP(WORD4_CIPHER_DO,
(config & HW_KEY_MASK_CIPHER_DO));
diff --git a/drivers/staging/ccree/hash_defs.h 
b/drivers/staging/ccree/hash_defs.h
index 9e01219..872ed97 100644
--- a/drivers/staging/ccree/hash_defs.h
+++ b/drivers/staging/ccree/hash_defs.h
@@ -44,14 +44,14 @@
 #define HASH_LARVAL_SHA512 0x5be0cd19, 0x137e2179, 0x1f83d9ab, 0xfb41bd6b, 
0x9b05688c, 0x2b3e6c1f, 0x510e527f, 0xade682d1, 0xa54ff53a, 0x5f1d36f1, 
0x3c6ef372, 0xfe94f82b, 0xbb67ae85, 0x84caa73b, 0x6a09e667, 0xf3bcc908
 #endif
 
-enum HashConfig1Padding {
+enum cc_hash_conf_pad {
HASH_PADDING_DISABLED = 0,
HASH_PADDING_ENABLED = 1,
HASH_DIGEST_RESULT_LITTLE_ENDIAN = 2,
HASH_CONFIG1_PADDING_RESERVE32 = S32_MAX,
 };
 
-enum HashCipherDoPadding {
+enum cc_hash_cipher_pad {
DO_NOT_PAD = 0,
DO_PAD = 1,
HASH_CIPHER_DO_PADDING_RESERVE32 = S32_MAX,
-- 
2.1.4

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[PATCH v3 07/18] staging: ccree: remove cycle count debug support

2017-06-04 Thread Gilad Ben-Yossef 
The ccree driver had support for rough performance debugging
via cycle counting which has bit rotted and can easily be
replcaed with perf. Remove it from the driver.

Signed-off-by: Gilad Ben-Yossef 
---
 drivers/staging/ccree/cc_hw_queue_defs.h |  14 
 drivers/staging/ccree/ssi_aead.c |  33 -
 drivers/staging/ccree/ssi_cipher.c   |  20 --
 drivers/staging/ccree/ssi_config.h   |   6 --
 drivers/staging/ccree/ssi_driver.c   |   8 ---
 drivers/staging/ccree/ssi_driver.h   |  25 ---
 drivers/staging/ccree/ssi_hash.c |  28 
 drivers/staging/ccree/ssi_request_mgr.c  | 116 ---
 8 files changed, 250 deletions(-)

diff --git a/drivers/staging/ccree/cc_hw_queue_defs.h 
b/drivers/staging/ccree/cc_hw_queue_defs.h
index c3f9d6a..e750817 100644
--- a/drivers/staging/ccree/cc_hw_queue_defs.h
+++ b/drivers/staging/ccree/cc_hw_queue_defs.h
@@ -29,8 +29,6 @@
 #define HW_DESC_SIZE_WORDS 6
 #define HW_QUEUE_SLOTS_MAX  15 /* Max. available slots in HW queue 
*/
 
-#define _HW_DESC_MONITOR_KICK 0x7FFFC00
-
 #define CC_REG_NAME(word, name) DX_DSCRPTR_QUEUE_WORD ## word ## _ ## name
 
 #define CC_REG_LOW(word, name)  \
@@ -606,16 +604,4 @@ static inline void set_cipher_do(struct cc_hw_desc *pdesc,
(config & HW_KEY_MASK_CIPHER_DO));
 }
 
-/*!
- * This macro sets the DIN field of a HW descriptors to star/stop monitor 
descriptor.
- * Used for performance measurements and debug purposes.
- *
- * \param pDesc pointer HW descriptor struct
- */
-#define HW_DESC_SET_DIN_MONITOR_CNTR(pDesc)
\
-   do {
\
-   CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_MEASURE_CNTR, VALUE, 
(pDesc)->word[1], _HW_DESC_MONITOR_KICK);   \
-   } while (0)
-
-
 #endif /*__CC_HW_QUEUE_DEFS_H__*/
diff --git a/drivers/staging/ccree/ssi_aead.c b/drivers/staging/ccree/ssi_aead.c
index a42bb49..e8936a3 100644
--- a/drivers/staging/ccree/ssi_aead.c
+++ b/drivers/staging/ccree/ssi_aead.c
@@ -217,9 +217,6 @@ static void ssi_aead_complete(struct device *dev, void 
*ssi_req, void __iomem *c
struct crypto_aead *tfm = crypto_aead_reqtfm(ssi_req);
struct ssi_aead_ctx *ctx = crypto_aead_ctx(tfm);
int err = 0;
-   DECL_CYCLE_COUNT_RESOURCES;
-
-   START_CYCLE_COUNT();
 
ssi_buffer_mgr_unmap_aead_request(dev, areq);
 
@@ -254,7 +251,6 @@ static void ssi_aead_complete(struct device *dev, void 
*ssi_req, void __iomem *c
}
}
 
-   END_CYCLE_COUNT(STAT_OP_TYPE_GENERIC, STAT_PHASE_4);
aead_request_complete(areq, err);
 }
 
@@ -521,10 +517,6 @@ ssi_get_plain_hmac_key(struct crypto_aead *tfm, const u8 
*key, unsigned int keyl
idx++;
}
 
-#ifdef ENABLE_CYCLE_COUNT
-   ssi_req.op_type = STAT_OP_TYPE_SETKEY;
-#endif
-
rc = send_request(ctx->drvdata, &ssi_req, desc, idx, 0);
if (unlikely(rc != 0))
SSI_LOG_ERR("send_request() failed (rc=%d)\n", rc);
@@ -546,14 +538,12 @@ ssi_aead_setkey(struct crypto_aead *tfm, const u8 *key, 
unsigned int keylen)
struct crypto_authenc_key_param *param;
struct cc_hw_desc desc[MAX_AEAD_SETKEY_SEQ];
int seq_len = 0, rc = -EINVAL;
-   DECL_CYCLE_COUNT_RESOURCES;
 
SSI_LOG_DEBUG("Setting key in context @%p for %s. key=%p keylen=%u\n",
ctx, crypto_tfm_alg_name(crypto_aead_tfm(tfm)), key, keylen);
 
CHECK_AND_RETURN_UPON_FIPS_ERROR();
/* STAT_PHASE_0: Init and sanity checks */
-   START_CYCLE_COUNT();
 
if (ctx->auth_mode != DRV_HASH_NULL) { /* authenc() alg. */
if (!RTA_OK(rta, keylen))
@@ -592,9 +582,7 @@ ssi_aead_setkey(struct crypto_aead *tfm, const u8 *key, 
unsigned int keylen)
if (unlikely(rc != 0))
goto badkey;
 
-   END_CYCLE_COUNT(STAT_OP_TYPE_SETKEY, STAT_PHASE_0);
/* STAT_PHASE_1: Copy key to ctx */
-   START_CYCLE_COUNT();
 
/* Get key material */
memcpy(ctx->enckey, key + ctx->auth_keylen, ctx->enc_keylen);
@@ -608,10 +596,8 @@ ssi_aead_setkey(struct crypto_aead *tfm, const u8 *key, 
unsigned int keylen)
goto badkey;
}
 
-   END_CYCLE_COUNT(STAT_OP_TYPE_SETKEY, STAT_PHASE_1);
 
/* STAT_PHASE_2: Create sequence */
-   START_CYCLE_COUNT();
 
switch (ctx->auth_mode) {
case DRV_HASH_SHA1:
@@ -629,15 +615,10 @@ ssi_aead_setkey(struct crypto_aead *tfm, const u8 *key, 
unsigned int keylen)
goto badkey;
}
 
-   END_CYCLE_COUNT(STAT_OP_TYPE_SETKEY, STAT_PHASE_2);
 
/* STAT_PHASE_3: Submit sequence to HW */
-   START_CYCLE_COUNT();
 
if (seq_len > 0) { /* For CCM there is no sequence to setup the key */
-#ifdef ENABLE_CYCLE_COUN

[PATCH v3 06/18] staging: ccree: remove unused debug macros

2017-06-04 Thread Gilad Ben-Yossef 
The DUMP_SGL() and DUMP_MLLI_TABLE() debug macros were
defined but not used anywhere and the difference of their
definitions for debug vs. none debug indicated this has
not being used in a while.

Remove the dead code.

Signed-off-by: Gilad Ben-Yossef 
---
 drivers/staging/ccree/ssi_buffer_mgr.c | 19 ---
 1 file changed, 19 deletions(-)

diff --git a/drivers/staging/ccree/ssi_buffer_mgr.c 
b/drivers/staging/ccree/ssi_buffer_mgr.c
index 63ffcd5..3252114 100644
--- a/drivers/staging/ccree/ssi_buffer_mgr.c
+++ b/drivers/staging/ccree/ssi_buffer_mgr.c
@@ -34,30 +34,11 @@
 #include "ssi_aead.h"
 
 #ifdef CC_DEBUG
-#define DUMP_SGL(sg) \
-   while (sg) { \
-   SSI_LOG_DEBUG("page=%p offset=%u length=%u (dma_len=%u) " \
-"dma_addr=%08x\n", sg_page(sg), (sg)->offset, \
-   (sg)->length, sg_dma_len(sg), (sg)->dma_address); \
-   (sg) = sg_next(sg); \
-   }
-#define DUMP_MLLI_TABLE(mlli_p, nents) \
-   do { \
-   SSI_LOG_DEBUG("mlli=%pK nents=%u\n", (mlli_p), (nents)); \
-   while((nents)--) { \
-   SSI_LOG_DEBUG("addr=0x%08X size=0x%08X\n", \
-(mlli_p)[LLI_WORD0_OFFSET], \
-(mlli_p)[LLI_WORD1_OFFSET]); \
-   (mlli_p) += LLI_ENTRY_WORD_SIZE; \
-   } \
-   } while (0)
 #define GET_DMA_BUFFER_TYPE(buff_type) ( \
((buff_type) == SSI_DMA_BUF_NULL) ? "BUF_NULL" : \
((buff_type) == SSI_DMA_BUF_DLLI) ? "BUF_DLLI" : \
((buff_type) == SSI_DMA_BUF_MLLI) ? "BUF_MLLI" : "BUF_INVALID")
 #else
-#define DX_BUFFER_MGR_DUMP_SGL(sg)
-#define DX_BUFFER_MGR_DUMP_MLLI_TABLE(mlli_p, nents)
 #define GET_DMA_BUFFER_TYPE(buff_type)
 #endif
 
-- 
2.1.4

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[PATCH v3 04/18] staging: ccree: refactor LLI access macros

2017-06-04 Thread Gilad Ben-Yossef 
The Linked List Item descriptors were being programmed via
a set of macros which suffer a few problems:
- Use of macros rather than inline leaves out parameter type
  checking and risks multiple macro parameter evaluation side
  effects.
- Implemented via hand rolled versions of bitfield operations.

This patch refactors LLI programming into a set of
of inline functions using generic kernel bitfield access
infrastructure, thus resolving the above issues and opening
the way later on to drop the hand rolled bitfield macros
once additional users are dropped in later patches in the
series.

Signed-off-by: Gilad Ben-Yossef 
---
 drivers/staging/ccree/cc_lli_defs.h| 39 ++
 drivers/staging/ccree/ssi_buffer_mgr.c |  8 +++
 2 files changed, 25 insertions(+), 22 deletions(-)

diff --git a/drivers/staging/ccree/cc_lli_defs.h 
b/drivers/staging/ccree/cc_lli_defs.h
index 857b94f..876dde0 100644
--- a/drivers/staging/ccree/cc_lli_defs.h
+++ b/drivers/staging/ccree/cc_lli_defs.h
@@ -26,24 +26,7 @@
  */
 #define DLLI_SIZE_BIT_SIZE 0x18
 
-#define CC_MAX_MLLI_ENTRY_SIZE 0x1
-
-#define LLI_SET_ADDR(__lli_p, __addr) do { \
-   u32 *lli_p = (u32 *)__lli_p;\
-   typeof(__addr) addr = __addr;   \
-   \
-   BITFIELD_SET(lli_p[LLI_WORD0_OFFSET],   \
-   LLI_LADDR_BIT_OFFSET,   \
-   LLI_LADDR_BIT_SIZE, (addr & U32_MAX));  \
-   \
-   BITFIELD_SET(lli_p[LLI_WORD1_OFFSET],   \
-   LLI_HADDR_BIT_OFFSET,   \
-   LLI_HADDR_BIT_SIZE, MSB64(addr));   \
-   } while (0)
-
-#define LLI_SET_SIZE(lli_p, size)  \
-   BITFIELD_SET(((u32 *)(lli_p))[LLI_WORD1_OFFSET],\
-   LLI_SIZE_BIT_OFFSET, LLI_SIZE_BIT_SIZE, size)
+#define CC_MAX_MLLI_ENTRY_SIZE 0x
 
 /* Size of entry */
 #define LLI_ENTRY_WORD_SIZE 2
@@ -60,4 +43,24 @@
 #define LLI_HADDR_BIT_OFFSET 16
 #define LLI_HADDR_BIT_SIZE 16
 
+#define LLI_SIZE_MASK GENMASK((LLI_SIZE_BIT_SIZE - 1), LLI_SIZE_BIT_OFFSET)
+#define LLI_HADDR_MASK GENMASK( \
+  (LLI_HADDR_BIT_OFFSET + LLI_HADDR_BIT_SIZE - 1),\
+   LLI_HADDR_BIT_OFFSET)
+
+static inline void cc_lli_set_addr(u32 *lli_p, dma_addr_t addr)
+{
+   lli_p[LLI_WORD0_OFFSET] = (addr & U32_MAX);
+#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
+   lli_p[LLI_WORD1_OFFSET] &= ~LLI_HADDR_MASK;
+   lli_p[LLI_WORD1_OFFSET] |= FIELD_PREP(LLI_HADDR_MASK, (addr >> 16));
+#endif /* CONFIG_ARCH_DMA_ADDR_T_64BIT */
+}
+
+static inline void cc_lli_set_size(u32 *lli_p, u16 size)
+{
+   lli_p[LLI_WORD1_OFFSET] &= ~LLI_SIZE_MASK;
+   lli_p[LLI_WORD1_OFFSET] |= FIELD_PREP(LLI_SIZE_MASK, size);
+}
+
 #endif /*_CC_LLI_DEFS_H_*/
diff --git a/drivers/staging/ccree/ssi_buffer_mgr.c 
b/drivers/staging/ccree/ssi_buffer_mgr.c
index f21dd26..24ba51d 100644
--- a/drivers/staging/ccree/ssi_buffer_mgr.c
+++ b/drivers/staging/ccree/ssi_buffer_mgr.c
@@ -186,8 +186,8 @@ static inline int ssi_buffer_mgr_render_buff_to_mlli(
 
/*handle buffer longer than 64 kbytes */
while (buff_size > CC_MAX_MLLI_ENTRY_SIZE ) {
-   LLI_SET_ADDR(mlli_entry_p,buff_dma);
-   LLI_SET_SIZE(mlli_entry_p, CC_MAX_MLLI_ENTRY_SIZE);
+   cc_lli_set_addr(mlli_entry_p, buff_dma);
+   cc_lli_set_size(mlli_entry_p, CC_MAX_MLLI_ENTRY_SIZE);
SSI_LOG_DEBUG("entry[%d]: single_buff=0x%08X 
size=%08X\n",*curr_nents,
   mlli_entry_p[LLI_WORD0_OFFSET],
   mlli_entry_p[LLI_WORD1_OFFSET]);
@@ -197,8 +197,8 @@ static inline int ssi_buffer_mgr_render_buff_to_mlli(
(*curr_nents)++;
}
/*Last entry */
-   LLI_SET_ADDR(mlli_entry_p,buff_dma);
-   LLI_SET_SIZE(mlli_entry_p, buff_size);
+   cc_lli_set_addr(mlli_entry_p, buff_dma);
+   cc_lli_set_size(mlli_entry_p, buff_size);
SSI_LOG_DEBUG("entry[%d]: single_buff=0x%08X size=%08X\n",*curr_nents,
   mlli_entry_p[LLI_WORD0_OFFSET],
   mlli_entry_p[LLI_WORD1_OFFSET]);
-- 
2.1.4

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[PATCH v3 05/18] staging: ccree: move M/LLI defines to header file

2017-06-04 Thread Gilad Ben-Yossef 
A bunch of macros used to define M/LLI descriptors where
being defined in the C file. Move them over to private
include file where other relevant definitions are stored.

Signed-off-by: Gilad Ben-Yossef 
---
 drivers/staging/ccree/cc_lli_defs.h| 8 
 drivers/staging/ccree/ssi_buffer_mgr.c | 7 ---
 2 files changed, 8 insertions(+), 7 deletions(-)

diff --git a/drivers/staging/ccree/cc_lli_defs.h 
b/drivers/staging/ccree/cc_lli_defs.h
index 876dde0..78811aa 100644
--- a/drivers/staging/ccree/cc_lli_defs.h
+++ b/drivers/staging/ccree/cc_lli_defs.h
@@ -28,6 +28,14 @@
 
 #define CC_MAX_MLLI_ENTRY_SIZE 0x
 
+#define LLI_MAX_NUM_OF_DATA_ENTRIES 128
+#define LLI_MAX_NUM_OF_ASSOC_DATA_ENTRIES 4
+#define MLLI_TABLE_MIN_ALIGNMENT 4 /* 32 bit alignment */
+#define MAX_NUM_OF_BUFFERS_IN_MLLI 4
+#define MAX_NUM_OF_TOTAL_MLLI_ENTRIES \
+   (2 * LLI_MAX_NUM_OF_DATA_ENTRIES + \
+LLI_MAX_NUM_OF_ASSOC_DATA_ENTRIES)
+
 /* Size of entry */
 #define LLI_ENTRY_WORD_SIZE 2
 #define LLI_ENTRY_BYTE_SIZE (LLI_ENTRY_WORD_SIZE * sizeof(u32))
diff --git a/drivers/staging/ccree/ssi_buffer_mgr.c 
b/drivers/staging/ccree/ssi_buffer_mgr.c
index 24ba51d..63ffcd5 100644
--- a/drivers/staging/ccree/ssi_buffer_mgr.c
+++ b/drivers/staging/ccree/ssi_buffer_mgr.c
@@ -33,13 +33,6 @@
 #include "ssi_hash.h"
 #include "ssi_aead.h"
 
-#define LLI_MAX_NUM_OF_DATA_ENTRIES 128
-#define LLI_MAX_NUM_OF_ASSOC_DATA_ENTRIES 4
-#define MLLI_TABLE_MIN_ALIGNMENT 4 /*Force the MLLI table to be align to 
uint32 */
-#define MAX_NUM_OF_BUFFERS_IN_MLLI 4
-#define MAX_NUM_OF_TOTAL_MLLI_ENTRIES (2*LLI_MAX_NUM_OF_DATA_ENTRIES + \
-   LLI_MAX_NUM_OF_ASSOC_DATA_ENTRIES )
-
 #ifdef CC_DEBUG
 #define DUMP_SGL(sg) \
while (sg) { \
-- 
2.1.4

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[PATCH v3 03/18] staging: ccree: remove 48 bit dma addr sim

2017-06-04 Thread Gilad Ben-Yossef 
Remove no longer needed code used to simulate 48 bit dma addresses
on 32 bit platforms for development purposes.

Signed-off-by: Gilad Ben-Yossef 
---
 drivers/staging/ccree/ssi_aead.c| 19 
 drivers/staging/ccree/ssi_buffer_mgr.c  | 83 -
 drivers/staging/ccree/ssi_buffer_mgr.h  | 16 ---
 drivers/staging/ccree/ssi_cipher.c  |  4 --
 drivers/staging/ccree/ssi_hash.c| 35 --
 drivers/staging/ccree/ssi_ivgen.c   |  3 --
 drivers/staging/ccree/ssi_request_mgr.c |  3 --
 7 files changed, 163 deletions(-)

diff --git a/drivers/staging/ccree/ssi_aead.c b/drivers/staging/ccree/ssi_aead.c
index b0db815..a42bb49 100644
--- a/drivers/staging/ccree/ssi_aead.c
+++ b/drivers/staging/ccree/ssi_aead.c
@@ -99,7 +99,6 @@ static void ssi_aead_exit(struct crypto_aead *tfm)
dev = &ctx->drvdata->plat_dev->dev;
/* Unmap enckey buffer */
if (ctx->enckey != NULL) {
-   SSI_RESTORE_DMA_ADDR_TO_48BIT(ctx->enckey_dma_addr);
dma_free_coherent(dev, AES_MAX_KEY_SIZE, ctx->enckey, 
ctx->enckey_dma_addr);
SSI_LOG_DEBUG("Freed enckey DMA buffer 
enckey_dma_addr=0x%llX\n",
(unsigned long long)ctx->enckey_dma_addr);
@@ -109,8 +108,6 @@ static void ssi_aead_exit(struct crypto_aead *tfm)
 
if (ctx->auth_mode == DRV_HASH_XCBC_MAC) { /* XCBC authetication */
if (ctx->auth_state.xcbc.xcbc_keys != NULL) {
-   SSI_RESTORE_DMA_ADDR_TO_48BIT(
-   ctx->auth_state.xcbc.xcbc_keys_dma_addr);
dma_free_coherent(dev, CC_AES_128_BIT_KEY_SIZE * 3,
ctx->auth_state.xcbc.xcbc_keys,
ctx->auth_state.xcbc.xcbc_keys_dma_addr);
@@ -121,8 +118,6 @@ static void ssi_aead_exit(struct crypto_aead *tfm)
ctx->auth_state.xcbc.xcbc_keys = NULL;
} else if (ctx->auth_mode != DRV_HASH_NULL) { /* HMAC auth. */
if (ctx->auth_state.hmac.ipad_opad != NULL) {
-   SSI_RESTORE_DMA_ADDR_TO_48BIT(
-   ctx->auth_state.hmac.ipad_opad_dma_addr);
dma_free_coherent(dev, 2 * MAX_HMAC_DIGEST_SIZE,
ctx->auth_state.hmac.ipad_opad,
ctx->auth_state.hmac.ipad_opad_dma_addr);
@@ -132,8 +127,6 @@ static void ssi_aead_exit(struct crypto_aead *tfm)
ctx->auth_state.hmac.ipad_opad = NULL;
}
if (ctx->auth_state.hmac.padded_authkey != NULL) {
-   SSI_RESTORE_DMA_ADDR_TO_48BIT(
-   ctx->auth_state.hmac.padded_authkey_dma_addr);
dma_free_coherent(dev, MAX_HMAC_BLOCK_SIZE,
ctx->auth_state.hmac.padded_authkey,
ctx->auth_state.hmac.padded_authkey_dma_addr);
@@ -171,7 +164,6 @@ static int ssi_aead_init(struct crypto_aead *tfm)
SSI_LOG_ERR("Failed allocating key buffer\n");
goto init_failed;
}
-   SSI_UPDATE_DMA_ADDR_TO_48BIT(ctx->enckey_dma_addr, AES_MAX_KEY_SIZE);
SSI_LOG_DEBUG("Allocated enckey buffer in context ctx->enckey=@%p\n", 
ctx->enckey);
 
/* Set default authlen value */
@@ -186,9 +178,6 @@ static int ssi_aead_init(struct crypto_aead *tfm)
SSI_LOG_ERR("Failed allocating buffer for XCBC keys\n");
goto init_failed;
}
-   SSI_UPDATE_DMA_ADDR_TO_48BIT(
-   ctx->auth_state.xcbc.xcbc_keys_dma_addr,
-   CC_AES_128_BIT_KEY_SIZE * 3);
} else if (ctx->auth_mode != DRV_HASH_NULL) { /* HMAC authentication */
/* Allocate dma-coherent buffer for IPAD + OPAD */
ctx->auth_state.hmac.ipad_opad = dma_alloc_coherent(dev,
@@ -198,9 +187,6 @@ static int ssi_aead_init(struct crypto_aead *tfm)
SSI_LOG_ERR("Failed allocating IPAD/OPAD buffer\n");
goto init_failed;
}
-   SSI_UPDATE_DMA_ADDR_TO_48BIT(
-   ctx->auth_state.hmac.ipad_opad_dma_addr,
-   2 * MAX_HMAC_DIGEST_SIZE);
SSI_LOG_DEBUG("Allocated authkey buffer in context 
ctx->authkey=@%p\n",
ctx->auth_state.hmac.ipad_opad);
 
@@ -211,9 +197,6 @@ static int ssi_aead_init(struct crypto_aead *tfm)
SSI_LOG_ERR("failed to allocate padded_authkey\n");
goto init_failed;
}
-   SSI_UPDATE_DMA_ADDR_TO_48BIT(
-   ctx->auth_state.hmac.padded_authkey_dma_addr,
-   MAX_HMAC_BLOCK_SIZE);
} else {
ctx->auth_state.hmac.ipad_opad = NULL;
ctx->auth_state.hmac.padded_authkey = NULL;
@@ -46

[PATCH v3 00/18] additional driver cleanups

2017-06-04 Thread Gilad Ben-Yossef 
This is another batch of clean ups for the ccree driver.
Mostly comprised of:
- Coding Style fixes
- Move to kernel infrastructure from custom constructs
- Replace macros with static inline functions
- Removal of dead code

Changes from v2:
- Rebase on top of commit ed5210cb07de90b8dc31a420466847755331536b
  ("Drivers: ccree: cc_hw_queue_defs.h - align block comments").
- Drop already upstream patches.
- Add three new patches to drop more unused code.

Changes from v1:
- Break up patches better to "do one thing" as indicated by GregKH
- Better description for some of the patches
- Better line breakup for code clarity as suggested by Joe Perches

Gilad Ben-Yossef (18):
  staging: ccree: replace bit shift with BIT macro
  staging: ccree: refactor HW command FIFO access
  staging: ccree: remove 48 bit dma addr sim
  staging: ccree: refactor LLI access macros
  staging: ccree: move M/LLI defines to header file
  staging: ccree: remove unused debug macros
  staging: ccree: remove cycle count debug support
  staging: ccree: move request_mgr to generic bitfield ops
  staging: ccree: remove custom bitfield macros
  staging: ccree: remove unused struct
  staging: ccree: use snake_case for hash enums
  staging: ccree: drop no longer used macro
  staging: ccree: remove dead code
  staging: ccree: remove spurious blank line
  staging: ccree: fix wrong whitespace usage
  staging: ccree: remove last remnants of sash algo
  staging: ccree: remove last remnants of sblkcipher
  staging: ccree: remove descriptor context definitions

 drivers/staging/ccree/cc_bitops.h|   35 -
 drivers/staging/ccree/cc_crypto_ctx.h|   88 +-
 drivers/staging/ccree/cc_hw_queue_defs.h |  686 ---
 drivers/staging/ccree/cc_lli_defs.h  |   49 +-
 drivers/staging/ccree/cc_regs.h  |   77 +-
 drivers/staging/ccree/dx_crys_kernel.h   |  308 +++
 drivers/staging/ccree/dx_host.h  |  256 +++---
 drivers/staging/ccree/hash_defs.h|   53 +-
 drivers/staging/ccree/ssi_aead.c |  953 ++---
 drivers/staging/ccree/ssi_buffer_mgr.c   |  117 +--
 drivers/staging/ccree/ssi_buffer_mgr.h   |   16 -
 drivers/staging/ccree/ssi_cipher.c   |  350 +++-
 drivers/staging/ccree/ssi_config.h   |6 -
 drivers/staging/ccree/ssi_driver.c   |8 -
 drivers/staging/ccree/ssi_driver.h   |   31 +-
 drivers/staging/ccree/ssi_fips_ll.c  |  704 
 drivers/staging/ccree/ssi_hash.c | 1343 +-
 drivers/staging/ccree/ssi_ivgen.c|   80 +-
 drivers/staging/ccree/ssi_request_mgr.c  |  161 +---
 drivers/staging/ccree/ssi_sram_mgr.c |8 +-
 20 files changed, 2230 insertions(+), 3099 deletions(-)
 delete mode 100644 drivers/staging/ccree/cc_bitops.h

-- 
2.1.4

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[PATCH v3 01/18] staging: ccree: replace bit shift with BIT macro

2017-06-04 Thread Gilad Ben-Yossef 
CC_CTX_SIZE was being defined using a hand rolled bit shift operation.
Replace with use of BIT macro.

Signed-off-by: Gilad Ben-Yossef 
---
 drivers/staging/ccree/cc_crypto_ctx.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/staging/ccree/cc_crypto_ctx.h 
b/drivers/staging/ccree/cc_crypto_ctx.h
index 1fc68de..20f3f9f 100644
--- a/drivers/staging/ccree/cc_crypto_ctx.h
+++ b/drivers/staging/ccree/cc_crypto_ctx.h
@@ -27,7 +27,7 @@
 #define CC_CTX_SIZE_LOG2 7
 #endif
 #endif
-#define CC_CTX_SIZE (1 << CC_CTX_SIZE_LOG2)
+#define CC_CTX_SIZE BIT(CC_CTX_SIZE_LOG2)
 #define CC_DRV_CTX_SIZE_WORDS (CC_CTX_SIZE >> 2)
 
 #define CC_DRV_DES_IV_SIZE 8
-- 
2.1.4

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Re: [PATCH 04/12] fs: ceph: CURRENT_TIME with ktime_get_real_ts()

2017-06-04 Thread Yan, Zheng 
On Fri, Jun 2, 2017 at 10:18 PM, Arnd Bergmann  wrote:
> On Fri, Jun 2, 2017 at 2:18 PM, Yan, Zheng  wrote:
>> On Fri, Jun 2, 2017 at 7:33 PM, Arnd Bergmann  wrote:
>>> On Fri, Jun 2, 2017 at 1:18 PM, Yan, Zheng  wrote:
>>> What I meant is another related problem in ceph_mkdir() where the
>>> i_ctime field of the parent inode is different between the persistent
>>> representation in the mds and the in-memory representation.
>>>
>>
>> I don't see any problem in mkdir case. Parent inode's i_ctime in mds is set 
>> to
>> r_stamp. When client receives request reply, it set its in-memory inode's 
>> ctime
>> to the same time stamp.
>
> Ok, I see it now, thanks for the clarification. Most other file systems do 
> this
> the other way round and update all fields in the in-memory inode structure
> first and then write that to persistent storage, so I was getting confused 
> about
> the order of events here.
>
> If I understand it all right, we have three different behaviors in ceph now,
> though the differences are very minor and probably don't ever matter:
>
> - in setattr(), we update ctime in the in-memory inode first and then send
>   the same time to the mds, and expect to set it again when the reply comes.
>
> - in ceph_write_iter write() and mmap/page_mkwrite(), we call
>   file_update_time() to set i_mtime and i_ctime to the same
>   timestamp first once a write is observed by the fs and then take
>   two other timestamps that we send to the mds, and update the
>   in-memory inode a second time when the reply comes. ctime
>   is never older than mtime here, as far as I can tell, but it may
>   be newer when the timer interrupt happens between taking the
>   two stamps.

We don't use request to send i_mtime/i_ctime to mds in this case.
Instead, we use cap flush message. i_mtime/i_ctime are directly
encoded in cap flush message. When mds receives the cap flush message,
it writes i_mtime/i_ctime to persistent storage and sends a cap flush
ack message to client. (when client receives the cap flush ack
message, it does not update i_mtime/i_ctime). There is no issue as you
described.

>
> - in all other calls, we only update the inode (and/or parent inode)
>   after the reply arrives.

There are two cases. 1. Client updates in-memory inode's ctime, it
sends the new ctime to mds through cap flush message. 2. client set
mds request's r_stamp and send the request to mds. MDS updates
relavent inodes' ctime and sends reply to client. Client updates
in-memory inodes' ctime according to the reply.

Regards
Yan, Zheng

>
>Arnd
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