Re: [PATCH 00/11] staging: gasket: fixes
On Sun, Oct 14, 2018 at 09:59:16PM -0700, Todd Poynor wrote: > From: Todd Poynor > > Various fixes for gasket/apex drivers. For some reason you seem to have ignored/missed this patch: Subject: [PATCH v3] staging: gasket: Fix sparse "incorrect type in assignment" warnings. that was sent last week. Any specific reason? thanks, greg k-h ___ devel mailing list de...@linuxdriverproject.org http://driverdev.linuxdriverproject.org/mailman/listinfo/driverdev-devel
Re: [PATCH 01/11] staging: gasket: core: debug log updates
On Sun, Oct 14, 2018 at 09:59:17PM -0700, Todd Poynor wrote: > From: Todd Poynor > > Add debug logs for device enable/disable events, Why? What is going to need this? > remove logs for > callbacks (the called functions can generate their own logs if needed). That's a different thing than "adding" them, so shouldn't this really be 2 patches? If it was, I could have accepted this patch already, and ignored the "add new logs" one :) thanks, greg k-h ___ devel mailing list de...@linuxdriverproject.org http://driverdev.linuxdriverproject.org/mailman/listinfo/driverdev-devel
Re: [PATCH 05/11] staging: gasket: page_table: rearrange gasket_page_table_entry
On Sun, Oct 14, 2018 at 09:59:21PM -0700, Todd Poynor wrote: > From: Nick Ewalt > > Rearrange gasket_page_table entry to reduce padding slop. In the future, defining exactly what "slop" is here would be nice :) thanks, greg k-h ___ devel mailing list de...@linuxdriverproject.org http://driverdev.linuxdriverproject.org/mailman/listinfo/driverdev-devel
Reply Immediately
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Re: [PATCH V4 7/15] KVM/MMU: Flush tlb directly in the kvm_zap_gfn_range()
On 13/10/2018 16:53, lantianyu1...@gmail.com wrote:
> + bool flush = false;
> int i;
>
> spin_lock(&kvm->mmu_lock);
> @@ -5654,18 +5655,27 @@ void kvm_zap_gfn_range(struct kvm *kvm, gfn_t
> gfn_start, gfn_t gfn_end)
> slots = __kvm_memslots(kvm, i);
> kvm_for_each_memslot(memslot, slots) {
> gfn_t start, end;
> + bool flush_tlb = true;
>
> start = max(gfn_start, memslot->base_gfn);
> end = min(gfn_end, memslot->base_gfn + memslot->npages);
> if (start >= end)
> continue;
>
> - slot_handle_level_range(kvm, memslot, kvm_zap_rmapp,
> - PT_PAGE_TABLE_LEVEL,
> PT_MAX_HUGEPAGE_LEVEL,
> - start, end - 1, true);
> + if (kvm_available_flush_tlb_with_range())
> + flush_tlb = false;
This should be moved outside the for, because it's invariant.
> + flush = slot_handle_level_range(kvm, memslot,
> + kvm_zap_rmapp, PT_PAGE_TABLE_LEVEL,
> + PT_MAX_HUGEPAGE_LEVEL, start,
> + end - 1, flush_tlb);
... and this should be "flush |= ".
> }
> }
>
> + if (flush && kvm_available_flush_tlb_with_range())
> + kvm_flush_remote_tlbs_with_address(kvm, gfn_start,
> + gfn_end - gfn_start + 1);
> +
... and this can be just if (flush), because if flush_tlb is true then
slot_handle_level_range always returns false.
Paolo
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Re: [PATCH V4 9/15] KVM: Add flush_link and parent_pte in the struct kvm_mmu_page
On 13/10/2018 16:54, lantianyu1...@gmail.com wrote:
> From: Lan Tianyu
>
> PV EPT tlb flush function will accept a list of flush ranges and
> use struct kvm_mmu_page as the list entry.
>
> Signed-off-by: Lan Tianyu
> ---
> arch/x86/include/asm/kvm_host.h | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/arch/x86/include/asm/kvm_host.h b/arch/x86/include/asm/kvm_host.h
> index 19985c602ed6..8279235285f8 100644
> --- a/arch/x86/include/asm/kvm_host.h
> +++ b/arch/x86/include/asm/kvm_host.h
> @@ -316,6 +316,7 @@ struct kvm_rmap_head {
>
> struct kvm_mmu_page {
> struct list_head link;
> + struct list_head flush_link;
This can be an hlist. However, you are not documenting what's the
locking here. There are many places in which KVM does a
"cond_resched_lock(&vcpu->kvm->mmu_lock);" and you need to explain how
flush_link is not live across that.
I would start from a simpler patch that just uses the list-based flush
in kvm_mmu_commit_zap_page, where you already have the list of things to
flush as invalid_list.
> struct hlist_node hash_link;
> bool unsync;
>
>
Also this is not adding parent_pte, so the subject is incorrect.
Paolo
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Re: [PATCH 00/11] staging: gasket: fixes
On Mon, Oct 15, 2018 at 12:33 AM Greg Kroah-Hartman wrote: > > On Sun, Oct 14, 2018 at 09:59:16PM -0700, Todd Poynor wrote: > > From: Todd Poynor > > > > Various fixes for gasket/apex drivers. > > For some reason you seem to have ignored/missed this patch: > Subject: [PATCH v3] staging: gasket: Fix sparse "incorrect type in > assignment" warnings. > that was sent last week. > > Any specific reason? Coming off a 2 week vacation, I'm behind on everything. I saw you had commented already, but I'll take a look as well, sure. > > thanks, > > greg k-h -- Todd ___ devel mailing list de...@linuxdriverproject.org http://driverdev.linuxdriverproject.org/mailman/listinfo/driverdev-devel
Re: [PATCH 00/11] staging: gasket: fixes
On Sun, Oct 14, 2018 at 09:59:16PM -0700, Todd Poynor wrote: > From: Todd Poynor > > Various fixes for gasket/apex drivers. I still can't find any explanation in the staging tree or in your comments what gasket even is. ___ devel mailing list de...@linuxdriverproject.org http://driverdev.linuxdriverproject.org/mailman/listinfo/driverdev-devel
Re: [PATCH V4 12/15] x86/hyper-v: Add HvFlushGuestAddressList hypercall support
On 13/10/2018 16:54, lantianyu1...@gmail.com wrote: > > +static int fill_flush_list(union hv_gpa_page_range gpa_list[], > + int offset, u64 start_gfn, u64 pages) Pass the entire struct hv_guest_mapping_flush_list to this function, it's simpler and it hides the gpa_list argument from range->parse_flush_list_func. > + if (!range->flush_list) > + gpa_n = fill_flush_list(flush->gpa_list, gpa_n, > + range->start_gfn, range->pages); > + else if (range->parse_flush_list_func) > + gpa_n = range->parse_flush_list_func(flush->gpa_list, gpa_n, > + range->flush_list, fill_flush_list); > + else You are making the code more complicated in order to avoid making fill_flush_list public. Just make it public and always go through the parse_flush_list_func case. In fact: - make parse_flush_list_func an argument of hyperv_flush_guest_mapping_range - drop struct hyperv_tlb_range completely, instead just pass a void* to hyperv_flush_guest_mapping_range and pass it back to the callback. The void * can point to the start_gfn/pages pair, it can be the flush_list, or anything else. Paolo ___ devel mailing list de...@linuxdriverproject.org http://driverdev.linuxdriverproject.org/mailman/listinfo/driverdev-devel
Re: [PATCH 00/11] staging: gasket: fixes
On Mon, Oct 15, 2018 at 03:29:49AM -0700, Christoph Hellwig wrote: > On Sun, Oct 14, 2018 at 09:59:16PM -0700, Todd Poynor wrote: > > From: Todd Poynor > > > > Various fixes for gasket/apex drivers. > > I still can't find any explanation in the staging tree or in your > comments what gasket even is. No one really knows, it will all eventually be deleted and they will just use the UIO interface in the end, but it's fun to watch them work themselves toward that over time :) greg k-h ___ devel mailing list de...@linuxdriverproject.org http://driverdev.linuxdriverproject.org/mailman/listinfo/driverdev-devel
Re: [PATCH V4 11/15] KVM/MMU: Replace tlb flush function with range list flush function
On 13/10/2018 16:54, lantianyu1...@gmail.com wrote:
> while (mmu_unsync_walk(parent, &pages)) {
> bool protected = false;
> + LIST_HEAD(flush_list);
>
> - for_each_sp(pages, sp, parents, i)
> + for_each_sp(pages, sp, parents, i) {
> protected |= rmap_write_protect(vcpu, sp->gfn);
> + kvm_mmu_queue_flush_request(sp, &flush_list);
> + }
Here you already know that the page has to be flushed, because you are
dealing with shadow page tables and those always use 4K pages. So the
check on is_last_page is unnecessary.
>
>pte_access, PT_PAGE_TABLE_LEVEL,
>gfn, spte_to_pfn(sp->spt[i]),
>true, false, host_writable);
> + if (set_spte_ret && kvm_available_flush_tlb_with_range())
> + kvm_mmu_queue_flush_request(sp, &flush_list);
> }
This is wrong, I think. sp is always the same throughout the loop, so
you are adding it multiple times to flush_list.
Instead, you need to add a separate range for each virtual address (in
this case L2 GPA) that is synced; but for each PTE that you call
set_spte here for, you could be syncing multiple L2 GPAs if a single
page is reused multiple times by the guest's EPT page tables.
And actually I may be missing something, but doesn't this apply to all
call sites? For mmu_sync_children you can do the flush in
__rmap_write_protect and return false, similar to the first part of the
series, but not for kvm_mmu_commit_zap_page and sync_page.
Can you simplify this series to only have hv_remote_flush_tlb_with_range
and remove all the flush_list stuff? That first part is safe and well
understood, because it uses the rmap and so it's clear that you have L2
GPAs at hand. Most of the remarks I made on the Hyper-V API will still
apply.
Paolo
> if (set_spte_ret & SET_SPTE_NEED_REMOTE_TLB_FLUSH)
> - kvm_flush_remote_tlbs(vcpu->kvm);
> + kvm_flush_remote_tlbs_with_list(vcpu->kvm, &flush_list);
>
> return nr_present;
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Re: [PATCH V4 6/15] KVM/MMU: Flush tlb directly in the kvm_set_pte_rmapp()
On 13/10/2018 16:53, lantianyu1...@gmail.com wrote:
> @@ -1781,6 +1781,11 @@ static int kvm_set_pte_rmapp(struct kvm *kvm, struct
> kvm_rmap_head *rmap_head,
> }
> }
>
> + if (need_flush && kvm_available_flush_tlb_with_range()) {
> + kvm_flush_remote_tlbs_with_address(kvm, gfn, 1);
> + return 0;
> + }
> +
Here you're passing an L1 GPA, not an L2 GPA. Is it correct?
Paolo
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Re: [PATCH V4 2/15] KVM/MMU: Add tlb flush with range helper function
On 14/10/2018 10:16, Thomas Gleixner wrote:
>>> +static inline bool kvm_available_flush_tlb_with_range(void)
>>> +{
>>> + return kvm_x86_ops->tlb_remote_flush_with_range;
>>> +}
>> Seems that kvm_available_flush_tlb_with_range() is not used in this patch…
> What's wrong with that?
>
> It provides the implementation and later patches make use of it. It's a
> sensible way to split patches into small, self contained entities.
That's true, on the other hand I have indeed a concerns with this patch:
this series is not bisectable at all, because all the new code is dead
until the very last patch. Uses of the new feature should come _after_
the implementation.
I don't have any big problem with what Liran pointed out (and I can live
with the unused static functions that would warn with -Wunused, too),
but the above should be fixed in v5, basically by moving patches 12-15
at the beginning of the series.
Paolo
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Re: [PATCH V4 00/15] x86/KVM/Hyper-v: Add HV ept tlb range flush hypercall support in KVM
On 13/10/2018 16:53, lantianyu1...@gmail.com wrote: > From: Lan Tianyu > > For nested memory virtualization, Hyper-v doesn't set write-protect > L1 hypervisor EPT page directory and page table node to track changes > while it relies on guest to tell it changes via HvFlushGuestAddressLlist > hypercall. HvFlushGuestAddressLlist hypercall provides a way to flush > EPT page table with ranges which are specified by L1 hypervisor. > > If L1 hypervisor uses INVEPT or HvFlushGuestAddressSpace hypercall to > flush EPT tlb, Hyper-V will invalidate associated EPT shadow page table > and sync L1's EPT table when next EPT page fault is triggered. > HvFlushGuestAddressLlist hypercall helps to avoid such redundant EPT > page fault and synchronization of shadow page table. So I just told you that the first part is well understood but I must retract that; after carefully reviewing the whole series, I think one of us is actually very confused. I am not afraid to say it can be me, but my understanding is that you're passing L1 GPAs to the hypercall and instead the spec says it expects L2 GPAs. (Consider that, because KVM's shadow paging code is shared between nested EPT and !EPT cases, every time you see gpa/gfn in the code it is for L1, while nested EPT GPAs are really what the code calls gva.) What's going on? Paolo ___ devel mailing list de...@linuxdriverproject.org http://driverdev.linuxdriverproject.org/mailman/listinfo/driverdev-devel
Re: [PATCH V4 7/15] KVM/MMU: Flush tlb directly in the kvm_zap_gfn_range()
Hi Paolo:
Thanks for your review.
On Mon, Oct 15, 2018 at 6:04 PM Paolo Bonzini wrote:
>
> On 13/10/2018 16:53, lantianyu1...@gmail.com wrote:
> > + bool flush = false;
> > int i;
> >
> > spin_lock(&kvm->mmu_lock);
> > @@ -5654,18 +5655,27 @@ void kvm_zap_gfn_range(struct kvm *kvm, gfn_t
> > gfn_start, gfn_t gfn_end)
> > slots = __kvm_memslots(kvm, i);
> > kvm_for_each_memslot(memslot, slots) {
> > gfn_t start, end;
> > + bool flush_tlb = true;
> >
> > start = max(gfn_start, memslot->base_gfn);
> > end = min(gfn_end, memslot->base_gfn +
> > memslot->npages);
> > if (start >= end)
> > continue;
> >
> > - slot_handle_level_range(kvm, memslot, kvm_zap_rmapp,
> > - PT_PAGE_TABLE_LEVEL,
> > PT_MAX_HUGEPAGE_LEVEL,
> > - start, end - 1, true);
> > + if (kvm_available_flush_tlb_with_range())
> > + flush_tlb = false;
>
> This should be moved outside the for, because it's invariant.
>
> > + flush = slot_handle_level_range(kvm, memslot,
> > + kvm_zap_rmapp, PT_PAGE_TABLE_LEVEL,
> > + PT_MAX_HUGEPAGE_LEVEL, start,
> > + end - 1, flush_tlb);
>
> ... and this should be "flush |= ".
> > }
> > }
> >
> > + if (flush && kvm_available_flush_tlb_with_range())
> > + kvm_flush_remote_tlbs_with_address(kvm, gfn_start,
> > + gfn_end - gfn_start + 1);
> > +
>
> ... and this can be just if (flush), because if flush_tlb is true then
> slot_handle_level_range always returns false.
OK. Will update.
--
Best regards
Tianyu Lan
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Re: [patch 00/11] x86/vdso: Cleanups, simmplifications and CLOCK_TAI support
On Thu, Oct 11, 2018 at 04:00:29PM -0700, Andy Lutomirski wrote: > On Thu, Oct 11, 2018 at 3:28 PM Marcelo Tosatti wrote: > > > > On Tue, Oct 09, 2018 at 01:09:42PM -0700, Andy Lutomirski wrote: > > > On Tue, Oct 9, 2018 at 8:28 AM Marcelo Tosatti > > > wrote: > > > > > > > > On Mon, Oct 08, 2018 at 10:38:22AM -0700, Andy Lutomirski wrote: > > > > > On Mon, Oct 8, 2018 at 8:27 AM Marcelo Tosatti > > > > > wrote: > > > > > > > > I read the comment three more times and even dug through the git > > > > > history. It seems like what you're saying is that, under certain > > > > > conditions (which arguably would be bugs in the core Linux timing > > > > > code), > > > > > > > > I don't see that as a bug. Its just a side effect of reading two > > > > different clocks (one is CLOCK_MONOTONIC and the other is TSC), > > > > and using those two clocks to as a "base + offset". > > > > > > > > As the comment explains, if you do that, can't guarantee monotonicity. > > > > > > > > > actually calling ktime_get_boot_ns() could be non-monotonic > > > > > with respect to the kvmclock timing. But get_kvmclock_ns() isn't used > > > > > for VM timing as such -- it's used for the IOCTL interfaces for > > > > > updating the time offset. So can you explain how my patch is > > > > > incorrect? > > > > > > > > ktime_get_boot_ns() has frequency correction applied, while > > > > reading masterclock + TSC offset does not. > > > > > > > > So the clock reads differ. > > > > > > > > > > Ah, okay, I finally think I see what's going on. In the kvmclock data > > > exposed to the guest, tsc_shift and tsc_to_system_mul come from > > > tgt_tsc_khz, whereas master_kernel_ns and master_cycle_now come from > > > CLOCK_BOOTTIME. So the kvmclock and kernel clock drift apart at a > > > rate given by the frequency shift and then suddenly agree again every > > > time the pvclock data is updated. > > > > Yes. > > > > > Is there a reason to do it this way? > > > > Since pvclock updates which update system_timestamp are expensive (must > > stop all vcpus), > > they should be avoided. > > > > Fair enough. > > > So only HW TSC counts > > makes sense. > > >, and used as offset against vcpu's tsc_timestamp. > > > > Why don't you just expose CLOCK_MONTONIC_RAW or CLOCK_MONOTONIC_RAW > plus suspend time, though? Then you would actually be tracking a real > kernel timekeeping mode, and you wouldn't need all this complicated > offsetting work to avoid accidentally going backwards. Can you outline how that would work ? ___ devel mailing list de...@linuxdriverproject.org http://driverdev.linuxdriverproject.org/mailman/listinfo/driverdev-devel
Re: [PATCH 0/7] staging: vc04_services: Some dead code removal
Stefan Wahren writes: > Hi Tuomas, > >> Tuomas Tynkkynen hat am 4. Oktober 2018 um 11:37 >> geschrieben: >> >> >> Drop various pieces of dead code from here and there to get rid of >> the remaining users of VCHI_CONNECTION_T. After that we get to drop >> entire header files worth of unused code. >> >> I've tested on a Raspberry Pi Model B (bcm2835_defconfig) that >> snd-bcm2835 can still play analog audio just fine. >> > > thanks and i'm fine with your patch series: > > Acked-by: Stefan Wahren > > Unfortunately this would break compilation of the downstream vchi > drivers like vcsm [1]. Personally i don't want to maintain another > one, because i cannot see the gain of the resulting effort. > > [1] - > https://github.com/raspberrypi/linux/tree/rpi-4.14.y/drivers/char/broadcom/vc_sm I think the main concern would be if we removed things necessary for 6by9's new vcsm (the one that will let us do dma-buf sharing between media decode and DRM). On the other hand, git revert is a thing, so it's not like we actually lose anything. signature.asc Description: PGP signature ___ devel mailing list de...@linuxdriverproject.org http://driverdev.linuxdriverproject.org/mailman/listinfo/driverdev-devel
Confidential Business Proposal
Dear Sir, Madam, A Strictly Confidential Business Proposal I am Mr.John Woods, a Consultant with the Department of Power and Steel here in Spain . I have been contracted by a wealthy individual and serving government official from somewhere in Africa who is interested in engaging your services for investment of a large volume of fund (Ten Million Five Hundred Thousand Dollars ) Which he Deposited with a Finance Company here in Spain . You will act as the beneficiary of the fund to carry out the investment of the fund in any business venture you consider lucrative. If you are capable of handling any type of investment in your country, Please, get back to me immediately and send your telephone and fax numbers to enable me communicate with you and provide you with further details. Note that 30% of the fund is your share (Commission) for securing the fund from the security company before the investment of the fund shall be carried out. This is necessary because the investor as a serving government official in his country of origin is eager to transfer ownership of the fund to you because he is not expected in his official capacity to own such huge sum of money. I will appreciate an urgent response from you. Yours faithfully, Mr.John Woods Email: johnwoods...@gmail.com ___ devel mailing list de...@linuxdriverproject.org http://driverdev.linuxdriverproject.org/mailman/listinfo/driverdev-devel
Confidential Business Proposal
Dear Sir, Madam, A Strictly Confidential Business Proposal I am Mr.John Woods, a Consultant with the Department of Power and Steel here in Spain . I have been contracted by a wealthy individual and serving government official from somewhere in Africa who is interested in engaging your services for investment of a large volume of fund (Ten Million Five Hundred Thousand Dollars ) Which he Deposited with a Finance Company here in Spain . You will act as the beneficiary of the fund to carry out the investment of the fund in any business venture you consider lucrative. If you are capable of handling any type of investment in your country, Please, get back to me immediately and send your telephone and fax numbers to enable me communicate with you and provide you with further details. Note that 30% of the fund is your share (Commission) for securing the fund from the security company before the investment of the fund shall be carried out. This is necessary because the investor as a serving government official in his country of origin is eager to transfer ownership of the fund to you because he is not expected in his official capacity to own such huge sum of money. I will appreciate an urgent response from you. Yours faithfully, Mr.John Woods Email: johnwoods...@gmail.com ___ devel mailing list de...@linuxdriverproject.org http://driverdev.linuxdriverproject.org/mailman/listinfo/driverdev-devel
[PATCH v5 00/17] staging: mt7621-pci: Parse ports info from DT and other minor cleanups
This patch series parse remaining port info from device tree storing it in mt7621_pcie_port struct created for this. Also minor cleanups are performed here: - Remove not used macros. - Use kernel reset_control functions. - Remove unused code. Changes in v5: - Patch 18 removed from the series. Already submited by Mamta Shukla (also applied) - Rebased onto staging-next Changes in v4: - Some patches of this series was previously added to staging. - Rebased onto staging-next. Changes in v3: - 'mt7621_pcie_enable_port' now returns an error instead of void to avoid a layering violation. - Delete 'mt7621_pcie_port_free' function and just delete port from the list in probe function. - Use parent node to get base address registers for each port. Changes in v2: - Rewrite phy part of the driver - fix some checkpatch complains - make use of sysctl from DT Hope this helps. Best regards, Sergio Paracuellos Sergio Paracuellos (17): staging: mt7621-pci: parse and init port data from device tree staging: mt7621-pci: replace return value if devm_pci_alloc_host_bridge call fails staging: mt7621-pci: add two helpers for read and write pcie register ports staging: mt7621-pci: factor out 'mt7621_pcie_enable_port' function staging: mt7621-pci: remove [ASSERT|DEASSERT]_SYSRST_PCIE macros staging: mt7621-pci: remove GPL2+ text from license header staging: mt7621-pci: remove two commented code lines staging: mt7621-pci: remove reset related unused macros staging: mt7621-pci: reagroup reset related macros all together staging: mt7621-pci: rewrite pcie phy related functions staging: mt7621-pci: factor out 'mt7621_enable_phy' function staging: mt7621-pci: debug port N_FTS inside 'mt7621_pcie_enable_port' staging: mt7621-pci: rename 'mt7621_pcie_enable_port' into 'mt7621_pcie_init_port' staging: mt7621-dts: add sysctl registers base address to pcie staging: mt7621-pci: remap and use sysctl from device tree staging: mt7621-pci: use a trailing */ on a separate line staging: mt7621-pci: use dev_* functions instead of printk drivers/staging/mt7621-dts/mt7621.dtsi | 4 +- drivers/staging/mt7621-pci/pci-mt7621.c | 583 2 files changed, 373 insertions(+), 214 deletions(-) -- 2.7.4 ___ devel mailing list de...@linuxdriverproject.org http://driverdev.linuxdriverproject.org/mailman/listinfo/driverdev-devel
[PATCH v5 01/17] staging: mt7621-pci: parse and init port data from device tree
Add initialization of each PCIe port reading and initializing
data using device tree.
Signed-off-by: Sergio Paracuellos
---
drivers/staging/mt7621-pci/pci-mt7621.c | 75 +++--
1 file changed, 71 insertions(+), 4 deletions(-)
diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c
b/drivers/staging/mt7621-pci/pci-mt7621.c
index 8371a9c..b7cb273 100644
--- a/drivers/staging/mt7621-pci/pci-mt7621.c
+++ b/drivers/staging/mt7621-pci/pci-mt7621.c
@@ -126,16 +126,20 @@ static int pcie_link_status;
/**
* struct mt7621_pcie_port - PCIe port information
- * @base: IO mapped register base
+ * @base: I/O mapped register base
* @list: port list
* @pcie: pointer to PCIe host info
- * @reset: pointer to port reset control
+ * @pcie_rst: pointer to port reset control
+ * @pcie_clk: PCIe clock
+ * @slot: port slot
*/
struct mt7621_pcie_port {
void __iomem *base;
struct list_head list;
struct mt7621_pcie *pcie;
- struct reset_control *reset;
+ struct reset_control *pcie_rst;
+ struct clk *pcie_clk;
+ u32 slot;
};
/**
@@ -382,10 +386,57 @@ static int mt7621_pci_parse_request_of_pci_ranges(struct
mt7621_pcie *pcie)
return 0;
}
+static int mt7621_pcie_parse_port(struct mt7621_pcie *pcie,
+ struct device_node *node,
+ int slot)
+{
+ struct mt7621_pcie_port *port;
+ struct device *dev = pcie->dev;
+ struct device_node *pnode = dev->of_node;
+ struct resource regs;
+ char name[6];
+ int err;
+
+ port = devm_kzalloc(dev, sizeof(*port), GFP_KERNEL);
+ if (!port)
+ return -ENOMEM;
+
+ err = of_address_to_resource(pnode, slot + 1, ®s);
+ if (err) {
+ dev_err(dev, "missing \"reg\" property\n");
+ return err;
+ }
+
+ port->base = devm_ioremap_resource(dev, ®s);
+ if (IS_ERR(port->base))
+ return PTR_ERR(port->base);
+
+ snprintf(name, sizeof(name), "pcie%d", slot);
+ port->pcie_clk = devm_clk_get(dev, name);
+ if (IS_ERR(port->pcie_clk)) {
+ dev_err(dev, "failed to get pcie%d clock\n", slot);
+ return PTR_ERR(port->pcie_clk);
+ }
+
+ port->pcie_rst = devm_reset_control_get_exclusive(dev, name);
+ if (PTR_ERR(port->pcie_rst) == -EPROBE_DEFER) {
+ dev_err(dev, "failed to get pcie%d reset control\n", slot);
+ return PTR_ERR(port->pcie_rst);
+ }
+
+ port->slot = slot;
+ port->pcie = pcie;
+
+ INIT_LIST_HEAD(&port->list);
+ list_add_tail(&port->list, &pcie->ports);
+
+ return 0;
+}
+
static int mt7621_pcie_parse_dt(struct mt7621_pcie *pcie)
{
struct device *dev = pcie->dev;
- struct device_node *node = dev->of_node;
+ struct device_node *node = dev->of_node, *child;
struct resource regs;
int err;
@@ -399,6 +450,22 @@ static int mt7621_pcie_parse_dt(struct mt7621_pcie *pcie)
if (IS_ERR(pcie->base))
return PTR_ERR(pcie->base);
+ for_each_available_child_of_node(node, child) {
+ int slot;
+
+ err = of_pci_get_devfn(child);
+ if (err < 0) {
+ dev_err(dev, "failed to parse devfn: %d\n", err);
+ return err;
+ }
+
+ slot = PCI_SLOT(err);
+
+ err = mt7621_pcie_parse_port(pcie, child, slot);
+ if (err)
+ return err;
+ }
+
return 0;
}
--
2.7.4
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[PATCH v5 03/17] staging: mt7621-pci: add two helpers for read and write pcie register ports
mt7621-pcie_port data structure has filed 'base' as the base address for
read and write related port registers. Create two inline functions
'pcie_port_read' and 'pcie_port_write' to make this task easier and
code more readable.
Signed-off-by: Sergio Paracuellos
---
drivers/staging/mt7621-pci/pci-mt7621.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c
b/drivers/staging/mt7621-pci/pci-mt7621.c
index 357bbdd..04e82c3 100644
--- a/drivers/staging/mt7621-pci/pci-mt7621.c
+++ b/drivers/staging/mt7621-pci/pci-mt7621.c
@@ -175,6 +175,17 @@ static inline void pcie_write(struct mt7621_pcie *pcie,
u32 val, u32 reg)
writel(val, pcie->base + reg);
}
+static inline u32 pcie_port_read(struct mt7621_pcie_port *port, u32 reg)
+{
+ return readl(port->base + reg);
+}
+
+static inline void pcie_port_write(struct mt7621_pcie_port *port,
+ u32 val, u32 reg)
+{
+ writel(val, port->base + reg);
+}
+
static inline u32 mt7621_pci_get_cfgaddr(unsigned int bus, unsigned int slot,
unsigned int func, unsigned int where)
{
--
2.7.4
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[PATCH v5 02/17] staging: mt7621-pci: replace return value if devm_pci_alloc_host_bridge call fails
Driver probe function calls 'devm_pci_alloc_host_bridge'. If this call fails it is returning -ENODEV. Return -ENOMEM instead which is more accurate for this. Signed-off-by: Sergio Paracuellos --- drivers/staging/mt7621-pci/pci-mt7621.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c b/drivers/staging/mt7621-pci/pci-mt7621.c index b7cb273..357bbdd 100644 --- a/drivers/staging/mt7621-pci/pci-mt7621.c +++ b/drivers/staging/mt7621-pci/pci-mt7621.c @@ -516,7 +516,7 @@ static int mt7621_pci_probe(struct platform_device *pdev) bridge = devm_pci_alloc_host_bridge(dev, sizeof(*pcie)); if (!bridge) - return -ENODEV; + return -ENOMEM; pcie = pci_host_bridge_priv(bridge); pcie->dev = dev; -- 2.7.4 ___ devel mailing list de...@linuxdriverproject.org http://driverdev.linuxdriverproject.org/mailman/listinfo/driverdev-devel
[PATCH v5 04/17] staging: mt7621-pci: factor out 'mt7621_pcie_enable_port' function
Driver probe function is a mess and shall be refactored a lot. At first
make use of assert and deassert control factoring out a new function
called 'mt7621_pcie_enable_port'.
Signed-off-by: Sergio Paracuellos
---
drivers/staging/mt7621-pci/pci-mt7621.c | 88 +++--
1 file changed, 41 insertions(+), 47 deletions(-)
diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c
b/drivers/staging/mt7621-pci/pci-mt7621.c
index 04e82c3..9be5ca1 100644
--- a/drivers/staging/mt7621-pci/pci-mt7621.c
+++ b/drivers/staging/mt7621-pci/pci-mt7621.c
@@ -480,6 +480,39 @@ static int mt7621_pcie_parse_dt(struct mt7621_pcie *pcie)
return 0;
}
+static int mt7621_pcie_enable_port(struct mt7621_pcie_port *port)
+{
+ struct mt7621_pcie *pcie = port->pcie;
+ struct device *dev = pcie->dev;
+ u32 slot = port->slot;
+ u32 val = 0;
+ int err;
+
+ err = clk_prepare_enable(port->pcie_clk);
+ if (err) {
+ dev_err(dev, "failed to enable pcie%d clock\n", slot);
+ return err;
+ }
+
+ reset_control_assert(port->pcie_rst);
+ reset_control_deassert(port->pcie_rst);
+
+ if ((pcie_port_read(port, RALINK_PCI_STATUS) & 0x1) == 0) {
+ dev_err(dev, "pcie%d no card, disable it (RST & CLK)\n", slot);
+ reset_control_assert(port->pcie_rst);
+ rt_sysc_m32(BIT(24 + slot), 0, RALINK_CLKCFG1);
+ pcie_link_status &= ~(1 << slot);
+ } else {
+ pcie_link_status |= BIT(slot);
+ val = pcie_read(pcie, RALINK_PCI_PCIMSK_ADDR);
+ /* enable pcie interrupt */
+ val |= BIT(20 + slot);
+ pcie_write(pcie, val, RALINK_PCI_PCIMSK_ADDR);
+ }
+
+ return 0;
+}
+
static int mt7621_pcie_request_resources(struct mt7621_pcie *pcie,
struct list_head *res)
{
@@ -518,6 +551,7 @@ static int mt7621_pci_probe(struct platform_device *pdev)
struct device *dev = &pdev->dev;
struct mt7621_pcie *pcie;
struct pci_host_bridge *bridge;
+ struct mt7621_pcie_port *port, *tmp;
int err;
u32 val = 0;
LIST_HEAD(res);
@@ -546,12 +580,6 @@ static int mt7621_pci_probe(struct platform_device *pdev)
ioport_resource.start = 0;
ioport_resource.end = ~0UL; /* no limit */
- val = RALINK_PCIE0_RST;
- val |= RALINK_PCIE1_RST;
- val |= RALINK_PCIE2_RST;
-
- ASSERT_SYSRST_PCIE(RALINK_PCIE0_RST | RALINK_PCIE1_RST |
RALINK_PCIE2_RST);
-
*(unsigned int *)(0xbe60) &= ~(0x3 << 10 | 0x3 << 3);
*(unsigned int *)(0xbe60) |= BIT(10) | BIT(3);
mdelay(100);
@@ -561,11 +589,13 @@ static int mt7621_pci_probe(struct platform_device *pdev)
mdelay(100);
- val = RALINK_PCIE0_RST;
- val |= RALINK_PCIE1_RST;
- val |= RALINK_PCIE2_RST;
-
- DEASSERT_SYSRST_PCIE(val);
+ list_for_each_entry_safe(port, tmp, &pcie->ports, list) {
+ err = mt7621_pcie_enable_port(port);
+ if (err) {
+ dev_err(dev, "enabling port %d failed\n", port->slot);
+ list_del(&port->list);
+ }
+ }
if ((*(unsigned int *)(0xbe0c) & 0x) == 0x0101) // MT7621 E2
bypass_pipe_rst(pcie);
@@ -591,42 +621,6 @@ static int mt7621_pci_probe(struct platform_device *pdev)
*(unsigned int *)(0xbe000620) |= BIT(19) | BIT(8) | BIT(7);
// set DATA
mdelay(1000);
- if ((pcie_read(pcie, RT6855_PCIE0_OFFSET + RALINK_PCI_STATUS) & 0x1) ==
0) {
- printk("PCIE0 no card, disable it(RST&CLK)\n");
- ASSERT_SYSRST_PCIE(RALINK_PCIE0_RST);
- rt_sysc_m32(RALINK_PCIE0_CLK_EN, 0, RALINK_CLKCFG1);
- pcie_link_status &= ~(BIT(0));
- } else {
- pcie_link_status |= BIT(0);
- val = pcie_read(pcie, RALINK_PCI_PCIMSK_ADDR);
- val |= BIT(20); // enable pcie1 interrupt
- pcie_write(pcie, val, RALINK_PCI_PCIMSK_ADDR);
- }
-
- if ((pcie_read(pcie, RT6855_PCIE1_OFFSET + RALINK_PCI_STATUS) & 0x1) ==
0) {
- printk("PCIE1 no card, disable it(RST&CLK)\n");
- ASSERT_SYSRST_PCIE(RALINK_PCIE1_RST);
- rt_sysc_m32(RALINK_PCIE1_CLK_EN, 0, RALINK_CLKCFG1);
- pcie_link_status &= ~(BIT(1));
- } else {
- pcie_link_status |= BIT(1);
- val = pcie_read(pcie, RALINK_PCI_PCIMSK_ADDR);
- val |= BIT(21); // enable pcie1 interrupt
- pcie_write(pcie, val, RALINK_PCI_PCIMSK_ADDR);
- }
-
- if ((pcie_read(pcie, RT6855_PCIE2_OFFSET + RALINK_PCI_STATUS) & 0x1) ==
0) {
- printk("PCIE2 no card, disable it(RST&CLK)\n");
- ASSERT_SYSRST_PCIE(RALINK_PCIE2_RST);
- rt_sysc_m32(RALINK_PCIE2_CLK_EN, 0, RAL
[PATCH v5 06/17] staging: mt7621-pci: remove GPL2+ text from license header
This file has a valid SPDX license line added so reamining GPL2+ boilerplate text is not needed at all. Remove it. Signed-off-by: Sergio Paracuellos --- drivers/staging/mt7621-pci/pci-mt7621.c | 31 +++ 1 file changed, 3 insertions(+), 28 deletions(-) diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c b/drivers/staging/mt7621-pci/pci-mt7621.c index d94587e..d61b287 100644 --- a/drivers/staging/mt7621-pci/pci-mt7621.c +++ b/drivers/staging/mt7621-pci/pci-mt7621.c @@ -1,33 +1,10 @@ // SPDX-License-Identifier: GPL-2.0+ -/** - * - * BRIEF MODULE DESCRIPTION +/* + * BRIEF MODULE DESCRIPTION * PCI init for Ralink RT2880 solution * - * Copyright 2007 Ralink Inc. (bruce_ch...@ralinktech.com.tw) - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN - * NO EVENT SHALL THE AUTHOR BELIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF - * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * Copyright 2007 Ralink Inc. (bruce_ch...@ralinktech.com.tw) * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - * - * - ** * May 2007 Bruce Chang * Initial Release * @@ -36,8 +13,6 @@ * * May 2011 Bruce Chang * support RT6855/MT7620 PCIe - * - ** */ #include -- 2.7.4 ___ devel mailing list de...@linuxdriverproject.org http://driverdev.linuxdriverproject.org/mailman/listinfo/driverdev-devel
[PATCH v5 12/17] staging: mt7621-pci: debug port N_FTS inside 'mt7621_pcie_enable_port'
Move debug for the port N_FTS from driver probe function to the more
appropiate one 'mt7621_pcie_enable_port'.
Signed-off-by: Sergio Paracuellos
---
drivers/staging/mt7621-pci/pci-mt7621.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c
b/drivers/staging/mt7621-pci/pci-mt7621.c
index 7e76d30..50c7bd7 100644
--- a/drivers/staging/mt7621-pci/pci-mt7621.c
+++ b/drivers/staging/mt7621-pci/pci-mt7621.c
@@ -575,6 +575,9 @@ static int mt7621_pcie_enable_port(struct mt7621_pcie_port
*port)
mt7621_enable_phy(port);
+ val = read_config(pcie, slot, 0x70c);
+ dev_info(dev, "Port %d N_FTS = %x\n", (unsigned int)val, slot);
+
return 0;
}
@@ -661,9 +664,6 @@ static int mt7621_pci_probe(struct platform_device *pdev)
if (err) {
dev_err(dev, "enabling port %d failed\n", slot);
list_del(&port->list);
- } else {
- val = read_config(pcie, slot, 0x70c);
- dev_info(dev, "Port %d N_FTS = %x\n", (unsigned
int)val, slot);
}
}
--
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[PATCH v5 13/17] staging: mt7621-pci: rename 'mt7621_pcie_enable_port' into 'mt7621_pcie_init_port'
Rename function 'mt7621_pcie_enable_port' with a name which is better
for what the function is really doing calling it 'mt7621_pcie_init_port'.
Signed-off-by: Sergio Paracuellos
---
drivers/staging/mt7621-pci/pci-mt7621.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c
b/drivers/staging/mt7621-pci/pci-mt7621.c
index 50c7bd7..11fe9ff 100644
--- a/drivers/staging/mt7621-pci/pci-mt7621.c
+++ b/drivers/staging/mt7621-pci/pci-mt7621.c
@@ -543,7 +543,7 @@ static int mt7621_pcie_parse_dt(struct mt7621_pcie *pcie)
return 0;
}
-static int mt7621_pcie_enable_port(struct mt7621_pcie_port *port)
+static int mt7621_pcie_init_port(struct mt7621_pcie_port *port)
{
struct mt7621_pcie *pcie = port->pcie;
struct device *dev = pcie->dev;
@@ -660,7 +660,7 @@ static int mt7621_pci_probe(struct platform_device *pdev)
list_for_each_entry_safe(port, tmp, &pcie->ports, list) {
u32 slot = port->slot;
- err = mt7621_pcie_enable_port(port);
+ err = mt7621_pcie_init_port(port);
if (err) {
dev_err(dev, "enabling port %d failed\n", slot);
list_del(&port->list);
--
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[PATCH v5 07/17] staging: mt7621-pci: remove two commented code lines
This two lines whch are commented are not needed at all. Remove them. Signed-off-by: Sergio Paracuellos --- drivers/staging/mt7621-pci/pci-mt7621.c | 5 - 1 file changed, 5 deletions(-) diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c b/drivers/staging/mt7621-pci/pci-mt7621.c index d61b287..c4adf86 100644 --- a/drivers/staging/mt7621-pci/pci-mt7621.c +++ b/drivers/staging/mt7621-pci/pci-mt7621.c @@ -629,11 +629,6 @@ pcie(2/1/0) link statuspcie2_num pcie1_num pcie0_num break; } -/* - ioport_resource.start = mt7621_res_pci_io1.start; - ioport_resource.end = mt7621_res_pci_io1.end; -*/ - pcie_write(pcie, 0x, RALINK_PCI_MEMBASE); pcie_write(pcie, RALINK_PCI_IO_MAP_BASE, RALINK_PCI_IOBASE); -- 2.7.4 ___ devel mailing list de...@linuxdriverproject.org http://driverdev.linuxdriverproject.org/mailman/listinfo/driverdev-devel
[PATCH v5 10/17] staging: mt7621-pci: rewrite pcie phy related functions
Function 'bypass_pipe_rst' and 'set_phy_for_ssc' can be
written in a cleaner way. Instead of use comments to see which
bits are the ones which are being enabled add new macros with
that information using BIT and GENMASK kernel macros. Avoid the
use of set_pcie_phy which is kind of dark and use new macros also
resetting and adding bits using bitwise operators directly in the
code. Now these function are offset-based on the port to use them
cleaner in driver probe functio and improving readability.
Signed-off-by: Sergio Paracuellos
---
drivers/staging/mt7621-pci/pci-mt7621.c | 294 +---
1 file changed, 195 insertions(+), 99 deletions(-)
diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c
b/drivers/staging/mt7621-pci/pci-mt7621.c
index 28c3f0a..5dce7af 100644
--- a/drivers/staging/mt7621-pci/pci-mt7621.c
+++ b/drivers/staging/mt7621-pci/pci-mt7621.c
@@ -66,9 +66,6 @@
#define RALINK_PCI_SUBID 0x0038
#define RALINK_PCI_STATUS 0x0050
-#define RALINK_PCIEPHY_P0P1_CTL_OFFSET 0x9000
-#define RALINK_PCIEPHY_P2_CTL_OFFSET 0xA000
-
#define RALINK_PCI_MM_MAP_BASE 0x6000
#define RALINK_PCI_IO_MAP_BASE 0x1e16
@@ -79,13 +76,79 @@
#define RALINK_PCIE_CLK_GEN1 0x80
#define MEMORY_BASE 0x0
+
static int pcie_link_status;
+/* pcie phy related macros */
+#define RALINK_PCIEPHY_P0P1_CTL_OFFSET 0x9000
+#define RALINK_PCIEPHY_P2_CTL_OFFSET 0xA000
+
+#define RG_P0_TO_P1_WIDTH 0x100
+
+#define RG_PE1_PIPE_REG0x02c
+#define RG_PE1_PIPE_RSTBIT(12)
+#define RG_PE1_PIPE_CMD_FRCBIT(4)
+
+#define RG_PE1_H_LCDDS_REG 0x49c
+#define RG_PE1_H_LCDDS_PCW GENMASK(30, 0)
+#define RG_PE1_H_LCDDS_PCW_VAL(x) ((0x7fff & (x)) << 0)
+
+#define RG_PE1_FRC_H_XTAL_REG 0x400
+#define RG_PE1_FRC_H_XTAL_TYPE BIT(8)
+#define RG_PE1_H_XTAL_TYPE GENMASK(10, 9)
+#define RG_PE1_H_XTAL_TYPE_VAL(x) ((0x3 & (x)) << 9)
+
+#define RG_PE1_FRC_PHY_REG 0x000
+#define RG_PE1_FRC_PHY_EN BIT(4)
+#define RG_PE1_PHY_EN BIT(5)
+
+#define RG_PE1_H_PLL_REG 0x490
+#define RG_PE1_H_PLL_BCGENMASK(23, 22)
+#define RG_PE1_H_PLL_BC_VAL(x) ((0x3 & (x)) << 22)
+#define RG_PE1_H_PLL_BPGENMASK(21, 18)
+#define RG_PE1_H_PLL_BP_VAL(x) ((0xf & (x)) << 18)
+#define RG_PE1_H_PLL_IRGENMASK(15, 12)
+#define RG_PE1_H_PLL_IR_VAL(x) ((0xf & (x)) << 12)
+#define RG_PE1_H_PLL_ICGENMASK(11, 8)
+#define RG_PE1_H_PLL_IC_VAL(x) ((0xf & (x)) << 8)
+#define RG_PE1_H_PLL_PREDIV GENMASK(7, 6)
+#define RG_PE1_H_PLL_PREDIV_VAL(x) ((0x3 & (x)) << 6)
+#define RG_PE1_PLL_DIVEN GENMASK(3, 1)
+#define RG_PE1_PLL_DIVEN_VAL(x)((0x7 & (x)) << 1)
+
+#define RG_PE1_H_PLL_FBKSEL_REG0x4bc
+#define RG_PE1_H_PLL_FBKSEL GENMASK(5, 4)
+#define RG_PE1_H_PLL_FBKSEL_VAL(x) ((0x3 & (x)) << 4)
+
+#defineRG_PE1_H_LCDDS_SSC_PRD_REG 0x4a4
+#define RG_PE1_H_LCDDS_SSC_PRD GENMASK(15, 0)
+#define RG_PE1_H_LCDDS_SSC_PRD_VAL(x) ((0x & (x)) << 0)
+
+#define RG_PE1_H_LCDDS_SSC_DELTA_REG 0x4a8
+#define RG_PE1_H_LCDDS_SSC_DELTAGENMASK(11, 0)
+#define RG_PE1_H_LCDDS_SSC_DELTA_VAL(x) ((0xfff & (x)) << 0)
+#define RG_PE1_H_LCDDS_SSC_DELTA1 GENMASK(27, 16)
+#define RG_PE1_H_LCDDS_SSC_DELTA1_VAL(x) ((0xff & (x)) << 16)
+
+#define RG_PE1_LCDDS_CLK_PH_INV_REG0x4a0
+#define RG_PE1_LCDDS_CLK_PH_INVBIT(5)
+
+#define RG_PE1_H_PLL_BR_REG0x4ac
+#define RG_PE1_H_PLL_BRGENMASK(18, 16)
+#define RG_PE1_H_PLL_BR_VAL(x) ((0x7 & (x)) << 16)
+
+#defineRG_PE1_MSTCKDIV_REG 0x414
+#define RG_PE1_MSTCKDIVGENMASK(7, 6)
+#define RG_PE1_MSTCKDIV_VAL(x) ((0x3 & (x)) << 6)
+
+#define RG_PE1_FRC_MSTCKDIVBIT(5)
+
/**
* struct mt7621_pcie_port - PCIe port information
* @base: I/O mapped register base
* @list: port list
* @pcie: pointer to PCIe host info
+ * @phy_reg_offset: offset to related phy registers
* @pcie_rst: pointer to port reset control
* @pcie_clk: PCIe clock
* @slot: port slot
@@ -94,6 +157,7 @@ struct mt7621_pcie_port {
void __iomem *base;
struct list_head list;
struct mt7621_pcie *pcie;
+ u32 phy_reg_offset;
struct reset_control *pcie_rst;
struct clk *pcie_clk;
u32 slot;
@@ -187,109 +251,140 @@ write_config(struct mt7621_pcie *pcie, unsigned int
dev, u32 reg, u32 val)
}
static void
-set_pcie_phy(struct mt7621_pcie *pcie, u32 offset,
-int start_b, int bits, int val)
+bypass_pipe_rst(struct mt7621_pcie_port *port)
{
+ struct mt7621_pcie *pcie = port->pcie;
+ u32 phy_offset = port->ph
[PATCH v5 09/17] staging: mt7621-pci: reagroup reset related macros all together
Reset bits related macros are in different parts. Reagroup all of them together to improve readability. Signed-off-by: Sergio Paracuellos --- drivers/staging/mt7621-pci/pci-mt7621.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c b/drivers/staging/mt7621-pci/pci-mt7621.c index c9ac92e..28c3f0a 100644 --- a/drivers/staging/mt7621-pci/pci-mt7621.c +++ b/drivers/staging/mt7621-pci/pci-mt7621.c @@ -45,6 +45,9 @@ #define RALINK_PCI_CONFIG_DATA 0x24 #define RALINK_PCI_MEMBASE 0x28 #define RALINK_PCI_IOBASE 0x2C + +/* RALINK_RSTCTRL bits */ +#define RALINK_PCIE_RSTBIT(23) #define RALINK_PCIE0_RST BIT(24) #define RALINK_PCIE1_RST BIT(25) #define RALINK_PCIE2_RST BIT(26) @@ -74,8 +77,6 @@ #define RALINK_GPIOMODE0x60 #define RALINK_PCIE_CLK_GEN0x7c #define RALINK_PCIE_CLK_GEN1 0x80 -//RALINK_RSTCTRL bit -#define RALINK_PCIE_RSTBIT(23) #define MEMORY_BASE 0x0 static int pcie_link_status; -- 2.7.4 ___ devel mailing list de...@linuxdriverproject.org http://driverdev.linuxdriverproject.org/mailman/listinfo/driverdev-devel
[PATCH v5 16/17] staging: mt7621-pci: use a trailing */ on a separate line
Chackpatch script is compalining about one comment which
is not following the kernel style. Fix it.
Signed-off-by: Sergio Paracuellos
---
drivers/staging/mt7621-pci/pci-mt7621.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c
b/drivers/staging/mt7621-pci/pci-mt7621.c
index 0fc98f7..afc8720 100644
--- a/drivers/staging/mt7621-pci/pci-mt7621.c
+++ b/drivers/staging/mt7621-pci/pci-mt7621.c
@@ -410,9 +410,11 @@ static void setup_cm_memory_region(struct resource
*mem_resource)
resource_size_t mask;
if (mips_cps_numiocu(0)) {
- /* FIXME: hardware doesn't accept mask values with 1s after
+ /*
+* FIXME: hardware doesn't accept mask values with 1s after
* 0s (e.g. 0xffef), so it would be great to warn if that's
-* about to happen */
+* about to happen
+*/
mask = ~(mem_resource->end - mem_resource->start);
write_gcr_reg1_base(mem_resource->start);
--
2.7.4
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[PATCH v5 08/17] staging: mt7621-pci: remove reset related unused macros
There are three macros which are not being used at all. Remove them. Signed-off-by: Sergio Paracuellos --- drivers/staging/mt7621-pci/pci-mt7621.c | 4 1 file changed, 4 deletions(-) diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c b/drivers/staging/mt7621-pci/pci-mt7621.c index c4adf86..c9ac92e 100644 --- a/drivers/staging/mt7621-pci/pci-mt7621.c +++ b/drivers/staging/mt7621-pci/pci-mt7621.c @@ -76,10 +76,6 @@ #define RALINK_PCIE_CLK_GEN1 0x80 //RALINK_RSTCTRL bit #define RALINK_PCIE_RSTBIT(23) -#define RALINK_PCI_RST BIT(24) -//RALINK_CLKCFG1 bit -#define RALINK_PCI_CLK_EN BIT(19) -#define RALINK_PCIE_CLK_EN BIT(21) #define MEMORY_BASE 0x0 static int pcie_link_status; -- 2.7.4 ___ devel mailing list de...@linuxdriverproject.org http://driverdev.linuxdriverproject.org/mailman/listinfo/driverdev-devel
[PATCH v5 15/17] staging: mt7621-pci: remap and use sysctl from device tree
There are some pointer read and writes which can be replaced
properly using sysctl registers readed from device tree. Remap
sysctl registers and replace in proper places.
Signed-off-by: Sergio Paracuellos
---
drivers/staging/mt7621-pci/pci-mt7621.c | 38 -
1 file changed, 33 insertions(+), 5 deletions(-)
diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c
b/drivers/staging/mt7621-pci/pci-mt7621.c
index 11fe9ff..0fc98f7 100644
--- a/drivers/staging/mt7621-pci/pci-mt7621.c
+++ b/drivers/staging/mt7621-pci/pci-mt7621.c
@@ -37,6 +37,12 @@
* devices.
*/
+/* sysctl */
+#define MT7621_CHIP_REV_ID 0x0c
+#define MT7621_GPIO_MODE 0x60
+#define CHIP_REV_MT7621_E2 0x0101
+
+/* pcie */
#define RALINK_PCIE0_CLK_ENBIT(24)
#define RALINK_PCIE1_CLK_ENBIT(25)
#define RALINK_PCIE2_CLK_ENBIT(26)
@@ -166,6 +172,7 @@ struct mt7621_pcie_port {
/**
* struct mt7621_pcie - PCIe host information
* @base: IO Mapped Register Base
+ * @sysctl: system control mapped register base
* @io: IO resource
* @mem: non-prefetchable memory resource
* @busn: bus range
@@ -175,6 +182,7 @@ struct mt7621_pcie_port {
*/
struct mt7621_pcie {
void __iomem *base;
+ void __iomem *sysctl;
struct device *dev;
struct resource io;
struct resource mem;
@@ -389,8 +397,10 @@ set_phy_for_ssc(struct mt7621_pcie_port *port)
static void mt7621_enable_phy(struct mt7621_pcie_port *port)
{
- /* MT7621 E2 */
- if ((*(unsigned int *)(0xbe0c) & 0x) == 0x0101)
+ struct mt7621_pcie *pcie = port->pcie;
+ u32 chip_rev_id = ioread32(pcie->sysctl + MT7621_CHIP_REV_ID);
+
+ if ((chip_rev_id & 0x) == CHIP_REV_MT7621_E2)
bypass_pipe_rst(port);
set_phy_for_ssc(port);
}
@@ -524,6 +534,16 @@ static int mt7621_pcie_parse_dt(struct mt7621_pcie *pcie)
if (IS_ERR(pcie->base))
return PTR_ERR(pcie->base);
+ err = of_address_to_resource(node, 4, ®s);
+ if (err) {
+ dev_err(dev, "missing \"reg\" property\n");
+ return err;
+ }
+
+ pcie->sysctl = devm_ioremap_resource(dev, ®s);
+ if (IS_ERR(pcie->sysctl))
+ return PTR_ERR(pcie->sysctl);
+
for_each_available_child_of_node(node, child) {
int slot;
@@ -614,6 +634,16 @@ static int mt7621_pcie_register_host(struct
pci_host_bridge *host,
return pci_host_probe(host);
}
+static void mt7621_set_gpio_mode(struct mt7621_pcie *pcie)
+{
+ u32 reg = ioread32(pcie->sysctl + MT7621_GPIO_MODE);
+
+ reg &= ~(0x3 << 10 | 0x3 << 3);
+ reg |= (BIT(10) | BIT(3));
+ iowrite32(reg, pcie->sysctl + MT7621_GPIO_MODE);
+ mdelay(100);
+}
+
static int mt7621_pci_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
@@ -648,9 +678,7 @@ static int mt7621_pci_probe(struct platform_device *pdev)
ioport_resource.start = 0;
ioport_resource.end = ~0UL; /* no limit */
- *(unsigned int *)(0xbe60) &= ~(0x3 << 10 | 0x3 << 3);
- *(unsigned int *)(0xbe60) |= BIT(10) | BIT(3);
- mdelay(100);
+ mt7621_set_gpio_mode(pcie);
*(unsigned int *)(0xbe000600) |= BIT(19) | BIT(8) | BIT(7); // use
GPIO19/GPIO8/GPIO7 (PERST_N/UART_RXD3/UART_TXD3)
mdelay(100);
*(unsigned int *)(0xbe000620) &= ~(BIT(19) | BIT(8) | BIT(7));
// clear DATA
--
2.7.4
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[PATCH v5 17/17] staging: mt7621-pci: use dev_* functions instead of printk
checkpatch script is complaining about the use of printk instead
of use more proper dev_* kernel functions. Replace all of them
removing warnings.
Signed-off-by: Sergio Paracuellos
---
drivers/staging/mt7621-pci/pci-mt7621.c | 14 --
1 file changed, 8 insertions(+), 6 deletions(-)
diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c
b/drivers/staging/mt7621-pci/pci-mt7621.c
index afc8720..6d26180 100644
--- a/drivers/staging/mt7621-pci/pci-mt7621.c
+++ b/drivers/staging/mt7621-pci/pci-mt7621.c
@@ -405,8 +405,10 @@ static void mt7621_enable_phy(struct mt7621_pcie_port
*port)
set_phy_for_ssc(port);
}
-static void setup_cm_memory_region(struct resource *mem_resource)
+static void setup_cm_memory_region(struct mt7621_pcie *pcie)
{
+ struct resource *mem_resource = &pcie->mem;
+ struct device *dev = pcie->dev;
resource_size_t mask;
if (mips_cps_numiocu(0)) {
@@ -419,7 +421,7 @@ static void setup_cm_memory_region(struct resource
*mem_resource)
write_gcr_reg1_base(mem_resource->start);
write_gcr_reg1_mask(mask | CM_GCR_REGn_MASK_CMTGT_IOCU0);
- printk("PCI coherence region base: 0x%08llx, mask/settings:
0x%08llx\n",
+ dev_info(dev, "PCI coherence region base: 0x%08llx,
mask/settings: 0x%08llx\n",
(unsigned long long)read_gcr_reg1_base(),
(unsigned long long)read_gcr_reg1_mask());
}
@@ -771,7 +773,7 @@ pcie(2/1/0) link status pcie2_num pcie1_num
pcie0_num
RT6855_PCIE0_OFFSET + RALINK_PCI_IMBASEBAR0_ADDR);
pcie_write(pcie, 0x06040001,
RT6855_PCIE0_OFFSET + RALINK_PCI_CLASS);
- printk("PCIE0 enabled\n");
+ dev_info(dev, "PCIE0 enabled\n");
}
//PCIe1
@@ -783,7 +785,7 @@ pcie(2/1/0) link status pcie2_num pcie1_num
pcie0_num
RT6855_PCIE1_OFFSET + RALINK_PCI_IMBASEBAR0_ADDR);
pcie_write(pcie, 0x06040001,
RT6855_PCIE1_OFFSET + RALINK_PCI_CLASS);
- printk("PCIE1 enabled\n");
+ dev_info(dev, "PCIE1 enabled\n");
}
//PCIe2
@@ -795,7 +797,7 @@ pcie(2/1/0) link status pcie2_num pcie1_num
pcie0_num
RT6855_PCIE2_OFFSET + RALINK_PCI_IMBASEBAR0_ADDR);
pcie_write(pcie, 0x06040001,
RT6855_PCIE2_OFFSET + RALINK_PCI_CLASS);
- printk("PCIE2 enabled\n");
+ dev_info(dev, "PCIE2 enabled\n");
}
switch (pcie_link_status) {
@@ -830,7 +832,7 @@ pcie(2/1/0) link status pcie2_num pcie1_num
pcie0_num
return err;
}
- setup_cm_memory_region(&pcie->mem);
+ setup_cm_memory_region(pcie);
err = mt7621_pcie_request_resources(pcie, &res);
if (err) {
--
2.7.4
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[PATCH v5 05/17] staging: mt7621-pci: remove [ASSERT|DEASSERT]_SYSRST_PCIE macros
Driver is using reset_control kernel API's to manage this so this
two macros are not needed anymore. Remove them.
Signed-off-by: Sergio Paracuellos
---
drivers/staging/mt7621-pci/pci-mt7621.c | 15 ---
1 file changed, 15 deletions(-)
diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c
b/drivers/staging/mt7621-pci/pci-mt7621.c
index 9be5ca1..d94587e 100644
--- a/drivers/staging/mt7621-pci/pci-mt7621.c
+++ b/drivers/staging/mt7621-pci/pci-mt7621.c
@@ -94,21 +94,6 @@
#define RALINK_PCI_MM_MAP_BASE 0x6000
#define RALINK_PCI_IO_MAP_BASE 0x1e16
-#define ASSERT_SYSRST_PCIE(val)\
- do {\
- if (rt_sysc_r32(SYSC_REG_CHIP_REV) == 0x00030101) \
- rt_sysc_m32(0, val, RALINK_RSTCTRL);\
- else\
- rt_sysc_m32(val, 0, RALINK_RSTCTRL);\
- } while (0)
-#define DEASSERT_SYSRST_PCIE(val) \
- do {\
- if (rt_sysc_r32(SYSC_REG_CHIP_REV) == 0x00030101) \
- rt_sysc_m32(val, 0, RALINK_RSTCTRL);\
- else\
- rt_sysc_m32(0, val, RALINK_RSTCTRL);\
- } while (0)
-
#define RALINK_CLKCFG1 0x30
#define RALINK_RSTCTRL 0x34
#define RALINK_GPIOMODE0x60
--
2.7.4
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[PATCH v5 14/17] staging: mt7621-dts: add sysctl registers base address to pcie
Add missing system control registers address in pcie node of the device tree. Signed-off-by: Sergio Paracuellos --- drivers/staging/mt7621-dts/mt7621.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/staging/mt7621-dts/mt7621.dtsi b/drivers/staging/mt7621-dts/mt7621.dtsi index 2e837e6..6b4bc43 100644 --- a/drivers/staging/mt7621-dts/mt7621.dtsi +++ b/drivers/staging/mt7621-dts/mt7621.dtsi @@ -397,8 +397,8 @@ reg = <0x1e14 0x100 /* host-pci bridge registers */ 0x1e142000 0x100/* pcie port 0 RC control registers */ 0x1e143000 0x100/* pcie port 1 RC control registers */ - 0x1e144000 0x100>; /* pcie port 2 RC control registers */ - + 0x1e144000 0x100/* pcie port 2 RC control registers */ + 0x1e00 0x100>; /* sysctl */ #address-cells = <3>; #size-cells = <2>; -- 2.7.4 ___ devel mailing list de...@linuxdriverproject.org http://driverdev.linuxdriverproject.org/mailman/listinfo/driverdev-devel
[PATCH v5 11/17] staging: mt7621-pci: factor out 'mt7621_enable_phy' function
Factor out a new function 'mt7621_enable_phy' for enabling the
pcie phy for each port and call it from 'mt7621_pcie_enable_port'.
Signed-off-by: Sergio Paracuellos
---
drivers/staging/mt7621-pci/pci-mt7621.c | 13 ++---
1 file changed, 10 insertions(+), 3 deletions(-)
diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c
b/drivers/staging/mt7621-pci/pci-mt7621.c
index 5dce7af..7e76d30 100644
--- a/drivers/staging/mt7621-pci/pci-mt7621.c
+++ b/drivers/staging/mt7621-pci/pci-mt7621.c
@@ -387,6 +387,14 @@ set_phy_for_ssc(struct mt7621_pcie_port *port)
pcie_write(pcie, val, offset);
}
+static void mt7621_enable_phy(struct mt7621_pcie_port *port)
+{
+ /* MT7621 E2 */
+ if ((*(unsigned int *)(0xbe0c) & 0x) == 0x0101)
+ bypass_pipe_rst(port);
+ set_phy_for_ssc(port);
+}
+
static void setup_cm_memory_region(struct resource *mem_resource)
{
resource_size_t mask;
@@ -565,6 +573,8 @@ static int mt7621_pcie_enable_port(struct mt7621_pcie_port
*port)
pcie_write(pcie, val, RALINK_PCI_PCIMSK_ADDR);
}
+ mt7621_enable_phy(port);
+
return 0;
}
@@ -652,9 +662,6 @@ static int mt7621_pci_probe(struct platform_device *pdev)
dev_err(dev, "enabling port %d failed\n", slot);
list_del(&port->list);
} else {
- if ((*(unsigned int *)(0xbe0c) & 0x) == 0x0101)
// MT7621 E2
- bypass_pipe_rst(port);
- set_phy_for_ssc(port);
val = read_config(pcie, slot, 0x70c);
dev_info(dev, "Port %d N_FTS = %x\n", (unsigned
int)val, slot);
}
--
2.7.4
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Re: [PATCH v3] staging: gasket: Fix sparse "incorrect type in assignment" warnings.
On Wed, Oct 10, 2018 at 2:14 PM Laurence Rochfort
wrote:
>
> Remove the coherent buffer __iomem cookie because the buffer is
> allocated from dma_alloc_coherent().
>
> warning: incorrect type in assignment (different address spaces)
>expected unsigned char [noderef] [usertype] *virt_base
>got void *[assigned] mem
> warning: incorrect type in argument 3 (different address spaces)
>expected void *cpu_addr
>got unsigned char [noderef] [usertype] *virt_base
>
> Signed-off-by: Laurence Rochfort
> ---
> Changes in v3:
> - Just remove the __iommem cookie, don't alter type.
>
> drivers/staging/gasket/gasket_core.h | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/staging/gasket/gasket_core.h
> b/drivers/staging/gasket/gasket_core.h
> index 275fd0b..e62adcd 100644
> --- a/drivers/staging/gasket/gasket_core.h
> +++ b/drivers/staging/gasket/gasket_core.h
> @@ -231,7 +231,7 @@ struct gasket_coherent_buffer_desc {
> /* Coherent buffer structure. */
> struct gasket_coherent_buffer {
> /* Virtual base address. */
> - u8 __iomem *virt_base;
> + u8 *virt_base;
>
> /* Physical base address. */
> ulong phys_base;
> --
> 2.9.5
Reviewed-by: Todd Poynor
Thanks!
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[PATCH net-next, v3] hv_netvsc: fix vf serial matching with pci slot info
From: Haiyang Zhang
The VF device's serial number is saved as a string in PCI slot's
kobj name, not the slot->number. This patch corrects the netvsc
driver, so the VF device can be successfully paired with synthetic
NIC.
Fixes: 00d7ddba1143 ("hv_netvsc: pair VF based on serial number")
Reported-by: Vitaly Kuznetsov
Signed-off-by: Haiyang Zhang
---
drivers/net/hyperv/netvsc_drv.c | 15 +++
1 file changed, 11 insertions(+), 4 deletions(-)
diff --git a/drivers/net/hyperv/netvsc_drv.c b/drivers/net/hyperv/netvsc_drv.c
index 9bcaf204a7d4..cf36e7ff3191 100644
--- a/drivers/net/hyperv/netvsc_drv.c
+++ b/drivers/net/hyperv/netvsc_drv.c
@@ -2030,14 +2030,15 @@ static void netvsc_vf_setup(struct work_struct *w)
rtnl_unlock();
}
-/* Find netvsc by VMBus serial number.
- * The PCI hyperv controller records the serial number as the slot.
+/* Find netvsc by VF serial number.
+ * The PCI hyperv controller records the serial number as the slot kobj name.
*/
static struct net_device *get_netvsc_byslot(const struct net_device *vf_netdev)
{
struct device *parent = vf_netdev->dev.parent;
struct net_device_context *ndev_ctx;
struct pci_dev *pdev;
+ u32 serial;
if (!parent || !dev_is_pci(parent))
return NULL; /* not a PCI device */
@@ -2048,16 +2049,22 @@ static struct net_device *get_netvsc_byslot(const
struct net_device *vf_netdev)
return NULL;
}
+ if (kstrtou32(pci_slot_name(pdev->slot), 10, &serial)) {
+ netdev_notice(vf_netdev, "Invalid vf serial:%s\n",
+ pci_slot_name(pdev->slot));
+ return NULL;
+ }
+
list_for_each_entry(ndev_ctx, &netvsc_dev_list, list) {
if (!ndev_ctx->vf_alloc)
continue;
- if (ndev_ctx->vf_serial == pdev->slot->number)
+ if (ndev_ctx->vf_serial == serial)
return hv_get_drvdata(ndev_ctx->device_ctx);
}
netdev_notice(vf_netdev,
- "no netdev found for slot %u\n", pdev->slot->number);
+ "no netdev found for vf serial:%u\n", serial);
return NULL;
}
--
2.18.0
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Re: [PATCH net-next, v3] hv_netvsc: fix vf serial matching with pci slot info
On Mon, 15 Oct 2018 19:06:15 +
Haiyang Zhang wrote:
> From: Haiyang Zhang
>
> The VF device's serial number is saved as a string in PCI slot's
> kobj name, not the slot->number. This patch corrects the netvsc
> driver, so the VF device can be successfully paired with synthetic
> NIC.
>
> Fixes: 00d7ddba1143 ("hv_netvsc: pair VF based on serial number")
> Reported-by: Vitaly Kuznetsov
> Signed-off-by: Haiyang Zhang
Reviewed-by: Stephen Hemminger
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Re: [PATCH 01/11] staging: gasket: core: debug log updates
On Mon, Oct 15, 2018 at 12:34 AM Greg Kroah-Hartman wrote: > > On Sun, Oct 14, 2018 at 09:59:17PM -0700, Todd Poynor wrote: > > From: Todd Poynor > > > > Add debug logs for device enable/disable events, > > Why? > > What is going to need this? As one of the few people actually developing for Apex chips (but this may be more soon), I ran into a situation where I cared about this. But I usually cobble together custom debugging for development situations, and generally don't get debug logs for released-in-the-wild drivers, so I'm fine not including these or any other debug logs. It sounds like debug logs face a pretty high bar for acceptance. I'm happy to send a patch removing all of 'em from gasket/apex if that's preferred. > > remove logs for > > callbacks (the called functions can generate their own logs if needed). > > That's a different thing than "adding" them, so shouldn't this really be > 2 patches? If it was, I could have accepted this patch already, and > ignored the "add new logs" one :) Sure, the callbacks most frequently occur during disable/enable events and were linked in my brain, but will send a new patch to just remove the useless callback logs. > > thanks, > > greg k-h ___ devel mailing list de...@linuxdriverproject.org http://driverdev.linuxdriverproject.org/mailman/listinfo/driverdev-devel
[PATCH] staging: add nrf24 driver
This patch adds driver for Nordic Semiconductor nRF24L01+ radio module.
Signed-off-by: Marcin Ciupak
---
drivers/staging/Kconfig | 2 +
drivers/staging/Makefile | 1 +
drivers/staging/nrf24/Kconfig | 16 +
drivers/staging/nrf24/Makefile| 3 +
drivers/staging/nrf24/TODO| 7 +
.../nrf24/devicetree/nrf24-spi0-overlay.dts | 54 ++
.../nrf24/devicetree/nrf24-spi1-overlay.dts | 54 ++
drivers/staging/nrf24/devicetree/nrf24.txt| 1 +
drivers/staging/nrf24/nRF24L01.h | 82 ++
drivers/staging/nrf24/nrf24_enums.h | 60 ++
drivers/staging/nrf24/nrf24_hal.c | 764 +++
drivers/staging/nrf24/nrf24_hal.h | 54 ++
drivers/staging/nrf24/nrf24_if.c | 917 ++
drivers/staging/nrf24/nrf24_if.h | 63 ++
drivers/staging/nrf24/nrf24_sysfs.c | 707 ++
drivers/staging/nrf24/nrf24_sysfs.h | 14 +
16 files changed, 2799 insertions(+)
create mode 100644 drivers/staging/nrf24/Kconfig
create mode 100644 drivers/staging/nrf24/Makefile
create mode 100644 drivers/staging/nrf24/TODO
create mode 100644 drivers/staging/nrf24/devicetree/nrf24-spi0-overlay.dts
create mode 100644 drivers/staging/nrf24/devicetree/nrf24-spi1-overlay.dts
create mode 100644 drivers/staging/nrf24/devicetree/nrf24.txt
create mode 100644 drivers/staging/nrf24/nRF24L01.h
create mode 100644 drivers/staging/nrf24/nrf24_enums.h
create mode 100644 drivers/staging/nrf24/nrf24_hal.c
create mode 100644 drivers/staging/nrf24/nrf24_hal.h
create mode 100644 drivers/staging/nrf24/nrf24_if.c
create mode 100644 drivers/staging/nrf24/nrf24_if.h
create mode 100644 drivers/staging/nrf24/nrf24_sysfs.c
create mode 100644 drivers/staging/nrf24/nrf24_sysfs.h
diff --git a/drivers/staging/Kconfig b/drivers/staging/Kconfig
index 1abf76be2aa8..55d688f3112e 100644
--- a/drivers/staging/Kconfig
+++ b/drivers/staging/Kconfig
@@ -126,4 +126,6 @@ source "drivers/staging/axis-fifo/Kconfig"
source "drivers/staging/erofs/Kconfig"
+source "drivers/staging/nrf24/Kconfig"
+
endif # STAGING
diff --git a/drivers/staging/Makefile b/drivers/staging/Makefile
index ab0cbe8815b1..c18e74df03af 100644
--- a/drivers/staging/Makefile
+++ b/drivers/staging/Makefile
@@ -53,3 +53,4 @@ obj-$(CONFIG_SOC_MT7621) += mt7621-dts/
obj-$(CONFIG_STAGING_GASKET_FRAMEWORK) += gasket/
obj-$(CONFIG_XIL_AXIS_FIFO)+= axis-fifo/
obj-$(CONFIG_EROFS_FS) += erofs/
+obj-$(CONFIG_NRF24)+= nrf24/
diff --git a/drivers/staging/nrf24/Kconfig b/drivers/staging/nrf24/Kconfig
new file mode 100644
index ..67ebf14dd982
--- /dev/null
+++ b/drivers/staging/nrf24/Kconfig
@@ -0,0 +1,16 @@
+config NRF24
+tristate "nRF24L01+ 2.4GHz radio module support"
+depends on SPI
+help
+ This enables support for Nordic Semiconductor nRF24L01+ radio module,
+ with the following features:
+- multiple radio module instances via nrfX
+- dedicated /dev/nrfX.Y device per pipe per instance
+- dynamic and static payload lengths
+- configuration via sysfs (/sys/class/nrfX)
+- poll mechanism
+- 64kB RX FIFO per pipe
+- 64kB TX FIFO
+
+ To compile this driver as a module, choose M here: the module will be
+ called nrf24.
diff --git a/drivers/staging/nrf24/Makefile b/drivers/staging/nrf24/Makefile
new file mode 100644
index ..f5222567c632
--- /dev/null
+++ b/drivers/staging/nrf24/Makefile
@@ -0,0 +1,3 @@
+obj-$(CONFIG_NRF24) += nrf24.o
+
+nrf24-objs := nrf24_if.o nrf24_hal.o nrf24_sysfs.o
diff --git a/drivers/staging/nrf24/TODO b/drivers/staging/nrf24/TODO
new file mode 100644
index ..a089e43faac5
--- /dev/null
+++ b/drivers/staging/nrf24/TODO
@@ -0,0 +1,7 @@
+Todo:
+- opening and closing pipes via sysfs
+- improve switching in between RX and TX
+- improve handling of MAX_RT interrupt
+- find and fix bugs
+- code cleanup
+
diff --git a/drivers/staging/nrf24/devicetree/nrf24-spi0-overlay.dts
b/drivers/staging/nrf24/devicetree/nrf24-spi0-overlay.dts
new file mode 100644
index ..130e6787b76d
--- /dev/null
+++ b/drivers/staging/nrf24/devicetree/nrf24-spi0-overlay.dts
@@ -0,0 +1,54 @@
+// SPDX-License-Identifier: GPL-2.0
+
+//
+// Copyright (C) 2017 Marcin Ciupak
+//
+
+// Definitions for NRF24
+/dts-v1/;
+/plugin/;
+
+/ {
+ compatible = "bcm,bcm2835", "bcm,bcm2708", "bcm,bcm2709";
+
+ fragment@0 {
+ target = <&spi0>;
+ __overlay__ {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+
+ spidev@0 {
+ status = "disabled";
+ };
+
+ nrf0: nrf0@0 {
+
[PATCH] staging: iio: adc: Add comments to prevent checks corrections
This patch adds 3 comments in 2 different files. These comments warn to don't correct the checks of type: "CHECK: spaces preferred around that '-'" Signed-off-by: Gabriel Capella --- drivers/staging/iio/adc/ad7192.c | 1 + drivers/staging/iio/adc/ad7280a.c | 2 ++ 2 files changed, 3 insertions(+) diff --git a/drivers/staging/iio/adc/ad7192.c b/drivers/staging/iio/adc/ad7192.c index acdbc07fd259..786ace19c240 100644 --- a/drivers/staging/iio/adc/ad7192.c +++ b/drivers/staging/iio/adc/ad7192.c @@ -354,6 +354,7 @@ ad7192_show_scale_available(struct device *dev, return len; } +/* Do not put spaces around the hyphen. #checkpatch.pl */ static IIO_DEVICE_ATTR_NAMED(in_v_m_v_scale_available, in_voltage-voltage_scale_available, 0444, ad7192_show_scale_available, NULL, 0); diff --git a/drivers/staging/iio/adc/ad7280a.c b/drivers/staging/iio/adc/ad7280a.c index 58420dcb406d..4927116a046c 100644 --- a/drivers/staging/iio/adc/ad7280a.c +++ b/drivers/staging/iio/adc/ad7280a.c @@ -749,6 +749,7 @@ static irqreturn_t ad7280_event_handler(int irq, void *private) return IRQ_HANDLED; } +/* Do not put spaces around the hyphen. #checkpatch.pl */ static IIO_DEVICE_ATTR_NAMED(in_thresh_low_value, in_voltage-voltage_thresh_low_value, 0644, @@ -756,6 +757,7 @@ static IIO_DEVICE_ATTR_NAMED(in_thresh_low_value, ad7280_write_channel_config, AD7280A_CELL_UNDERVOLTAGE); +/* Do not put spaces around the hyphen. #checkpatch.pl */ static IIO_DEVICE_ATTR_NAMED(in_thresh_high_value, in_voltage-voltage_thresh_high_value, 0644, -- ___ devel mailing list de...@linuxdriverproject.org http://driverdev.linuxdriverproject.org/mailman/listinfo/driverdev-devel
[PATCH] drivers: staging: rtl*: fix spelling mistake "Orginial" -> "Original"
From: Colin Ian King
Trivial fix to common spelling mistakes in some rtl* drivers
Signed-off-by: Colin Ian King
---
drivers/staging/rtl8188eu/hal/odm.c | 8
drivers/staging/rtl8723bs/hal/odm_EdcaTurboCheck.c | 8
drivers/staging/rtlwifi/phydm/phydm_edcaturbocheck.c | 8
3 files changed, 12 insertions(+), 12 deletions(-)
diff --git a/drivers/staging/rtl8188eu/hal/odm.c
b/drivers/staging/rtl8188eu/hal/odm.c
index 5a0c38ecb15e..9c8fa61c92ac 100644
--- a/drivers/staging/rtl8188eu/hal/odm.c
+++ b/drivers/staging/rtl8188eu/hal/odm.c
@@ -1025,10 +1025,10 @@ void ODM_EdcaTurboInit(struct odm_dm_struct *pDM_Odm)
pDM_Odm->DM_EDCA_Table.bIsCurRDLState = false;
Adapter->recvpriv.bIsAnyNonBEPkts = false;
- ODM_RT_TRACE(pDM_Odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("Orginial VO
PARAM: 0x%x\n", usb_read32(Adapter, ODM_EDCA_VO_PARAM)));
- ODM_RT_TRACE(pDM_Odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("Orginial VI
PARAM: 0x%x\n", usb_read32(Adapter, ODM_EDCA_VI_PARAM)));
- ODM_RT_TRACE(pDM_Odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("Orginial BE
PARAM: 0x%x\n", usb_read32(Adapter, ODM_EDCA_BE_PARAM)));
- ODM_RT_TRACE(pDM_Odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("Orginial BK
PARAM: 0x%x\n", usb_read32(Adapter, ODM_EDCA_BK_PARAM)));
+ ODM_RT_TRACE(pDM_Odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("Original VO
PARAM: 0x%x\n", usb_read32(Adapter, ODM_EDCA_VO_PARAM)));
+ ODM_RT_TRACE(pDM_Odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("Original VI
PARAM: 0x%x\n", usb_read32(Adapter, ODM_EDCA_VI_PARAM)));
+ ODM_RT_TRACE(pDM_Odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("Original BE
PARAM: 0x%x\n", usb_read32(Adapter, ODM_EDCA_BE_PARAM)));
+ ODM_RT_TRACE(pDM_Odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("Original BK
PARAM: 0x%x\n", usb_read32(Adapter, ODM_EDCA_BK_PARAM)));
} /* ODM_InitEdcaTurbo */
void odm_EdcaTurboCheck(struct odm_dm_struct *pDM_Odm)
diff --git a/drivers/staging/rtl8723bs/hal/odm_EdcaTurboCheck.c
b/drivers/staging/rtl8723bs/hal/odm_EdcaTurboCheck.c
index 0e674f39ef03..b7ebce7a6ff9 100644
--- a/drivers/staging/rtl8723bs/hal/odm_EdcaTurboCheck.c
+++ b/drivers/staging/rtl8723bs/hal/odm_EdcaTurboCheck.c
@@ -39,16 +39,16 @@ void ODM_EdcaTurboInit(void *pDM_VOID)
Adapter->recvpriv.bIsAnyNonBEPkts = false;
ODM_RT_TRACE(pDM_Odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD,
-("Orginial VO PARAM: 0x%x\n",
+("Original VO PARAM: 0x%x\n",
rtw_read32(pDM_Odm->Adapter, ODM_EDCA_VO_PARAM)));
ODM_RT_TRACE(pDM_Odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD,
-("Orginial VI PARAM: 0x%x\n",
+("Original VI PARAM: 0x%x\n",
rtw_read32(pDM_Odm->Adapter, ODM_EDCA_VI_PARAM)));
ODM_RT_TRACE(pDM_Odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD,
-("Orginial BE PARAM: 0x%x\n",
+("Original BE PARAM: 0x%x\n",
rtw_read32(pDM_Odm->Adapter, ODM_EDCA_BE_PARAM)));
ODM_RT_TRACE(pDM_Odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD,
-("Orginial BK PARAM: 0x%x\n",
+("Original BK PARAM: 0x%x\n",
rtw_read32(pDM_Odm->Adapter, ODM_EDCA_BK_PARAM)));
} /* ODM_InitEdcaTurbo */
diff --git a/drivers/staging/rtlwifi/phydm/phydm_edcaturbocheck.c
b/drivers/staging/rtlwifi/phydm/phydm_edcaturbocheck.c
index cd12512628c0..b5bd4fb20c90 100644
--- a/drivers/staging/rtlwifi/phydm/phydm_edcaturbocheck.c
+++ b/drivers/staging/rtlwifi/phydm/phydm_edcaturbocheck.c
@@ -25,13 +25,13 @@ void odm_edca_turbo_init(void *dm_void)
dm->dm_edca_table.is_current_turbo_edca = false;
dm->dm_edca_table.is_cur_rdl_state = false;
- ODM_RT_TRACE(dm, ODM_COMP_EDCA_TURBO, "Orginial VO PARAM: 0x%x\n",
+ ODM_RT_TRACE(dm, ODM_COMP_EDCA_TURBO, "Original VO PARAM: 0x%x\n",
odm_read_4byte(dm, ODM_EDCA_VO_PARAM));
- ODM_RT_TRACE(dm, ODM_COMP_EDCA_TURBO, "Orginial VI PARAM: 0x%x\n",
+ ODM_RT_TRACE(dm, ODM_COMP_EDCA_TURBO, "Original VI PARAM: 0x%x\n",
odm_read_4byte(dm, ODM_EDCA_VI_PARAM));
- ODM_RT_TRACE(dm, ODM_COMP_EDCA_TURBO, "Orginial BE PARAM: 0x%x\n",
+ ODM_RT_TRACE(dm, ODM_COMP_EDCA_TURBO, "Original BE PARAM: 0x%x\n",
odm_read_4byte(dm, ODM_EDCA_BE_PARAM));
- ODM_RT_TRACE(dm, ODM_COMP_EDCA_TURBO, "Orginial BK PARAM: 0x%x\n",
+ ODM_RT_TRACE(dm, ODM_COMP_EDCA_TURBO, "Original BK PARAM: 0x%x\n",
odm_read_4byte(dm, ODM_EDCA_BK_PARAM));
} /* ODM_InitEdcaTurbo */
--
2.19.1
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Re: [PATCH net-next,v3] hv_netvsc: fix vf serial matching with pci slot info
From: Haiyang Zhang
Date: Mon, 15 Oct 2018 19:06:15 +
> From: Haiyang Zhang
>
> The VF device's serial number is saved as a string in PCI slot's
> kobj name, not the slot->number. This patch corrects the netvsc
> driver, so the VF device can be successfully paired with synthetic
> NIC.
>
> Fixes: 00d7ddba1143 ("hv_netvsc: pair VF based on serial number")
> Reported-by: Vitaly Kuznetsov
> Signed-off-by: Haiyang Zhang
Applied.
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