Re: [PATCH v3 09/15] media: sunxi: Add support for the A31 MIPI CSI-2 controller
Hi, On Mon 14 Dec 20, 12:39, Maxime Ripard wrote: > On Fri, Dec 11, 2020 at 04:57:02PM +0100, Paul Kocialkowski wrote: > > +#define sun6i_mipi_csi2_subdev_video(subdev) \ > > + container_of(subdev, struct sun6i_mipi_csi2_video, subdev) > > + > > +#define sun6i_mipi_csi2_video_dev(video) \ > > + container_of(video, struct sun6i_mipi_csi2_dev, video) > > Isn't it a bit unsafe? > > The second subdev and video here is not the variable passed in the macro > but the field in the structure, so any attempt at using those two macros > with anything but a variable named subdev or video will result in a > compilation issue? Yep you're totally right. Will fix in the next revision! Cheers, Paul -- Paul Kocialkowski, Bootlin Embedded Linux and kernel engineering https://bootlin.com signature.asc Description: PGP signature ___ devel mailing list de...@linuxdriverproject.org http://driverdev.linuxdriverproject.org/mailman/listinfo/driverdev-devel
[PATCH v4 00/15] Allwinner MIPI CSI-2 support for A31/V3s/A83T
This series introduces support for MIPI CSI-2, with the A31 controller that is found on most SoCs (A31, V3s and probably V5) as well as the A83T-specific controller. While the former uses the same MIPI D-PHY that is already supported for DSI, the latter embeds its own D-PHY. In order to distinguish the use of the D-PHY between Rx mode (for MIPI CSI-2) and Tx mode (for MIPI DSI), a submode is introduced for D-PHY in the PHY API. This allows adding Rx support in the A31 D-PHY driver. A few changes and fixes are applied to the A31 CSI controller driver, in order to support the MIPI CSI-2 use-case. Changes since v3: - Fixed single-item phys description in sun6i mipi csi-2 binding; - Fixed variables names in macros using container_of; - Fixed style issue with operators at the end of lines; - Reworked source endpoint/subdev assignment in sun6i-csi to handle link_validate error case; - Removed unrelated dt change in sun8i-a83t mipi csi-2 driver; - Added collected tags. Changes since v2: - added Kconfig depend on PM since it's not optional; - removed phy-names for A31 MIPI CSI-2 controller; - removed v3s compatible in the A31 MIPI CSI-2 controller driver; - removed A31 CSI controller single-port binding deprecation; - removed empty dt port definitions; - fixed minor checkpatch warnings; - added collected tags; - added media-ctl output in cover letter. Changes since v1: - reworked fwnode and media graph on the CSI controller end to have one port per interface, which solves the bus type representation issue; - removed unused IRQ handlers in the MIPI CSI-2 bridges; - avoided the use of devm_regmap_init_mmio_clk; - deasserted reset before enabling clocks; - fixed reported return code issues (ret |=, missing checks); - applied requested cosmetic changes (backward goto, etc); - switched over to runtime PM for the mipi csi-2 bridge drivers; - selected PHY_SUN6I_MIPI_DPHY in Kconfig for sun6i-mipi-csi2; - registered nodes with mipi csi-2 bridge subdevs; - used V4L2 format info instead of switch/case for sun6i-csi bpp; - fixed device-tree bindings as requested (useless properties, license); - fixed mipi bridge dt instances names; - added PHY API documentation about mode/power on order requirement; - fixed clock error return code in d-phy code; - fixed D-PHY mode check in d-phy code; - added MAINTAINERS entries for the new drivers; - added V4L2 compliance results; - added various comments and rework commit mesages as requested. Media ctl outputs for the testing setups are available below: # sun6i-csi + sun6i-mipi-csi2 + ov5648 Media device information driver sun6i-csi model Allwinner Video Capture Device serial bus infoplatform:1cb.camera hw revision 0x0 driver version 5.10.0 Device topology - entity 1: sun6i-csi (2 pads, 1 link) type Node subtype V4L flags 0 device node name /dev/video0 pad0: Sink pad1: Sink <- "sun6i-mipi-csi2":1 [ENABLED] - entity 6: sun6i-mipi-csi2 (2 pads, 2 links) type V4L2 subdev subtype Unknown flags 0 device node name /dev/v4l-subdev0 pad0: Sink [fmt:unknown/0x0] <- "ov5648 0-0036":0 [ENABLED,IMMUTABLE] pad1: Source [fmt:unknown/0x0] -> "sun6i-csi":1 [ENABLED] - entity 9: ov5648 0-0036 (1 pad, 1 link) type V4L2 subdev subtype Sensor flags 0 device node name /dev/v4l-subdev1 pad0: Source [fmt:SBGGR8_1X8/2592x1944@1/15 field:none colorspace:raw xfer:none ycbcr:601 quantization:full-range] -> "sun6i-mipi-csi2":0 [ENABLED,IMMUTABLE] # sun6i-csi + sun8i-a83t-mipi-csi2 + ov8865 Media device information driver sun6i-csi model Allwinner Video Capture Device serial bus infoplatform:1cb.camera hw revision 0x0 driver version 5.10.0 Device topology - entity 1: sun6i-csi (2 pads, 1 link) type Node subtype V4L flags 0 device node name /dev/video0 pad0: Sink pad1: Sink <- "sun8i-a83t-mipi-csi2":1 [ENABLED] - entity 6: sun8i-a83t-mipi-csi2 (2 pads, 2 links) type V4L2 subdev subtype Unknown flags 0 device node name /dev/v4l-subdev0 pad0: Sink [fmt:unknown/0x0] <- "ov8865 1-0036":0 [ENABLED,IMMUTABLE] pad1: Source [fmt:unknown/0x0] -> "sun6i-csi":1 [ENABLED] - entity 9: ov8865 1-0036 (1 pad, 1 link) type V4L2 subdev subtype Sensor flags 0 device node name /dev/v4l-subdev1 pad0: Source [fmt:SBGGR10_1X10/3264x2448@1/30 field:none colorspace:raw xfer:none ycbcr:601 quantization:full-range] -> "sun8i-a83t-mipi-csi2":0 [ENABLED,IMMUTABLE] V4L2 compliance runs are available below: # sun6i-csi + sun6i-mipi-csi2 + ov5648
[PATCH v4 02/15] phy: Distinguish between Rx and Tx for MIPI D-PHY with submodes
As some D-PHY controllers support both Rx and Tx mode, we need a way for users to explicitly request one or the other. For instance, Rx mode can be used along with MIPI CSI-2 while Tx mode can be used with MIPI DSI. Introduce new MIPI D-PHY PHY submodes to use with PHY_MODE_MIPI_DPHY. The default (zero value) is kept to Tx so only the rkisp1 driver, which uses D-PHY in Rx mode, needs to be adapted. Signed-off-by: Paul Kocialkowski Acked-by: Helen Koike --- drivers/staging/media/rkisp1/rkisp1-isp.c | 3 ++- include/linux/phy/phy-mipi-dphy.h | 13 + 2 files changed, 15 insertions(+), 1 deletion(-) diff --git a/drivers/staging/media/rkisp1/rkisp1-isp.c b/drivers/staging/media/rkisp1/rkisp1-isp.c index a9715b0b7264..f1167995688a 100644 --- a/drivers/staging/media/rkisp1/rkisp1-isp.c +++ b/drivers/staging/media/rkisp1/rkisp1-isp.c @@ -914,7 +914,8 @@ static int rkisp1_mipi_csi2_start(struct rkisp1_isp *isp, phy_mipi_dphy_get_default_config(pixel_clock, isp->sink_fmt->bus_width, sensor->lanes, cfg); - phy_set_mode(sensor->dphy, PHY_MODE_MIPI_DPHY); + phy_set_mode_ext(cdev->dphy, PHY_MODE_MIPI_DPHY, +PHY_MIPI_DPHY_SUBMODE_RX); phy_configure(sensor->dphy, &opts); phy_power_on(sensor->dphy); diff --git a/include/linux/phy/phy-mipi-dphy.h b/include/linux/phy/phy-mipi-dphy.h index a877ffee845d..0f57ef46a8b5 100644 --- a/include/linux/phy/phy-mipi-dphy.h +++ b/include/linux/phy/phy-mipi-dphy.h @@ -6,6 +6,19 @@ #ifndef __PHY_MIPI_DPHY_H_ #define __PHY_MIPI_DPHY_H_ +/** + * enum phy_mipi_dphy_submode - MIPI D-PHY sub-mode + * + * A MIPI D-PHY can be used to transmit or receive data. + * Since some controllers can support both, the direction to enable is specified + * with the PHY sub-mode. Transmit is assumed by default with phy_set_mode. + */ + +enum phy_mipi_dphy_submode { + PHY_MIPI_DPHY_SUBMODE_TX = 0, + PHY_MIPI_DPHY_SUBMODE_RX, +}; + /** * struct phy_configure_opts_mipi_dphy - MIPI D-PHY configuration set * -- 2.29.2 ___ devel mailing list de...@linuxdriverproject.org http://driverdev.linuxdriverproject.org/mailman/listinfo/driverdev-devel
[PATCH v4 01/15] docs: phy: Add a part about PHY mode and submode
Besides giving pointers to the relevant functions for PHY mode and submode configuration, this clarifies the need to set them before powering on the PHY. Signed-off-by: Paul Kocialkowski Reviewed-by: Maxime Ripard --- Documentation/driver-api/phy/phy.rst | 18 ++ 1 file changed, 18 insertions(+) diff --git a/Documentation/driver-api/phy/phy.rst b/Documentation/driver-api/phy/phy.rst index 8fc1ce0bb905..6cbc72707a49 100644 --- a/Documentation/driver-api/phy/phy.rst +++ b/Documentation/driver-api/phy/phy.rst @@ -195,3 +195,21 @@ DeviceTree Binding The documentation for PHY dt binding can be found @ Documentation/devicetree/bindings/phy/phy-bindings.txt + +PHY Mode and Submode + + +Once a reference to a PHY is obtained by a controller, the PHY can be configured +to a PHY mode and submode. PHY modes are described in the `phy_mode` enum while +submodes are specific to the selected PHY mode. + +Mode and submode configuration is done by calling:: + + int phy_set_mode_ext(struct phy *phy, enum phy_mode mode, int submode); + +If no submode is to be configured, users can call:: + + int phy_set_mode(struct phy *phy, enum phy_mode mode); + +The PHY mode and submode must not be configured after the PHY has already been +powered on. -- 2.29.2 ___ devel mailing list de...@linuxdriverproject.org http://driverdev.linuxdriverproject.org/mailman/listinfo/driverdev-devel
[PATCH v4 04/15] media: sun6i-csi: Use common V4L2 format info for storage bpp
V4L2 has a common helper which can be used for calculating the number of stored bits per pixels of a given (stored) image format. Use the helper-returned structure instead of our own switch/case list. Note that a few formats are not in that list so we keep them as special cases. The custom switch/case was also wrong concerning 10/12-bit Bayer formats, which are aligned to 16 bits in memory. Using the common helper fixes it. Fixes: 5cc7522d8965 ("media: sun6i: Add support for Allwinner CSI V3s") Signed-off-by: Paul Kocialkowski Acked-by: Maxime Ripard --- .../platform/sunxi/sun6i-csi/sun6i_csi.h | 55 +++ 1 file changed, 20 insertions(+), 35 deletions(-) diff --git a/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi.h b/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi.h index c626821aaedb..092445f04c60 100644 --- a/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi.h +++ b/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi.h @@ -86,53 +86,38 @@ void sun6i_csi_update_buf_addr(struct sun6i_csi *csi, dma_addr_t addr); */ void sun6i_csi_set_stream(struct sun6i_csi *csi, bool enable); -/* get bpp form v4l2 pixformat */ +/* get memory storage bpp from v4l2 pixformat */ static inline int sun6i_csi_get_bpp(unsigned int pixformat) { + const struct v4l2_format_info *info; + unsigned int i; + int bpp = 0; + + /* Handle special cases unknown to V4L2 format info first. */ switch (pixformat) { - case V4L2_PIX_FMT_SBGGR8: - case V4L2_PIX_FMT_SGBRG8: - case V4L2_PIX_FMT_SGRBG8: - case V4L2_PIX_FMT_SRGGB8: case V4L2_PIX_FMT_JPEG: return 8; - case V4L2_PIX_FMT_SBGGR10: - case V4L2_PIX_FMT_SGBRG10: - case V4L2_PIX_FMT_SGRBG10: - case V4L2_PIX_FMT_SRGGB10: - return 10; - case V4L2_PIX_FMT_SBGGR12: - case V4L2_PIX_FMT_SGBRG12: - case V4L2_PIX_FMT_SGRBG12: - case V4L2_PIX_FMT_SRGGB12: case V4L2_PIX_FMT_HM12: - case V4L2_PIX_FMT_NV12: - case V4L2_PIX_FMT_NV21: - case V4L2_PIX_FMT_YUV420: - case V4L2_PIX_FMT_YVU420: return 12; - case V4L2_PIX_FMT_YUYV: - case V4L2_PIX_FMT_YVYU: - case V4L2_PIX_FMT_UYVY: - case V4L2_PIX_FMT_VYUY: - case V4L2_PIX_FMT_NV16: - case V4L2_PIX_FMT_NV61: - case V4L2_PIX_FMT_YUV422P: - case V4L2_PIX_FMT_RGB565: case V4L2_PIX_FMT_RGB565X: return 16; - case V4L2_PIX_FMT_RGB24: - case V4L2_PIX_FMT_BGR24: - return 24; - case V4L2_PIX_FMT_RGB32: - case V4L2_PIX_FMT_BGR32: - return 32; - default: + } + + info = v4l2_format_info(pixformat); + if (!info) { WARN(1, "Unsupported pixformat: 0x%x\n", pixformat); - break; + return 0; + } + + for (i = 0; i < info->comp_planes; i++) { + unsigned int hdiv = (i == 0) ? 1 : info->hdiv; + unsigned int vdiv = (i == 0) ? 1 : info->vdiv; + + /* We return bits per pixel while V4L2 format info is bytes. */ + bpp += 8 * info->bpp[i] / hdiv / vdiv; } - return 0; + return bpp; } #endif /* __SUN6I_CSI_H__ */ -- 2.29.2 ___ devel mailing list de...@linuxdriverproject.org http://driverdev.linuxdriverproject.org/mailman/listinfo/driverdev-devel
[PATCH v4 08/15] dt-bindings: media: Add A31 MIPI CSI-2 bindings documentation
This introduces YAML bindings documentation for the A31 MIPI CSI-2 controller. Signed-off-by: Paul Kocialkowski --- .../media/allwinner,sun6i-a31-mipi-csi2.yaml | 149 ++ 1 file changed, 149 insertions(+) create mode 100644 Documentation/devicetree/bindings/media/allwinner,sun6i-a31-mipi-csi2.yaml diff --git a/Documentation/devicetree/bindings/media/allwinner,sun6i-a31-mipi-csi2.yaml b/Documentation/devicetree/bindings/media/allwinner,sun6i-a31-mipi-csi2.yaml new file mode 100644 index ..bb05105c45b7 --- /dev/null +++ b/Documentation/devicetree/bindings/media/allwinner,sun6i-a31-mipi-csi2.yaml @@ -0,0 +1,149 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/allwinner,sun6i-a31-mipi-csi2.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Allwinner A31 MIPI CSI-2 Device Tree Bindings + +maintainers: + - Paul Kocialkowski + +properties: + compatible: +oneOf: + - const: allwinner,sun6i-a31-mipi-csi2 + - items: + - const: allwinner,sun8i-v3s-mipi-csi2 + - const: allwinner,sun6i-a31-mipi-csi2 + + reg: +maxItems: 1 + + interrupts: +maxItems: 1 + + clocks: +items: + - description: Bus Clock + - description: Module Clock + + clock-names: +items: + - const: bus + - const: mod + + phys: +maxItems: 1 +description: MIPI D-PHY + + resets: +maxItems: 1 + + # See ./video-interfaces.txt for details + ports: +type: object + +properties: + port@0: +type: object +description: Input port, connect to a MIPI CSI-2 sensor + +properties: + reg: +const: 0 + + endpoint: +type: object + +properties: + remote-endpoint: true + + data-lanes: +minItems: 1 +maxItems: 4 + +required: + - data-lanes + - remote-endpoint + +required: + - endpoint + +additionalProperties: false + + port@1: +type: object +description: Output port, connect to a CSI controller + +properties: + reg: +const: 1 + + endpoint: +type: object + +properties: + remote-endpoint: true + +required: + - remote-endpoint + +required: + - endpoint + +additionalProperties: false + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - resets + +additionalProperties: false + +examples: + - | +#include +#include +#include + +mipi_csi2: csi@1cb1000 { +compatible = "allwinner,sun8i-v3s-mipi-csi2", + "allwinner,sun6i-a31-mipi-csi2"; +reg = <0x01cb1000 0x1000>; +interrupts = ; +clocks = <&ccu CLK_BUS_CSI>, + <&ccu CLK_CSI1_SCLK>; +clock-names = "bus", "mod"; +resets = <&ccu RST_BUS_CSI>; + +phys = <&dphy>; + +ports { +#address-cells = <1>; +#size-cells = <0>; + +mipi_csi2_in: port@0 { +reg = <0>; + +mipi_csi2_in_ov5648: endpoint { +data-lanes = <1 2 3 4>; + +remote-endpoint = <&ov5648_out_mipi_csi2>; +}; +}; + +mipi_csi2_out: port@1 { +reg = <1>; + +mipi_csi2_out_csi0: endpoint { +remote-endpoint = <&csi0_in_mipi_csi2>; +}; +}; +}; +}; + +... -- 2.29.2 ___ devel mailing list de...@linuxdriverproject.org http://driverdev.linuxdriverproject.org/mailman/listinfo/driverdev-devel
[PATCH v4 09/15] media: sunxi: Add support for the A31 MIPI CSI-2 controller
The A31 MIPI CSI-2 controller is a dedicated MIPI CSI-2 bridge found on Allwinner SoCs such as the A31 and V3/V3s. It is a standalone block, connected to the CSI controller on one side and to the MIPI D-PHY block on the other. It has a dedicated address space, interrupt line and clock. It is represented as a V4L2 subdev to the CSI controller and takes a MIPI CSI-2 sensor as its own subdev, all using the fwnode graph and media controller API. Only 8-bit and 10-bit Bayer formats are currently supported. While up to 4 internal channels to the CSI controller exist, only one is currently supported by this implementation. Signed-off-by: Paul Kocialkowski --- drivers/media/platform/sunxi/Kconfig | 1 + drivers/media/platform/sunxi/Makefile | 1 + .../platform/sunxi/sun6i-mipi-csi2/Kconfig| 12 + .../platform/sunxi/sun6i-mipi-csi2/Makefile | 4 + .../sunxi/sun6i-mipi-csi2/sun6i_mipi_csi2.c | 590 ++ .../sunxi/sun6i-mipi-csi2/sun6i_mipi_csi2.h | 117 6 files changed, 725 insertions(+) create mode 100644 drivers/media/platform/sunxi/sun6i-mipi-csi2/Kconfig create mode 100644 drivers/media/platform/sunxi/sun6i-mipi-csi2/Makefile create mode 100644 drivers/media/platform/sunxi/sun6i-mipi-csi2/sun6i_mipi_csi2.c create mode 100644 drivers/media/platform/sunxi/sun6i-mipi-csi2/sun6i_mipi_csi2.h diff --git a/drivers/media/platform/sunxi/Kconfig b/drivers/media/platform/sunxi/Kconfig index 7151cc249afa..9684e07454ad 100644 --- a/drivers/media/platform/sunxi/Kconfig +++ b/drivers/media/platform/sunxi/Kconfig @@ -2,3 +2,4 @@ source "drivers/media/platform/sunxi/sun4i-csi/Kconfig" source "drivers/media/platform/sunxi/sun6i-csi/Kconfig" +source "drivers/media/platform/sunxi/sun6i-mipi-csi2/Kconfig" diff --git a/drivers/media/platform/sunxi/Makefile b/drivers/media/platform/sunxi/Makefile index fc537c9f5ca9..887a7cae8fca 100644 --- a/drivers/media/platform/sunxi/Makefile +++ b/drivers/media/platform/sunxi/Makefile @@ -2,5 +2,6 @@ obj-y += sun4i-csi/ obj-y += sun6i-csi/ +obj-y += sun6i-mipi-csi2/ obj-y += sun8i-di/ obj-y += sun8i-rotate/ diff --git a/drivers/media/platform/sunxi/sun6i-mipi-csi2/Kconfig b/drivers/media/platform/sunxi/sun6i-mipi-csi2/Kconfig new file mode 100644 index ..47f1bb0779a8 --- /dev/null +++ b/drivers/media/platform/sunxi/sun6i-mipi-csi2/Kconfig @@ -0,0 +1,12 @@ +# SPDX-License-Identifier: GPL-2.0-only +config VIDEO_SUN6I_MIPI_CSI2 + tristate "Allwinner A31 MIPI CSI-2 Controller Driver" + depends on ARCH_SUNXI || COMPILE_TEST + depends on PM && COMMON_CLK && VIDEO_V4L2 + select REGMAP_MMIO + select PHY_SUN6I_MIPI_DPHY + select MEDIA_CONTROLLER + select VIDEO_V4L2_SUBDEV_API + select V4L2_FWNODE + help + Support for the Allwinner A31 MIPI CSI-2 Controller. diff --git a/drivers/media/platform/sunxi/sun6i-mipi-csi2/Makefile b/drivers/media/platform/sunxi/sun6i-mipi-csi2/Makefile new file mode 100644 index ..14e4e03818b5 --- /dev/null +++ b/drivers/media/platform/sunxi/sun6i-mipi-csi2/Makefile @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0-only +sun6i-mipi-csi2-y += sun6i_mipi_csi2.o + +obj-$(CONFIG_VIDEO_SUN6I_MIPI_CSI2) += sun6i-mipi-csi2.o diff --git a/drivers/media/platform/sunxi/sun6i-mipi-csi2/sun6i_mipi_csi2.c b/drivers/media/platform/sunxi/sun6i-mipi-csi2/sun6i_mipi_csi2.c new file mode 100644 index ..87307beda4cf --- /dev/null +++ b/drivers/media/platform/sunxi/sun6i-mipi-csi2/sun6i_mipi_csi2.c @@ -0,0 +1,590 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2020 Bootlin + * Author: Paul Kocialkowski + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "sun6i_mipi_csi2.h" + +#define MODULE_NAME"sun6i-mipi-csi2" + +static const u32 sun6i_mipi_csi2_mbus_codes[] = { + MEDIA_BUS_FMT_SBGGR8_1X8, + MEDIA_BUS_FMT_SGBRG8_1X8, + MEDIA_BUS_FMT_SGRBG8_1X8, + MEDIA_BUS_FMT_SRGGB8_1X8, + MEDIA_BUS_FMT_SBGGR10_1X10, + MEDIA_BUS_FMT_SGBRG10_1X10, + MEDIA_BUS_FMT_SGRBG10_1X10, + MEDIA_BUS_FMT_SRGGB10_1X10, +}; + +/* Video */ + +static int sun6i_mipi_csi2_s_stream(struct v4l2_subdev *subdev, int on) +{ + struct sun6i_mipi_csi2_video *video = + sun6i_mipi_csi2_subdev_video(subdev); + struct sun6i_mipi_csi2_dev *cdev = sun6i_mipi_csi2_video_dev(video); + struct v4l2_subdev *remote_subdev = video->remote_subdev; + struct v4l2_fwnode_bus_mipi_csi2 *bus_mipi_csi2 = + &video->endpoint.bus.mipi_csi2; + union phy_configure_opts dphy_opts = { 0 }; + struct phy_configure_opts_mipi_dphy *dphy_cfg = &dphy_opts.mipi_dphy; + struct regmap *regmap = cdev->regmap; + struct v4l2_ctrl *ctrl; + unsigned int lanes_count; + unsigned int bpp; + unsigne
[PATCH v4 07/15] media: sun6i-csi: Add support for MIPI CSI-2 bridge input
The A31 CSI controller supports a MIPI CSI-2 bridge input, which has its own dedicated port in the fwnode graph. Support for this input is added with this change: - two pads are defined for the media entity instead of one and only one needs to be connected at a time; - the pads currently match the fwnode graph representation; - links are created between our pads and the subdevs for each interface and are no longer immutable so that userspace can select which interface to use in case both are bound to a subdev; - fwnode endpoints are parsed and stored for each interface; - the active subdev (and fwnode endpoint) is retrieved when validating the media link at stream on time and cleared at stream off; - an error is raised if both links are active at the same time; - the MIPI interface bit is set if the MIPI CSI-2 bridge endpoint is active. In the future, the media entity representation might evolve to: - distinguish the internal parallel bridge and data formatter; - represent each of the 4 internal channels that can exist between the parallel bridge (for BT656 time-multiplex) and MIPI CSI-2 (internal channels can be mapped to virtual channels); - connect the controller's output to the ISP instead of its DMA engine. Finally note that the MIPI CSI-2 bridges should not be linked in the fwnode graph unless they have a sensor subdev attached. Signed-off-by: Paul Kocialkowski --- .../platform/sunxi/sun6i-csi/sun6i_csi.c | 123 ++ .../platform/sunxi/sun6i-csi/sun6i_csi.h | 9 +- .../platform/sunxi/sun6i-csi/sun6i_video.c| 57 .../platform/sunxi/sun6i-csi/sun6i_video.h| 7 +- 4 files changed, 142 insertions(+), 54 deletions(-) diff --git a/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi.c b/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi.c index f1150de94e98..dcf465d73579 100644 --- a/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi.c +++ b/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi.c @@ -49,6 +49,7 @@ static inline struct sun6i_csi_dev *sun6i_csi_to_dev(struct sun6i_csi *csi) /* TODO add 10&12 bit YUV, RGB support */ bool sun6i_csi_is_format_supported(struct sun6i_csi *csi, + struct v4l2_fwnode_endpoint *endpoint, u32 pixformat, u32 mbus_code) { struct sun6i_csi_dev *sdev = sun6i_csi_to_dev(csi); @@ -58,9 +59,9 @@ bool sun6i_csi_is_format_supported(struct sun6i_csi *csi, * 8bit and 16bit bus width. * Identify the media bus format from device tree. */ - if ((sdev->csi.v4l2_ep.bus_type == V4L2_MBUS_PARALLEL -|| sdev->csi.v4l2_ep.bus_type == V4L2_MBUS_BT656) -&& sdev->csi.v4l2_ep.bus.parallel.bus_width == 16) { + if ((endpoint->bus_type == V4L2_MBUS_PARALLEL || +endpoint->bus_type == V4L2_MBUS_BT656) && + endpoint->bus.parallel.bus_width == 16) { switch (pixformat) { case V4L2_PIX_FMT_HM12: case V4L2_PIX_FMT_NV12: @@ -373,7 +374,7 @@ static enum csi_input_seq get_csi_input_seq(struct sun6i_csi_dev *sdev, static void sun6i_csi_setup_bus(struct sun6i_csi_dev *sdev) { - struct v4l2_fwnode_endpoint *endpoint = &sdev->csi.v4l2_ep; + struct v4l2_fwnode_endpoint *endpoint = sdev->csi.video.source_endpoint; struct sun6i_csi *csi = &sdev->csi; unsigned char bus_width; u32 flags; @@ -459,6 +460,9 @@ static void sun6i_csi_setup_bus(struct sun6i_csi_dev *sdev) if (flags & V4L2_MBUS_PCLK_SAMPLE_FALLING) cfg |= CSI_IF_CFG_CLK_POL_FALLING_EDGE; break; + case V4L2_MBUS_CSI2_DPHY: + cfg |= CSI_IF_CFG_MIPI_IF_MIPI; + break; default: dev_warn(sdev->dev, "Unsupported bus type: %d\n", endpoint->bus_type); @@ -636,11 +640,11 @@ void sun6i_csi_set_stream(struct sun6i_csi *csi, bool enable) * Media Controller and V4L2 */ static int sun6i_csi_link_entity(struct sun6i_csi *csi, +struct media_pad *sink_pad, struct media_entity *entity, -struct fwnode_handle *fwnode) +struct fwnode_handle *fwnode, bool enabled) { struct media_entity *sink; - struct media_pad *sink_pad; int src_pad_index; int ret; @@ -654,14 +658,12 @@ static int sun6i_csi_link_entity(struct sun6i_csi *csi, src_pad_index = ret; sink = &csi->video.vdev.entity; - sink_pad = &csi->video.pad; dev_dbg(csi->dev, "creating %s:%u -> %s:%u link\n", entity->name, src_pad_index, sink->name, sink_pad->index); ret = media_create_pad_link(entity, src_pad_index, sink, sink_pad->index, - MEDIA_LNK_FL_ENABLED | -
[PATCH v4 03/15] phy: allwinner: phy-sun6i-mipi-dphy: Support D-PHY Rx mode for MIPI CSI-2
The Allwinner A31 D-PHY supports both Rx and Tx modes. While the latter is already supported and used for MIPI DSI this adds support for the former, to be used with MIPI CSI-2. This implementation is inspired by Allwinner's V3s Linux SDK implementation, which was used as a documentation base. Signed-off-by: Paul Kocialkowski Acked-by: Maxime Ripard --- drivers/phy/allwinner/phy-sun6i-mipi-dphy.c | 164 +++- 1 file changed, 160 insertions(+), 4 deletions(-) diff --git a/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c b/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c index 1fa761ba6cbb..0389b6b670d6 100644 --- a/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c +++ b/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c @@ -24,6 +24,14 @@ #define SUN6I_DPHY_TX_CTL_REG 0x04 #define SUN6I_DPHY_TX_CTL_HS_TX_CLK_CONT BIT(28) +#define SUN6I_DPHY_RX_CTL_REG 0x08 +#define SUN6I_DPHY_RX_CTL_EN_DBC BIT(31) +#define SUN6I_DPHY_RX_CTL_RX_CLK_FORCE BIT(24) +#define SUN6I_DPHY_RX_CTL_RX_D3_FORCE BIT(23) +#define SUN6I_DPHY_RX_CTL_RX_D2_FORCE BIT(22) +#define SUN6I_DPHY_RX_CTL_RX_D1_FORCE BIT(21) +#define SUN6I_DPHY_RX_CTL_RX_D0_FORCE BIT(20) + #define SUN6I_DPHY_TX_TIME0_REG0x10 #define SUN6I_DPHY_TX_TIME0_HS_TRAIL(n)(((n) & 0xff) << 24) #define SUN6I_DPHY_TX_TIME0_HS_PREPARE(n) (((n) & 0xff) << 16) @@ -44,12 +52,29 @@ #define SUN6I_DPHY_TX_TIME4_HS_TX_ANA1(n) (((n) & 0xff) << 8) #define SUN6I_DPHY_TX_TIME4_HS_TX_ANA0(n) ((n) & 0xff) +#define SUN6I_DPHY_RX_TIME0_REG0x30 +#define SUN6I_DPHY_RX_TIME0_HS_RX_SYNC(n) (((n) & 0xff) << 24) +#define SUN6I_DPHY_RX_TIME0_HS_RX_CLK_MISS(n) (((n) & 0xff) << 16) +#define SUN6I_DPHY_RX_TIME0_LP_RX(n) (((n) & 0xff) << 8) + +#define SUN6I_DPHY_RX_TIME1_REG0x34 +#define SUN6I_DPHY_RX_TIME1_RX_DLY(n) (((n) & 0xfff) << 20) +#define SUN6I_DPHY_RX_TIME1_LP_RX_ULPS_WP(n) ((n) & 0xf) + +#define SUN6I_DPHY_RX_TIME2_REG0x38 +#define SUN6I_DPHY_RX_TIME2_HS_RX_ANA1(n) (((n) & 0xff) << 8) +#define SUN6I_DPHY_RX_TIME2_HS_RX_ANA0(n) ((n) & 0xff) + +#define SUN6I_DPHY_RX_TIME3_REG0x40 +#define SUN6I_DPHY_RX_TIME3_LPRST_DLY(n) (((n) & 0x) << 16) + #define SUN6I_DPHY_ANA0_REG0x4c #define SUN6I_DPHY_ANA0_REG_PWSBIT(31) #define SUN6I_DPHY_ANA0_REG_DMPC BIT(28) #define SUN6I_DPHY_ANA0_REG_DMPD(n)(((n) & 0xf) << 24) #define SUN6I_DPHY_ANA0_REG_SLV(n) (((n) & 7) << 12) #define SUN6I_DPHY_ANA0_REG_DEN(n) (((n) & 0xf) << 8) +#define SUN6I_DPHY_ANA0_REG_SFB(n) (((n) & 3) << 2) #define SUN6I_DPHY_ANA1_REG0x50 #define SUN6I_DPHY_ANA1_REG_VTTMODEBIT(31) @@ -92,6 +117,8 @@ struct sun6i_dphy { struct phy *phy; struct phy_configure_opts_mipi_dphy config; + + int submode; }; static int sun6i_dphy_init(struct phy *phy) @@ -105,6 +132,18 @@ static int sun6i_dphy_init(struct phy *phy) return 0; } +static int sun6i_dphy_set_mode(struct phy *phy, enum phy_mode mode, int submode) +{ + struct sun6i_dphy *dphy = phy_get_drvdata(phy); + + if (mode != PHY_MODE_MIPI_DPHY) + return -EINVAL; + + dphy->submode = submode; + + return 0; +} + static int sun6i_dphy_configure(struct phy *phy, union phy_configure_opts *opts) { struct sun6i_dphy *dphy = phy_get_drvdata(phy); @@ -119,9 +158,8 @@ static int sun6i_dphy_configure(struct phy *phy, union phy_configure_opts *opts) return 0; } -static int sun6i_dphy_power_on(struct phy *phy) +static int sun6i_dphy_tx_power_on(struct sun6i_dphy *dphy) { - struct sun6i_dphy *dphy = phy_get_drvdata(phy); u8 lanes_mask = GENMASK(dphy->config.lanes - 1, 0); regmap_write(dphy->regs, SUN6I_DPHY_TX_CTL_REG, @@ -211,12 +249,129 @@ static int sun6i_dphy_power_on(struct phy *phy) return 0; } +static int sun6i_dphy_rx_power_on(struct sun6i_dphy *dphy) +{ + /* Physical clock rate is actually half of symbol rate with DDR. */ + unsigned long mipi_symbol_rate = dphy->config.hs_clk_rate; + unsigned long dphy_clk_rate; + unsigned int rx_dly; + unsigned int lprst_dly; + u32 value; + + dphy_clk_rate = clk_get_rate(dphy->mod_clk); + if (!dphy_clk_rate) + return -EINVAL; + + /* Hardcoded timing parameters from the Allwinner BSP. */ + regmap_write(dphy->regs, SUN6I_DPHY_RX_TIME0_REG, +SUN6I_DPHY_RX_TIME0_HS_RX_SYNC(255) | +SUN6I_DPHY_RX_TIME0_HS_RX_CLK_MISS(255) | +SUN6I_DPHY_RX_TIME0_LP_RX(255)); + + /* +* Formula from the Allwinner BSP, with hardcoded coefficients +* (probably internal divider/multiplier). +*/ + rx_d
[PATCH v4 14/15] ARM: dts: sun8i: a83t: Add MIPI CSI-2 controller node
MIPI CSI-2 is supported on the A83T with a dedicated controller that covers both the protocol and D-PHY. It can be connected to the CSI interface as a V4L2 subdev through the fwnode graph. This is not done by default since connecting the bridge without a subdev attached to it will cause a failure on the CSI driver. Signed-off-by: Paul Kocialkowski --- arch/arm/boot/dts/sun8i-a83t.dtsi | 26 ++ 1 file changed, 26 insertions(+) diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi b/arch/arm/boot/dts/sun8i-a83t.dtsi index c010b27fdb6a..d6d55c12b995 100644 --- a/arch/arm/boot/dts/sun8i-a83t.dtsi +++ b/arch/arm/boot/dts/sun8i-a83t.dtsi @@ -1066,6 +1066,32 @@ csi_in: port { }; }; + mipi_csi2: csi@1cb1000 { + compatible = "allwinner,sun8i-a83t-mipi-csi2"; + reg = <0x01cb1000 0x1000>; + interrupts = ; + clocks = <&ccu CLK_BUS_CSI>, +<&ccu CLK_CSI_SCLK>, +<&ccu CLK_MIPI_CSI>, +<&ccu CLK_CSI_MISC>; + clock-names = "bus", "mod", "mipi", "misc"; + resets = <&ccu RST_BUS_CSI>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + mipi_csi2_in: port@0 { + reg = <0>; + }; + + mipi_csi2_out: port@1 { + reg = <1>; + }; + }; + }; + hdmi: hdmi@1ee { compatible = "allwinner,sun8i-a83t-dw-hdmi"; reg = <0x01ee 0x1>; -- 2.29.2 ___ devel mailing list de...@linuxdriverproject.org http://driverdev.linuxdriverproject.org/mailman/listinfo/driverdev-devel
[PATCH v4 06/15] dt-bindings: media: sun6i-a31-csi: Add MIPI CSI-2 input port
The A31 CSI controller supports two distinct input interfaces: parallel and an external MIPI CSI-2 bridge. The parallel interface is often connected to a set of hardware pins while the MIPI CSI-2 bridge is an internal FIFO-ish link. As a result, these two inputs are distinguished as two different ports. Note that only one of the two may be present on a controller instance. For example, the V3s has one controller dedicated to MIPI-CSI2 and one dedicated to parallel. Update the binding with an explicit ports node that holds two distinct port nodes: one for parallel input and one for MIPI CSI-2. This is backward-compatible with the single-port approach that was previously taken for representing the parallel interface port, which stays enumerated as fwnode port 0. Note that additional ports may be added in the future, especially to support feeding the CSI controller's output to the ISP. Signed-off-by: Paul Kocialkowski Reviewed-by: Rob Herring --- .../media/allwinner,sun6i-a31-csi.yaml| 88 --- 1 file changed, 75 insertions(+), 13 deletions(-) diff --git a/Documentation/devicetree/bindings/media/allwinner,sun6i-a31-csi.yaml b/Documentation/devicetree/bindings/media/allwinner,sun6i-a31-csi.yaml index 1fd9b5532a21..77ded77505e9 100644 --- a/Documentation/devicetree/bindings/media/allwinner,sun6i-a31-csi.yaml +++ b/Documentation/devicetree/bindings/media/allwinner,sun6i-a31-csi.yaml @@ -67,6 +67,62 @@ properties: additionalProperties: false + ports: +type: object + +properties: + port@0: +type: object +description: Parallel input port, connect to a parallel sensor + +properties: + reg: +const: 0 + + endpoint: +type: object + +properties: + remote-endpoint: true + + bus-width: +enum: [ 8, 10, 12, 16 ] + + pclk-sample: true + hsync-active: true + vsync-active: true + +required: + - bus-width + - remote-endpoint + +required: + - endpoint + +additionalProperties: false + + port@1: +type: object +description: MIPI CSI-2 bridge input port + +properties: + reg: +const: 1 + + endpoint: +type: object + +properties: + remote-endpoint: true + +required: + - remote-endpoint + +required: + - endpoint + +additionalProperties: false + required: - compatible - reg @@ -95,19 +151,25 @@ examples: "ram"; resets = <&ccu RST_BUS_CSI>; -port { -/* Parallel bus endpoint */ -csi1_ep: endpoint { -remote-endpoint = <&adv7611_ep>; -bus-width = <16>; - -/* - * If hsync-active/vsync-active are missing, - * embedded BT.656 sync is used. - */ - hsync-active = <0>; /* Active low */ - vsync-active = <0>; /* Active low */ - pclk-sample = <1>; /* Rising */ +ports { +#address-cells = <1>; +#size-cells = <0>; + +port@0 { +reg = <0>; +/* Parallel bus endpoint */ +csi1_ep: endpoint { +remote-endpoint = <&adv7611_ep>; +bus-width = <16>; + +/* + * If hsync-active/vsync-active are missing, + * embedded BT.656 sync is used. + */ + hsync-active = <0>; /* Active low */ + vsync-active = <0>; /* Active low */ + pclk-sample = <1>; /* Rising */ +}; }; }; }; -- 2.29.2 ___ devel mailing list de...@linuxdriverproject.org http://driverdev.linuxdriverproject.org/mailman/listinfo/driverdev-devel
[PATCH v4 10/15] ARM: dts: sun8i: v3s: Add nodes for MIPI CSI-2 support
MIPI CSI-2 is supported on the V3s with an A31-based MIPI CSI-2 bridge controller. The controller uses a separate D-PHY, which is the same that is otherwise used for MIPI DSI, but used in Rx mode. On the V3s, the CSI0 controller is dedicated to MIPI CSI-2 as it does not have access to any parallel interface pins. Add all the necessary nodes (CSI0, MIPI CSI-2 bridge and D-PHY) to support the MIPI CSI-2 interface. Note that a fwnode graph link is created between CSI0 and MIPI CSI-2 even when no sensor is connected. This will result in a probe failure for the controller as long as no sensor is connected but this is fine since no other interface is available. Signed-off-by: Paul Kocialkowski --- arch/arm/boot/dts/sun8i-v3s.dtsi | 67 1 file changed, 67 insertions(+) diff --git a/arch/arm/boot/dts/sun8i-v3s.dtsi b/arch/arm/boot/dts/sun8i-v3s.dtsi index 7b2d684aeb97..b7f2bcd25c86 100644 --- a/arch/arm/boot/dts/sun8i-v3s.dtsi +++ b/arch/arm/boot/dts/sun8i-v3s.dtsi @@ -530,6 +530,31 @@ spi0: spi@1c68000 { #size-cells = <0>; }; + csi0: camera@1cb { + compatible = "allwinner,sun8i-v3s-csi"; + reg = <0x01cb 0x1000>; + interrupts = ; + clocks = <&ccu CLK_BUS_CSI>, +<&ccu CLK_CSI1_SCLK>, +<&ccu CLK_DRAM_CSI>; + clock-names = "bus", "mod", "ram"; + resets = <&ccu RST_BUS_CSI>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + + csi0_in_mipi_csi2: endpoint { + remote-endpoint = <&mipi_csi2_out_csi0>; + }; + }; + }; + }; + csi1: camera@1cb4000 { compatible = "allwinner,sun8i-v3s-csi"; reg = <0x01cb4000 0x3000>; @@ -552,5 +577,47 @@ gic: interrupt-controller@1c81000 { #interrupt-cells = <3>; interrupts = ; }; + + mipi_csi2: csi@1cb1000 { + compatible = "allwinner,sun8i-v3s-mipi-csi2", +"allwinner,sun6i-a31-mipi-csi2"; + reg = <0x01cb1000 0x1000>; + interrupts = ; + clocks = <&ccu CLK_BUS_CSI>, +<&ccu CLK_CSI1_SCLK>; + clock-names = "bus", "mod"; + resets = <&ccu RST_BUS_CSI>; + status = "disabled"; + + phys = <&dphy>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + mipi_csi2_in: port@0 { + reg = <0>; + }; + + mipi_csi2_out: port@1 { + reg = <1>; + + mipi_csi2_out_csi0: endpoint { + remote-endpoint = <&csi0_in_mipi_csi2>; + }; + }; + }; + }; + + dphy: d-phy@1cb2000 { + compatible = "allwinner,sun6i-a31-mipi-dphy"; + reg = <0x01cb2000 0x1000>; + clocks = <&ccu CLK_BUS_CSI>, +<&ccu CLK_MIPI_CSI>; + clock-names = "bus", "mod"; + resets = <&ccu RST_BUS_CSI>; + status = "disabled"; + #phy-cells = <0>; + }; }; }; -- 2.29.2 ___ devel mailing list de...@linuxdriverproject.org http://driverdev.linuxdriverproject.org/mailman/listinfo/driverdev-devel
[PATCH v4 05/15] media: sun6i-csi: Only configure the interface data width for parallel
Bits related to the interface data width are only applicable to the parallel interface and are irrelevant when the CSI controller is taking input from the MIPI CSI-2 controller. In prevision of adding support for this case, set these bits conditionally so there is no ambiguity. The conditional block is moved around before the interlaced conditional block for nicer code symmetry (conditional blocks first) while at it. Co-developed-by: Kévin L'hôpital Signed-off-by: Kévin L'hôpital Signed-off-by: Paul Kocialkowski --- .../platform/sunxi/sun6i-csi/sun6i_csi.c | 42 +++ 1 file changed, 25 insertions(+), 17 deletions(-) diff --git a/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi.c b/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi.c index 531a4cccd14a..f1150de94e98 100644 --- a/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi.c +++ b/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi.c @@ -378,8 +378,13 @@ static void sun6i_csi_setup_bus(struct sun6i_csi_dev *sdev) unsigned char bus_width; u32 flags; u32 cfg; + bool input_parallel = false; bool input_interlaced = false; + if (endpoint->bus_type == V4L2_MBUS_PARALLEL || + endpoint->bus_type == V4L2_MBUS_BT656) + input_parallel = true; + if (csi->config.field == V4L2_FIELD_INTERLACED || csi->config.field == V4L2_FIELD_INTERLACED_TB || csi->config.field == V4L2_FIELD_INTERLACED_BT) @@ -395,6 +400,26 @@ static void sun6i_csi_setup_bus(struct sun6i_csi_dev *sdev) CSI_IF_CFG_HREF_POL_MASK | CSI_IF_CFG_FIELD_MASK | CSI_IF_CFG_SRC_TYPE_MASK); + if (input_parallel) { + switch (bus_width) { + case 8: + cfg |= CSI_IF_CFG_IF_DATA_WIDTH_8BIT; + break; + case 10: + cfg |= CSI_IF_CFG_IF_DATA_WIDTH_10BIT; + break; + case 12: + cfg |= CSI_IF_CFG_IF_DATA_WIDTH_12BIT; + break; + case 16: /* No need to configure DATA_WIDTH for 16bit */ + break; + default: + dev_warn(sdev->dev, "Unsupported bus width: %u\n", +bus_width); + break; + } + } + if (input_interlaced) cfg |= CSI_IF_CFG_SRC_TYPE_INTERLACED; else @@ -440,23 +465,6 @@ static void sun6i_csi_setup_bus(struct sun6i_csi_dev *sdev) break; } - switch (bus_width) { - case 8: - cfg |= CSI_IF_CFG_IF_DATA_WIDTH_8BIT; - break; - case 10: - cfg |= CSI_IF_CFG_IF_DATA_WIDTH_10BIT; - break; - case 12: - cfg |= CSI_IF_CFG_IF_DATA_WIDTH_12BIT; - break; - case 16: /* No need to configure DATA_WIDTH for 16bit */ - break; - default: - dev_warn(sdev->dev, "Unsupported bus width: %u\n", bus_width); - break; - } - regmap_write(sdev->regmap, CSI_IF_CFG_REG, cfg); } -- 2.29.2 ___ devel mailing list de...@linuxdriverproject.org http://driverdev.linuxdriverproject.org/mailman/listinfo/driverdev-devel
[PATCH v4 15/15] MAINTAINERS: Add entry for the Allwinner A83T MIPI CSI-2 bridge
Add myself as maintainer of the A83T MIPI CSI-2 bridge media driver. Signed-off-by: Paul Kocialkowski --- MAINTAINERS | 8 1 file changed, 8 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index a1352171778b..3b48612657b6 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -717,6 +717,14 @@ T: git git://linuxtv.org/media_tree.git F: Documentation/devicetree/bindings/media/allwinner,sun6i-a31-mipi-csi2.yaml F: drivers/media/platform/sunxi/sun6i-mipi-csi2/ +ALLWINNER A83T MIPI CSI-2 BRIDGE +M: Paul Kocialkowski +L: linux-me...@vger.kernel.org +S: Maintained +T: git git://linuxtv.org/media_tree.git +F: Documentation/devicetree/bindings/media/allwinner,sun8i-a83t-mipi-csi2.yaml +F: drivers/media/platform/sunxi/sun8i-a83t-mipi-csi2/ + ALLWINNER CPUFREQ DRIVER M: Yangtao Li L: linux...@vger.kernel.org -- 2.29.2 ___ devel mailing list de...@linuxdriverproject.org http://driverdev.linuxdriverproject.org/mailman/listinfo/driverdev-devel
[PATCH v4 11/15] MAINTAINERS: Add entry for the Allwinner A31 MIPI CSI-2 bridge
Add myself as maintainer of the A31 MIPI CSI-2 bridge media driver. Signed-off-by: Paul Kocialkowski --- MAINTAINERS | 8 1 file changed, 8 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 0644128640fb..a1352171778b 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -709,6 +709,14 @@ T: git git://linuxtv.org/media_tree.git F: Documentation/devicetree/bindings/media/allwinner,sun4i-a10-csi.yaml F: drivers/media/platform/sunxi/sun4i-csi/ +ALLWINNER A31 MIPI CSI-2 BRIDGE +M: Paul Kocialkowski +L: linux-me...@vger.kernel.org +S: Maintained +T: git git://linuxtv.org/media_tree.git +F: Documentation/devicetree/bindings/media/allwinner,sun6i-a31-mipi-csi2.yaml +F: drivers/media/platform/sunxi/sun6i-mipi-csi2/ + ALLWINNER CPUFREQ DRIVER M: Yangtao Li L: linux...@vger.kernel.org -- 2.29.2 ___ devel mailing list de...@linuxdriverproject.org http://driverdev.linuxdriverproject.org/mailman/listinfo/driverdev-devel
[PATCH v4 12/15] dt-bindings: media: Add A83T MIPI CSI-2 bindings documentation
This introduces YAML bindings documentation for the A83T MIPI CSI-2 controller. Signed-off-by: Paul Kocialkowski Reviewed-by: Rob Herring --- .../media/allwinner,sun8i-a83t-mipi-csi2.yaml | 147 ++ 1 file changed, 147 insertions(+) create mode 100644 Documentation/devicetree/bindings/media/allwinner,sun8i-a83t-mipi-csi2.yaml diff --git a/Documentation/devicetree/bindings/media/allwinner,sun8i-a83t-mipi-csi2.yaml b/Documentation/devicetree/bindings/media/allwinner,sun8i-a83t-mipi-csi2.yaml new file mode 100644 index ..e607fae7d85e --- /dev/null +++ b/Documentation/devicetree/bindings/media/allwinner,sun8i-a83t-mipi-csi2.yaml @@ -0,0 +1,147 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/allwinner,sun8i-a83t-mipi-csi2.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Allwinner A83T MIPI CSI-2 Device Tree Bindings + +maintainers: + - Paul Kocialkowski + +properties: + compatible: +const: allwinner,sun8i-a83t-mipi-csi2 + + reg: +maxItems: 1 + + interrupts: +maxItems: 1 + + clocks: +items: + - description: Bus Clock + - description: Module Clock + - description: MIPI-specific Clock + - description: Misc CSI Clock + + clock-names: +items: + - const: bus + - const: mod + - const: mipi + - const: misc + + resets: +maxItems: 1 + + # See ./video-interfaces.txt for details + ports: +type: object + +properties: + port@0: +type: object +description: Input port, connect to a MIPI CSI-2 sensor + +properties: + reg: +const: 0 + + endpoint: +type: object + +properties: + remote-endpoint: true + + clock-lanes: +maxItems: 1 + + data-lanes: +minItems: 1 +maxItems: 4 + +required: + - data-lanes + - remote-endpoint + +required: + - endpoint + +additionalProperties: false + + port@1: +type: object +description: Output port, connect to a CSI controller + +properties: + reg: +const: 1 + + endpoint: +type: object + +properties: + remote-endpoint: true + +required: + - remote-endpoint + +required: + - endpoint + +additionalProperties: false + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - resets + +additionalProperties: false + +examples: + - | +#include +#include +#include + +mipi_csi2: csi@1cb1000 { +compatible = "allwinner,sun8i-a83t-mipi-csi2"; +reg = <0x01cb1000 0x1000>; +interrupts = ; +clocks = <&ccu CLK_BUS_CSI>, + <&ccu CLK_CSI_SCLK>, + <&ccu CLK_MIPI_CSI>, + <&ccu CLK_CSI_MISC>; +clock-names = "bus", "mod", "mipi", "misc"; +resets = <&ccu RST_BUS_CSI>; + +ports { +#address-cells = <1>; +#size-cells = <0>; + +mipi_csi2_in: port@0 { +reg = <0>; + +mipi_csi2_in_ov8865: endpoint { +data-lanes = <1 2 3 4>; + +remote-endpoint = <&ov8865_out_mipi_csi2>; +}; +}; + +mipi_csi2_out: port@1 { +reg = <1>; + +mipi_csi2_out_csi: endpoint { +remote-endpoint = <&csi_in_mipi_csi2>; +}; +}; +}; +}; + +... -- 2.29.2 ___ devel mailing list de...@linuxdriverproject.org http://driverdev.linuxdriverproject.org/mailman/listinfo/driverdev-devel
[PATCH v4 13/15] media: sunxi: Add support for the A83T MIPI CSI-2 controller
The A83T supports MIPI CSI-2 with a composite controller, covering both the protocol logic and the D-PHY implementation. This controller seems to be found on the A83T only and probably was abandoned since. This implementation splits the protocol and D-PHY registers and uses the PHY framework internally. The D-PHY is not registered as a standalone PHY driver since it cannot be used with any other controller. There are a few notable points about the controller: - The initialisation sequence involes writing specific magic init values that do not seem to make any particular sense given the concerned register fields; - Interrupts appear to be hitting regardless of the interrupt mask registers, which can cause a serious flood when transmission errors occur. Only 8-bit and 10-bit Bayer formats are currently supported. While up to 4 internal channels to the CSI controller exist, only one is currently supported by this implementation. This work is based on the first version of the driver submitted by Kévin L'hôpital, which was adapted to mainline from the Allwinner BSP. This version integrates MIPI CSI-2 support as a standalone V4L2 subdev instead of merging it in the sun6i-csi driver. It was tested on a Banana Pi M3 board with an OV8865 sensor in a 4-lane configuration. Signed-off-by: Paul Kocialkowski --- drivers/media/platform/sunxi/Kconfig | 1 + drivers/media/platform/sunxi/Makefile | 1 + .../sunxi/sun8i-a83t-mipi-csi2/Kconfig| 11 + .../sunxi/sun8i-a83t-mipi-csi2/Makefile | 4 + .../sun8i-a83t-mipi-csi2/sun8i_a83t_dphy.c| 92 +++ .../sun8i-a83t-mipi-csi2/sun8i_a83t_dphy.h| 39 ++ .../sun8i_a83t_mipi_csi2.c| 657 ++ .../sun8i_a83t_mipi_csi2.h| 197 ++ 8 files changed, 1002 insertions(+) create mode 100644 drivers/media/platform/sunxi/sun8i-a83t-mipi-csi2/Kconfig create mode 100644 drivers/media/platform/sunxi/sun8i-a83t-mipi-csi2/Makefile create mode 100644 drivers/media/platform/sunxi/sun8i-a83t-mipi-csi2/sun8i_a83t_dphy.c create mode 100644 drivers/media/platform/sunxi/sun8i-a83t-mipi-csi2/sun8i_a83t_dphy.h create mode 100644 drivers/media/platform/sunxi/sun8i-a83t-mipi-csi2/sun8i_a83t_mipi_csi2.c create mode 100644 drivers/media/platform/sunxi/sun8i-a83t-mipi-csi2/sun8i_a83t_mipi_csi2.h diff --git a/drivers/media/platform/sunxi/Kconfig b/drivers/media/platform/sunxi/Kconfig index 9684e07454ad..db4c07be7e4c 100644 --- a/drivers/media/platform/sunxi/Kconfig +++ b/drivers/media/platform/sunxi/Kconfig @@ -3,3 +3,4 @@ source "drivers/media/platform/sunxi/sun4i-csi/Kconfig" source "drivers/media/platform/sunxi/sun6i-csi/Kconfig" source "drivers/media/platform/sunxi/sun6i-mipi-csi2/Kconfig" +source "drivers/media/platform/sunxi/sun8i-a83t-mipi-csi2/Kconfig" diff --git a/drivers/media/platform/sunxi/Makefile b/drivers/media/platform/sunxi/Makefile index 887a7cae8fca..9aa01cb01883 100644 --- a/drivers/media/platform/sunxi/Makefile +++ b/drivers/media/platform/sunxi/Makefile @@ -3,5 +3,6 @@ obj-y += sun4i-csi/ obj-y += sun6i-csi/ obj-y += sun6i-mipi-csi2/ +obj-y += sun8i-a83t-mipi-csi2/ obj-y += sun8i-di/ obj-y += sun8i-rotate/ diff --git a/drivers/media/platform/sunxi/sun8i-a83t-mipi-csi2/Kconfig b/drivers/media/platform/sunxi/sun8i-a83t-mipi-csi2/Kconfig new file mode 100644 index ..60e7a9c41065 --- /dev/null +++ b/drivers/media/platform/sunxi/sun8i-a83t-mipi-csi2/Kconfig @@ -0,0 +1,11 @@ +# SPDX-License-Identifier: GPL-2.0-only +config VIDEO_SUN8I_A83T_MIPI_CSI2 + tristate "Allwinner A83T MIPI CSI-2 Controller and D-PHY Driver" + depends on ARCH_SUNXI || COMPILE_TEST + depends on PM && COMMON_CLK && VIDEO_V4L2 + select REGMAP_MMIO + select MEDIA_CONTROLLER + select VIDEO_V4L2_SUBDEV_API + select V4L2_FWNODE + help + Support for the Allwinner A83T MIPI CSI-2 Controller and D-PHY. diff --git a/drivers/media/platform/sunxi/sun8i-a83t-mipi-csi2/Makefile b/drivers/media/platform/sunxi/sun8i-a83t-mipi-csi2/Makefile new file mode 100644 index ..1427d15a879a --- /dev/null +++ b/drivers/media/platform/sunxi/sun8i-a83t-mipi-csi2/Makefile @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0-only +sun8i-a83t-mipi-csi2-y += sun8i_a83t_mipi_csi2.o sun8i_a83t_dphy.o + +obj-$(CONFIG_VIDEO_SUN8I_A83T_MIPI_CSI2) += sun8i-a83t-mipi-csi2.o diff --git a/drivers/media/platform/sunxi/sun8i-a83t-mipi-csi2/sun8i_a83t_dphy.c b/drivers/media/platform/sunxi/sun8i-a83t-mipi-csi2/sun8i_a83t_dphy.c new file mode 100644 index ..c380065eb7c9 --- /dev/null +++ b/drivers/media/platform/sunxi/sun8i-a83t-mipi-csi2/sun8i_a83t_dphy.c @@ -0,0 +1,92 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2020 Bootlin + * Author: Paul Kocialkowski + */ + +#include +#include + +#include "sun8i_a83t_dphy.h" +#include "sun8i_a83t_mipi_csi2.h" + +static int sun8i
[driver-core:readfile] BUILD SUCCESS 9ed3954fe8fed889adf643c7c83c1140fc117c59
allnoconfig c6x allyesconfig mips allyesconfig mips allmodconfig powerpc allyesconfig powerpc allmodconfig powerpc allnoconfig i386 randconfig-a005-20201231 i386 randconfig-a006-20201231 i386 randconfig-a003-20201231 i386 randconfig-a004-20201231 i386 randconfig-a002-20201231 i386 randconfig-a001-20201231 x86_64 randconfig-a015-20201231 x86_64 randconfig-a014-20201231 x86_64 randconfig-a011-20201231 x86_64 randconfig-a016-20201231 x86_64 randconfig-a013-20201231 x86_64 randconfig-a012-20201231 i386 randconfig-a016-20201231 i386 randconfig-a015-20201231 i386 randconfig-a016-20210101 i386 randconfig-a011-20210101 i386 randconfig-a014-20210101 i386 randconfig-a015-20210101 i386 randconfig-a013-20210101 i386 randconfig-a012-20210101 i386 randconfig-a014-20201231 i386 randconfig-a012-20201231 i386 randconfig-a011-20201231 i386 randconfig-a013-20201231 riscvnommu_k210_defconfig riscvallyesconfig riscvnommu_virt_defconfig riscv allnoconfig riscv defconfig riscvallmodconfig x86_64 rhel x86_64 allyesconfig x86_64rhel-7.6-kselftests x86_64 defconfig x86_64 rhel-8.3 x86_64 rhel-8.3-kbuiltin x86_64 kexec clang tested configs: x86_64 randconfig-a005-20201231 x86_64 randconfig-a006-20201231 x86_64 randconfig-a001-20201231 x86_64 randconfig-a002-20201231 x86_64 randconfig-a004-20201231 x86_64 randconfig-a003-20201231 --- 0-DAY CI Kernel Test Service, Intel Corporation https://lists.01.org/hyperkitty/list/kbuild-...@lists.01.org ___ devel mailing list de...@linuxdriverproject.org http://driverdev.linuxdriverproject.org/mailman/listinfo/driverdev-devel
Re: [PATCH v5 2/6] dt: bindings: add mt7621-clk device tree binding documentation
On Sun, Dec 20, 2020 at 10:37:20AM +0100, Sergio Paracuellos wrote: > Adds device tree binding documentation for clocks in the > MT7621 SOC. > > Signed-off-by: Sergio Paracuellos > --- > .../bindings/clock/mediatek,mt7621-clk.yaml | 52 +++ > 1 file changed, 52 insertions(+) > create mode 100644 > Documentation/devicetree/bindings/clock/mediatek,mt7621-clk.yaml > > diff --git a/Documentation/devicetree/bindings/clock/mediatek,mt7621-clk.yaml > b/Documentation/devicetree/bindings/clock/mediatek,mt7621-clk.yaml > new file mode 100644 > index ..f58d01bdc82c > --- /dev/null > +++ b/Documentation/devicetree/bindings/clock/mediatek,mt7621-clk.yaml > @@ -0,0 +1,52 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/clock/mediatek,mt7621-clk.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: MT7621 Clock Device Tree Bindings > + > +maintainers: > + - Sergio Paracuellos > + > +description: | > + The MT7621 has a PLL controller from where the cpu clock is provided > + as well as derived clocks for the bus and the peripherals. It also > + can gate SoC device clocks. > + > + Each clock is assigned an identifier and client nodes use this identifier > + to specify the clock which they consume. > + > + All these identifiers could be found in: > + [1]: . > + > +properties: > + compatible: > +const: mediatek,mt7621-clk > + > + "#clock-cells": > +description: > + The first cell indicates the clock number, see [1] for available > + clocks. > +const: 1 > + > + clock-output-names: > +maxItems: 8 > + > +required: > + - compatible > + - '#clock-cells' > + > +additionalProperties: false > + > +examples: > + - | > +#include > + > +pll { > + compatible = "mediatek,mt7621-clk"; > + #clock-cells = <1>; > + clock-output-names = "xtal", "cpu", "bus", > + "50m", "125m", "150m", > + "250m", "270m"; How do you access this h/w. There's nothing defined like 'reg' or a parent node or... The suggestion on v4 was to get rid of the child node by merging it with the parent like this: +sysc: sysc@0 { + compatible = "mediatek,mt7621-sysc", "syscon"; + reg = <0x0 0x100>; + #clock-cells = <1>; + clock-output-names = "xtal", "cpu", "bus", + "50m", "125m", "150m", + "250m", "270m"; +}; Whether you need child nodes or not really depends on what all is in the 'mt7621-sysc' h/w block. Rob ___ devel mailing list de...@linuxdriverproject.org http://driverdev.linuxdriverproject.org/mailman/listinfo/driverdev-devel
Re: [PATCH v5 2/6] dt: bindings: add mt7621-clk device tree binding documentation
Hi Rob, Thanks for the review. On Thu, Dec 31, 2020 at 11:38 PM Rob Herring wrote: > > On Sun, Dec 20, 2020 at 10:37:20AM +0100, Sergio Paracuellos wrote: > > Adds device tree binding documentation for clocks in the > > MT7621 SOC. > > > > Signed-off-by: Sergio Paracuellos > > --- > > .../bindings/clock/mediatek,mt7621-clk.yaml | 52 +++ > > 1 file changed, 52 insertions(+) > > create mode 100644 > > Documentation/devicetree/bindings/clock/mediatek,mt7621-clk.yaml > > > > diff --git > > a/Documentation/devicetree/bindings/clock/mediatek,mt7621-clk.yaml > > b/Documentation/devicetree/bindings/clock/mediatek,mt7621-clk.yaml > > new file mode 100644 > > index ..f58d01bdc82c > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/clock/mediatek,mt7621-clk.yaml > > @@ -0,0 +1,52 @@ > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > > +%YAML 1.2 > > +--- > > +$id: http://devicetree.org/schemas/clock/mediatek,mt7621-clk.yaml# > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > + > > +title: MT7621 Clock Device Tree Bindings > > + > > +maintainers: > > + - Sergio Paracuellos > > + > > +description: | > > + The MT7621 has a PLL controller from where the cpu clock is provided > > + as well as derived clocks for the bus and the peripherals. It also > > + can gate SoC device clocks. > > + > > + Each clock is assigned an identifier and client nodes use this identifier > > + to specify the clock which they consume. > > + > > + All these identifiers could be found in: > > + [1]: . > > + > > +properties: > > + compatible: > > +const: mediatek,mt7621-clk > > + > > + "#clock-cells": > > +description: > > + The first cell indicates the clock number, see [1] for available > > + clocks. > > +const: 1 > > + > > + clock-output-names: > > +maxItems: 8 > > + > > +required: > > + - compatible > > + - '#clock-cells' > > + > > +additionalProperties: false > > + > > +examples: > > + - | > > +#include > > + > > +pll { > > + compatible = "mediatek,mt7621-clk"; > > + #clock-cells = <1>; > > + clock-output-names = "xtal", "cpu", "bus", > > + "50m", "125m", "150m", > > + "250m", "270m"; > > How do you access this h/w. There's nothing defined like 'reg' or > a parent node or... Through read write operations defined in "asm/mach-ralink/ralink_regs.h. Please, see my explanation below. > > The suggestion on v4 was to get rid of the child node by merging it with > the parent like this: > > +sysc: sysc@0 { > + compatible = "mediatek,mt7621-sysc", "syscon"; > + reg = <0x0 0x100>; > + #clock-cells = <1>; > + clock-output-names = "xtal", "cpu", "bus", > + "50m", "125m", "150m", > + "250m", "270m"; > +}; > > Whether you need child nodes or not really depends on what all is in the > 'mt7621-sysc' h/w block. All the drivers in this platform make use of arch operations defined in "asm/mach-ralink/ralink_regs.h". This mediatek,mt7621-sysc is directly mapped by the architecture in arch/mips/ralink/mt7621.c in function void __init ralink_of_remap(void). This is the first address in the virtual space and from here "rt_sysc_membase" and "rt_memc_membase" are used to access the hardware control registers through read and write operations. So "mediatek,mt7621-sysc" cannot be remapped from clock driver. The benefits I found at first of using the syscon as child node was to avoid the use of architecture dependant operations but at the end I realized that we need to access another register which is not in the syscon block and it is not also well documented so the use of arch operations is mandatory to make things work. That's why I end up in just follow the architecture driver style and use this in the same way, trying to maintain as clean as possible. Is it ok then to declare it as it is in this way? > > Rob Best regards, Sergio Paracuellos ___ devel mailing list de...@linuxdriverproject.org http://driverdev.linuxdriverproject.org/mailman/listinfo/driverdev-devel