[PATCH v3 3/4] staging: hikey9xx: phy-hi3670-usb3.c: hi3670_is_abbclk_seleted() returns bool

2021-01-15 Thread Mauro Carvalho Chehab 
Instead of using 1/0 for true/false, change the type to boolean
and change the returned value.

Signed-off-by: Mauro Carvalho Chehab 
---
 drivers/staging/hikey9xx/phy-hi3670-usb3.c | 10 +-
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/drivers/staging/hikey9xx/phy-hi3670-usb3.c 
b/drivers/staging/hikey9xx/phy-hi3670-usb3.c
index cffe6c58dfd7..b5fed306fcbf 100644
--- a/drivers/staging/hikey9xx/phy-hi3670-usb3.c
+++ b/drivers/staging/hikey9xx/phy-hi3670-usb3.c
@@ -326,24 +326,24 @@ static int hi3670_phy_set_params(struct hi3670_priv *priv)
return ret;
 }
 
-static int hi3670_is_abbclk_seleted(struct hi3670_priv *priv)
+static bool hi3670_is_abbclk_seleted(struct hi3670_priv *priv)
 {
u32 reg;
 
if (!priv->sctrl) {
dev_err(priv->dev, "priv->sctrl is null!\n");
-   return 1;
+   return true;
}
 
if (regmap_read(priv->sctrl, SCTRL_SCDEEPSLEEPED, ®)) {
dev_err(priv->dev, "SCTRL_SCDEEPSLEEPED read failed!\n");
-   return 1;
+   return true;
}
 
if ((reg & USB_CLK_SELECTED) == 0)
-   return 1;
+   return true;
 
-   return 0;
+   return false;
 }
 
 static int hi3670_config_phy_clock(struct hi3670_priv *priv)
-- 
2.29.2

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[PATCH v3 1/4] staging: hikey9xx: phy-hi3670-usb3.c: use bitfield macros

2021-01-15 Thread Mauro Carvalho Chehab 
Cleanup the bitfield macros by using FIELD_PREP() and GENMASK().

While here, place all hexadecimal values in lowercase.

Signed-off-by: Mauro Carvalho Chehab 
---
 drivers/staging/hikey9xx/phy-hi3670-usb3.c | 61 ++
 1 file changed, 28 insertions(+), 33 deletions(-)

diff --git a/drivers/staging/hikey9xx/phy-hi3670-usb3.c 
b/drivers/staging/hikey9xx/phy-hi3670-usb3.c
index 4fc013911a78..722cabaa9bd9 100644
--- a/drivers/staging/hikey9xx/phy-hi3670-usb3.c
+++ b/drivers/staging/hikey9xx/phy-hi3670-usb3.c
@@ -8,6 +8,7 @@
  * Authors: Yu Chen 
  */
 
+#include 
 #include 
 #include 
 #include 
@@ -41,15 +42,15 @@
 #define SC_CLK_USB3PHY_3MUX1_SEL   BIT(25)
 
 #define USB3OTG_CTRL0  (0x00)
-#define USB3OTG_CTRL3  (0x0C)
+#define USB3OTG_CTRL3  (0x0c)
 #define USB3OTG_CTRL4  (0x10)
 #define USB3OTG_CTRL5  (0x14)
-#define USB3OTG_CTRL7  (0x1C)
+#define USB3OTG_CTRL7  (0x1c)
 #define USB_MISC_CFG50 (0x50)
 #define USB_MISC_CFG54 (0x54)
 #define USB_MISC_CFG58 (0x58)
-#define USB_MISC_CFG5C (0x5C)
-#define USB_MISC_CFGA0 (0xA0)
+#define USB_MISC_CFG5C (0x5c)
+#define USB_MISC_CFGA0 (0xa0)
 #define TCA_CLK_RST(0x200)
 #define TCA_INTR_EN(0x204)
 #define TCA_INTR_STS   (0x208)
@@ -66,14 +67,14 @@
 
 #define CTRL5_USB2_SIDDQ   BIT(0)
 
-#define CTRL7_USB2_REFCLKSEL_MASK  (3 << 3)
-#define CTRL7_USB2_REFCLKSEL_ABB   (3 << 3)
-#define CTRL7_USB2_REFCLKSEL_PAD   (2 << 3)
+#define CTRL7_USB2_REFCLKSEL_MASK  GENMASK(4, 3)
+#define CTRL7_USB2_REFCLKSEL_ABB   (BIT(4) | BIT(3))
+#define CTRL7_USB2_REFCLKSEL_PAD   BIT(4)
 
 #define CFG50_USB3_PHY_TEST_POWERDOWN  BIT(23)
 
-#define CFG54_USB31PHY_CR_ADDR_MASK(0x)
-#define CFG54_USB31PHY_CR_ADDR_SHIFT   (16)
+#define CFG54_USB31PHY_CR_ADDR_MASKGENMASK(31, 16)
+
 #define CFG54_USB3PHY_REF_USE_PAD  BIT(12)
 #define CFG54_PHY0_PMA_PWR_STABLE  BIT(11)
 #define CFG54_PHY0_PCS_PWR_STABLE  BIT(9)
@@ -84,8 +85,7 @@
 #define CFG54_USB31PHY_CR_CLK  BIT(2)
 #define CFG54_USB3_PHY0_ANA_PWR_EN BIT(1)
 
-#define CFG58_USB31PHY_CR_DATA_MASK (0x)
-#define CFG58_USB31PHY_CR_DATA_RD_START (16)
+#define CFG58_USB31PHY_CR_DATA_MASK GENMASK(31, 16)
 
 #define CFG5C_USB3_PHY0_SS_MPLLA_SSC_ENBIT(1)
 
@@ -102,20 +102,20 @@
 #define CLK_RST_SUSPEND_CLK_EN BIT(0)
 
 #define GCFG_ROLE_HSTDEV   BIT(4)
-#define GCFG_OP_MODE   (3 << 0)
+#define GCFG_OP_MODE   GENMASK(1, 0)
 #define GCFG_OP_MODE_CTRL_SYNC_MODEBIT(0)
 
 #define TCPC_VALID BIT(4)
 #define TCPC_LOW_POWER_EN  BIT(3)
-#define TCPC_MUX_CONTROL_MASK  (3 << 0)
+#define TCPC_MUX_CONTROL_MASK  GENMASK(1, 0)
 #define TCPC_MUX_CONTROL_USB31 BIT(0)
 
 #define SYSMODE_CFG_TYPEC_DISABLE  BIT(3)
 
-#define VBUS_CTRL_POWERPRESENT_OVERRD  (3 << 2)
-#define VBUS_CTRL_VBUSVALID_OVERRD (3 << 0)
+#define VBUS_CTRL_POWERPRESENT_OVERRD  GENMASK(3, 2)
+#define VBUS_CTRL_VBUSVALID_OVERRD GENMASK(1, 0)
 
-#define KIRIN970_USB_DEFAULT_PHY_PARAM (0xFDFEE4)
+#define KIRIN970_USB_DEFAULT_PHY_PARAM (0xfdfee4)
 #define KIRIN970_USB_DEFAULT_PHY_VBOOST(0x5)
 
 #define TX_VBOOST_LVL_REG  (0xf)
@@ -162,16 +162,14 @@ static int hi3670_phy_cr_set_sel(struct regmap *usb31misc)
 
 static int hi3670_phy_cr_start(struct regmap *usb31misc, int direction)
 {
-   int ret;
+   int ret, reg;
 
if (direction)
-   ret = regmap_update_bits(usb31misc, USB_MISC_CFG54,
-CFG54_USB31PHY_CR_WR_EN,
-CFG54_USB31PHY_CR_WR_EN);
+   reg = CFG54_USB31PHY_CR_WR_EN;
else
-   ret = regmap_update_bits(usb31misc, USB_MISC_CFG54,
-CFG54_USB31PHY_CR_RD_EN,
-CFG54_USB31PHY_CR_RD_EN);
+   reg = CFG54_USB31PHY_CR_RD_EN;
+
+   ret = regmap_update_bits(usb31misc, USB_MISC_CFG54, reg, reg);
 
if (ret)
return ret;
@@ -180,10 +178,8 @@ static int hi3670_phy_cr_start(struct regmap *usb31misc, 
int direction)
if (ret)
return ret;
 
-   ret = regmap_update_bits(usb31misc, USB_MISC_CFG54,
-CFG54_USB31PHY_CR_RD_EN | 
CFG54_USB31PHY_CR_WR_EN, 0);
-
-   return ret;
+   return regmap_update_bits(usb31misc, USB_MISC_CFG54,
+ CFG54_USB31PHY_CR_RD_EN | 
CFG54_USB31PHY_CR_WR_EN, 0);
 }
 
 static int hi3670_phy_cr_wait_ack(struct regmap *usb31misc)
@@ -216,9 +212,9 @@ static int hi3670_phy_cr_set_addr(struct regmap *usb31misc, 
u32 addr)
if

[PATCH v3 0/4] Promote Hikey 970 USB phy out of staging

2021-01-15 Thread Mauro Carvalho Chehab 
Hi Vinod/Rob,

This series moves  the Hikey 970 USB PHY driver out of staging.

The 3 initial patches address the issues pointed by Vinod:

patch 1 change the logic to use GENMASK and FIELD_GET/FIELD_PREP macros.
It also places all hexadecimal values in lowercase;

patch 2 add a delay inside the retry logic;

patch 3 changes a function to return a boolean.

The 4th patch is actually identical to the patch I sent previously:
it just moves the driver to drivers/phy and add a blank line at the
yaml driver:

 rename drivers/staging/hikey9xx/phy-hi3670-usb3.yaml => 
Documentation/devicetree/bindings/phy/hisilicon,hi3670-usb3.yaml (99%)
 rename drivers/{staging/hikey9xx => phy/hisilicon}/phy-hi3670-usb3.c (100%)

In order to make this series easier to review, I'm submitting it with
--no-merges. This way, you can check the  driver and DT bindings
as a hole while reviewing the last patch.

-

v3: 
- no changes on patches 1-2 nor at phy-hi3670-usb3.c;
- yaml renamed to: hisilicon,hi3670-usb3.yaml 
- Added a blank line after maintainers at hisilicon,hi3670-usb3.yaml 

Mauro Carvalho Chehab (4):
  staging: hikey9xx: phy-hi3670-usb3.c: use bitfield macros
  staging: hikey9xx: phy-hi3670-usb3.c: adjust retry logic
  staging: hikey9xx: phy-hi3670-usb3.c: hi3670_is_abbclk_seleted()
returns bool
  phy: phy-hi3670-usb3: move driver from staging into phy

 .../bindings/phy/phy-hi3670-usb3.yaml |  72 ++
 MAINTAINERS   |   9 +-
 drivers/phy/hisilicon/Kconfig |  10 +
 drivers/phy/hisilicon/Makefile|   1 +
 drivers/phy/hisilicon/phy-hi3670-usb3.c   | 668 +
 drivers/staging/hikey9xx/Kconfig  |  11 -
 drivers/staging/hikey9xx/Makefile |   2 -
 drivers/staging/hikey9xx/phy-hi3670-usb3.c| 671 --
 drivers/staging/hikey9xx/phy-hi3670-usb3.yaml |  72 --
 9 files changed, 759 insertions(+), 757 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/phy/phy-hi3670-usb3.yaml
 create mode 100644 drivers/phy/hisilicon/phy-hi3670-usb3.c
 delete mode 100644 drivers/staging/hikey9xx/phy-hi3670-usb3.c
 delete mode 100644 drivers/staging/hikey9xx/phy-hi3670-usb3.yaml

-- 
2.29.2


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[PATCH v3 2/4] staging: hikey9xx: phy-hi3670-usb3.c: adjust retry logic

2021-01-15 Thread Mauro Carvalho Chehab 
Instead of running a loop up to 100k times, add a small
delay inside it, running it up to 10 times, waiting up
to 100-200 us.

It should be noticed that I don't have the datasheet for
this PHY. So, not sure if this time will cover all
situations.

Signed-off-by: Mauro Carvalho Chehab 
---
 drivers/staging/hikey9xx/phy-hi3670-usb3.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/staging/hikey9xx/phy-hi3670-usb3.c 
b/drivers/staging/hikey9xx/phy-hi3670-usb3.c
index 722cabaa9bd9..cffe6c58dfd7 100644
--- a/drivers/staging/hikey9xx/phy-hi3670-usb3.c
+++ b/drivers/staging/hikey9xx/phy-hi3670-usb3.c
@@ -185,7 +185,7 @@ static int hi3670_phy_cr_start(struct regmap *usb31misc, 
int direction)
 static int hi3670_phy_cr_wait_ack(struct regmap *usb31misc)
 {
u32 reg;
-   int retry = 10;
+   int retry = 10;
int ret;
 
while (retry-- > 0) {
@@ -198,6 +198,8 @@ static int hi3670_phy_cr_wait_ack(struct regmap *usb31misc)
ret = hi3670_phy_cr_clk(usb31misc);
if (ret)
return ret;
+
+   usleep_range(10, 20);
}
 
return -ETIMEDOUT;
-- 
2.29.2

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[PATCH v3 4/4] phy: phy-hi3670-usb3: move driver from staging into phy

2021-01-15 Thread Mauro Carvalho Chehab 
The phy USB3 driver for Hisilicon 970 (hi3670) is ready
for mainstream. Mode it from staging into the main driver's
phy/ directory.

Signed-off-by: Mauro Carvalho Chehab 
---
 .../bindings/phy/phy-hi3670-usb3.yaml |  72 ++
 MAINTAINERS   |   9 +-
 drivers/phy/hisilicon/Kconfig |  10 +
 drivers/phy/hisilicon/Makefile|   1 +
 drivers/phy/hisilicon/phy-hi3670-usb3.c   | 668 ++
 drivers/staging/hikey9xx/Kconfig  |  11 -
 drivers/staging/hikey9xx/Makefile |   2 -
 drivers/staging/hikey9xx/phy-hi3670-usb3.c| 668 --
 drivers/staging/hikey9xx/phy-hi3670-usb3.yaml |  72 --
 9 files changed, 759 insertions(+), 754 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/phy/phy-hi3670-usb3.yaml
 create mode 100644 drivers/phy/hisilicon/phy-hi3670-usb3.c
 delete mode 100644 drivers/staging/hikey9xx/phy-hi3670-usb3.c
 delete mode 100644 drivers/staging/hikey9xx/phy-hi3670-usb3.yaml

diff --git a/Documentation/devicetree/bindings/phy/phy-hi3670-usb3.yaml 
b/Documentation/devicetree/bindings/phy/phy-hi3670-usb3.yaml
new file mode 100644
index ..125a5d6546ae
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/phy-hi3670-usb3.yaml
@@ -0,0 +1,72 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/hisilicon,hi3670-usb3.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Hisilicon Kirin970 USB PHY
+
+maintainers:
+  - Mauro Carvalho Chehab 
+description: |+
+  Bindings for USB3 PHY on HiSilicon Kirin 970.
+
+properties:
+  compatible:
+const: hisilicon,hi3670-usb-phy
+
+  "#phy-cells":
+const: 0
+
+  hisilicon,pericrg-syscon:
+$ref: '/schemas/types.yaml#/definitions/phandle'
+description: phandle of syscon used to control iso refclk.
+
+  hisilicon,pctrl-syscon:
+$ref: '/schemas/types.yaml#/definitions/phandle'
+description: phandle of syscon used to control usb tcxo.
+
+  hisilicon,sctrl-syscon:
+$ref: '/schemas/types.yaml#/definitions/phandle'
+description: phandle of syscon used to control phy deep sleep.
+
+  hisilicon,eye-diagram-param:
+$ref: /schemas/types.yaml#/definitions/uint32
+description: Eye diagram for phy.
+
+  hisilicon,tx-vboost-lvl:
+$ref: /schemas/types.yaml#/definitions/uint32
+description: TX level vboost for phy.
+
+required:
+  - compatible
+  - hisilicon,pericrg-syscon
+  - hisilicon,pctrl-syscon
+  - hisilicon,sctrl-syscon
+  - hisilicon,eye-diagram-param
+  - hisilicon,tx-vboost-lvl
+  - "#phy-cells"
+
+additionalProperties: false
+
+examples:
+  - |
+bus {
+  #address-cells = <2>;
+  #size-cells = <2>;
+
+  usb3_otg_bc: usb3_otg_bc@ff20 {
+compatible = "syscon", "simple-mfd";
+reg = <0x0 0xff20 0x0 0x1000>;
+
+usb_phy {
+  compatible = "hisilicon,hi3670-usb-phy";
+  #phy-cells = <0>;
+  hisilicon,pericrg-syscon = <&crg_ctrl>;
+  hisilicon,pctrl-syscon = <&pctrl>;
+  hisilicon,sctrl-syscon = <&sctrl>;
+  hisilicon,eye-diagram-param = <0xfdfee4>;
+  hisilicon,tx-vboost-lvl = <0x5>;
+};
+  };
+};
diff --git a/MAINTAINERS b/MAINTAINERS
index 281de213ef47..8d858e8d5a52 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -18088,7 +18088,7 @@ L:  linux-...@vger.kernel.org
 S: Maintained
 F: drivers/usb/roles/intel-xhci-usb-role-switch.c
 
-USB IP DRIVER FOR HISILICON KIRIN
+USB IP DRIVER FOR HISILICON KIRIN 960
 M: Yu Chen 
 M: Binghui Wang 
 L: linux-...@vger.kernel.org
@@ -18096,6 +18096,13 @@ S: Maintained
 F: Documentation/devicetree/bindings/phy/hisilicon,hi3660-usb3.yaml
 F: drivers/phy/hisilicon/phy-hi3660-usb3.c
 
+USB IP DRIVER FOR HISILICON KIRIN 970
+M: Mauro Carvalho Chehab 
+L: linux-...@vger.kernel.org
+S: Maintained
+F: Documentation/devicetree/bindings/phy/hisilicon,kirin970-usb3.yaml
+F: drivers/phy/hisilicon/phy-kirin970-usb3.c
+
 USB ISP116X DRIVER
 M: Olav Kongas 
 L: linux-...@vger.kernel.org
diff --git a/drivers/phy/hisilicon/Kconfig b/drivers/phy/hisilicon/Kconfig
index 1c73053bcc98..4d008cfc279c 100644
--- a/drivers/phy/hisilicon/Kconfig
+++ b/drivers/phy/hisilicon/Kconfig
@@ -23,6 +23,16 @@ config PHY_HI3660_USB
 
  To compile this driver as a module, choose M here.
 
+config PHY_HI3670_USB
+   tristate "hi3670 USB PHY support"
+   depends on (ARCH_HISI && ARM64) || COMPILE_TEST
+   select GENERIC_PHY
+   select MFD_SYSCON
+   help
+ Enable this to support the HISILICON HI3670 USB PHY.
+
+ To compile this driver as a module, choose M here.
+
 config PHY_HISTB_COMBPHY
tristate "HiSilicon STB SoCs COMBPHY support"
depends on (ARCH_HISI && ARM64) || COMPILE_TEST
diff --git a/drivers/phy/hisilicon/Makefile b/drivers/phy/hisilicon/Makefile
index 92e874ae9c74..51729868145b 100644
--

Re: [PATCH v3 4/4] phy: phy-hi3670-usb3: move driver from staging into phy

2021-01-15 Thread Joe Perches 
On Fri, 2021-01-15 at 09:10 +0100, Mauro Carvalho Chehab wrote:
> The phy USB3 driver for Hisilicon 970 (hi3670) is ready
> for mainstream. Mode it from staging into the main driver's
> phy/ directory.
[]
> diff --git a/Documentation/devicetree/bindings/phy/phy-hi3670-usb3.yaml 
> b/Documentation/devicetree/bindings/phy/phy-hi3670-usb3.yaml
[]
> +++ b/Documentation/devicetree/bindings/phy/phy-hi3670-usb3.yaml
> @@ -0,0 +1,72 @@
> +# SPDX-License-Identifier: GPL-2.0
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/phy/hisilicon,hi3670-usb3.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Hisilicon Kirin970 USB PHY
> +
> +maintainers:
> +  - Mauro Carvalho Chehab 
> +description: |+
> +  Bindings for USB3 PHY on HiSilicon Kirin 970.

The cover letter for v3 says there's a blank link after maintainers:
here but not found...


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Re: [PATCH v3 4/4] phy: phy-hi3670-usb3: move driver from staging into phy

2021-01-15 Thread Rob Herring 
On Fri, 15 Jan 2021 09:10:03 +0100, Mauro Carvalho Chehab wrote:
> The phy USB3 driver for Hisilicon 970 (hi3670) is ready
> for mainstream. Mode it from staging into the main driver's
> phy/ directory.
> 
> Signed-off-by: Mauro Carvalho Chehab 
> ---
>  .../bindings/phy/phy-hi3670-usb3.yaml |  72 ++
>  MAINTAINERS   |   9 +-
>  drivers/phy/hisilicon/Kconfig |  10 +
>  drivers/phy/hisilicon/Makefile|   1 +
>  drivers/phy/hisilicon/phy-hi3670-usb3.c   | 668 ++
>  drivers/staging/hikey9xx/Kconfig  |  11 -
>  drivers/staging/hikey9xx/Makefile |   2 -
>  drivers/staging/hikey9xx/phy-hi3670-usb3.c| 668 --
>  drivers/staging/hikey9xx/phy-hi3670-usb3.yaml |  72 --
>  9 files changed, 759 insertions(+), 754 deletions(-)
>  create mode 100644 Documentation/devicetree/bindings/phy/phy-hi3670-usb3.yaml
>  create mode 100644 drivers/phy/hisilicon/phy-hi3670-usb3.c
>  delete mode 100644 drivers/staging/hikey9xx/phy-hi3670-usb3.c
>  delete mode 100644 drivers/staging/hikey9xx/phy-hi3670-usb3.yaml
> 

My bot found errors running 'make dt_binding_check' on your patch:

yamllint warnings/errors:

dtschema/dtc warnings/errors:
./Documentation/devicetree/bindings/phy/phy-hi3670-usb3.yaml: $id: relative 
path/filename doesn't match actual path or filename
expected: http://devicetree.org/schemas/phy/phy-hi3670-usb3.yaml#

See https://patchwork.ozlabs.org/patch/1426831

This check can fail if there are any dependencies. The base for a patch
series is generally the most recent rc1.

If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:

pip3 install dtschema --upgrade

Please check and re-submit.

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[staging:staging-linus] BUILD SUCCESS a1bfb0ccf94dc79223d0db0d50237d3b3898f0b2

2021-01-15 Thread kernel test robot 
tree/branch: https://git.kernel.org/pub/scm/linux/kernel/git/gregkh/staging.git 
staging-linus
branch HEAD: a1bfb0ccf94dc79223d0db0d50237d3b3898f0b2  Merge tag 
'iio-fixes-for-5.11a' of 
https://git.kernel.org/pub/scm/linux/kernel/git/jic23/iio into staging-linus

elapsed time: 727m

configs tested: 129
configs skipped: 4

The following configs have been built successfully.
More configs may be tested in the coming days.

gcc tested configs:
arm defconfig
arm64allyesconfig
arm64   defconfig
arm  allyesconfig
arm  allmodconfig
i386 alldefconfig
powerpc   bluestone_defconfig
sh  urquell_defconfig
arm mxs_defconfig
ia64zx1_defconfig
arm  ixp4xx_defconfig
mips  maltasmvp_eva_defconfig
sh   j2_defconfig
powerpc mpc8560_ads_defconfig
sh shx3_defconfig
arm  pxa168_defconfig
powerpcge_imp3a_defconfig
powerpc mpc834x_itx_defconfig
mips decstation_defconfig
mips bigsur_defconfig
powerpccell_defconfig
powerpc   mpc834x_itxgp_defconfig
um i386_defconfig
mips  malta_kvm_defconfig
shecovec24-romimage_defconfig
arm   viper_defconfig
sh  rsk7201_defconfig
arm bcm2835_defconfig
sh sh03_defconfig
powerpc tqm8555_defconfig
mips   ip32_defconfig
sh  defconfig
mips   ip27_defconfig
m68k   m5249evb_defconfig
powerpc   ppc64_defconfig
armmulti_v5_defconfig
arm s3c2410_defconfig
arm   imx_v4_v5_defconfig
arm socfpga_defconfig
m68k amcore_defconfig
powerpc sbc8548_defconfig
s390defconfig
armvexpress_defconfig
powerpc canyonlands_defconfig
sh  sh7785lcr_32bit_defconfig
mips   ci20_defconfig
openriscor1ksim_defconfig
xtensa  nommu_kc705_defconfig
sparcalldefconfig
mipse55_defconfig
powerpc tqm8541_defconfig
arm lpc18xx_defconfig
sh  kfr2r09_defconfig
sh espt_defconfig
m68k   sun3_defconfig
powerpc ksi8560_defconfig
arm   mainstone_defconfig
armxcep_defconfig
mips  maltaaprp_defconfig
ia64 allmodconfig
ia64defconfig
ia64 allyesconfig
m68k allmodconfig
m68kdefconfig
m68k allyesconfig
nios2   defconfig
arc  allyesconfig
nds32 allnoconfig
c6x  allyesconfig
nds32   defconfig
nios2allyesconfig
cskydefconfig
alpha   defconfig
alphaallyesconfig
xtensa   allyesconfig
h8300allyesconfig
arc defconfig
sh   allmodconfig
parisc  defconfig
s390 allyesconfig
parisc   allyesconfig
i386 allyesconfig
sparcallyesconfig
sparc   defconfig
i386   tinyconfig
i386defconfig
mips allyesconfig
mips allmodconfig
powerpc  allyesconfig
powerpc  allmodconfig
powerpc   allnoconfig
x86_64   randconfig-a004-20210115
x86_64   randconfig-a006-20210115
x86_64   randconfig-a001-20210115
x86_64   randconfig-a003-20210115
x86_64   randconfig-a005-20210115
x86_64   randconfig-a002-20210115
i386 randconfig-a002-20210115
i386 randconfig-a00

[PATCH v5 02/16] phy: Distinguish between Rx and Tx for MIPI D-PHY with submodes

2021-01-15 Thread Paul Kocialkowski 
As some D-PHY controllers support both Rx and Tx mode, we need a way for
users to explicitly request one or the other. For instance, Rx mode can
be used along with MIPI CSI-2 while Tx mode can be used with MIPI DSI.

Introduce new MIPI D-PHY PHY submodes to use with PHY_MODE_MIPI_DPHY.
The default (zero value) is kept to Tx so only the rkisp1 driver, which
uses D-PHY in Rx mode, needs to be adapted.

Signed-off-by: Paul Kocialkowski 
Acked-by: Helen Koike 
---
 drivers/media/platform/rockchip/rkisp1/rkisp1-isp.c |  3 ++-
 include/linux/phy/phy-mipi-dphy.h   | 13 +
 2 files changed, 15 insertions(+), 1 deletion(-)

diff --git a/drivers/media/platform/rockchip/rkisp1/rkisp1-isp.c 
b/drivers/media/platform/rockchip/rkisp1/rkisp1-isp.c
index 2e5b57e3aedc..cab261644102 100644
--- a/drivers/media/platform/rockchip/rkisp1/rkisp1-isp.c
+++ b/drivers/media/platform/rockchip/rkisp1/rkisp1-isp.c
@@ -948,7 +948,8 @@ static int rkisp1_mipi_csi2_start(struct rkisp1_isp *isp,
 
phy_mipi_dphy_get_default_config(pixel_clock, isp->sink_fmt->bus_width,
 sensor->lanes, cfg);
-   phy_set_mode(sensor->dphy, PHY_MODE_MIPI_DPHY);
+   phy_set_mode_ext(cdev->dphy, PHY_MODE_MIPI_DPHY,
+PHY_MIPI_DPHY_SUBMODE_RX);
phy_configure(sensor->dphy, &opts);
phy_power_on(sensor->dphy);
 
diff --git a/include/linux/phy/phy-mipi-dphy.h 
b/include/linux/phy/phy-mipi-dphy.h
index a877ffee845d..0f57ef46a8b5 100644
--- a/include/linux/phy/phy-mipi-dphy.h
+++ b/include/linux/phy/phy-mipi-dphy.h
@@ -6,6 +6,19 @@
 #ifndef __PHY_MIPI_DPHY_H_
 #define __PHY_MIPI_DPHY_H_
 
+/**
+ * enum phy_mipi_dphy_submode - MIPI D-PHY sub-mode
+ *
+ * A MIPI D-PHY can be used to transmit or receive data.
+ * Since some controllers can support both, the direction to enable is 
specified
+ * with the PHY sub-mode. Transmit is assumed by default with phy_set_mode.
+ */
+
+enum phy_mipi_dphy_submode {
+   PHY_MIPI_DPHY_SUBMODE_TX = 0,
+   PHY_MIPI_DPHY_SUBMODE_RX,
+};
+
 /**
  * struct phy_configure_opts_mipi_dphy - MIPI D-PHY configuration set
  *
-- 
2.30.0

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[PATCH v5 01/16] docs: phy: Add a part about PHY mode and submode

2021-01-15 Thread Paul Kocialkowski 
Besides giving pointers to the relevant functions for PHY mode and
submode configuration, this clarifies the need to set them before
powering on the PHY.

Signed-off-by: Paul Kocialkowski 
Reviewed-by: Maxime Ripard 
---
 Documentation/driver-api/phy/phy.rst | 18 ++
 1 file changed, 18 insertions(+)

diff --git a/Documentation/driver-api/phy/phy.rst 
b/Documentation/driver-api/phy/phy.rst
index 8fc1ce0bb905..6cbc72707a49 100644
--- a/Documentation/driver-api/phy/phy.rst
+++ b/Documentation/driver-api/phy/phy.rst
@@ -195,3 +195,21 @@ DeviceTree Binding
 
 The documentation for PHY dt binding can be found @
 Documentation/devicetree/bindings/phy/phy-bindings.txt
+
+PHY Mode and Submode
+
+
+Once a reference to a PHY is obtained by a controller, the PHY can be 
configured
+to a PHY mode and submode. PHY modes are described in the `phy_mode` enum while
+submodes are specific to the selected PHY mode.
+
+Mode and submode configuration is done by calling::
+
+   int phy_set_mode_ext(struct phy *phy, enum phy_mode mode, int submode);
+
+If no submode is to be configured, users can call::
+
+   int phy_set_mode(struct phy *phy, enum phy_mode mode);
+
+The PHY mode and submode must not be configured after the PHY has already been
+powered on.
-- 
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[PATCH v5 03/16] phy: allwinner: phy-sun6i-mipi-dphy: Support D-PHY Rx mode for MIPI CSI-2

2021-01-15 Thread Paul Kocialkowski 
The Allwinner A31 D-PHY supports both Rx and Tx modes. While the latter
is already supported and used for MIPI DSI this adds support for the
former, to be used with MIPI CSI-2.

This implementation is inspired by Allwinner's V3s Linux SDK
implementation, which was used as a documentation base.

Signed-off-by: Paul Kocialkowski 
Acked-by: Maxime Ripard 
---
 drivers/phy/allwinner/phy-sun6i-mipi-dphy.c | 164 +++-
 1 file changed, 160 insertions(+), 4 deletions(-)

diff --git a/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c 
b/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c
index f0bc87d654d4..326383e72528 100644
--- a/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c
+++ b/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c
@@ -24,6 +24,14 @@
 #define SUN6I_DPHY_TX_CTL_REG  0x04
 #define SUN6I_DPHY_TX_CTL_HS_TX_CLK_CONT   BIT(28)
 
+#define SUN6I_DPHY_RX_CTL_REG  0x08
+#define SUN6I_DPHY_RX_CTL_EN_DBC   BIT(31)
+#define SUN6I_DPHY_RX_CTL_RX_CLK_FORCE BIT(24)
+#define SUN6I_DPHY_RX_CTL_RX_D3_FORCE  BIT(23)
+#define SUN6I_DPHY_RX_CTL_RX_D2_FORCE  BIT(22)
+#define SUN6I_DPHY_RX_CTL_RX_D1_FORCE  BIT(21)
+#define SUN6I_DPHY_RX_CTL_RX_D0_FORCE  BIT(20)
+
 #define SUN6I_DPHY_TX_TIME0_REG0x10
 #define SUN6I_DPHY_TX_TIME0_HS_TRAIL(n)(((n) & 0xff) << 24)
 #define SUN6I_DPHY_TX_TIME0_HS_PREPARE(n)  (((n) & 0xff) << 16)
@@ -44,12 +52,29 @@
 #define SUN6I_DPHY_TX_TIME4_HS_TX_ANA1(n)  (((n) & 0xff) << 8)
 #define SUN6I_DPHY_TX_TIME4_HS_TX_ANA0(n)  ((n) & 0xff)
 
+#define SUN6I_DPHY_RX_TIME0_REG0x30
+#define SUN6I_DPHY_RX_TIME0_HS_RX_SYNC(n)  (((n) & 0xff) << 24)
+#define SUN6I_DPHY_RX_TIME0_HS_RX_CLK_MISS(n)  (((n) & 0xff) << 16)
+#define SUN6I_DPHY_RX_TIME0_LP_RX(n)   (((n) & 0xff) << 8)
+
+#define SUN6I_DPHY_RX_TIME1_REG0x34
+#define SUN6I_DPHY_RX_TIME1_RX_DLY(n)  (((n) & 0xfff) << 20)
+#define SUN6I_DPHY_RX_TIME1_LP_RX_ULPS_WP(n)   ((n) & 0xf)
+
+#define SUN6I_DPHY_RX_TIME2_REG0x38
+#define SUN6I_DPHY_RX_TIME2_HS_RX_ANA1(n)  (((n) & 0xff) << 8)
+#define SUN6I_DPHY_RX_TIME2_HS_RX_ANA0(n)  ((n) & 0xff)
+
+#define SUN6I_DPHY_RX_TIME3_REG0x40
+#define SUN6I_DPHY_RX_TIME3_LPRST_DLY(n)   (((n) & 0x) << 16)
+
 #define SUN6I_DPHY_ANA0_REG0x4c
 #define SUN6I_DPHY_ANA0_REG_PWSBIT(31)
 #define SUN6I_DPHY_ANA0_REG_DMPC   BIT(28)
 #define SUN6I_DPHY_ANA0_REG_DMPD(n)(((n) & 0xf) << 24)
 #define SUN6I_DPHY_ANA0_REG_SLV(n) (((n) & 7) << 12)
 #define SUN6I_DPHY_ANA0_REG_DEN(n) (((n) & 0xf) << 8)
+#define SUN6I_DPHY_ANA0_REG_SFB(n) (((n) & 3) << 2)
 
 #define SUN6I_DPHY_ANA1_REG0x50
 #define SUN6I_DPHY_ANA1_REG_VTTMODEBIT(31)
@@ -92,6 +117,8 @@ struct sun6i_dphy {
 
struct phy  *phy;
struct phy_configure_opts_mipi_dphy config;
+
+   int submode;
 };
 
 static int sun6i_dphy_init(struct phy *phy)
@@ -105,6 +132,18 @@ static int sun6i_dphy_init(struct phy *phy)
return 0;
 }
 
+static int sun6i_dphy_set_mode(struct phy *phy, enum phy_mode mode, int 
submode)
+{
+   struct sun6i_dphy *dphy = phy_get_drvdata(phy);
+
+   if (mode != PHY_MODE_MIPI_DPHY)
+   return -EINVAL;
+
+   dphy->submode = submode;
+
+   return 0;
+}
+
 static int sun6i_dphy_configure(struct phy *phy, union phy_configure_opts 
*opts)
 {
struct sun6i_dphy *dphy = phy_get_drvdata(phy);
@@ -119,9 +158,8 @@ static int sun6i_dphy_configure(struct phy *phy, union 
phy_configure_opts *opts)
return 0;
 }
 
-static int sun6i_dphy_power_on(struct phy *phy)
+static int sun6i_dphy_tx_power_on(struct sun6i_dphy *dphy)
 {
-   struct sun6i_dphy *dphy = phy_get_drvdata(phy);
u8 lanes_mask = GENMASK(dphy->config.lanes - 1, 0);
 
regmap_write(dphy->regs, SUN6I_DPHY_TX_CTL_REG,
@@ -211,12 +249,129 @@ static int sun6i_dphy_power_on(struct phy *phy)
return 0;
 }
 
+static int sun6i_dphy_rx_power_on(struct sun6i_dphy *dphy)
+{
+   /* Physical clock rate is actually half of symbol rate with DDR. */
+   unsigned long mipi_symbol_rate = dphy->config.hs_clk_rate;
+   unsigned long dphy_clk_rate;
+   unsigned int rx_dly;
+   unsigned int lprst_dly;
+   u32 value;
+
+   dphy_clk_rate = clk_get_rate(dphy->mod_clk);
+   if (!dphy_clk_rate)
+   return -EINVAL;
+
+   /* Hardcoded timing parameters from the Allwinner BSP. */
+   regmap_write(dphy->regs, SUN6I_DPHY_RX_TIME0_REG,
+SUN6I_DPHY_RX_TIME0_HS_RX_SYNC(255) |
+SUN6I_DPHY_RX_TIME0_HS_RX_CLK_MISS(255) |
+SUN6I_DPHY_RX_TIME0_LP_RX(255));
+
+   /*
+* Formula from the Allwinner BSP, with hardcoded coefficients
+* (probably internal divider/multiplier).
+*/
+   rx_d

[PATCH v5 06/16] media: sun6i-csi: Only configure the interface data width for parallel

2021-01-15 Thread Paul Kocialkowski 
Bits related to the interface data width are only applicable to the
parallel interface and are irrelevant when the CSI controller is taking
input from the MIPI CSI-2 controller.

In prevision of adding support for this case, set these bits
conditionally so there is no ambiguity. The conditional block is
moved around before the interlaced conditional block for nicer code
symmetry (conditional blocks first) while at it.

Co-developed-by: Kévin L'hôpital 
Signed-off-by: Kévin L'hôpital 
Signed-off-by: Paul Kocialkowski 
Acked-by: Maxime Ripard 
---
 .../platform/sunxi/sun6i-csi/sun6i_csi.c  | 42 +++
 1 file changed, 25 insertions(+), 17 deletions(-)

diff --git a/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi.c 
b/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi.c
index 1a11a6174a17..d06028f42534 100644
--- a/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi.c
+++ b/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi.c
@@ -378,8 +378,13 @@ static void sun6i_csi_setup_bus(struct sun6i_csi_dev *sdev)
unsigned char bus_width;
u32 flags;
u32 cfg;
+   bool input_parallel = false;
bool input_interlaced = false;
 
+   if (endpoint->bus_type == V4L2_MBUS_PARALLEL ||
+   endpoint->bus_type == V4L2_MBUS_BT656)
+   input_parallel = true;
+
if (csi->config.field == V4L2_FIELD_INTERLACED
|| csi->config.field == V4L2_FIELD_INTERLACED_TB
|| csi->config.field == V4L2_FIELD_INTERLACED_BT)
@@ -395,6 +400,26 @@ static void sun6i_csi_setup_bus(struct sun6i_csi_dev *sdev)
 CSI_IF_CFG_HREF_POL_MASK | CSI_IF_CFG_FIELD_MASK |
 CSI_IF_CFG_SRC_TYPE_MASK);
 
+   if (input_parallel) {
+   switch (bus_width) {
+   case 8:
+   cfg |= CSI_IF_CFG_IF_DATA_WIDTH_8BIT;
+   break;
+   case 10:
+   cfg |= CSI_IF_CFG_IF_DATA_WIDTH_10BIT;
+   break;
+   case 12:
+   cfg |= CSI_IF_CFG_IF_DATA_WIDTH_12BIT;
+   break;
+   case 16: /* No need to configure DATA_WIDTH for 16bit */
+   break;
+   default:
+   dev_warn(sdev->dev, "Unsupported bus width: %u\n",
+bus_width);
+   break;
+   }
+   }
+
if (input_interlaced)
cfg |= CSI_IF_CFG_SRC_TYPE_INTERLACED;
else
@@ -440,23 +465,6 @@ static void sun6i_csi_setup_bus(struct sun6i_csi_dev *sdev)
break;
}
 
-   switch (bus_width) {
-   case 8:
-   cfg |= CSI_IF_CFG_IF_DATA_WIDTH_8BIT;
-   break;
-   case 10:
-   cfg |= CSI_IF_CFG_IF_DATA_WIDTH_10BIT;
-   break;
-   case 12:
-   cfg |= CSI_IF_CFG_IF_DATA_WIDTH_12BIT;
-   break;
-   case 16: /* No need to configure DATA_WIDTH for 16bit */
-   break;
-   default:
-   dev_warn(sdev->dev, "Unsupported bus width: %u\n", bus_width);
-   break;
-   }
-
regmap_write(sdev->regmap, CSI_IF_CFG_REG, cfg);
 }
 
-- 
2.30.0

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[PATCH v5 00/16] Allwinner MIPI CSI-2 support for A31/V3s/A83T

2021-01-15 Thread Paul Kocialkowski 
This series introduces support for MIPI CSI-2, with the A31 controller that is
found on most SoCs (A31, V3s and probably V5) as well as the A83T-specific
controller. While the former uses the same MIPI D-PHY that is already supported
for DSI, the latter embeds its own D-PHY.

In order to distinguish the use of the D-PHY between Rx mode (for MIPI CSI-2)
and Tx mode (for MIPI DSI), a submode is introduced for D-PHY in the PHY API.
This allows adding Rx support in the A31 D-PHY driver.

A few changes and fixes are applied to the A31 CSI controller driver, in order
to support the MIPI CSI-2 use-case.

Changes since v4:
- Added patch to stop using v4l2_async_notifier_parse_fwnode_endpoints;
- Fixed checkpatch strict issues (parenthesis alignment);
- Fixed runtime PM call order and disable;
- Fixed fwnode_handle_put order;
- Brought back phy-names for A31 since it's mandatory according to the generic
  PHY binding and needed by the code;
- Added collected tags.

Changes since v3:
- Fixed single-item phys description in sun6i mipi csi-2 binding;
- Fixed variables names in macros using container_of;
- Fixed style issue with operators at the end of lines;
- Reworked source endpoint/subdev assignment in sun6i-csi to handle
  link_validate error case;
- Removed unrelated dt change in sun8i-a83t mipi csi-2 driver;
- Added collected tags.

Changes since v2:
- added Kconfig depend on PM since it's not optional;
- removed phy-names for A31 MIPI CSI-2 controller;
- removed v3s compatible in the A31 MIPI CSI-2 controller driver;
- removed A31 CSI controller single-port binding deprecation;
- removed empty dt port definitions;
- fixed minor checkpatch warnings;
- added collected tags;
- added media-ctl output in cover letter.

Changes since v1:
- reworked fwnode and media graph on the CSI controller end to have one port
  per interface, which solves the bus type representation issue;
- removed unused IRQ handlers in the MIPI CSI-2 bridges;
- avoided the use of devm_regmap_init_mmio_clk;
- deasserted reset before enabling clocks;
- fixed reported return code issues (ret |=, missing checks);
- applied requested cosmetic changes (backward goto, etc);
- switched over to runtime PM for the mipi csi-2 bridge drivers;
- selected PHY_SUN6I_MIPI_DPHY in Kconfig for sun6i-mipi-csi2;
- registered nodes with mipi csi-2 bridge subdevs;
- used V4L2 format info instead of switch/case for sun6i-csi bpp;
- fixed device-tree bindings as requested (useless properties, license);
- fixed mipi bridge dt instances names;
- added PHY API documentation about mode/power on order requirement;
- fixed clock error return code in d-phy code;
- fixed D-PHY mode check in d-phy code;
- added MAINTAINERS entries for the new drivers;
- added V4L2 compliance results;
- added various comments and rework commit mesages as requested.

Media ctl outputs for the testing setups are available below:

# sun6i-csi + sun6i-mipi-csi2 + ov5648

Media device information

driver  sun6i-csi
model   Allwinner Video Capture Device
serial  
bus infoplatform:1cb.camera
hw revision 0x0
driver version  5.10.0

Device topology
- entity 1: sun6i-csi (2 pads, 1 link)
type Node subtype V4L flags 0
device node name /dev/video0
pad0: Sink
pad1: Sink
<- "sun6i-mipi-csi2":1 [ENABLED]

- entity 6: sun6i-mipi-csi2 (2 pads, 2 links)
type V4L2 subdev subtype Unknown flags 0
device node name /dev/v4l-subdev0
pad0: Sink
[fmt:unknown/0x0]
<- "ov5648 0-0036":0 [ENABLED,IMMUTABLE]
pad1: Source
[fmt:unknown/0x0]
-> "sun6i-csi":1 [ENABLED]

- entity 9: ov5648 0-0036 (1 pad, 1 link)
type V4L2 subdev subtype Sensor flags 0
device node name /dev/v4l-subdev1
pad0: Source
[fmt:SBGGR8_1X8/2592x1944@1/15 field:none colorspace:raw 
xfer:none ycbcr:601 quantization:full-range]
-> "sun6i-mipi-csi2":0 [ENABLED,IMMUTABLE]

# sun6i-csi + sun8i-a83t-mipi-csi2 + ov8865

Media device information

driver  sun6i-csi
model   Allwinner Video Capture Device
serial  
bus infoplatform:1cb.camera
hw revision 0x0
driver version  5.10.0

Device topology
- entity 1: sun6i-csi (2 pads, 1 link)
type Node subtype V4L flags 0
device node name /dev/video0
pad0: Sink
pad1: Sink
<- "sun8i-a83t-mipi-csi2":1 [ENABLED]

- entity 6: sun8i-a83t-mipi-csi2 (2 pads, 2 links)
type V4L2 subdev subtype Unknown flags 0
device node name /dev/v4l-subdev0
pad0: Sink
[fmt:unknown/0x0]
<- "ov8865 1-0036":0 [ENABLED,IMMUTABLE]
pad1: Source
[fmt:unknown/0x0]
-> "sun6i-csi":1 [ENABLED]

- entity 9: ov8865 1-0036 (1 pad, 1 link)
type V4L2

[PATCH v5 05/16] media: sun6i-csi: Use common V4L2 format info for storage bpp

2021-01-15 Thread Paul Kocialkowski 
V4L2 has a common helper which can be used for calculating the number
of stored bits per pixels of a given (stored) image format.

Use the helper-returned structure instead of our own switch/case list.
Note that a few formats are not in that list so we keep them as
special cases.

The custom switch/case was also wrong concerning 10/12-bit Bayer
formats, which are aligned to 16 bits in memory. Using the common
helper fixes it.

Fixes: 5cc7522d8965 ("media: sun6i: Add support for Allwinner CSI V3s")
Signed-off-by: Paul Kocialkowski 
Acked-by: Maxime Ripard 
---
 .../platform/sunxi/sun6i-csi/sun6i_csi.h  | 55 +++
 1 file changed, 20 insertions(+), 35 deletions(-)

diff --git a/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi.h 
b/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi.h
index 7f3389c70794..7cd23cd74685 100644
--- a/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi.h
+++ b/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi.h
@@ -87,53 +87,38 @@ void sun6i_csi_update_buf_addr(struct sun6i_csi *csi, 
dma_addr_t addr);
  */
 void sun6i_csi_set_stream(struct sun6i_csi *csi, bool enable);
 
-/* get bpp form v4l2 pixformat */
+/* get memory storage bpp from v4l2 pixformat */
 static inline int sun6i_csi_get_bpp(unsigned int pixformat)
 {
+   const struct v4l2_format_info *info;
+   unsigned int i;
+   int bpp = 0;
+
+   /* Handle special cases unknown to V4L2 format info first. */
switch (pixformat) {
-   case V4L2_PIX_FMT_SBGGR8:
-   case V4L2_PIX_FMT_SGBRG8:
-   case V4L2_PIX_FMT_SGRBG8:
-   case V4L2_PIX_FMT_SRGGB8:
case V4L2_PIX_FMT_JPEG:
return 8;
-   case V4L2_PIX_FMT_SBGGR10:
-   case V4L2_PIX_FMT_SGBRG10:
-   case V4L2_PIX_FMT_SGRBG10:
-   case V4L2_PIX_FMT_SRGGB10:
-   return 10;
-   case V4L2_PIX_FMT_SBGGR12:
-   case V4L2_PIX_FMT_SGBRG12:
-   case V4L2_PIX_FMT_SGRBG12:
-   case V4L2_PIX_FMT_SRGGB12:
case V4L2_PIX_FMT_HM12:
-   case V4L2_PIX_FMT_NV12:
-   case V4L2_PIX_FMT_NV21:
-   case V4L2_PIX_FMT_YUV420:
-   case V4L2_PIX_FMT_YVU420:
return 12;
-   case V4L2_PIX_FMT_YUYV:
-   case V4L2_PIX_FMT_YVYU:
-   case V4L2_PIX_FMT_UYVY:
-   case V4L2_PIX_FMT_VYUY:
-   case V4L2_PIX_FMT_NV16:
-   case V4L2_PIX_FMT_NV61:
-   case V4L2_PIX_FMT_YUV422P:
-   case V4L2_PIX_FMT_RGB565:
case V4L2_PIX_FMT_RGB565X:
return 16;
-   case V4L2_PIX_FMT_RGB24:
-   case V4L2_PIX_FMT_BGR24:
-   return 24;
-   case V4L2_PIX_FMT_RGB32:
-   case V4L2_PIX_FMT_BGR32:
-   return 32;
-   default:
+   }
+
+   info = v4l2_format_info(pixformat);
+   if (!info) {
WARN(1, "Unsupported pixformat: 0x%x\n", pixformat);
-   break;
+   return 0;
+   }
+
+   for (i = 0; i < info->comp_planes; i++) {
+   unsigned int hdiv = (i == 0) ? 1 : info->hdiv;
+   unsigned int vdiv = (i == 0) ? 1 : info->vdiv;
+
+   /* We return bits per pixel while V4L2 format info is bytes. */
+   bpp += 8 * info->bpp[i] / hdiv / vdiv;
}
 
-   return 0;
+   return bpp;
 }
 
 #endif /* __SUN6I_CSI_H__ */
-- 
2.30.0

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[PATCH v5 04/16] media: sun6i-csi: Stop using the deprecated fwnode endpoint parser

2021-01-15 Thread Paul Kocialkowski 
The v4l2_async_notifier_parse_fwnode_endpoints helper is getting
deprecated in favor of explicit parsing of the endpoints.

Implement it instead of using this deprecated function.

Since this was the last user of the helper, it should now be safe to
remove.

Signed-off-by: Paul Kocialkowski 
---
 .../platform/sunxi/sun6i-csi/sun6i_csi.c  | 69 ---
 .../platform/sunxi/sun6i-csi/sun6i_csi.h  |  1 +
 2 files changed, 44 insertions(+), 26 deletions(-)

diff --git a/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi.c 
b/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi.c
index c3b2f27b99d2..1a11a6174a17 100644
--- a/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi.c
+++ b/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi.c
@@ -693,28 +693,6 @@ static const struct v4l2_async_notifier_operations 
sun6i_csi_async_ops = {
.complete = sun6i_subdev_notify_complete,
 };
 
-static int sun6i_csi_fwnode_parse(struct device *dev,
- struct v4l2_fwnode_endpoint *vep,
- struct v4l2_async_subdev *asd)
-{
-   struct sun6i_csi *csi = dev_get_drvdata(dev);
-
-   if (vep->base.port || vep->base.id) {
-   dev_warn(dev, "Only support a single port with one endpoint\n");
-   return -ENOTCONN;
-   }
-
-   switch (vep->bus_type) {
-   case V4L2_MBUS_PARALLEL:
-   case V4L2_MBUS_BT656:
-   csi->v4l2_ep = *vep;
-   return 0;
-   default:
-   dev_err(dev, "Unsupported media bus type\n");
-   return -ENOTCONN;
-   }
-}
-
 static void sun6i_csi_v4l2_cleanup(struct sun6i_csi *csi)
 {
media_device_unregister(&csi->media_dev);
@@ -726,6 +704,48 @@ static void sun6i_csi_v4l2_cleanup(struct sun6i_csi *csi)
media_device_cleanup(&csi->media_dev);
 }
 
+static int sun6i_csi_v4l2_fwnode_init(struct sun6i_csi *csi)
+{
+   struct v4l2_fwnode_endpoint *endpoint = NULL;
+   struct fwnode_handle *handle = NULL;
+   int ret;
+
+   /* Parallel */
+
+   endpoint = &csi->v4l2_ep;
+   handle = fwnode_graph_get_endpoint_by_id(dev_fwnode(csi->dev), 0, 0,
+FWNODE_GRAPH_ENDPOINT_NEXT);
+   if (!handle)
+   return 0;
+
+   ret = v4l2_fwnode_endpoint_parse(handle, endpoint);
+   if (ret)
+   goto error;
+
+   if (endpoint->bus_type != V4L2_MBUS_PARALLEL &&
+   endpoint->bus_type != V4L2_MBUS_BT656) {
+   dev_err(csi->dev, "Unsupported parallel media bus type\n");
+   ret = -ENOTCONN;
+   goto error;
+   }
+
+   ret = v4l2_async_notifier_add_fwnode_remote_subdev(&csi->notifier,
+  handle,
+  &csi->subdev);
+   if (ret)
+   goto error;
+
+   fwnode_handle_put(handle);
+
+   return 0;
+
+error:
+   if (handle)
+   fwnode_handle_put(handle);
+
+   return ret;
+}
+
 static int sun6i_csi_v4l2_init(struct sun6i_csi *csi)
 {
int ret;
@@ -760,10 +780,7 @@ static int sun6i_csi_v4l2_init(struct sun6i_csi *csi)
if (ret)
goto unreg_v4l2;
 
-   ret = v4l2_async_notifier_parse_fwnode_endpoints(csi->dev,
-&csi->notifier,
-sizeof(struct 
v4l2_async_subdev),
-
sun6i_csi_fwnode_parse);
+   ret = sun6i_csi_v4l2_fwnode_init(csi);
if (ret)
goto clean_video;
 
diff --git a/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi.h 
b/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi.h
index c626821aaedb..7f3389c70794 100644
--- a/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi.h
+++ b/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi.h
@@ -38,6 +38,7 @@ struct sun6i_csi {
struct v4l2_device  v4l2_dev;
struct media_device media_dev;
 
+   struct v4l2_async_subdevsubdev;
struct v4l2_async_notifier  notifier;
 
/* video port settings */
-- 
2.30.0

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[PATCH v5 10/16] media: sunxi: Add support for the A31 MIPI CSI-2 controller

2021-01-15 Thread Paul Kocialkowski 
The A31 MIPI CSI-2 controller is a dedicated MIPI CSI-2 bridge
found on Allwinner SoCs such as the A31 and V3/V3s.

It is a standalone block, connected to the CSI controller on one side
and to the MIPI D-PHY block on the other. It has a dedicated address
space, interrupt line and clock.

It is represented as a V4L2 subdev to the CSI controller and takes a
MIPI CSI-2 sensor as its own subdev, all using the fwnode graph and
media controller API.

Only 8-bit and 10-bit Bayer formats are currently supported.
While up to 4 internal channels to the CSI controller exist, only one
is currently supported by this implementation.

Signed-off-by: Paul Kocialkowski 
Acked-by: Maxime Ripard 
---
 drivers/media/platform/sunxi/Kconfig  |   1 +
 drivers/media/platform/sunxi/Makefile |   1 +
 .../platform/sunxi/sun6i-mipi-csi2/Kconfig|  12 +
 .../platform/sunxi/sun6i-mipi-csi2/Makefile   |   4 +
 .../sunxi/sun6i-mipi-csi2/sun6i_mipi_csi2.c   | 600 ++
 .../sunxi/sun6i-mipi-csi2/sun6i_mipi_csi2.h   | 117 
 6 files changed, 735 insertions(+)
 create mode 100644 drivers/media/platform/sunxi/sun6i-mipi-csi2/Kconfig
 create mode 100644 drivers/media/platform/sunxi/sun6i-mipi-csi2/Makefile
 create mode 100644 
drivers/media/platform/sunxi/sun6i-mipi-csi2/sun6i_mipi_csi2.c
 create mode 100644 
drivers/media/platform/sunxi/sun6i-mipi-csi2/sun6i_mipi_csi2.h

diff --git a/drivers/media/platform/sunxi/Kconfig 
b/drivers/media/platform/sunxi/Kconfig
index 7151cc249afa..9684e07454ad 100644
--- a/drivers/media/platform/sunxi/Kconfig
+++ b/drivers/media/platform/sunxi/Kconfig
@@ -2,3 +2,4 @@
 
 source "drivers/media/platform/sunxi/sun4i-csi/Kconfig"
 source "drivers/media/platform/sunxi/sun6i-csi/Kconfig"
+source "drivers/media/platform/sunxi/sun6i-mipi-csi2/Kconfig"
diff --git a/drivers/media/platform/sunxi/Makefile 
b/drivers/media/platform/sunxi/Makefile
index fc537c9f5ca9..887a7cae8fca 100644
--- a/drivers/media/platform/sunxi/Makefile
+++ b/drivers/media/platform/sunxi/Makefile
@@ -2,5 +2,6 @@
 
 obj-y  += sun4i-csi/
 obj-y  += sun6i-csi/
+obj-y  += sun6i-mipi-csi2/
 obj-y  += sun8i-di/
 obj-y  += sun8i-rotate/
diff --git a/drivers/media/platform/sunxi/sun6i-mipi-csi2/Kconfig 
b/drivers/media/platform/sunxi/sun6i-mipi-csi2/Kconfig
new file mode 100644
index ..47f1bb0779a8
--- /dev/null
+++ b/drivers/media/platform/sunxi/sun6i-mipi-csi2/Kconfig
@@ -0,0 +1,12 @@
+# SPDX-License-Identifier: GPL-2.0-only
+config VIDEO_SUN6I_MIPI_CSI2
+   tristate "Allwinner A31 MIPI CSI-2 Controller Driver"
+   depends on ARCH_SUNXI || COMPILE_TEST
+   depends on PM && COMMON_CLK && VIDEO_V4L2
+   select REGMAP_MMIO
+   select PHY_SUN6I_MIPI_DPHY
+   select MEDIA_CONTROLLER
+   select VIDEO_V4L2_SUBDEV_API
+   select V4L2_FWNODE
+   help
+  Support for the Allwinner A31 MIPI CSI-2 Controller.
diff --git a/drivers/media/platform/sunxi/sun6i-mipi-csi2/Makefile 
b/drivers/media/platform/sunxi/sun6i-mipi-csi2/Makefile
new file mode 100644
index ..14e4e03818b5
--- /dev/null
+++ b/drivers/media/platform/sunxi/sun6i-mipi-csi2/Makefile
@@ -0,0 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0-only
+sun6i-mipi-csi2-y += sun6i_mipi_csi2.o
+
+obj-$(CONFIG_VIDEO_SUN6I_MIPI_CSI2) += sun6i-mipi-csi2.o
diff --git a/drivers/media/platform/sunxi/sun6i-mipi-csi2/sun6i_mipi_csi2.c 
b/drivers/media/platform/sunxi/sun6i-mipi-csi2/sun6i_mipi_csi2.c
new file mode 100644
index ..69186f0c35c2
--- /dev/null
+++ b/drivers/media/platform/sunxi/sun6i-mipi-csi2/sun6i_mipi_csi2.c
@@ -0,0 +1,600 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2020 Bootlin
+ * Author: Paul Kocialkowski 
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "sun6i_mipi_csi2.h"
+
+#define MODULE_NAME"sun6i-mipi-csi2"
+
+static const u32 sun6i_mipi_csi2_mbus_codes[] = {
+   MEDIA_BUS_FMT_SBGGR8_1X8,
+   MEDIA_BUS_FMT_SGBRG8_1X8,
+   MEDIA_BUS_FMT_SGRBG8_1X8,
+   MEDIA_BUS_FMT_SRGGB8_1X8,
+   MEDIA_BUS_FMT_SBGGR10_1X10,
+   MEDIA_BUS_FMT_SGBRG10_1X10,
+   MEDIA_BUS_FMT_SGRBG10_1X10,
+   MEDIA_BUS_FMT_SRGGB10_1X10,
+};
+
+/* Video */
+
+static int sun6i_mipi_csi2_s_stream(struct v4l2_subdev *subdev, int on)
+{
+   struct sun6i_mipi_csi2_video *video =
+   sun6i_mipi_csi2_subdev_video(subdev);
+   struct sun6i_mipi_csi2_dev *cdev = sun6i_mipi_csi2_video_dev(video);
+   struct v4l2_subdev *remote_subdev = video->remote_subdev;
+   struct v4l2_fwnode_bus_mipi_csi2 *bus_mipi_csi2 =
+   &video->endpoint.bus.mipi_csi2;
+   union phy_configure_opts dphy_opts = { 0 };
+   struct phy_configure_opts_mipi_dphy *dphy_cfg = &dphy_opts.mipi_dphy;
+   struct regmap *regmap = cdev->regmap;
+   struct v4l2_ctrl *ctrl;
+   unsigned int lanes_count;
+   unsigned

[PATCH v5 08/16] media: sun6i-csi: Add support for MIPI CSI-2 bridge input

2021-01-15 Thread Paul Kocialkowski 
The A31 CSI controller supports a MIPI CSI-2 bridge input, which has
its own dedicated port in the fwnode graph.

Support for this input is added with this change:
- two pads are defined for the media entity instead of one
  and only one needs to be connected at a time;
- the pads currently match the fwnode graph representation;
- links are created between our pads and the subdevs for each
  interface and are no longer immutable so that userspace can select
  which interface to use in case both are bound to a subdev;
- fwnode endpoints are parsed and stored for each interface;
- the active subdev (and fwnode endpoint) is retrieved when validating
  the media link at stream on time and cleared at stream off;
- an error is raised if both links are active at the same time;
- the MIPI interface bit is set if the MIPI CSI-2 bridge endpoint is
  active.

In the future, the media entity representation might evolve to:
- distinguish the internal parallel bridge and data formatter;
- represent each of the 4 internal channels that can exist between
  the parallel bridge (for BT656 time-multiplex) and MIPI CSI-2
  (internal channels can be mapped to virtual channels);
- connect the controller's output to the ISP instead of its
  DMA engine.

Finally note that the MIPI CSI-2 bridges should not be linked in
the fwnode graph unless they have a sensor subdev attached.

Signed-off-by: Paul Kocialkowski 
Acked-by: Maxime Ripard 
---
 .../platform/sunxi/sun6i-csi/sun6i_csi.c  | 111 +++---
 .../platform/sunxi/sun6i-csi/sun6i_csi.h  |   9 +-
 .../platform/sunxi/sun6i-csi/sun6i_video.c|  57 +
 .../platform/sunxi/sun6i-csi/sun6i_video.h|   7 +-
 4 files changed, 137 insertions(+), 47 deletions(-)

diff --git a/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi.c 
b/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi.c
index d06028f42534..55cac91f8282 100644
--- a/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi.c
+++ b/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi.c
@@ -49,6 +49,7 @@ static inline struct sun6i_csi_dev *sun6i_csi_to_dev(struct 
sun6i_csi *csi)
 
 /* TODO add 10&12 bit YUV, RGB support */
 bool sun6i_csi_is_format_supported(struct sun6i_csi *csi,
+  struct v4l2_fwnode_endpoint *endpoint,
   u32 pixformat, u32 mbus_code)
 {
struct sun6i_csi_dev *sdev = sun6i_csi_to_dev(csi);
@@ -58,9 +59,9 @@ bool sun6i_csi_is_format_supported(struct sun6i_csi *csi,
 * 8bit and 16bit bus width.
 * Identify the media bus format from device tree.
 */
-   if ((sdev->csi.v4l2_ep.bus_type == V4L2_MBUS_PARALLEL
-|| sdev->csi.v4l2_ep.bus_type == V4L2_MBUS_BT656)
-&& sdev->csi.v4l2_ep.bus.parallel.bus_width == 16) {
+   if ((endpoint->bus_type == V4L2_MBUS_PARALLEL ||
+endpoint->bus_type == V4L2_MBUS_BT656) &&
+   endpoint->bus.parallel.bus_width == 16) {
switch (pixformat) {
case V4L2_PIX_FMT_HM12:
case V4L2_PIX_FMT_NV12:
@@ -373,7 +374,7 @@ static enum csi_input_seq get_csi_input_seq(struct 
sun6i_csi_dev *sdev,
 
 static void sun6i_csi_setup_bus(struct sun6i_csi_dev *sdev)
 {
-   struct v4l2_fwnode_endpoint *endpoint = &sdev->csi.v4l2_ep;
+   struct v4l2_fwnode_endpoint *endpoint = sdev->csi.video.source_endpoint;
struct sun6i_csi *csi = &sdev->csi;
unsigned char bus_width;
u32 flags;
@@ -459,6 +460,9 @@ static void sun6i_csi_setup_bus(struct sun6i_csi_dev *sdev)
if (flags & V4L2_MBUS_PCLK_SAMPLE_FALLING)
cfg |= CSI_IF_CFG_CLK_POL_FALLING_EDGE;
break;
+   case V4L2_MBUS_CSI2_DPHY:
+   cfg |= CSI_IF_CFG_MIPI_IF_MIPI;
+   break;
default:
dev_warn(sdev->dev, "Unsupported bus type: %d\n",
 endpoint->bus_type);
@@ -636,11 +640,11 @@ void sun6i_csi_set_stream(struct sun6i_csi *csi, bool 
enable)
  * Media Controller and V4L2
  */
 static int sun6i_csi_link_entity(struct sun6i_csi *csi,
+struct media_pad *sink_pad,
 struct media_entity *entity,
-struct fwnode_handle *fwnode)
+struct fwnode_handle *fwnode, bool enabled)
 {
struct media_entity *sink;
-   struct media_pad *sink_pad;
int src_pad_index;
int ret;
 
@@ -654,14 +658,12 @@ static int sun6i_csi_link_entity(struct sun6i_csi *csi,
src_pad_index = ret;
 
sink = &csi->video.vdev.entity;
-   sink_pad = &csi->video.pad;
 
dev_dbg(csi->dev, "creating %s:%u -> %s:%u link\n",
entity->name, src_pad_index, sink->name, sink_pad->index);
ret = media_create_pad_link(entity, src_pad_index, sink,
sink_pad->index,
-   MEDIA_LNK_FL_ENABLED |
-

[PATCH v5 09/16] dt-bindings: media: Add A31 MIPI CSI-2 bindings documentation

2021-01-15 Thread Paul Kocialkowski 
This introduces YAML bindings documentation for the A31 MIPI CSI-2
controller.

Signed-off-by: Paul Kocialkowski 
Reviewed-by: Maxime Ripard 
Reviewed-by: Rob Herring 
---
 .../media/allwinner,sun6i-a31-mipi-csi2.yaml  | 156 ++
 1 file changed, 156 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/media/allwinner,sun6i-a31-mipi-csi2.yaml

diff --git 
a/Documentation/devicetree/bindings/media/allwinner,sun6i-a31-mipi-csi2.yaml 
b/Documentation/devicetree/bindings/media/allwinner,sun6i-a31-mipi-csi2.yaml
new file mode 100644
index ..309336b93a87
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/allwinner,sun6i-a31-mipi-csi2.yaml
@@ -0,0 +1,156 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/media/allwinner,sun6i-a31-mipi-csi2.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Allwinner A31 MIPI CSI-2 Device Tree Bindings
+
+maintainers:
+  - Paul Kocialkowski 
+
+properties:
+  compatible:
+oneOf:
+  - const: allwinner,sun6i-a31-mipi-csi2
+  - items:
+  - const: allwinner,sun8i-v3s-mipi-csi2
+  - const: allwinner,sun6i-a31-mipi-csi2
+
+  reg:
+maxItems: 1
+
+  interrupts:
+maxItems: 1
+
+  clocks:
+items:
+  - description: Bus Clock
+  - description: Module Clock
+
+  clock-names:
+items:
+  - const: bus
+  - const: mod
+
+  phys:
+maxItems: 1
+description: MIPI D-PHY
+
+  phy-names:
+items:
+  - const: dphy
+
+  resets:
+maxItems: 1
+
+  # See ./video-interfaces.txt for details
+  ports:
+type: object
+
+properties:
+  port@0:
+type: object
+description: Input port, connect to a MIPI CSI-2 sensor
+
+properties:
+  reg:
+const: 0
+
+  endpoint:
+type: object
+
+properties:
+  remote-endpoint: true
+
+  data-lanes:
+minItems: 1
+maxItems: 4
+
+required:
+  - data-lanes
+  - remote-endpoint
+
+required:
+  - endpoint
+
+additionalProperties: false
+
+  port@1:
+type: object
+description: Output port, connect to a CSI controller
+
+properties:
+  reg:
+const: 1
+
+  endpoint:
+type: object
+
+properties:
+  remote-endpoint: true
+
+required:
+  - remote-endpoint
+
+required:
+  - endpoint
+
+additionalProperties: false
+
+required:
+  - compatible
+  - reg
+  - interrupts
+  - clocks
+  - clock-names
+  - phys
+  - phy-names
+  - resets
+
+additionalProperties: false
+
+examples:
+  - |
+#include 
+#include 
+#include 
+
+mipi_csi2: csi@1cb1000 {
+compatible = "allwinner,sun8i-v3s-mipi-csi2",
+ "allwinner,sun6i-a31-mipi-csi2";
+reg = <0x01cb1000 0x1000>;
+interrupts = ;
+clocks = <&ccu CLK_BUS_CSI>,
+ <&ccu CLK_CSI1_SCLK>;
+clock-names = "bus", "mod";
+resets = <&ccu RST_BUS_CSI>;
+
+phys = <&dphy>;
+phy-names = "dphy";
+
+ports {
+#address-cells = <1>;
+#size-cells = <0>;
+
+mipi_csi2_in: port@0 {
+reg = <0>;
+
+mipi_csi2_in_ov5648: endpoint {
+data-lanes = <1 2 3 4>;
+
+remote-endpoint = <&ov5648_out_mipi_csi2>;
+};
+};
+
+mipi_csi2_out: port@1 {
+reg = <1>;
+
+mipi_csi2_out_csi0: endpoint {
+remote-endpoint = <&csi0_in_mipi_csi2>;
+};
+};
+};
+};
+
+...
-- 
2.30.0

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[PATCH v5 07/16] dt-bindings: media: sun6i-a31-csi: Add MIPI CSI-2 input port

2021-01-15 Thread Paul Kocialkowski 
The A31 CSI controller supports two distinct input interfaces:
parallel and an external MIPI CSI-2 bridge. The parallel interface
is often connected to a set of hardware pins while the MIPI CSI-2
bridge is an internal FIFO-ish link. As a result, these two inputs
are distinguished as two different ports.

Note that only one of the two may be present on a controller instance.
For example, the V3s has one controller dedicated to MIPI-CSI2 and one
dedicated to parallel.

Update the binding with an explicit ports node that holds two distinct
port nodes: one for parallel input and one for MIPI CSI-2.

This is backward-compatible with the single-port approach that was
previously taken for representing the parallel interface port, which
stays enumerated as fwnode port 0.

Note that additional ports may be added in the future, especially to
support feeding the CSI controller's output to the ISP.

Signed-off-by: Paul Kocialkowski 
Reviewed-by: Rob Herring 
Acked-by: Maxime Ripard 
---
 .../media/allwinner,sun6i-a31-csi.yaml| 88 ---
 1 file changed, 75 insertions(+), 13 deletions(-)

diff --git 
a/Documentation/devicetree/bindings/media/allwinner,sun6i-a31-csi.yaml 
b/Documentation/devicetree/bindings/media/allwinner,sun6i-a31-csi.yaml
index 1fd9b5532a21..77ded77505e9 100644
--- a/Documentation/devicetree/bindings/media/allwinner,sun6i-a31-csi.yaml
+++ b/Documentation/devicetree/bindings/media/allwinner,sun6i-a31-csi.yaml
@@ -67,6 +67,62 @@ properties:
 
 additionalProperties: false
 
+  ports:
+type: object
+
+properties:
+  port@0:
+type: object
+description: Parallel input port, connect to a parallel sensor
+
+properties:
+  reg:
+const: 0
+
+  endpoint:
+type: object
+
+properties:
+  remote-endpoint: true
+
+  bus-width:
+enum: [ 8, 10, 12, 16 ]
+
+  pclk-sample: true
+  hsync-active: true
+  vsync-active: true
+
+required:
+  - bus-width
+  - remote-endpoint
+
+required:
+  - endpoint
+
+additionalProperties: false
+
+  port@1:
+type: object
+description: MIPI CSI-2 bridge input port
+
+properties:
+  reg:
+const: 1
+
+  endpoint:
+type: object
+
+properties:
+  remote-endpoint: true
+
+required:
+  - remote-endpoint
+
+required:
+  - endpoint
+
+additionalProperties: false
+
 required:
   - compatible
   - reg
@@ -95,19 +151,25 @@ examples:
   "ram";
 resets = <&ccu RST_BUS_CSI>;
 
-port {
-/* Parallel bus endpoint */
-csi1_ep: endpoint {
-remote-endpoint = <&adv7611_ep>;
-bus-width = <16>;
-
-/*
- * If hsync-active/vsync-active are missing,
- * embedded BT.656 sync is used.
- */
- hsync-active = <0>; /* Active low */
- vsync-active = <0>; /* Active low */
- pclk-sample = <1>;  /* Rising */
+ports {
+#address-cells = <1>;
+#size-cells = <0>;
+
+port@0 {
+reg = <0>;
+/* Parallel bus endpoint */
+csi1_ep: endpoint {
+remote-endpoint = <&adv7611_ep>;
+bus-width = <16>;
+
+/*
+ * If hsync-active/vsync-active are missing,
+ * embedded BT.656 sync is used.
+ */
+ hsync-active = <0>; /* Active low */
+ vsync-active = <0>; /* Active low */
+ pclk-sample = <1>;  /* Rising */
+};
 };
 };
 };
-- 
2.30.0

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[PATCH v5 13/16] dt-bindings: media: Add A83T MIPI CSI-2 bindings documentation

2021-01-15 Thread Paul Kocialkowski 
This introduces YAML bindings documentation for the A83T MIPI CSI-2
controller.

Signed-off-by: Paul Kocialkowski 
Reviewed-by: Rob Herring 
---
 .../media/allwinner,sun8i-a83t-mipi-csi2.yaml | 147 ++
 1 file changed, 147 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/media/allwinner,sun8i-a83t-mipi-csi2.yaml

diff --git 
a/Documentation/devicetree/bindings/media/allwinner,sun8i-a83t-mipi-csi2.yaml 
b/Documentation/devicetree/bindings/media/allwinner,sun8i-a83t-mipi-csi2.yaml
new file mode 100644
index ..e607fae7d85e
--- /dev/null
+++ 
b/Documentation/devicetree/bindings/media/allwinner,sun8i-a83t-mipi-csi2.yaml
@@ -0,0 +1,147 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/media/allwinner,sun8i-a83t-mipi-csi2.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Allwinner A83T MIPI CSI-2 Device Tree Bindings
+
+maintainers:
+  - Paul Kocialkowski 
+
+properties:
+  compatible:
+const: allwinner,sun8i-a83t-mipi-csi2
+
+  reg:
+maxItems: 1
+
+  interrupts:
+maxItems: 1
+
+  clocks:
+items:
+  - description: Bus Clock
+  - description: Module Clock
+  - description: MIPI-specific Clock
+  - description: Misc CSI Clock
+
+  clock-names:
+items:
+  - const: bus
+  - const: mod
+  - const: mipi
+  - const: misc
+
+  resets:
+maxItems: 1
+
+  # See ./video-interfaces.txt for details
+  ports:
+type: object
+
+properties:
+  port@0:
+type: object
+description: Input port, connect to a MIPI CSI-2 sensor
+
+properties:
+  reg:
+const: 0
+
+  endpoint:
+type: object
+
+properties:
+  remote-endpoint: true
+
+  clock-lanes:
+maxItems: 1
+
+  data-lanes:
+minItems: 1
+maxItems: 4
+
+required:
+  - data-lanes
+  - remote-endpoint
+
+required:
+  - endpoint
+
+additionalProperties: false
+
+  port@1:
+type: object
+description: Output port, connect to a CSI controller
+
+properties:
+  reg:
+const: 1
+
+  endpoint:
+type: object
+
+properties:
+  remote-endpoint: true
+
+required:
+  - remote-endpoint
+
+required:
+  - endpoint
+
+additionalProperties: false
+
+required:
+  - compatible
+  - reg
+  - interrupts
+  - clocks
+  - clock-names
+  - resets
+
+additionalProperties: false
+
+examples:
+  - |
+#include 
+#include 
+#include 
+
+mipi_csi2: csi@1cb1000 {
+compatible = "allwinner,sun8i-a83t-mipi-csi2";
+reg = <0x01cb1000 0x1000>;
+interrupts = ;
+clocks = <&ccu CLK_BUS_CSI>,
+ <&ccu CLK_CSI_SCLK>,
+ <&ccu CLK_MIPI_CSI>,
+ <&ccu CLK_CSI_MISC>;
+clock-names = "bus", "mod", "mipi", "misc";
+resets = <&ccu RST_BUS_CSI>;
+
+ports {
+#address-cells = <1>;
+#size-cells = <0>;
+
+mipi_csi2_in: port@0 {
+reg = <0>;
+
+mipi_csi2_in_ov8865: endpoint {
+data-lanes = <1 2 3 4>;
+
+remote-endpoint = <&ov8865_out_mipi_csi2>;
+};
+};
+
+mipi_csi2_out: port@1 {
+reg = <1>;
+
+mipi_csi2_out_csi: endpoint {
+remote-endpoint = <&csi_in_mipi_csi2>;
+};
+};
+};
+};
+
+...
-- 
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[PATCH v5 11/16] ARM: dts: sun8i: v3s: Add nodes for MIPI CSI-2 support

2021-01-15 Thread Paul Kocialkowski 
MIPI CSI-2 is supported on the V3s with an A31-based MIPI CSI-2 bridge
controller. The controller uses a separate D-PHY, which is the same
that is otherwise used for MIPI DSI, but used in Rx mode.

On the V3s, the CSI0 controller is dedicated to MIPI CSI-2 as it does
not have access to any parallel interface pins.

Add all the necessary nodes (CSI0, MIPI CSI-2 bridge and D-PHY) to
support the MIPI CSI-2 interface.

Note that a fwnode graph link is created between CSI0 and MIPI CSI-2
even when no sensor is connected. This will result in a probe failure
for the controller as long as no sensor is connected but this is fine
since no other interface is available.

Signed-off-by: Paul Kocialkowski 
---
 arch/arm/boot/dts/sun8i-v3s.dtsi | 68 
 1 file changed, 68 insertions(+)

diff --git a/arch/arm/boot/dts/sun8i-v3s.dtsi b/arch/arm/boot/dts/sun8i-v3s.dtsi
index f8f19d8fa795..7eae0295ba73 100644
--- a/arch/arm/boot/dts/sun8i-v3s.dtsi
+++ b/arch/arm/boot/dts/sun8i-v3s.dtsi
@@ -530,6 +530,31 @@ spi0: spi@1c68000 {
#size-cells = <0>;
};
 
+   csi0: camera@1cb {
+   compatible = "allwinner,sun8i-v3s-csi";
+   reg = <0x01cb 0x1000>;
+   interrupts = ;
+   clocks = <&ccu CLK_BUS_CSI>,
+<&ccu CLK_CSI1_SCLK>,
+<&ccu CLK_DRAM_CSI>;
+   clock-names = "bus", "mod", "ram";
+   resets = <&ccu RST_BUS_CSI>;
+   status = "disabled";
+
+   ports {
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   port@1 {
+   reg = <1>;
+
+   csi0_in_mipi_csi2: endpoint {
+   remote-endpoint = 
<&mipi_csi2_out_csi0>;
+   };
+   };
+   };
+   };
+
csi1: camera@1cb4000 {
compatible = "allwinner,sun8i-v3s-csi";
reg = <0x01cb4000 0x3000>;
@@ -552,5 +577,48 @@ gic: interrupt-controller@1c81000 {
#interrupt-cells = <3>;
interrupts = ;
};
+
+   mipi_csi2: csi@1cb1000 {
+   compatible = "allwinner,sun8i-v3s-mipi-csi2",
+"allwinner,sun6i-a31-mipi-csi2";
+   reg = <0x01cb1000 0x1000>;
+   interrupts = ;
+   clocks = <&ccu CLK_BUS_CSI>,
+<&ccu CLK_CSI1_SCLK>;
+   clock-names = "bus", "mod";
+   resets = <&ccu RST_BUS_CSI>;
+   status = "disabled";
+
+   phys = <&dphy>;
+   phy-names = "dphy";
+
+   ports {
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   mipi_csi2_in: port@0 {
+   reg = <0>;
+   };
+
+   mipi_csi2_out: port@1 {
+   reg = <1>;
+
+   mipi_csi2_out_csi0: endpoint {
+   remote-endpoint = 
<&csi0_in_mipi_csi2>;
+   };
+   };
+   };
+   };
+
+   dphy: d-phy@1cb2000 {
+   compatible = "allwinner,sun6i-a31-mipi-dphy";
+   reg = <0x01cb2000 0x1000>;
+   clocks = <&ccu CLK_BUS_CSI>,
+<&ccu CLK_MIPI_CSI>;
+   clock-names = "bus", "mod";
+   resets = <&ccu RST_BUS_CSI>;
+   status = "disabled";
+   #phy-cells = <0>;
+   };
};
 };
-- 
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[PATCH v5 15/16] ARM: dts: sun8i: a83t: Add MIPI CSI-2 controller node

2021-01-15 Thread Paul Kocialkowski 
MIPI CSI-2 is supported on the A83T with a dedicated controller that
covers both the protocol and D-PHY. It can be connected to the CSI
interface as a V4L2 subdev through the fwnode graph.

This is not done by default since connecting the bridge without a
subdev attached to it will cause a failure on the CSI driver.

Signed-off-by: Paul Kocialkowski 
---
 arch/arm/boot/dts/sun8i-a83t.dtsi | 26 ++
 1 file changed, 26 insertions(+)

diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi 
b/arch/arm/boot/dts/sun8i-a83t.dtsi
index c010b27fdb6a..d6d55c12b995 100644
--- a/arch/arm/boot/dts/sun8i-a83t.dtsi
+++ b/arch/arm/boot/dts/sun8i-a83t.dtsi
@@ -1066,6 +1066,32 @@ csi_in: port {
};
};
 
+   mipi_csi2: csi@1cb1000 {
+   compatible = "allwinner,sun8i-a83t-mipi-csi2";
+   reg = <0x01cb1000 0x1000>;
+   interrupts = ;
+   clocks = <&ccu CLK_BUS_CSI>,
+<&ccu CLK_CSI_SCLK>,
+<&ccu CLK_MIPI_CSI>,
+<&ccu CLK_CSI_MISC>;
+   clock-names = "bus", "mod", "mipi", "misc";
+   resets = <&ccu RST_BUS_CSI>;
+   status = "disabled";
+
+   ports {
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   mipi_csi2_in: port@0 {
+   reg = <0>;
+   };
+
+   mipi_csi2_out: port@1 {
+   reg = <1>;
+   };
+   };
+   };
+
hdmi: hdmi@1ee {
compatible = "allwinner,sun8i-a83t-dw-hdmi";
reg = <0x01ee 0x1>;
-- 
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[PATCH v5 12/16] MAINTAINERS: Add entry for the Allwinner A31 MIPI CSI-2 bridge

2021-01-15 Thread Paul Kocialkowski 
Add myself as maintainer of the A31 MIPI CSI-2 bridge media driver.

Signed-off-by: Paul Kocialkowski 
---
 MAINTAINERS | 8 
 1 file changed, 8 insertions(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index 57f9e3047227..a41c41f6387c 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -710,6 +710,14 @@ T: git git://linuxtv.org/media_tree.git
 F: Documentation/devicetree/bindings/media/allwinner,sun4i-a10-csi.yaml
 F: drivers/media/platform/sunxi/sun4i-csi/
 
+ALLWINNER A31 MIPI CSI-2 BRIDGE
+M: Paul Kocialkowski 
+L: linux-me...@vger.kernel.org
+S: Maintained
+T: git git://linuxtv.org/media_tree.git
+F: 
Documentation/devicetree/bindings/media/allwinner,sun6i-a31-mipi-csi2.yaml
+F: drivers/media/platform/sunxi/sun6i-mipi-csi2/
+
 ALLWINNER CPUFREQ DRIVER
 M: Yangtao Li 
 L: linux...@vger.kernel.org
-- 
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[PATCH v5 14/16] media: sunxi: Add support for the A83T MIPI CSI-2 controller

2021-01-15 Thread Paul Kocialkowski 
The A83T supports MIPI CSI-2 with a composite controller, covering
both the protocol logic and the D-PHY implementation. This controller
seems to be found on the A83T only and probably was abandoned since.

This implementation splits the protocol and D-PHY registers and
uses the PHY framework internally. The D-PHY is not registered as a
standalone PHY driver since it cannot be used with any other
controller.

There are a few notable points about the controller:
- The initialisation sequence involes writing specific magic init
  values that do not seem to make any particular sense given the
  concerned register fields;
- Interrupts appear to be hitting regardless of the interrupt mask
  registers, which can cause a serious flood when transmission errors
  occur.

Only 8-bit and 10-bit Bayer formats are currently supported.
While up to 4 internal channels to the CSI controller exist, only one
is currently supported by this implementation.

This work is based on the first version of the driver submitted by
Kévin L'hôpital, which was adapted to mainline from the Allwinner BSP.
This version integrates MIPI CSI-2 support as a standalone V4L2 subdev
instead of merging it in the sun6i-csi driver.

It was tested on a Banana Pi M3 board with an OV8865 sensor in a 4-lane
configuration.

Signed-off-by: Paul Kocialkowski 
Acked-by: Maxime Ripard 
---
 drivers/media/platform/sunxi/Kconfig  |   1 +
 drivers/media/platform/sunxi/Makefile |   1 +
 .../sunxi/sun8i-a83t-mipi-csi2/Kconfig|  11 +
 .../sunxi/sun8i-a83t-mipi-csi2/Makefile   |   4 +
 .../sun8i-a83t-mipi-csi2/sun8i_a83t_dphy.c|  92 +++
 .../sun8i-a83t-mipi-csi2/sun8i_a83t_dphy.h|  39 +
 .../sun8i_a83t_mipi_csi2.c| 666 ++
 .../sun8i_a83t_mipi_csi2.h| 197 ++
 8 files changed, 1011 insertions(+)
 create mode 100644 drivers/media/platform/sunxi/sun8i-a83t-mipi-csi2/Kconfig
 create mode 100644 drivers/media/platform/sunxi/sun8i-a83t-mipi-csi2/Makefile
 create mode 100644 
drivers/media/platform/sunxi/sun8i-a83t-mipi-csi2/sun8i_a83t_dphy.c
 create mode 100644 
drivers/media/platform/sunxi/sun8i-a83t-mipi-csi2/sun8i_a83t_dphy.h
 create mode 100644 
drivers/media/platform/sunxi/sun8i-a83t-mipi-csi2/sun8i_a83t_mipi_csi2.c
 create mode 100644 
drivers/media/platform/sunxi/sun8i-a83t-mipi-csi2/sun8i_a83t_mipi_csi2.h

diff --git a/drivers/media/platform/sunxi/Kconfig 
b/drivers/media/platform/sunxi/Kconfig
index 9684e07454ad..db4c07be7e4c 100644
--- a/drivers/media/platform/sunxi/Kconfig
+++ b/drivers/media/platform/sunxi/Kconfig
@@ -3,3 +3,4 @@
 source "drivers/media/platform/sunxi/sun4i-csi/Kconfig"
 source "drivers/media/platform/sunxi/sun6i-csi/Kconfig"
 source "drivers/media/platform/sunxi/sun6i-mipi-csi2/Kconfig"
+source "drivers/media/platform/sunxi/sun8i-a83t-mipi-csi2/Kconfig"
diff --git a/drivers/media/platform/sunxi/Makefile 
b/drivers/media/platform/sunxi/Makefile
index 887a7cae8fca..9aa01cb01883 100644
--- a/drivers/media/platform/sunxi/Makefile
+++ b/drivers/media/platform/sunxi/Makefile
@@ -3,5 +3,6 @@
 obj-y  += sun4i-csi/
 obj-y  += sun6i-csi/
 obj-y  += sun6i-mipi-csi2/
+obj-y  += sun8i-a83t-mipi-csi2/
 obj-y  += sun8i-di/
 obj-y  += sun8i-rotate/
diff --git a/drivers/media/platform/sunxi/sun8i-a83t-mipi-csi2/Kconfig 
b/drivers/media/platform/sunxi/sun8i-a83t-mipi-csi2/Kconfig
new file mode 100644
index ..60e7a9c41065
--- /dev/null
+++ b/drivers/media/platform/sunxi/sun8i-a83t-mipi-csi2/Kconfig
@@ -0,0 +1,11 @@
+# SPDX-License-Identifier: GPL-2.0-only
+config VIDEO_SUN8I_A83T_MIPI_CSI2
+   tristate "Allwinner A83T MIPI CSI-2 Controller and D-PHY Driver"
+   depends on ARCH_SUNXI || COMPILE_TEST
+   depends on PM && COMMON_CLK && VIDEO_V4L2
+   select REGMAP_MMIO
+   select MEDIA_CONTROLLER
+   select VIDEO_V4L2_SUBDEV_API
+   select V4L2_FWNODE
+   help
+  Support for the Allwinner A83T MIPI CSI-2 Controller and D-PHY.
diff --git a/drivers/media/platform/sunxi/sun8i-a83t-mipi-csi2/Makefile 
b/drivers/media/platform/sunxi/sun8i-a83t-mipi-csi2/Makefile
new file mode 100644
index ..1427d15a879a
--- /dev/null
+++ b/drivers/media/platform/sunxi/sun8i-a83t-mipi-csi2/Makefile
@@ -0,0 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0-only
+sun8i-a83t-mipi-csi2-y += sun8i_a83t_mipi_csi2.o sun8i_a83t_dphy.o
+
+obj-$(CONFIG_VIDEO_SUN8I_A83T_MIPI_CSI2) += sun8i-a83t-mipi-csi2.o
diff --git 
a/drivers/media/platform/sunxi/sun8i-a83t-mipi-csi2/sun8i_a83t_dphy.c 
b/drivers/media/platform/sunxi/sun8i-a83t-mipi-csi2/sun8i_a83t_dphy.c
new file mode 100644
index ..c380065eb7c9
--- /dev/null
+++ b/drivers/media/platform/sunxi/sun8i-a83t-mipi-csi2/sun8i_a83t_dphy.c
@@ -0,0 +1,92 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2020 Bootlin
+ * Author: Paul Kocialkowski 
+ */
+
+#include 
+#include 
+
+#include "sun8i_a83t_dphy.h"
+#include "sun8i_a83t_mipi_csi

[PATCH v5 16/16] MAINTAINERS: Add entry for the Allwinner A83T MIPI CSI-2 bridge

2021-01-15 Thread Paul Kocialkowski 
Add myself as maintainer of the A83T MIPI CSI-2 bridge media driver.

Signed-off-by: Paul Kocialkowski 
---
 MAINTAINERS | 8 
 1 file changed, 8 insertions(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index a41c41f6387c..af8095085f0f 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -718,6 +718,14 @@ T: git git://linuxtv.org/media_tree.git
 F: 
Documentation/devicetree/bindings/media/allwinner,sun6i-a31-mipi-csi2.yaml
 F: drivers/media/platform/sunxi/sun6i-mipi-csi2/
 
+ALLWINNER A83T MIPI CSI-2 BRIDGE
+M: Paul Kocialkowski 
+L: linux-me...@vger.kernel.org
+S: Maintained
+T: git git://linuxtv.org/media_tree.git
+F: 
Documentation/devicetree/bindings/media/allwinner,sun8i-a83t-mipi-csi2.yaml
+F: drivers/media/platform/sunxi/sun8i-a83t-mipi-csi2/
+
 ALLWINNER CPUFREQ DRIVER
 M: Yangtao Li 
 L: linux...@vger.kernel.org
-- 
2.30.0

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