[PATCH] staging: rts5208: Fixed 80 char & indent warnings
This patch fixes the 80 char length warnings and an indent suspect warning
identified by the checkpath.pl script for the entire ms.c file leaving
with no more warnings or errors left to be fixed for it.
Signed-off-by: Ragavendra Nagraj
---
drivers/staging/rts5208/ms.c | 43 +-
1 file changed, 26 insertions(+), 17 deletions(-)
diff --git a/drivers/staging/rts5208/ms.c b/drivers/staging/rts5208/ms.c
index 4c38ff9..d645d76 100644
--- a/drivers/staging/rts5208/ms.c
+++ b/drivers/staging/rts5208/ms.c
@@ -916,7 +916,7 @@ static int ms_read_attribute_info(struct rtsx_chip *chip)
#else
if (buf[cur_addr_off + 8] == 0x10)
#endif
- {
+ {
sys_info_addr = ((u32)buf[cur_addr_off + 0] << 24) |
((u32)buf[cur_addr_off + 1] << 16) |
((u32)buf[cur_addr_off + 2] << 8) |
@@ -2382,7 +2382,7 @@ static int ms_build_l2p_tbl(struct rtsx_chip *chip, int
seg_no)
phy_blk = ms_get_unused_block(chip, 0);
retval = ms_copy_page(chip, tmp_blk, phy_blk,
- log_blk, 0, ms_card->page_off +
1);
+ log_blk, 0, ms_card->page_off + 1);
if (retval != STATUS_SUCCESS)
TRACE_RET(chip, STATUS_FAIL);
@@ -2582,11 +2582,11 @@ static int mspro_rw_multi_sector(struct scsi_cmnd *srb,
if (ms_card->seq_mode) {
if ((ms_card->pre_dir != srb->sc_data_direction)
- || ((ms_card->pre_sec_addr +
ms_card->pre_sec_cnt) != start_sector)
- || (mode_2k && (ms_card->seq_mode &
MODE_512_SEQ))
- || (!mode_2k && (ms_card->seq_mode &
MODE_2K_SEQ))
- || !(val & MS_INT_BREQ)
- || ((ms_card->total_sec_cnt + sector_cnt) >
0xFE00)) {
+ || ((ms_card->pre_sec_addr + ms_card->pre_sec_cnt) != start_sector)
+ || (mode_2k && (ms_card->seq_mode & MODE_512_SEQ))
+ || (!mode_2k && (ms_card->seq_mode & MODE_2K_SEQ))
+ || !(val & MS_INT_BREQ)
+ || ((ms_card->total_sec_cnt + sector_cnt) > 0xFE00)) {
ms_card->seq_mode = 0;
ms_card->total_sec_cnt = 0;
if (val & MS_INT_BREQ) {
@@ -2594,7 +2594,7 @@ static int mspro_rw_multi_sector(struct scsi_cmnd *srb,
if (retval != STATUS_SUCCESS)
TRACE_RET(chip, STATUS_FAIL);
- rtsx_write_register(chip, RBCTL, RB_FLUSH,
RB_FLUSH);
+ rtsx_write_register(chip, RBCTL, RB_FLUSH, RB_FLUSH);
}
}
}
@@ -2684,7 +2684,8 @@ static int mspro_read_format_progress(struct rtsx_chip
*chip,
}
if (!(tmp & MS_INT_BREQ)) {
- if ((tmp & (MS_INT_CED | MS_INT_BREQ | MS_INT_CMDNK |
MS_INT_ERR)) == MS_INT_CED) {
+ if ((tmp & (MS_INT_CED | MS_INT_BREQ | MS_INT_CMDNK
+ | MS_INT_ERR)) == MS_INT_CED) {
ms_card->format_status = FORMAT_SUCCESS;
return STATUS_SUCCESS;
}
@@ -2938,11 +2939,15 @@ static int ms_read_multiple_pages(struct rtsx_chip
*chip, u16 phy_blk,
if (retval != STATUS_SUCCESS) {
if (!(chip->card_wp & MS_CARD)) {
reset_ms(chip);
- ms_set_page_status(log_blk,
setPS_NG, extra, MS_EXTRA_SIZE);
- ms_write_extra_data(chip,
phy_blk,
- page_addr,
extra, MS_EXTRA_SIZE);
+ ms_set_page_status(log_blk,
+ setPS_NG,
+ extra, MS_EXTRA_SIZE);
+ ms_write_extra_data(chip,
+ phy_blk, page_addr,
+ extra, MS_EXTRA_SIZE);
}
- ms_set_err_code(chip,
MS_FLASH_READ_ERROR);
+ ms_set_err_code(chip,
+ MS_FLASH_READ_ERROR);
TRACE_RET(chip, STATUS_FAIL);
[PATCH] staging: sm750fb: Fixed C99 comments warnings
This patch fixes the C99-style "// ..." comments warnings identified by the
checkpath.pl script for the entire ddk750_chip.c file by using the
appropriate C89 "/* ... */" style comments accordingly.
Signed-off-by: Ragavendra Nagraj
---
drivers/staging/sm750fb/ddk750_chip.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/staging/sm750fb/ddk750_chip.c
b/drivers/staging/sm750fb/ddk750_chip.c
index 02f9326..1fb00a4 100644
--- a/drivers/staging/sm750fb/ddk750_chip.c
+++ b/drivers/staging/sm750fb/ddk750_chip.c
@@ -17,7 +17,7 @@ logical_chip_type_t getChipType(void)
char physicalRev;
logical_chip_type_t chip;
- physicalID = devId750;//either 0x718 or 0x750
+ physicalID = devId750;/*either 0x718 or 0x750*/
physicalRev = revId750;
if (physicalID == 0x718)
@@ -264,7 +264,7 @@ int ddk750_initHw(initchip_param_t * pInitParam)
unsigned int ulReg;
#if 0
- //move the code to map regiter function.
+ /*move the code to map regiter function.*/
if(getChipType() == SM718){
/* turn on big endian bit*/
ulReg = PEEK32(0x74);
@@ -501,7 +501,7 @@ unsigned int calcPllValue(unsigned int
request_orig,pll_value_t *pll)
}
}
- //printk("Finally:
pll->n[%lu],m[%lu],od[%lu],pod[%lu]\n",pll->N,pll->M,pll->OD,pll->POD);
+ /*printk("Finally:
pll->n[%lu],m[%lu],od[%lu],pod[%lu]\n",pll->N,pll->M,pll->OD,pll->POD);*/
return ret;
}
@@ -597,13 +597,13 @@ pll_value_t *pPLL /* Structure to hold the
value to be set in PLL */
}
/* Restore input frequency from Khz to hz unit */
-//pPLL->inputFreq *= 1000;
+/*pPLL->inputFreq *= 1000;*/
ulRequestClk *= 1000;
pPLL->inputFreq = DEFAULT_INPUT_CLOCK; /* Default reference clock */
/* Output debug information */
- //DDKDEBUGPRINT((DISPLAY_LEVEL, "calcPllValue: Requested Frequency =
%d\n", ulRequestClk));
- //DDKDEBUGPRINT((DISPLAY_LEVEL, "calcPllValue: Input CLK = %dHz, M=%d,
N=%d, OD=%d, POD=%d\n", pPLL->inputFreq, pPLL->M, pPLL->N, pPLL->OD,
pPLL->POD));
+ /*DDKDEBUGPRINT((DISPLAY_LEVEL, "calcPllValue: Requested Frequency =
%d\n", ulRequestClk));*/
+ /*DDKDEBUGPRINT((DISPLAY_LEVEL, "calcPllValue: Input CLK = %dHz, M=%d,
N=%d, OD=%d, POD=%d\n", pPLL->inputFreq, pPLL->M, pPLL->N, pPLL->OD,
pPLL->POD));*/
/* Return actual frequency that the PLL can set */
ret = calcPLL(pPLL);
--
1.7.10.4
___
devel mailing list
de...@linuxdriverproject.org
http://driverdev.linuxdriverproject.org/mailman/listinfo/driverdev-devel
[PATCH v5] staging: sm750fb: Fixed no space and indent warns
This patch fixes the no spaces and indent warnings identified by the
checkpath.pl script for the entire ddk750_chip.c file by using
appropriate tab spaces and indents accordingly.
Signed-off-by: Ragavendra Nagraj
---
Changes in v5:
- Created patch for latest staging-next branch.
drivers/staging/sm750fb/ddk750_chip.c | 460 -
1 file changed, 230 insertions(+), 230 deletions(-)
diff --git a/drivers/staging/sm750fb/ddk750_chip.c
b/drivers/staging/sm750fb/ddk750_chip.c
index 33add64..02f9326 100644
--- a/drivers/staging/sm750fb/ddk750_chip.c
+++ b/drivers/staging/sm750fb/ddk750_chip.c
@@ -20,22 +20,22 @@ logical_chip_type_t getChipType(void)
physicalID = devId750;//either 0x718 or 0x750
physicalRev = revId750;
-if (physicalID == 0x718)
-{
-chip = SM718;
-}
-else if (physicalID == 0x750)
-{
-chip = SM750;
+ if (physicalID == 0x718)
+ {
+ chip = SM718;
+ }
+ else if (physicalID == 0x750)
+ {
+ chip = SM750;
/* SM750 and SM750LE are different in their revision ID only. */
if (physicalRev == SM750LE_REVISION_ID){
chip = SM750LE;
}
-}
-else
-{
-chip = SM_UNKNOWN;
-}
+ }
+ else
+ {
+ chip = SM_UNKNOWN;
+ }
return chip;
}
@@ -43,63 +43,63 @@ logical_chip_type_t getChipType(void)
inline unsigned int twoToPowerOfx(unsigned long x)
{
-unsigned long i;
-unsigned long result = 1;
+ unsigned long i;
+ unsigned long result = 1;
-for (i=1; i<=x; i++)
-result *= 2;
-return result;
+ for (i=1; i<=x; i++)
+ result *= 2;
+ return result;
}
inline unsigned int calcPLL(pll_value_t *pPLL)
{
-return (pPLL->inputFreq * pPLL->M / pPLL->N / twoToPowerOfx(pPLL->OD) /
twoToPowerOfx(pPLL->POD));
+ return (pPLL->inputFreq * pPLL->M / pPLL->N / twoToPowerOfx(pPLL->OD) /
twoToPowerOfx(pPLL->POD));
}
unsigned int getPllValue(clock_type_t clockType, pll_value_t *pPLL)
{
-unsigned int ulPllReg = 0;
-
-pPLL->inputFreq = DEFAULT_INPUT_CLOCK;
-pPLL->clockType = clockType;
-
-switch (clockType)
-{
-case MXCLK_PLL:
-ulPllReg = PEEK32(MXCLK_PLL_CTRL);
-break;
-case PRIMARY_PLL:
-ulPllReg = PEEK32(PANEL_PLL_CTRL);
-break;
-case SECONDARY_PLL:
-ulPllReg = PEEK32(CRT_PLL_CTRL);
-break;
-case VGA0_PLL:
-ulPllReg = PEEK32(VGA_PLL0_CTRL);
-break;
-case VGA1_PLL:
-ulPllReg = PEEK32(VGA_PLL1_CTRL);
-break;
-}
-
-pPLL->M = FIELD_GET(ulPllReg, PANEL_PLL_CTRL, M);
-pPLL->N = FIELD_GET(ulPllReg, PANEL_PLL_CTRL, N);
-pPLL->OD = FIELD_GET(ulPllReg, PANEL_PLL_CTRL, OD);
-pPLL->POD = FIELD_GET(ulPllReg, PANEL_PLL_CTRL, POD);
-
-return calcPLL(pPLL);
+ unsigned int ulPllReg = 0;
+
+ pPLL->inputFreq = DEFAULT_INPUT_CLOCK;
+ pPLL->clockType = clockType;
+
+ switch (clockType)
+ {
+ case MXCLK_PLL:
+ ulPllReg = PEEK32(MXCLK_PLL_CTRL);
+ break;
+ case PRIMARY_PLL:
+ ulPllReg = PEEK32(PANEL_PLL_CTRL);
+ break;
+ case SECONDARY_PLL:
+ ulPllReg = PEEK32(CRT_PLL_CTRL);
+ break;
+ case VGA0_PLL:
+ ulPllReg = PEEK32(VGA_PLL0_CTRL);
+ break;
+ case VGA1_PLL:
+ ulPllReg = PEEK32(VGA_PLL1_CTRL);
+ break;
+ }
+
+ pPLL->M = FIELD_GET(ulPllReg, PANEL_PLL_CTRL, M);
+ pPLL->N = FIELD_GET(ulPllReg, PANEL_PLL_CTRL, N);
+ pPLL->OD = FIELD_GET(ulPllReg, PANEL_PLL_CTRL, OD);
+ pPLL->POD = FIELD_GET(ulPllReg, PANEL_PLL_CTRL, POD);
+
+ return calcPLL(pPLL);
}
unsigned int getChipClock(void)
{
-pll_value_t pll;
+ pll_value_t pll;
#if 1
if(getChipType() == SM750LE)
return MHz(130);
#endif
-return getPllValue(MXCLK_PLL, &pll);
+ return getPllValue(MXCLK_PLL, &pll);
}
@@ -110,75 +110,75 @@ unsigned int getChipClock(void)
*/
void setChipClock(unsigned int frequency)
{
-pll_value_t pll;
-unsigned int ulActualMxClk;
+ pll_value_t pll;
+ unsigned int ulActualMxClk;
#if 1
- /* Cheok_0509: For SM750LE, the chip clock is fixed. Nothing to
set. */
- if (getChipType() == SM750LE)
- return;
+ /* Cheok_0509: For SM750LE, the chip clock is fixed. Nothing to set. */
+ if (getChipType() == SM750LE)
+ return;
#endif
-if (frequency != 0)
-{
-/*
- * Set up PLL, a structure to hold the value to be set in clocks.
[PATCH v4] staging: sm750fb: Fixed no space and indent warns
This patch fixes the no spaces and indent warnings identified by the
checkpath.pl script for the entire ddk750_chip.c file by using
appropriate tab spaces and indents accordingly.
Signed-off-by: Ragavendra Nagraj
---
drivers/staging/sm750fb/ddk750_chip.c | 462 -
1 file changed, 231 insertions(+), 231 deletions(-)
diff --git a/drivers/staging/sm750fb/ddk750_chip.c
b/drivers/staging/sm750fb/ddk750_chip.c
index b71169e..fd78b17 100644
--- a/drivers/staging/sm750fb/ddk750_chip.c
+++ b/drivers/staging/sm750fb/ddk750_chip.c
@@ -20,22 +20,22 @@ logical_chip_type_t getChipType()
physicalID = devId750;//either 0x718 or 0x750
physicalRev = revId750;
-if (physicalID == 0x718)
-{
-chip = SM718;
-}
-else if (physicalID == 0x750)
-{
-chip = SM750;
+ if (physicalID == 0x718)
+ {
+ chip = SM718;
+ }
+ else if (physicalID == 0x750)
+ {
+ chip = SM750;
/* SM750 and SM750LE are different in their revision ID only. */
if (physicalRev == SM750LE_REVISION_ID){
chip = SM750LE;
}
-}
-else
-{
-chip = SM_UNKNOWN;
-}
+ }
+ else
+ {
+ chip = SM_UNKNOWN;
+ }
return chip;
}
@@ -43,63 +43,63 @@ logical_chip_type_t getChipType()
inline unsigned int twoToPowerOfx(unsigned long x)
{
-unsigned long i;
-unsigned long result = 1;
+ unsigned long i;
+ unsigned long result = 1;
-for (i=1; i<=x; i++)
-result *= 2;
-return result;
+ for (i=1; i<=x; i++)
+ result *= 2;
+ return result;
}
inline unsigned int calcPLL(pll_value_t *pPLL)
{
-return (pPLL->inputFreq * pPLL->M / pPLL->N / twoToPowerOfx(pPLL->OD) /
twoToPowerOfx(pPLL->POD));
+ return (pPLL->inputFreq * pPLL->M / pPLL->N / twoToPowerOfx(pPLL->OD) /
twoToPowerOfx(pPLL->POD));
}
unsigned int getPllValue(clock_type_t clockType, pll_value_t *pPLL)
{
-unsigned int ulPllReg = 0;
-
-pPLL->inputFreq = DEFAULT_INPUT_CLOCK;
-pPLL->clockType = clockType;
-
-switch (clockType)
-{
-case MXCLK_PLL:
-ulPllReg = PEEK32(MXCLK_PLL_CTRL);
-break;
-case PRIMARY_PLL:
-ulPllReg = PEEK32(PANEL_PLL_CTRL);
-break;
-case SECONDARY_PLL:
-ulPllReg = PEEK32(CRT_PLL_CTRL);
-break;
-case VGA0_PLL:
-ulPllReg = PEEK32(VGA_PLL0_CTRL);
-break;
-case VGA1_PLL:
-ulPllReg = PEEK32(VGA_PLL1_CTRL);
-break;
-}
-
-pPLL->M = FIELD_GET(ulPllReg, PANEL_PLL_CTRL, M);
-pPLL->N = FIELD_GET(ulPllReg, PANEL_PLL_CTRL, N);
-pPLL->OD = FIELD_GET(ulPllReg, PANEL_PLL_CTRL, OD);
-pPLL->POD = FIELD_GET(ulPllReg, PANEL_PLL_CTRL, POD);
-
-return calcPLL(pPLL);
+ unsigned int ulPllReg = 0;
+
+ pPLL->inputFreq = DEFAULT_INPUT_CLOCK;
+ pPLL->clockType = clockType;
+
+ switch (clockType)
+ {
+ case MXCLK_PLL:
+ ulPllReg = PEEK32(MXCLK_PLL_CTRL);
+ break;
+ case PRIMARY_PLL:
+ ulPllReg = PEEK32(PANEL_PLL_CTRL);
+ break;
+ case SECONDARY_PLL:
+ ulPllReg = PEEK32(CRT_PLL_CTRL);
+ break;
+ case VGA0_PLL:
+ ulPllReg = PEEK32(VGA_PLL0_CTRL);
+ break;
+ case VGA1_PLL:
+ ulPllReg = PEEK32(VGA_PLL1_CTRL);
+ break;
+ }
+
+ pPLL->M = FIELD_GET(ulPllReg, PANEL_PLL_CTRL, M);
+ pPLL->N = FIELD_GET(ulPllReg, PANEL_PLL_CTRL, N);
+ pPLL->OD = FIELD_GET(ulPllReg, PANEL_PLL_CTRL, OD);
+ pPLL->POD = FIELD_GET(ulPllReg, PANEL_PLL_CTRL, POD);
+
+ return calcPLL(pPLL);
}
unsigned int getChipClock()
{
-pll_value_t pll;
+ pll_value_t pll;
#if 1
if(getChipType() == SM750LE)
return MHz(130);
#endif
-return getPllValue(MXCLK_PLL, &pll);
+ return getPllValue(MXCLK_PLL, &pll);
}
@@ -110,75 +110,75 @@ unsigned int getChipClock()
*/
void setChipClock(unsigned int frequency)
{
-pll_value_t pll;
-unsigned int ulActualMxClk;
+ pll_value_t pll;
+ unsigned int ulActualMxClk;
#if 1
- /* Cheok_0509: For SM750LE, the chip clock is fixed. Nothing to
set. */
- if (getChipType() == SM750LE)
- return;
+ /* Cheok_0509: For SM750LE, the chip clock is fixed. Nothing to set. */
+ if (getChipType() == SM750LE)
+ return;
#endif
-if (frequency != 0)
-{
-/*
- * Set up PLL, a structure to hold the value to be set in clocks.
- */
-pll.inputFreq = DEFAULT_INPUT_CLOCK; /* Defined in CLOCK.H */
-pll.clockType
[PATCH] staging:sm750fb:Fixed no space and indent warnings
This patch fixes the no spaces and indent warnings identified by the
checkpath.pl script for the entire ddk750_chip.c file by using appropriate tab
spaces and indents accordingly.
Signed-off-by: Ragavendra Nagraj
---
drivers/staging/sm750fb/ddk750_chip.c | 454 -
1 file changed, 227 insertions(+), 227 deletions(-)
diff --git a/drivers/staging/sm750fb/ddk750_chip.c
b/drivers/staging/sm750fb/ddk750_chip.c
index b71169e..5c9a118 100644
--- a/drivers/staging/sm750fb/ddk750_chip.c
+++ b/drivers/staging/sm750fb/ddk750_chip.c
@@ -20,22 +20,22 @@ logical_chip_type_t getChipType()
physicalID = devId750;//either 0x718 or 0x750
physicalRev = revId750;
-if (physicalID == 0x718)
-{
-chip = SM718;
-}
-else if (physicalID == 0x750)
-{
-chip = SM750;
+ if (physicalID == 0x718)
+ {
+ chip = SM718;
+ }
+ else if (physicalID == 0x750)
+ {
+ chip = SM750;
/* SM750 and SM750LE are different in their revision ID only. */
if (physicalRev == SM750LE_REVISION_ID){
chip = SM750LE;
}
-}
-else
-{
-chip = SM_UNKNOWN;
-}
+ }
+ else
+ {
+ chip = SM_UNKNOWN;
+ }
return chip;
}
@@ -43,63 +43,63 @@ logical_chip_type_t getChipType()
inline unsigned int twoToPowerOfx(unsigned long x)
{
-unsigned long i;
-unsigned long result = 1;
+ unsigned long i;
+ unsigned long result = 1;
-for (i=1; i<=x; i++)
-result *= 2;
-return result;
+ for (i=1; i<=x; i++)
+ result *= 2;
+ return result;
}
inline unsigned int calcPLL(pll_value_t *pPLL)
{
-return (pPLL->inputFreq * pPLL->M / pPLL->N / twoToPowerOfx(pPLL->OD) /
twoToPowerOfx(pPLL->POD));
+ return (pPLL->inputFreq * pPLL->M / pPLL->N / twoToPowerOfx(pPLL->OD) /
twoToPowerOfx(pPLL->POD));
}
unsigned int getPllValue(clock_type_t clockType, pll_value_t *pPLL)
{
-unsigned int ulPllReg = 0;
-
-pPLL->inputFreq = DEFAULT_INPUT_CLOCK;
-pPLL->clockType = clockType;
-
-switch (clockType)
-{
-case MXCLK_PLL:
-ulPllReg = PEEK32(MXCLK_PLL_CTRL);
-break;
-case PRIMARY_PLL:
-ulPllReg = PEEK32(PANEL_PLL_CTRL);
-break;
-case SECONDARY_PLL:
-ulPllReg = PEEK32(CRT_PLL_CTRL);
-break;
-case VGA0_PLL:
-ulPllReg = PEEK32(VGA_PLL0_CTRL);
-break;
-case VGA1_PLL:
-ulPllReg = PEEK32(VGA_PLL1_CTRL);
-break;
-}
-
-pPLL->M = FIELD_GET(ulPllReg, PANEL_PLL_CTRL, M);
-pPLL->N = FIELD_GET(ulPllReg, PANEL_PLL_CTRL, N);
-pPLL->OD = FIELD_GET(ulPllReg, PANEL_PLL_CTRL, OD);
-pPLL->POD = FIELD_GET(ulPllReg, PANEL_PLL_CTRL, POD);
-
-return calcPLL(pPLL);
+ unsigned int ulPllReg = 0;
+
+ pPLL->inputFreq = DEFAULT_INPUT_CLOCK;
+ pPLL->clockType = clockType;
+
+ switch (clockType)
+ {
+ case MXCLK_PLL:
+ ulPllReg = PEEK32(MXCLK_PLL_CTRL);
+ break;
+ case PRIMARY_PLL:
+ ulPllReg = PEEK32(PANEL_PLL_CTRL);
+ break;
+ case SECONDARY_PLL:
+ ulPllReg = PEEK32(CRT_PLL_CTRL);
+ break;
+ case VGA0_PLL:
+ ulPllReg = PEEK32(VGA_PLL0_CTRL);
+ break;
+ case VGA1_PLL:
+ ulPllReg = PEEK32(VGA_PLL1_CTRL);
+ break;
+ }
+
+ pPLL->M = FIELD_GET(ulPllReg, PANEL_PLL_CTRL, M);
+ pPLL->N = FIELD_GET(ulPllReg, PANEL_PLL_CTRL, N);
+ pPLL->OD = FIELD_GET(ulPllReg, PANEL_PLL_CTRL, OD);
+ pPLL->POD = FIELD_GET(ulPllReg, PANEL_PLL_CTRL, POD);
+
+ return calcPLL(pPLL);
}
unsigned int getChipClock()
{
-pll_value_t pll;
+ pll_value_t pll;
#if 1
if(getChipType() == SM750LE)
return MHz(130);
#endif
-return getPllValue(MXCLK_PLL, &pll);
+ return getPllValue(MXCLK_PLL, &pll);
}
@@ -110,75 +110,75 @@ unsigned int getChipClock()
*/
void setChipClock(unsigned int frequency)
{
-pll_value_t pll;
-unsigned int ulActualMxClk;
+ pll_value_t pll;
+ unsigned int ulActualMxClk;
#if 1
/* Cheok_0509: For SM750LE, the chip clock is fixed. Nothing to
set. */
if (getChipType() == SM750LE)
return;
#endif
-if (frequency != 0)
-{
-/*
- * Set up PLL, a structure to hold the value to be set in clocks.
- */
-pll.inputFreq = DEFAULT_INPUT_CLOCK; /* Defined in CLOCK.H */
-pll.clockType = MXCLK_PLL;
-
-/*
- * Call calcPllValue() to fill up the other fields for PLL structure.
- * Sometime, the ch
[PATCH] staging:sm750fb:Fixed no space and indent warnings
This patch fixes the no spaces and indent warnings identified by the
checkpath.pl
script for the entire ddk750_chip.c file by using appropriate tab spaces
and indents accordingly.
Signed-off-by: Ragavendra Nagraj
---
drivers/staging/sm750fb/ddk750_chip.c | 454 -
1 file changed, 227 insertions(+), 227 deletions(-)
diff --git a/drivers/staging/sm750fb/ddk750_chip.c
b/drivers/staging/sm750fb/ddk750_chip.c
index b71169e..715baae 100644
--- a/drivers/staging/sm750fb/ddk750_chip.c
+++ b/drivers/staging/sm750fb/ddk750_chip.c
@@ -20,22 +20,22 @@ logical_chip_type_t getChipType()
physicalID = devId750;//either 0x718 or 0x750
physicalRev = revId750;
-if (physicalID == 0x718)
-{
-chip = SM718;
-}
-else if (physicalID == 0x750)
-{
-chip = SM750;
+ if (physicalID == 0x718)
+ {
+ chip = SM718;
+ }
+ else if (physicalID == 0x750)
+ {
+ chip = SM750;
/* SM750 and SM750LE are different in their revision ID only. */
if (physicalRev == SM750LE_REVISION_ID){
chip = SM750LE;
}
-}
-else
-{
-chip = SM_UNKNOWN;
-}
+ }
+ else
+ {
+ chip = SM_UNKNOWN;
+ }
return chip;
}
@@ -43,63 +43,63 @@ logical_chip_type_t getChipType()
inline unsigned int twoToPowerOfx(unsigned long x)
{
-unsigned long i;
-unsigned long result = 1;
+ unsigned long i;
+ unsigned long result = 1;
-for (i=1; i<=x; i++)
-result *= 2;
-return result;
+ for (i=1; i<=x; i++)
+ result *= 2;
+ return result;
}
inline unsigned int calcPLL(pll_value_t *pPLL)
{
-return (pPLL->inputFreq * pPLL->M / pPLL->N / twoToPowerOfx(pPLL->OD) /
twoToPowerOfx(pPLL->POD));
+ return (pPLL->inputFreq * pPLL->M / pPLL->N / twoToPowerOfx(pPLL->OD) /
twoToPowerOfx(pPLL->POD));
}
unsigned int getPllValue(clock_type_t clockType, pll_value_t *pPLL)
{
-unsigned int ulPllReg = 0;
-
-pPLL->inputFreq = DEFAULT_INPUT_CLOCK;
-pPLL->clockType = clockType;
-
-switch (clockType)
-{
-case MXCLK_PLL:
-ulPllReg = PEEK32(MXCLK_PLL_CTRL);
-break;
-case PRIMARY_PLL:
-ulPllReg = PEEK32(PANEL_PLL_CTRL);
-break;
-case SECONDARY_PLL:
-ulPllReg = PEEK32(CRT_PLL_CTRL);
-break;
-case VGA0_PLL:
-ulPllReg = PEEK32(VGA_PLL0_CTRL);
-break;
-case VGA1_PLL:
-ulPllReg = PEEK32(VGA_PLL1_CTRL);
-break;
-}
-
-pPLL->M = FIELD_GET(ulPllReg, PANEL_PLL_CTRL, M);
-pPLL->N = FIELD_GET(ulPllReg, PANEL_PLL_CTRL, N);
-pPLL->OD = FIELD_GET(ulPllReg, PANEL_PLL_CTRL, OD);
-pPLL->POD = FIELD_GET(ulPllReg, PANEL_PLL_CTRL, POD);
-
-return calcPLL(pPLL);
+ unsigned int ulPllReg = 0;
+
+ pPLL->inputFreq = DEFAULT_INPUT_CLOCK;
+ pPLL->clockType = clockType;
+
+ switch (clockType)
+ {
+ case MXCLK_PLL:
+ ulPllReg = PEEK32(MXCLK_PLL_CTRL);
+ break;
+ case PRIMARY_PLL:
+ ulPllReg = PEEK32(PANEL_PLL_CTRL);
+ break;
+ case SECONDARY_PLL:
+ ulPllReg = PEEK32(CRT_PLL_CTRL);
+ break;
+ case VGA0_PLL:
+ ulPllReg = PEEK32(VGA_PLL0_CTRL);
+ break;
+ case VGA1_PLL:
+ ulPllReg = PEEK32(VGA_PLL1_CTRL);
+ break;
+ }
+
+ pPLL->M = FIELD_GET(ulPllReg, PANEL_PLL_CTRL, M);
+ pPLL->N = FIELD_GET(ulPllReg, PANEL_PLL_CTRL, N);
+ pPLL->OD = FIELD_GET(ulPllReg, PANEL_PLL_CTRL, OD);
+ pPLL->POD = FIELD_GET(ulPllReg, PANEL_PLL_CTRL, POD);
+
+ return calcPLL(pPLL);
}
unsigned int getChipClock()
{
-pll_value_t pll;
+ pll_value_t pll;
#if 1
if(getChipType() == SM750LE)
return MHz(130);
#endif
-return getPllValue(MXCLK_PLL, &pll);
+ return getPllValue(MXCLK_PLL, &pll);
}
@@ -110,75 +110,75 @@ unsigned int getChipClock()
*/
void setChipClock(unsigned int frequency)
{
-pll_value_t pll;
-unsigned int ulActualMxClk;
+ pll_value_t pll;
+ unsigned int ulActualMxClk;
#if 1
/* Cheok_0509: For SM750LE, the chip clock is fixed. Nothing to
set. */
if (getChipType() == SM750LE)
return;
#endif
-if (frequency != 0)
-{
-/*
- * Set up PLL, a structure to hold the value to be set in clocks.
- */
-pll.inputFreq = DEFAULT_INPUT_CLOCK; /* Defined in CLOCK.H */
-pll.clockType = MXCLK_PLL;
-
-/*
- * Call calcPllValue() to fill up the other fields for PLL structure.
- * Sometime, t
[PATCH] staging: sm750fb: Fixed no space warnings
This patch fixes the no spaces warning identified by the checkpath.pl
script for the entire ddk750_chip.c file by using appropriate tab spaces
instead.
Signed-off-by: Ragavendra Nagraj
---
drivers/staging/sm750fb/ddk750_chip.c | 364 -
1 file changed, 182 insertions(+), 182 deletions(-)
diff --git a/drivers/staging/sm750fb/ddk750_chip.c
b/drivers/staging/sm750fb/ddk750_chip.c
index b71169e..4567e08 100644
--- a/drivers/staging/sm750fb/ddk750_chip.c
+++ b/drivers/staging/sm750fb/ddk750_chip.c
@@ -20,22 +20,22 @@ logical_chip_type_t getChipType()
physicalID = devId750;//either 0x718 or 0x750
physicalRev = revId750;
-if (physicalID == 0x718)
-{
-chip = SM718;
-}
-else if (physicalID == 0x750)
-{
-chip = SM750;
+ if (physicalID == 0x718)
+ {
+ chip = SM718;
+ }
+ else if (physicalID == 0x750)
+ {
+ chip = SM750;
/* SM750 and SM750LE are different in their revision ID only. */
if (physicalRev == SM750LE_REVISION_ID){
chip = SM750LE;
}
-}
-else
-{
-chip = SM_UNKNOWN;
-}
+ }
+ else
+ {
+ chip = SM_UNKNOWN;
+ }
return chip;
}
@@ -43,63 +43,63 @@ logical_chip_type_t getChipType()
inline unsigned int twoToPowerOfx(unsigned long x)
{
-unsigned long i;
-unsigned long result = 1;
+ unsigned long i;
+ unsigned long result = 1;
-for (i=1; i<=x; i++)
-result *= 2;
-return result;
+ for (i=1; i<=x; i++)
+ result *= 2;
+ return result;
}
inline unsigned int calcPLL(pll_value_t *pPLL)
{
-return (pPLL->inputFreq * pPLL->M / pPLL->N / twoToPowerOfx(pPLL->OD) /
twoToPowerOfx(pPLL->POD));
+ return (pPLL->inputFreq * pPLL->M / pPLL->N / twoToPowerOfx(pPLL->OD) /
twoToPowerOfx(pPLL->POD));
}
unsigned int getPllValue(clock_type_t clockType, pll_value_t *pPLL)
{
-unsigned int ulPllReg = 0;
-
-pPLL->inputFreq = DEFAULT_INPUT_CLOCK;
-pPLL->clockType = clockType;
-
-switch (clockType)
-{
-case MXCLK_PLL:
-ulPllReg = PEEK32(MXCLK_PLL_CTRL);
-break;
-case PRIMARY_PLL:
-ulPllReg = PEEK32(PANEL_PLL_CTRL);
-break;
-case SECONDARY_PLL:
-ulPllReg = PEEK32(CRT_PLL_CTRL);
-break;
-case VGA0_PLL:
-ulPllReg = PEEK32(VGA_PLL0_CTRL);
-break;
-case VGA1_PLL:
-ulPllReg = PEEK32(VGA_PLL1_CTRL);
-break;
-}
-
-pPLL->M = FIELD_GET(ulPllReg, PANEL_PLL_CTRL, M);
-pPLL->N = FIELD_GET(ulPllReg, PANEL_PLL_CTRL, N);
-pPLL->OD = FIELD_GET(ulPllReg, PANEL_PLL_CTRL, OD);
-pPLL->POD = FIELD_GET(ulPllReg, PANEL_PLL_CTRL, POD);
-
-return calcPLL(pPLL);
+ unsigned int ulPllReg = 0;
+
+ pPLL->inputFreq = DEFAULT_INPUT_CLOCK;
+ pPLL->clockType = clockType;
+
+ switch (clockType)
+ {
+ case MXCLK_PLL:
+ ulPllReg = PEEK32(MXCLK_PLL_CTRL);
+ break;
+ case PRIMARY_PLL:
+ ulPllReg = PEEK32(PANEL_PLL_CTRL);
+ break;
+ case SECONDARY_PLL:
+ ulPllReg = PEEK32(CRT_PLL_CTRL);
+ break;
+ case VGA0_PLL:
+ ulPllReg = PEEK32(VGA_PLL0_CTRL);
+ break;
+ case VGA1_PLL:
+ ulPllReg = PEEK32(VGA_PLL1_CTRL);
+ break;
+ }
+
+ pPLL->M = FIELD_GET(ulPllReg, PANEL_PLL_CTRL, M);
+ pPLL->N = FIELD_GET(ulPllReg, PANEL_PLL_CTRL, N);
+ pPLL->OD = FIELD_GET(ulPllReg, PANEL_PLL_CTRL, OD);
+ pPLL->POD = FIELD_GET(ulPllReg, PANEL_PLL_CTRL, POD);
+
+ return calcPLL(pPLL);
}
unsigned int getChipClock()
{
-pll_value_t pll;
+ pll_value_t pll;
#if 1
if(getChipType() == SM750LE)
return MHz(130);
#endif
-return getPllValue(MXCLK_PLL, &pll);
+ return getPllValue(MXCLK_PLL, &pll);
}
@@ -110,75 +110,75 @@ unsigned int getChipClock()
*/
void setChipClock(unsigned int frequency)
{
-pll_value_t pll;
-unsigned int ulActualMxClk;
+ pll_value_t pll;
+ unsigned int ulActualMxClk;
#if 1
/* Cheok_0509: For SM750LE, the chip clock is fixed. Nothing to
set. */
if (getChipType() == SM750LE)
return;
#endif
-if (frequency != 0)
-{
+ if (frequency != 0)
+ {
/*
* Set up PLL, a structure to hold the value to be set in clocks.
*/
-pll.inputFreq = DEFAULT_INPUT_CLOCK; /* Defined in CLOCK.H */
-pll.clockType = MXCLK_PLL;
+ pll.inputFreq = DEFAULT_INPUT_CLOCK; /* Defined in CLOCK.H */
+ pll.clockType = MXCLK_PLL;
/*
* Call calcPllValue
[PATCH] staging: sm750fb: braces, indents, spaces fix
This patch removes the braces for the single line if statement. It fixes
the indent positions correctly. It fixes the spaces appropriately making the
code give no
warnings by the checpath.pl. Please accept.
Signed-off-by: Ragavendra Nagraj
---
drivers/staging/sm750fb/ddk750_chip.c | 22 --
1 file changed, 8 insertions(+), 14 deletions(-)
diff --git a/drivers/staging/sm750fb/ddk750_chip.c
b/drivers/staging/sm750fb/ddk750_chip.c
index b71169e..041a05a 100644
--- a/drivers/staging/sm750fb/ddk750_chip.c
+++ b/drivers/staging/sm750fb/ddk750_chip.c
@@ -20,22 +20,16 @@ logical_chip_type_t getChipType()
physicalID = devId750;//either 0x718 or 0x750
physicalRev = revId750;
-if (physicalID == 0x718)
-{
-chip = SM718;
-}
-else if (physicalID == 0x750)
-{
-chip = SM750;
+ if (physicalID == 0x718) {
+ chip = SM718;
+ } else if (physicalID == 0x750) {
+ chip = SM750;
/* SM750 and SM750LE are different in their revision ID only. */
- if (physicalRev == SM750LE_REVISION_ID){
+ if (physicalRev == SM750LE_REVISION_ID)
chip = SM750LE;
- }
-}
-else
-{
-chip = SM_UNKNOWN;
-}
+ } else {
+ chip = SM_UNKNOWN;
+ }
return chip;
}
--
1.7.10.4
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