Re: [PATCH] staging: vc04_services: Fix bulk cache maintenance

2017-05-10 Thread Phil Elwell 
On 10/05/2017 10:06, Greg Kroah-Hartman wrote:
> On Wed, May 10, 2017 at 09:42:43AM +0100, Phil Elwell wrote:
>> On 04/05/2017 18:51, Stefan Wahren wrote:
>>>
 Phil Elwell  hat am 4. Mai 2017 um 11:58 geschrieben:


 vchiq_arm supports transfers less than one page and at arbitrary
 alignment, using the dma-mapping API to perform its cache maintenance
 (even though the VPU drives the DMA hardware). Read (DMA_FROM_DEVICE)
 operations use cache invalidation for speed, falling back to
 clean+invalidate on partial cache lines, with writes (DMA_TO_DEVICE)
 using flushes.

 If a read transfer has ends which aren't page-aligned, performing cache
 maintenance as if they were whole pages can lead to memory corruption
 since the partial cache lines at the ends (and any cache lines before or
 after the transfer area) will be invalidated. This bug was masked until
 the disabling of the cache flush in flush_dcache_page().

 Honouring the requested transfer start- and end-points prevents the
 corruption.

 Fixes: cf9caf192988 ("staging: vc04_services: Replace dmac_map_area with 
 dmac_map_sg")
 Signed-off-by: Phil Elwell 
>>>
>>> Reported-by: Stefan Wahren 
>>> Tested-by: Stefan Wahren 
>>>
>>> In order to clarify the context of this issue:
>>>
>>> http://lists.infradead.org/pipermail/linux-rpi-kernel/2017-April/006149.html
>>
>> Thanks, Stefan.
>>
>> Is there no feedback other on this patch? It's been in the rpi-4.11.y 
>> downstream
>> branch for a week now with favourable results - see issue
>> https://github.com/raspberrypi/linux/issues/1977 and pr
>> https://github.com/raspberrypi/linux/pull/1987.
> 
> It's the middle of the merge window, I can't do anything with this
> until after 4.12-rc1 comes out.  Please be patient...

Yes, of course - that's the kind of feedback I was looking for.

Thanks,

Phil
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Re: [PATCH] staging: vc04_services: Fix bulk cache maintenance

2017-05-10 Thread Greg Kroah-Hartman 
On Wed, May 10, 2017 at 09:42:43AM +0100, Phil Elwell wrote:
> On 04/05/2017 18:51, Stefan Wahren wrote:
> > 
> >> Phil Elwell  hat am 4. Mai 2017 um 11:58 geschrieben:
> >>
> >>
> >> vchiq_arm supports transfers less than one page and at arbitrary
> >> alignment, using the dma-mapping API to perform its cache maintenance
> >> (even though the VPU drives the DMA hardware). Read (DMA_FROM_DEVICE)
> >> operations use cache invalidation for speed, falling back to
> >> clean+invalidate on partial cache lines, with writes (DMA_TO_DEVICE)
> >> using flushes.
> >>
> >> If a read transfer has ends which aren't page-aligned, performing cache
> >> maintenance as if they were whole pages can lead to memory corruption
> >> since the partial cache lines at the ends (and any cache lines before or
> >> after the transfer area) will be invalidated. This bug was masked until
> >> the disabling of the cache flush in flush_dcache_page().
> >>
> >> Honouring the requested transfer start- and end-points prevents the
> >> corruption.
> >>
> >> Fixes: cf9caf192988 ("staging: vc04_services: Replace dmac_map_area with 
> >> dmac_map_sg")
> >> Signed-off-by: Phil Elwell 
> > 
> > Reported-by: Stefan Wahren 
> > Tested-by: Stefan Wahren 
> > 
> > In order to clarify the context of this issue:
> > 
> > http://lists.infradead.org/pipermail/linux-rpi-kernel/2017-April/006149.html
> 
> Thanks, Stefan.
> 
> Is there no feedback other on this patch? It's been in the rpi-4.11.y 
> downstream
> branch for a week now with favourable results - see issue
> https://github.com/raspberrypi/linux/issues/1977 and pr
> https://github.com/raspberrypi/linux/pull/1987.

It's the middle of the merge window, I can't do anything with this
until after 4.12-rc1 comes out.  Please be patient...

thanks,

greg k-h
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Re: [PATCH] staging: vc04_services: Fix bulk cache maintenance

2017-05-10 Thread Phil Elwell 
On 04/05/2017 18:51, Stefan Wahren wrote:
> 
>> Phil Elwell  hat am 4. Mai 2017 um 11:58 geschrieben:
>>
>>
>> vchiq_arm supports transfers less than one page and at arbitrary
>> alignment, using the dma-mapping API to perform its cache maintenance
>> (even though the VPU drives the DMA hardware). Read (DMA_FROM_DEVICE)
>> operations use cache invalidation for speed, falling back to
>> clean+invalidate on partial cache lines, with writes (DMA_TO_DEVICE)
>> using flushes.
>>
>> If a read transfer has ends which aren't page-aligned, performing cache
>> maintenance as if they were whole pages can lead to memory corruption
>> since the partial cache lines at the ends (and any cache lines before or
>> after the transfer area) will be invalidated. This bug was masked until
>> the disabling of the cache flush in flush_dcache_page().
>>
>> Honouring the requested transfer start- and end-points prevents the
>> corruption.
>>
>> Fixes: cf9caf192988 ("staging: vc04_services: Replace dmac_map_area with 
>> dmac_map_sg")
>> Signed-off-by: Phil Elwell 
> 
> Reported-by: Stefan Wahren 
> Tested-by: Stefan Wahren 
> 
> In order to clarify the context of this issue:
> 
> http://lists.infradead.org/pipermail/linux-rpi-kernel/2017-April/006149.html

Thanks, Stefan.

Is there no feedback other on this patch? It's been in the rpi-4.11.y downstream
branch for a week now with favourable results - see issue
https://github.com/raspberrypi/linux/issues/1977 and pr
https://github.com/raspberrypi/linux/pull/1987.

Phil
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Re: [PATCH] staging: vc04_services: Fix bulk cache maintenance

2017-05-04 Thread Stefan Wahren 

> Phil Elwell  hat am 4. Mai 2017 um 11:58 geschrieben:
> 
> 
> vchiq_arm supports transfers less than one page and at arbitrary
> alignment, using the dma-mapping API to perform its cache maintenance
> (even though the VPU drives the DMA hardware). Read (DMA_FROM_DEVICE)
> operations use cache invalidation for speed, falling back to
> clean+invalidate on partial cache lines, with writes (DMA_TO_DEVICE)
> using flushes.
> 
> If a read transfer has ends which aren't page-aligned, performing cache
> maintenance as if they were whole pages can lead to memory corruption
> since the partial cache lines at the ends (and any cache lines before or
> after the transfer area) will be invalidated. This bug was masked until
> the disabling of the cache flush in flush_dcache_page().
> 
> Honouring the requested transfer start- and end-points prevents the
> corruption.
> 
> Fixes: cf9caf192988 ("staging: vc04_services: Replace dmac_map_area with 
> dmac_map_sg")
> Signed-off-by: Phil Elwell 

Reported-by: Stefan Wahren 
Tested-by: Stefan Wahren 

In order to clarify the context of this issue:

http://lists.infradead.org/pipermail/linux-rpi-kernel/2017-April/006149.html
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[PATCH] staging: vc04_services: Fix bulk cache maintenance

2017-05-04 Thread Phil Elwell 
vchiq_arm supports transfers less than one page and at arbitrary
alignment, using the dma-mapping API to perform its cache maintenance
(even though the VPU drives the DMA hardware). Read (DMA_FROM_DEVICE)
operations use cache invalidation for speed, falling back to
clean+invalidate on partial cache lines, with writes (DMA_TO_DEVICE)
using flushes.

If a read transfer has ends which aren't page-aligned, performing cache
maintenance as if they were whole pages can lead to memory corruption
since the partial cache lines at the ends (and any cache lines before or
after the transfer area) will be invalidated. This bug was masked until
the disabling of the cache flush in flush_dcache_page().

Honouring the requested transfer start- and end-points prevents the
corruption.

Fixes: cf9caf192988 ("staging: vc04_services: Replace dmac_map_area with 
dmac_map_sg")
Signed-off-by: Phil Elwell 
---
 .../interface/vchiq_arm/vchiq_2835_arm.c   | 31 +-
 1 file changed, 19 insertions(+), 12 deletions(-)

diff --git a/drivers/staging/vc04_services/interface/vchiq_arm/vchiq_2835_arm.c 
b/drivers/staging/vc04_services/interface/vchiq_arm/vchiq_2835_arm.c
index 3aeffcb..02e9736 100644
--- a/drivers/staging/vc04_services/interface/vchiq_arm/vchiq_2835_arm.c
+++ b/drivers/staging/vc04_services/interface/vchiq_arm/vchiq_2835_arm.c
@@ -501,8 +501,15 @@ int vchiq_platform_init(struct platform_device *pdev, 
VCHIQ_STATE_T *state)
 */
sg_init_table(scatterlist, num_pages);
/* Now set the pages for each scatterlist */
-   for (i = 0; i < num_pages; i++)
-   sg_set_page(scatterlist + i, pages[i], PAGE_SIZE, 0);
+   for (i = 0; i < num_pages; i++) {
+   unsigned int len = PAGE_SIZE - offset;
+
+   if (len > count)
+   len = count;
+   sg_set_page(scatterlist + i, pages[i], len, offset);
+   offset = 0;
+   count -= len;
+   }
 
dma_buffers = dma_map_sg(g_dev,
 scatterlist,
@@ -523,20 +530,20 @@ int vchiq_platform_init(struct platform_device *pdev, 
VCHIQ_STATE_T *state)
u32 addr = sg_dma_address(sg);
 
/* Note: addrs is the address + page_count - 1
-* The firmware expects the block to be page
+* The firmware expects blocks after the first to be page-
 * aligned and a multiple of the page size
 */
WARN_ON(len == 0);
-   WARN_ON(len & ~PAGE_MASK);
-   WARN_ON(addr & ~PAGE_MASK);
+   WARN_ON(i && (i != (dma_buffers - 1)) && (len & ~PAGE_MASK));
+   WARN_ON(i && (addr & ~PAGE_MASK));
if (k > 0 &&
-   ((addrs[k - 1] & PAGE_MASK) |
-   ((addrs[k - 1] & ~PAGE_MASK) + 1) << PAGE_SHIFT)
-   == addr) {
-   addrs[k - 1] += (len >> PAGE_SHIFT);
-   } else {
-   addrs[k++] = addr | ((len >> PAGE_SHIFT) - 1);
-   }
+   ((addrs[k - 1] & PAGE_MASK) +
+(((addrs[k - 1] & ~PAGE_MASK) + 1) << PAGE_SHIFT))
+   == (addr & PAGE_MASK))
+   addrs[k - 1] += ((len + PAGE_SIZE - 1) >> PAGE_SHIFT);
+   else
+   addrs[k++] = (addr & PAGE_MASK) |
+   (((len + PAGE_SIZE - 1) >> PAGE_SHIFT) - 1);
}
 
/* Partial cache lines (fragments) require special measures */
-- 
1.9.1

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