---
drivers/staging/bcm/DDRInit.c | 59 ---
1 file changed, 39 insertions(+), 20 deletions(-)
diff --git a/drivers/staging/bcm/DDRInit.c b/drivers/staging/bcm/DDRInit.c
index 4564f40..4226c93 100644
--- a/drivers/staging/bcm/DDRInit.c
+++ b/drivers/staging/bcm/DDRInit.c
@@ -7,7 +7,8 @@
/* DDR INIT-133Mhz */
#define T3_SKIP_CLOCK_PROGRAM_DUMP_133MHZ 12 /* index for 0x0F007000 */
-static struct bcm_ddr_setting asT3_DDRSetting133MHz[] = { /* DPLL Clock
Setting */
+static struct bcm_ddr_setting asT3_DDRSetting133MHz[] = {
+ /* DPLL Clock Setting */
{0x0F000800, 0x7212},
{0x0f000820, 0x07F13FFF},
{0x0f000810, 0x0F95},
@@ -65,7 +66,8 @@ static struct bcm_ddr_setting asT3_DDRSetting133MHz[] = { /*
DPLL Clock Setting
};
/* 80Mhz */
#define T3_SKIP_CLOCK_PROGRAM_DUMP_80MHZ 10 /* index for 0x0F007000 */
-static struct bcm_ddr_setting asT3_DDRSetting80MHz[] = { /* DPLL Clock
Setting */
+static struct bcm_ddr_setting asT3_DDRSetting80MHz[] = {
+ /* DPLL Clock Setting */
{0x0f000810, 0x0F95},
{0x0f000820, 0x07f1},
{0x0f000860, 0x},
@@ -117,7 +119,8 @@ static struct bcm_ddr_setting asT3_DDRSetting80MHz[] = {
/* DPLL Clock Setting
};
/* 100Mhz */
#define T3_SKIP_CLOCK_PROGRAM_DUMP_100MHZ 13 /* index for 0x0F007000 */
-static struct bcm_ddr_setting asT3_DDRSetting100MHz[] = { /* DPLL Clock
Setting */
+static struct bcm_ddr_setting asT3_DDRSetting100MHz[] = {
+ /* DPLL Clock Setting */
{0x0F000800, 0x7008},
{0x0f000810, 0x0F95},
{0x0f000820, 0x07F13E3F},
@@ -189,7 +192,8 @@ static struct bcm_ddr_setting asDPLL_266MHZ[] = {
};
#define T3B_SKIP_CLOCK_PROGRAM_DUMP_133MHZ 11 /* index for 0x0F007000 */
-static struct bcm_ddr_setting asT3B_DDRSetting133MHz[] = { /* DPLL Clock
Setting */
+static struct bcm_ddr_setting asT3B_DDRSetting133MHz[] = {
+ /* DPLL Clock Setting */
{0x0f000810, 0x0F95},
{0x0f000810, 0x0F95},
{0x0f000810, 0x0F95},
@@ -247,7 +251,8 @@ static struct bcm_ddr_setting asT3B_DDRSetting133MHz[] = {
/* DPLL Clock Settin
};
#define T3B_SKIP_CLOCK_PROGRAM_DUMP_80MHZ 9 /* index for 0x0F007000 */
-static struct bcm_ddr_setting asT3B_DDRSetting80MHz[] = { /* DPLL Clock
Setting */
+static struct bcm_ddr_setting asT3B_DDRSetting80MHz[] = {
+ /* DPLL Clock Setting */
{0x0f000810, 0x0F95},
{0x0f000820, 0x07F13FFF},
{0x0f000840, 0x0FFF1F00},
@@ -301,7 +306,8 @@ static struct bcm_ddr_setting asT3B_DDRSetting80MHz[] = {
/* DPLL Clock Setting
/* 100Mhz */
#define T3B_SKIP_CLOCK_PROGRAM_DUMP_100MHZ 9 /* index for 0x0F007000 */
-static struct bcm_ddr_setting asT3B_DDRSetting100MHz[] = { /* DPLL Clock
Setting */
+static struct bcm_ddr_setting asT3B_DDRSetting100MHz[] = {
+ /* DPLL Clock Setting */
{0x0f000810, 0x0F95},
{0x0f000820, 0x07F1369B},
{0x0f000840, 0x0FFF0800},
@@ -356,7 +362,8 @@ static struct bcm_ddr_setting asT3B_DDRSetting100MHz[] = {
/* DPLL Clock Settin
#define T3LP_SKIP_CLOCK_PROGRAM_DUMP_133MHZ 9 /* index for 0x0F007000 */
-static struct bcm_ddr_setting asT3LP_DDRSetting133MHz[] = { /* DPLL Clock
Setting */
+static struct bcm_ddr_setting asT3LP_DDRSetting133MHz[] = {
+ /* DPLL Clock Setting */
{0x0f000820, 0x03F1365B},
{0x0f000810, 0x2F95},
{0x0f000880, 0x03DD},
@@ -416,7 +423,8 @@ static struct bcm_ddr_setting asT3LP_DDRSetting133MHz[] = {
/* DPLL Clock Setti
};
#define T3LP_SKIP_CLOCK_PROGRAM_DUMP_100MHZ 11 /* index for 0x0F007000 */
-static struct bcm_ddr_setting asT3LP_DDRSetting100MHz[] = { /* DPLL Clock
Setting */
+static struct bcm_ddr_setting asT3LP_DDRSetting100MHz[] = {
+ /* DPLL Clock Setting */
{0x0f000810, 0x2F95},
{0x0f000820, 0x03F1369B},
{0x0f000840, 0x0fff},
@@ -476,7 +484,8 @@ static struct bcm_ddr_setting asT3LP_DDRSetting100MHz[] = {
/* DPLL Clock Setti
};
#define T3LP_SKIP_CLOCK_PROGRAM_DUMP_80MHZ 9 /* index for 0x0F007000 */
-static struct bcm_ddr_setting asT3LP_DDRSetting80MHz[] = { /* DPLL Clock
Setting */
+static struct bcm_ddr_setting asT3LP_DDRSetting80MHz[] = {
+ /* DPLL Clock Setting */
{0x0f000820, 0x07F13FFF},
{0x0f000810, 0x2F95},
{0x0f000860, 0x},
@@ -536,7 +545,8 @@ static struct bcm_ddr_setting asT3LP_DDRSetting80MHz[] = {
/* DPLL Clock Settin
/* T3 LP-B (UMA-B) */
#define T3LPB_SKIP_CLOCK_PROGRAM_DUMP_160MHZ 7 /* index for 0x0F007000 */
-static struct bcm_ddr_setting asT3LPB_DDRSetting160MHz[] = { /* DPLL Clock
Setting */
+static struct bcm_ddr_setting asT3LPB_DDRSetting160MHz[] = {
+ /* DPLL Clock Setting */
{0x0f000820, 0x03F137DB},
{0x0f000810, 0x01842795},
{0x0f000860, 0x},
@@ -544,7 +554,8 @@ static struct bcm_ddr_setting asT3LPB_DDRSetting160MHz[] =
{ /* DPLL Clock S