Re: [PATCH v2 2/2] phy: ralink: Add PHY driver for MT7621 PCIe PHY
Hi Kishon, On Wed, Apr 17, 2019 at 7:58 AM Kishon Vijay Abraham I wrote: > > Hi, > > On 30/03/19 11:20 AM, Sergio Paracuellos wrote: > > This patch adds a driver for the PCIe PHY of MT7621 SoC. > > > > Signed-off-by: Sergio Paracuellos > > --- > > drivers/phy/ralink/Kconfig | 7 + > > drivers/phy/ralink/Makefile | 1 + > > drivers/phy/ralink/phy-mt7621-pci.c | 401 > > 3 files changed, 409 insertions(+) > > create mode 100644 drivers/phy/ralink/phy-mt7621-pci.c > > > > diff --git a/drivers/phy/ralink/Kconfig b/drivers/phy/ralink/Kconfig > > index 14fd219535ef..87943a10f210 100644 > > --- a/drivers/phy/ralink/Kconfig > > +++ b/drivers/phy/ralink/Kconfig > > @@ -1,6 +1,13 @@ > > # > > # PHY drivers for Ralink platforms. > > # > > +config PHY_MT7621_PCI > > + tristate "MediaTek MT7621 PCI PHY Driver" > > Shouldn't this be in drivers/phy/mediatek/ then? I am not sure about this, it is mediatek but it only appears on ralink so, I don't know where it should be placed. Maybe Neil has an opinion about this. > > + depends on RALINK && OF > > Add depends on COMPILE_TEST. Will do. > > + select GENERIC_PHY > > + help > > + Say 'Y' here to add support for MediaTek MT7621 PCI PHY driver, > > + > > config PHY_RALINK_USB > > tristate "Ralink USB PHY driver" > > depends on RALINK || COMPILE_TEST > > diff --git a/drivers/phy/ralink/Makefile b/drivers/phy/ralink/Makefile > > index 5c9e326e8757..2052d5649863 100644 > > --- a/drivers/phy/ralink/Makefile > > +++ b/drivers/phy/ralink/Makefile > > @@ -1 +1,2 @@ > > +obj-$(CONFIG_PHY_MT7621_PCI) += phy-mt7621-pci.o > > obj-$(CONFIG_PHY_RALINK_USB) += phy-ralink-usb.o > > diff --git a/drivers/phy/ralink/phy-mt7621-pci.c > > b/drivers/phy/ralink/phy-mt7621-pci.c > > new file mode 100644 > > index ..118302c122ee > > --- /dev/null > > +++ b/drivers/phy/ralink/phy-mt7621-pci.c > > @@ -0,0 +1,401 @@ > > +// SPDX-License-Identifier: GPL-2.0+ > > +/* > > + * Mediatek MT7621 PCI PHY Driver > > + * Author: Sergio Paracuellos > > + */ > > + > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > + > > +#define RALINK_CLKCFG1 0x30 > > +#define CHIP_REV_MT7621_E2 0x0101 > > Is this PHY specific or SoC revision? If it is SoC, we should use > soc_device_attribute and soc_device_match. Depending on revision reset lines are inverted and somebypasses need to be performed to properly initialize the phy. I'll take a look of how this can be done better using soc_device_attribute and soc_device_match as you are pointing out here. > > + > > +#define PCIE_PORT_CLK_EN(x) BIT(24 + (x)) > > + > > +#define RG_PE1_PIPE_REG 0x02c > > +#define RG_PE1_PIPE_RST BIT(12) > > +#define RG_PE1_PIPE_CMD_FRC BIT(4) > > + > > +#define RG_P0_TO_P1_WIDTH0x100 > > +#define RG_PE1_H_LCDDS_REG 0x49c > > +#define RG_PE1_H_LCDDS_PCW GENMASK(30, 0) > > +#define RG_PE1_H_LCDDS_PCW_VAL(x)((0x7fff & (x)) << 0) > > + > > +#define RG_PE1_FRC_H_XTAL_REG0x400 > > +#define RG_PE1_FRC_H_XTAL_TYPE BIT(8) > > +#define RG_PE1_H_XTAL_TYPE GENMASK(10, 9) > > +#define RG_PE1_H_XTAL_TYPE_VAL(x)((0x3 & (x)) << 9) > > + > > +#define RG_PE1_FRC_PHY_REG 0x000 > > +#define RG_PE1_FRC_PHY_ENBIT(4) > > +#define RG_PE1_PHY_ENBIT(5) > > + > > +#define RG_PE1_H_PLL_REG 0x490 > > +#define RG_PE1_H_PLL_BC GENMASK(23, 22) > > +#define RG_PE1_H_PLL_BC_VAL(x) ((0x3 & (x)) << 22) > > +#define RG_PE1_H_PLL_BP GENMASK(21, 18) > > +#define RG_PE1_H_PLL_BP_VAL(x) ((0xf & (x)) << 18) > > +#define RG_PE1_H_PLL_IR GENMASK(15, 12) > > +#define RG_PE1_H_PLL_IR_VAL(x) ((0xf & (x)) << 12) > > +#define RG_PE1_H_PLL_IC GENMASK(11, 8) > > +#define RG_PE1_H_PLL_IC_VAL(x) ((0xf & (x)) << 8) > > +#define RG_PE1_H_PLL_PREDIV GENMASK(7, 6) > > +#define RG_PE1_H_PLL_PREDIV_VAL(x) ((0x3 & (x)) << 6) > > +#define RG_PE1_PLL_DIVEN GENMASK(3, 1) > > +#define RG_PE1_PLL_DIVEN_VAL(x) ((0x7 & (x)) << 1) > > + > > +#define RG_PE1_H_PLL_FBKSEL_REG 0x4bc > > +#define RG_PE1_H_PLL_FBKSEL GENMASK(5, 4) > > +#define RG_PE1_H_PLL_FBKSEL_VAL(x) ((0x3 & (x)) << 4) > > + > > +#define RG_PE1_H_LCDDS_SSC_PRD_REG 0x4a4 > > +#define RG_PE1_H_LCDDS_SSC_PRD GENMASK(15, 0) > > +#define
Re: [PATCH v2 2/2] phy: ralink: Add PHY driver for MT7621 PCIe PHY
Hi, On 30/03/19 11:20 AM, Sergio Paracuellos wrote: > This patch adds a driver for the PCIe PHY of MT7621 SoC. > > Signed-off-by: Sergio Paracuellos > --- > drivers/phy/ralink/Kconfig | 7 + > drivers/phy/ralink/Makefile | 1 + > drivers/phy/ralink/phy-mt7621-pci.c | 401 > 3 files changed, 409 insertions(+) > create mode 100644 drivers/phy/ralink/phy-mt7621-pci.c > > diff --git a/drivers/phy/ralink/Kconfig b/drivers/phy/ralink/Kconfig > index 14fd219535ef..87943a10f210 100644 > --- a/drivers/phy/ralink/Kconfig > +++ b/drivers/phy/ralink/Kconfig > @@ -1,6 +1,13 @@ > # > # PHY drivers for Ralink platforms. > # > +config PHY_MT7621_PCI > + tristate "MediaTek MT7621 PCI PHY Driver" Shouldn't this be in drivers/phy/mediatek/ then? > + depends on RALINK && OF Add depends on COMPILE_TEST. > + select GENERIC_PHY > + help > + Say 'Y' here to add support for MediaTek MT7621 PCI PHY driver, > + > config PHY_RALINK_USB > tristate "Ralink USB PHY driver" > depends on RALINK || COMPILE_TEST > diff --git a/drivers/phy/ralink/Makefile b/drivers/phy/ralink/Makefile > index 5c9e326e8757..2052d5649863 100644 > --- a/drivers/phy/ralink/Makefile > +++ b/drivers/phy/ralink/Makefile > @@ -1 +1,2 @@ > +obj-$(CONFIG_PHY_MT7621_PCI) += phy-mt7621-pci.o > obj-$(CONFIG_PHY_RALINK_USB) += phy-ralink-usb.o > diff --git a/drivers/phy/ralink/phy-mt7621-pci.c > b/drivers/phy/ralink/phy-mt7621-pci.c > new file mode 100644 > index ..118302c122ee > --- /dev/null > +++ b/drivers/phy/ralink/phy-mt7621-pci.c > @@ -0,0 +1,401 @@ > +// SPDX-License-Identifier: GPL-2.0+ > +/* > + * Mediatek MT7621 PCI PHY Driver > + * Author: Sergio Paracuellos > + */ > + > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > + > +#define RALINK_CLKCFG1 0x30 > +#define CHIP_REV_MT7621_E2 0x0101 Is this PHY specific or SoC revision? If it is SoC, we should use soc_device_attribute and soc_device_match. > + > +#define PCIE_PORT_CLK_EN(x) BIT(24 + (x)) > + > +#define RG_PE1_PIPE_REG 0x02c > +#define RG_PE1_PIPE_RST BIT(12) > +#define RG_PE1_PIPE_CMD_FRC BIT(4) > + > +#define RG_P0_TO_P1_WIDTH0x100 > +#define RG_PE1_H_LCDDS_REG 0x49c > +#define RG_PE1_H_LCDDS_PCW GENMASK(30, 0) > +#define RG_PE1_H_LCDDS_PCW_VAL(x)((0x7fff & (x)) << 0) > + > +#define RG_PE1_FRC_H_XTAL_REG0x400 > +#define RG_PE1_FRC_H_XTAL_TYPE BIT(8) > +#define RG_PE1_H_XTAL_TYPE GENMASK(10, 9) > +#define RG_PE1_H_XTAL_TYPE_VAL(x)((0x3 & (x)) << 9) > + > +#define RG_PE1_FRC_PHY_REG 0x000 > +#define RG_PE1_FRC_PHY_ENBIT(4) > +#define RG_PE1_PHY_ENBIT(5) > + > +#define RG_PE1_H_PLL_REG 0x490 > +#define RG_PE1_H_PLL_BC GENMASK(23, 22) > +#define RG_PE1_H_PLL_BC_VAL(x) ((0x3 & (x)) << 22) > +#define RG_PE1_H_PLL_BP GENMASK(21, 18) > +#define RG_PE1_H_PLL_BP_VAL(x) ((0xf & (x)) << 18) > +#define RG_PE1_H_PLL_IR GENMASK(15, 12) > +#define RG_PE1_H_PLL_IR_VAL(x) ((0xf & (x)) << 12) > +#define RG_PE1_H_PLL_IC GENMASK(11, 8) > +#define RG_PE1_H_PLL_IC_VAL(x) ((0xf & (x)) << 8) > +#define RG_PE1_H_PLL_PREDIV GENMASK(7, 6) > +#define RG_PE1_H_PLL_PREDIV_VAL(x) ((0x3 & (x)) << 6) > +#define RG_PE1_PLL_DIVEN GENMASK(3, 1) > +#define RG_PE1_PLL_DIVEN_VAL(x) ((0x7 & (x)) << 1) > + > +#define RG_PE1_H_PLL_FBKSEL_REG 0x4bc > +#define RG_PE1_H_PLL_FBKSEL GENMASK(5, 4) > +#define RG_PE1_H_PLL_FBKSEL_VAL(x) ((0x3 & (x)) << 4) > + > +#define RG_PE1_H_LCDDS_SSC_PRD_REG 0x4a4 > +#define RG_PE1_H_LCDDS_SSC_PRD GENMASK(15, 0) > +#define RG_PE1_H_LCDDS_SSC_PRD_VAL(x)((0x & (x)) << 0) > + > +#define RG_PE1_H_LCDDS_SSC_DELTA_REG 0x4a8 > +#define RG_PE1_H_LCDDS_SSC_DELTA GENMASK(11, 0) > +#define RG_PE1_H_LCDDS_SSC_DELTA_VAL(x) ((0xfff & (x)) << 0) > +#define RG_PE1_H_LCDDS_SSC_DELTA1GENMASK(27, 16) > +#define RG_PE1_H_LCDDS_SSC_DELTA1_VAL(x) ((0xff & (x)) << 16) > + > +#define RG_PE1_LCDDS_CLK_PH_INV_REG 0x4a0 > +#define RG_PE1_LCDDS_CLK_PH_INV BIT(5) > + > +#define RG_PE1_H_PLL_BR_REG 0x4ac > +#define RG_PE1_H_PLL_BR GENMASK(18, 16) > +#define RG_PE1_H_PLL_BR_VAL(x) (
Re: [PATCH v2 2/2] phy: ralink: Add PHY driver for MT7621 PCIe PHY
Hi all! On Sat, Mar 30, 2019 at 6:50 AM Sergio Paracuellos wrote: > > This patch adds a driver for the PCIe PHY of MT7621 SoC. > > Signed-off-by: Sergio Paracuellos > --- > drivers/phy/ralink/Kconfig | 7 + > drivers/phy/ralink/Makefile | 1 + > drivers/phy/ralink/phy-mt7621-pci.c | 401 > 3 files changed, 409 insertions(+) > create mode 100644 drivers/phy/ralink/phy-mt7621-pci.c Any comments on this? Thanks in advance for your time. Best regards, Sergio Paracuellos > > diff --git a/drivers/phy/ralink/Kconfig b/drivers/phy/ralink/Kconfig > index 14fd219535ef..87943a10f210 100644 > --- a/drivers/phy/ralink/Kconfig > +++ b/drivers/phy/ralink/Kconfig > @@ -1,6 +1,13 @@ > # > # PHY drivers for Ralink platforms. > # > +config PHY_MT7621_PCI > + tristate "MediaTek MT7621 PCI PHY Driver" > + depends on RALINK && OF > + select GENERIC_PHY > + help > + Say 'Y' here to add support for MediaTek MT7621 PCI PHY driver, > + > config PHY_RALINK_USB > tristate "Ralink USB PHY driver" > depends on RALINK || COMPILE_TEST > diff --git a/drivers/phy/ralink/Makefile b/drivers/phy/ralink/Makefile > index 5c9e326e8757..2052d5649863 100644 > --- a/drivers/phy/ralink/Makefile > +++ b/drivers/phy/ralink/Makefile > @@ -1 +1,2 @@ > +obj-$(CONFIG_PHY_MT7621_PCI) += phy-mt7621-pci.o > obj-$(CONFIG_PHY_RALINK_USB) += phy-ralink-usb.o > diff --git a/drivers/phy/ralink/phy-mt7621-pci.c > b/drivers/phy/ralink/phy-mt7621-pci.c > new file mode 100644 > index ..118302c122ee > --- /dev/null > +++ b/drivers/phy/ralink/phy-mt7621-pci.c > @@ -0,0 +1,401 @@ > +// SPDX-License-Identifier: GPL-2.0+ > +/* > + * Mediatek MT7621 PCI PHY Driver > + * Author: Sergio Paracuellos > + */ > + > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > + > +#define RALINK_CLKCFG1 0x30 > +#define CHIP_REV_MT7621_E2 0x0101 > + > +#define PCIE_PORT_CLK_EN(x)BIT(24 + (x)) > + > +#define RG_PE1_PIPE_REG0x02c > +#define RG_PE1_PIPE_RSTBIT(12) > +#define RG_PE1_PIPE_CMD_FRCBIT(4) > + > +#define RG_P0_TO_P1_WIDTH 0x100 > +#define RG_PE1_H_LCDDS_REG 0x49c > +#define RG_PE1_H_LCDDS_PCW GENMASK(30, 0) > +#define RG_PE1_H_LCDDS_PCW_VAL(x) ((0x7fff & (x)) << 0) > + > +#define RG_PE1_FRC_H_XTAL_REG 0x400 > +#define RG_PE1_FRC_H_XTAL_TYPE BIT(8) > +#define RG_PE1_H_XTAL_TYPE GENMASK(10, 9) > +#define RG_PE1_H_XTAL_TYPE_VAL(x) ((0x3 & (x)) << 9) > + > +#define RG_PE1_FRC_PHY_REG 0x000 > +#define RG_PE1_FRC_PHY_EN BIT(4) > +#define RG_PE1_PHY_EN BIT(5) > + > +#define RG_PE1_H_PLL_REG 0x490 > +#define RG_PE1_H_PLL_BCGENMASK(23, 22) > +#define RG_PE1_H_PLL_BC_VAL(x) ((0x3 & (x)) << 22) > +#define RG_PE1_H_PLL_BPGENMASK(21, 18) > +#define RG_PE1_H_PLL_BP_VAL(x) ((0xf & (x)) << 18) > +#define RG_PE1_H_PLL_IRGENMASK(15, 12) > +#define RG_PE1_H_PLL_IR_VAL(x) ((0xf & (x)) << 12) > +#define RG_PE1_H_PLL_ICGENMASK(11, 8) > +#define RG_PE1_H_PLL_IC_VAL(x) ((0xf & (x)) << 8) > +#define RG_PE1_H_PLL_PREDIVGENMASK(7, 6) > +#define RG_PE1_H_PLL_PREDIV_VAL(x) ((0x3 & (x)) << 6) > +#define RG_PE1_PLL_DIVEN GENMASK(3, 1) > +#define RG_PE1_PLL_DIVEN_VAL(x)((0x7 & (x)) << 1) > + > +#define RG_PE1_H_PLL_FBKSEL_REG0x4bc > +#define RG_PE1_H_PLL_FBKSELGENMASK(5, 4) > +#define RG_PE1_H_PLL_FBKSEL_VAL(x) ((0x3 & (x)) << 4) > + > +#defineRG_PE1_H_LCDDS_SSC_PRD_REG 0x4a4 > +#define RG_PE1_H_LCDDS_SSC_PRD GENMASK(15, 0) > +#define RG_PE1_H_LCDDS_SSC_PRD_VAL(x) ((0x & (x)) << 0) > + > +#define RG_PE1_H_LCDDS_SSC_DELTA_REG 0x4a8 > +#define RG_PE1_H_LCDDS_SSC_DELTA GENMASK(11, 0) > +#define RG_PE1_H_LCDDS_SSC_DELTA_VAL(x)((0xfff & (x)) << 0) > +#define RG_PE1_H_LCDDS_SSC_DELTA1 GENMASK(27, 16) > +#define RG_PE1_H_LCDDS_SSC_DELTA1_VAL(x) ((0xff & (x)) << 16) > + > +#define RG_PE1_LCDDS_CLK_PH_INV_REG0x4a0 > +#define RG_PE1_LCDDS_CLK_PH_INVBIT(5) > + > +#define RG_PE1_H_PLL_BR_REG0x4ac > +#define RG_PE1_H_PLL_BRGENMASK(18, 16) > +#define RG_PE1_H_PLL_BR_VAL(x) ((0x7 & (x)) << 16) > + > +#defineRG_PE1_MSTCKDIV_R
[PATCH v2 2/2] phy: ralink: Add PHY driver for MT7621 PCIe PHY
This patch adds a driver for the PCIe PHY of MT7621 SoC. Signed-off-by: Sergio Paracuellos --- drivers/phy/ralink/Kconfig | 7 + drivers/phy/ralink/Makefile | 1 + drivers/phy/ralink/phy-mt7621-pci.c | 401 3 files changed, 409 insertions(+) create mode 100644 drivers/phy/ralink/phy-mt7621-pci.c diff --git a/drivers/phy/ralink/Kconfig b/drivers/phy/ralink/Kconfig index 14fd219535ef..87943a10f210 100644 --- a/drivers/phy/ralink/Kconfig +++ b/drivers/phy/ralink/Kconfig @@ -1,6 +1,13 @@ # # PHY drivers for Ralink platforms. # +config PHY_MT7621_PCI + tristate "MediaTek MT7621 PCI PHY Driver" + depends on RALINK && OF + select GENERIC_PHY + help + Say 'Y' here to add support for MediaTek MT7621 PCI PHY driver, + config PHY_RALINK_USB tristate "Ralink USB PHY driver" depends on RALINK || COMPILE_TEST diff --git a/drivers/phy/ralink/Makefile b/drivers/phy/ralink/Makefile index 5c9e326e8757..2052d5649863 100644 --- a/drivers/phy/ralink/Makefile +++ b/drivers/phy/ralink/Makefile @@ -1 +1,2 @@ +obj-$(CONFIG_PHY_MT7621_PCI) += phy-mt7621-pci.o obj-$(CONFIG_PHY_RALINK_USB) += phy-ralink-usb.o diff --git a/drivers/phy/ralink/phy-mt7621-pci.c b/drivers/phy/ralink/phy-mt7621-pci.c new file mode 100644 index ..118302c122ee --- /dev/null +++ b/drivers/phy/ralink/phy-mt7621-pci.c @@ -0,0 +1,401 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Mediatek MT7621 PCI PHY Driver + * Author: Sergio Paracuellos + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define RALINK_CLKCFG1 0x30 +#define CHIP_REV_MT7621_E2 0x0101 + +#define PCIE_PORT_CLK_EN(x)BIT(24 + (x)) + +#define RG_PE1_PIPE_REG0x02c +#define RG_PE1_PIPE_RSTBIT(12) +#define RG_PE1_PIPE_CMD_FRCBIT(4) + +#define RG_P0_TO_P1_WIDTH 0x100 +#define RG_PE1_H_LCDDS_REG 0x49c +#define RG_PE1_H_LCDDS_PCW GENMASK(30, 0) +#define RG_PE1_H_LCDDS_PCW_VAL(x) ((0x7fff & (x)) << 0) + +#define RG_PE1_FRC_H_XTAL_REG 0x400 +#define RG_PE1_FRC_H_XTAL_TYPE BIT(8) +#define RG_PE1_H_XTAL_TYPE GENMASK(10, 9) +#define RG_PE1_H_XTAL_TYPE_VAL(x) ((0x3 & (x)) << 9) + +#define RG_PE1_FRC_PHY_REG 0x000 +#define RG_PE1_FRC_PHY_EN BIT(4) +#define RG_PE1_PHY_EN BIT(5) + +#define RG_PE1_H_PLL_REG 0x490 +#define RG_PE1_H_PLL_BCGENMASK(23, 22) +#define RG_PE1_H_PLL_BC_VAL(x) ((0x3 & (x)) << 22) +#define RG_PE1_H_PLL_BPGENMASK(21, 18) +#define RG_PE1_H_PLL_BP_VAL(x) ((0xf & (x)) << 18) +#define RG_PE1_H_PLL_IRGENMASK(15, 12) +#define RG_PE1_H_PLL_IR_VAL(x) ((0xf & (x)) << 12) +#define RG_PE1_H_PLL_ICGENMASK(11, 8) +#define RG_PE1_H_PLL_IC_VAL(x) ((0xf & (x)) << 8) +#define RG_PE1_H_PLL_PREDIVGENMASK(7, 6) +#define RG_PE1_H_PLL_PREDIV_VAL(x) ((0x3 & (x)) << 6) +#define RG_PE1_PLL_DIVEN GENMASK(3, 1) +#define RG_PE1_PLL_DIVEN_VAL(x)((0x7 & (x)) << 1) + +#define RG_PE1_H_PLL_FBKSEL_REG0x4bc +#define RG_PE1_H_PLL_FBKSELGENMASK(5, 4) +#define RG_PE1_H_PLL_FBKSEL_VAL(x) ((0x3 & (x)) << 4) + +#defineRG_PE1_H_LCDDS_SSC_PRD_REG 0x4a4 +#define RG_PE1_H_LCDDS_SSC_PRD GENMASK(15, 0) +#define RG_PE1_H_LCDDS_SSC_PRD_VAL(x) ((0x & (x)) << 0) + +#define RG_PE1_H_LCDDS_SSC_DELTA_REG 0x4a8 +#define RG_PE1_H_LCDDS_SSC_DELTA GENMASK(11, 0) +#define RG_PE1_H_LCDDS_SSC_DELTA_VAL(x)((0xfff & (x)) << 0) +#define RG_PE1_H_LCDDS_SSC_DELTA1 GENMASK(27, 16) +#define RG_PE1_H_LCDDS_SSC_DELTA1_VAL(x) ((0xff & (x)) << 16) + +#define RG_PE1_LCDDS_CLK_PH_INV_REG0x4a0 +#define RG_PE1_LCDDS_CLK_PH_INVBIT(5) + +#define RG_PE1_H_PLL_BR_REG0x4ac +#define RG_PE1_H_PLL_BRGENMASK(18, 16) +#define RG_PE1_H_PLL_BR_VAL(x) ((0x7 & (x)) << 16) + +#defineRG_PE1_MSTCKDIV_REG 0x414 +#define RG_PE1_MSTCKDIVGENMASK(7, 6) +#define RG_PE1_MSTCKDIV_VAL(x) ((0x3 & (x)) << 6) + +#define RG_PE1_FRC_MSTCKDIVBIT(5) + +#define MAX_PHYS 2 + +/** + * struct mt7621_pci_phy_instance - Mt7621 Pcie PHY device + * @phy: pointer to the kernel PHY device + * @port_base: base register + * @i