[PATCH] staging: rtl8188eu: remove unused definitions from hal8188e_phy_reg.h
Remove unused definitions from the file hal8188e_phy_reg.h. Signed-off-by: Michael Straube --- .../rtl8188eu/include/hal8188e_phy_reg.h | 881 -- 1 file changed, 881 deletions(-) diff --git a/drivers/staging/rtl8188eu/include/hal8188e_phy_reg.h b/drivers/staging/rtl8188eu/include/hal8188e_phy_reg.h index 53afcea21c96..bd915a1f2511 100644 --- a/drivers/staging/rtl8188eu/include/hal8188e_phy_reg.h +++ b/drivers/staging/rtl8188eu/include/hal8188e_phy_reg.h @@ -16,55 +16,10 @@ /* 5. Other definition for BB/RF R/W */ /* */ - -/* */ -/* 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF */ -/* 1. Page1(0x100) */ -/* */ -#definerPMAC_Reset 0x100 -#definerPMAC_TxStart 0x104 -#definerPMAC_TxLegacySIG 0x108 -#definerPMAC_TxHTSIG1 0x10c -#definerPMAC_TxHTSIG2 0x110 -#definerPMAC_PHYDebug 0x114 -#definerPMAC_TxPacketNum 0x118 -#definerPMAC_TxIdle0x11c -#definerPMAC_TxMACHeader0 0x120 -#definerPMAC_TxMACHeader1 0x124 -#definerPMAC_TxMACHeader2 0x128 -#definerPMAC_TxMACHeader3 0x12c -#definerPMAC_TxMACHeader4 0x130 -#definerPMAC_TxMACHeader5 0x134 -#definerPMAC_TxDataType0x138 -#definerPMAC_TxRandomSeed 0x13c -#definerPMAC_CCKPLCPPreamble 0x140 -#definerPMAC_CCKPLCPHeader 0x144 -#definerPMAC_CCKCRC16 0x148 -#definerPMAC_OFDMRxCRC32OK 0x170 -#definerPMAC_OFDMRxCRC32Er 0x174 -#definerPMAC_OFDMRxParityEr0x178 -#definerPMAC_OFDMRxCRC8Er 0x17c -#definerPMAC_CCKCRxRC16Er 0x180 -#definerPMAC_CCKCRxRC32Er 0x184 -#definerPMAC_CCKCRxRC32OK 0x188 -#definerPMAC_TxStatus 0x18c - -/* 2. Page2(0x200) */ -/* The following two definition are only used for USB interface. */ -#defineRF_BB_CMD_ADDR 0x02c0 /* RF/BB r/w cmd address. */ -#defineRF_BB_CMD_DATA 0x02c4 /* RF/BB r/w cmd data. */ - /* 3. Page8(0x800) */ #definerFPGA0_RFMOD0x800 /* RF mode & CCK TxSC RF BW Setting */ - -#definerFPGA0_TxInfo 0x804 /* Status report?? */ -#definerFPGA0_PSDFunction 0x808 - #definerFPGA0_TxGainStage 0x80c /* Set TX PWR init gain? */ -#definerFPGA0_RFTiming10x810 /* Useless now */ -#definerFPGA0_RFTiming20x814 - #definerFPGA0_XA_HSSIParameter10x820 /* RF 3 wire register */ #definerFPGA0_XA_HSSIParameter20x824 #definerFPGA0_XB_HSSIParameter10x828 @@ -73,9 +28,6 @@ #definerFPGA0_XA_LSSIParameter 0x840 #definerFPGA0_XB_LSSIParameter 0x844 -#definerFPGA0_RFWakeUpParameter0x850 /* Useless now */ -#definerFPGA0_RFSleepUpParameter 0x854 - #definerFPGA0_XAB_SwitchControl0x858 /* RF Channel switch */ #definerFPGA0_XCD_SwitchControl0x85c @@ -86,181 +38,63 @@ #definerFPGA0_XCD_RFInterfaceSW0x874 #definerFPGA0_XAB_RFParameter 0x878 /* RF Parameter */ -#definerFPGA0_XCD_RFParameter 0x87c - -/* Crystal cap setting RF-R/W protection for parameter4?? */ -#definerFPGA0_AnalogParameter1 0x880 -#definerFPGA0_AnalogParameter2 0x884 -#definerFPGA0_AnalogParameter3 0x888 -/* enable ad/da clock1 for dual-phy */ -#definerFPGA0_AdDaClockEn 0x888 -#definerFPGA0_AnalogParameter4 0x88c #definerFPGA0_XA_LSSIReadBack 0x8a0 /* Tranceiver LSSI Readback */ #definerFPGA0_XB_LSSIReadBack 0x8a4 -#definerFPGA0_XC_LSSIReadBack 0x8a8 -#definerFPGA0_XD_LSSIReadBack 0x8ac -#definerFPGA0_PSDReport0x8b4 /* Useless now */ -/* Transceiver A HSPI Readback */ #defineTransceiverA_HSPI_Readback 0x8b8 -/* Transceiver B HSPI Readback */ #defineTransceiverB_HSPI_Readback 0x8bc -/* Useless now RF Interface Readback Value */ #definerFPGA0_XAB_RFInterfaceRB0x8e0 -#definerFPGA0_XCD_RFInterfaceRB0x8e4 /* Useless now */ /* 4. Page9(0x900) */ /* RF mode & OFDM TxSC RF BW Setting?? */ #definerFPGA1_RFMOD0x900 -#definerFPGA1_TxBlock 0x904 /* Useless now */ -#definerFPGA1_DebugSelect 0x908 /* Useless now */ -#definerFPGA1_TxInfo 0x90c /* Useless now Status report */ - /* 5. PageA(0xA00) */ /* Set Control channel to upper or lower - required only for 40MHz */ #definerCCK0_System0xa00 -/* Disable init gain
RE: [PATCH] x86/hyper-v: Zero out the VP assist page to fix CPU offlining
From: Dexuan Cui Sent: Wednesday, July 3, 2019 6:46 PM
>
> When a CPU is being offlined, the CPU usually still receives a few
> interrupts (e.g. reschedule IPIs), after hv_cpu_die() disables the
> HV_X64_MSR_VP_ASSIST_PAGE, so hv_apic_eoi_write() may not write the EOI
> MSR, if the apic_assist field's bit0 happens to be 1; as a result, Hyper-V
> may not be able to deliver all the interrupts to the CPU, and the CPU may
> not be stopped, and the kernel will hang soon.
>
> The VP ASSIST PAGE is an "overlay" page (see Hyper-V TLFS's Section
> 5.2.1 "GPA Overlay Pages"), so with this fix we're sure the apic_assist
> field is still zero, after the VP ASSIST PAGE is disabled.
>
> Fixes: ba696429d290 ("x86/hyper-v: Implement EOI assist")
> Signed-off-by: Dexuan Cui
> ---
> arch/x86/hyperv/hv_init.c | 8 +++-
> 1 file changed, 7 insertions(+), 1 deletion(-)
>
> diff --git a/arch/x86/hyperv/hv_init.c b/arch/x86/hyperv/hv_init.c
> index 0e033ef11a9f..db51a301f759 100644
> --- a/arch/x86/hyperv/hv_init.c
> +++ b/arch/x86/hyperv/hv_init.c
> @@ -60,8 +60,14 @@ static int hv_cpu_init(unsigned int cpu)
> if (!hv_vp_assist_page)
> return 0;
>
> + /*
> + * The ZERO flag is necessary, because in the case of CPU offlining
> + * the page can still be used by hv_apic_eoi_write() for a while,
> + * after the VP ASSIST PAGE is disabled in hv_cpu_die().
> + */
> if (!*hvp)
> - *hvp = __vmalloc(PAGE_SIZE, GFP_KERNEL, PAGE_KERNEL);
> + *hvp = __vmalloc(PAGE_SIZE, GFP_KERNEL | __GFP_ZERO,
> + PAGE_KERNEL);
>
> if (*hvp) {
> u64 val;
> --
> 2.19.1
Reviewed-by: Michael Kelley
[PATCH 1/3] staging: most: dim2: Replace function dim_norm_ctrl_async_buffer_size()
Remove function dim_norm_ctrl_async_buffer_size as it does nothing
except call norm_ctrl_async_buffer_size.
Rename norm_ctrl_async_buffer_size to dim_norm_ctrl_async_buffer_size to
maintain compatibility with call sites of the latter.
Change type of new dim_norm_ctrl_async_buffer_size from static inline to
non-static to match the old version.
Modify only remaining call site of norm_ctrl_async_buffer_size to call
dim_norm_ctrl_async_buffer_size instead.
Issue found with Coccinelle.
Signed-off-by: Nishka Dasgupta
---
drivers/staging/most/dim2/hal.c | 9 ++---
1 file changed, 2 insertions(+), 7 deletions(-)
diff --git a/drivers/staging/most/dim2/hal.c b/drivers/staging/most/dim2/hal.c
index 699e02f83bd4..d4d532e76147 100644
--- a/drivers/staging/most/dim2/hal.c
+++ b/drivers/staging/most/dim2/hal.c
@@ -471,7 +471,7 @@ static inline bool check_bytes_per_frame(u32
bytes_per_frame)
return true;
}
-static inline u16 norm_ctrl_async_buffer_size(u16 buf_size)
+u16 dim_norm_ctrl_async_buffer_size(u16 buf_size)
{
u16 const max_size = (u16)ADT1_CTRL_ASYNC_BD_MASK + 1u;
@@ -652,7 +652,7 @@ static bool channel_start(struct dim_channel *ch, u32
buf_addr, u16 buf_size)
return dim_on_error(DIM_ERR_BAD_BUFFER_SIZE, "Bad buffer size");
if (ch->packet_length == 0 && ch->bytes_per_frame == 0 &&
- buf_size != norm_ctrl_async_buffer_size(buf_size))
+ buf_size != dim_norm_ctrl_async_buffer_size(buf_size))
return dim_on_error(DIM_ERR_BAD_BUFFER_SIZE,
"Bad control/async buffer size");
@@ -780,11 +780,6 @@ void dim_service_mlb_int_irq(void)
dimcb_io_write(&g.dim2->MS1, 0);
}
-u16 dim_norm_ctrl_async_buffer_size(u16 buf_size)
-{
- return norm_ctrl_async_buffer_size(buf_size);
-}
-
/**
* Retrieves maximal possible correct buffer size for isochronous data type
* conform to given packet length and not bigger than given buffer size.
--
2.19.1
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[PATCH 3/3] staging: most: dim2: Remove function dimcb_io_write()
Remove function dimcb_io_write as all it does is call writel.
Modify calls to dimcb_io_write to writel, flipping the order of the
arguments as required.
Issue found with Coccinelle.
Signed-off-by: Nishka Dasgupta
---
drivers/staging/most/dim2/dim2.c | 10
drivers/staging/most/dim2/hal.c | 79 +++-
drivers/staging/most/dim2/hal.h | 2 -
3 files changed, 38 insertions(+), 53 deletions(-)
diff --git a/drivers/staging/most/dim2/dim2.c b/drivers/staging/most/dim2/dim2.c
index 8d3da8e1d436..043a3e14fdfc 100644
--- a/drivers/staging/most/dim2/dim2.c
+++ b/drivers/staging/most/dim2/dim2.c
@@ -128,16 +128,6 @@ bool dim2_sysfs_get_state_cb(void)
return state;
}
-/**
- * dimcb_io_write - callback from HAL to write value to an I/O register
- * @ptr32: register address
- * @value: value to write
- */
-void dimcb_io_write(u32 __iomem *ptr32, u32 value)
-{
- writel(value, ptr32);
-}
-
/**
* dimcb_on_error - callback from HAL to report miscommunication between
* HDM and HAL
diff --git a/drivers/staging/most/dim2/hal.c b/drivers/staging/most/dim2/hal.c
index fcf5d2a0f491..39e17a7d2f24 100644
--- a/drivers/staging/most/dim2/hal.c
+++ b/drivers/staging/most/dim2/hal.c
@@ -144,13 +144,13 @@ static void free_dbr(int offs, int size)
static void dim2_transfer_madr(u32 val)
{
- dimcb_io_write(&g.dim2->MADR, val);
+ writel(val, &g.dim2->MADR);
/* wait for transfer completion */
while ((readl(&g.dim2->MCTL) & 1) != 1)
continue;
- dimcb_io_write(&g.dim2->MCTL, 0); /* clear transfer complete */
+ writel(0, &g.dim2->MCTL); /* clear transfer complete */
}
static void dim2_clear_dbr(u16 addr, u16 size)
@@ -160,8 +160,8 @@ static void dim2_clear_dbr(u16 addr, u16 size)
u16 const end_addr = addr + size;
u32 const cmd = bit_mask(MADR_WNR_BIT) | bit_mask(MADR_TB_BIT);
- dimcb_io_write(&g.dim2->MCTL, 0); /* clear transfer complete */
- dimcb_io_write(&g.dim2->MDAT0, 0);
+ writel(0, &g.dim2->MCTL); /* clear transfer complete */
+ writel(0, &g.dim2->MDAT0);
for (; addr < end_addr; addr++)
dim2_transfer_madr(cmd | addr);
@@ -178,21 +178,21 @@ static void dim2_write_ctr_mask(u32 ctr_addr, const u32
*mask, const u32 *value)
{
enum { MADR_WNR_BIT = 31 };
- dimcb_io_write(&g.dim2->MCTL, 0); /* clear transfer complete */
+ writel(0, &g.dim2->MCTL); /* clear transfer complete */
if (mask[0] != 0)
- dimcb_io_write(&g.dim2->MDAT0, value[0]);
+ writel(value[0], &g.dim2->MDAT0);
if (mask[1] != 0)
- dimcb_io_write(&g.dim2->MDAT1, value[1]);
+ writel(value[1], &g.dim2->MDAT1);
if (mask[2] != 0)
- dimcb_io_write(&g.dim2->MDAT2, value[2]);
+ writel(value[2], &g.dim2->MDAT2);
if (mask[3] != 0)
- dimcb_io_write(&g.dim2->MDAT3, value[3]);
+ writel(value[3], &g.dim2->MDAT3);
- dimcb_io_write(&g.dim2->MDWE0, mask[0]);
- dimcb_io_write(&g.dim2->MDWE1, mask[1]);
- dimcb_io_write(&g.dim2->MDWE2, mask[2]);
- dimcb_io_write(&g.dim2->MDWE3, mask[3]);
+ writel(mask[0], &g.dim2->MDWE0);
+ writel(mask[1], &g.dim2->MDWE1);
+ writel(mask[2], &g.dim2->MDWE2);
+ writel(mask[3], &g.dim2->MDWE3);
dim2_transfer_madr(bit_mask(MADR_WNR_BIT) | ctr_addr);
}
@@ -357,15 +357,13 @@ static void dim2_configure_channel(
dim2_configure_cat(AHB_CAT, ch_addr, type, is_tx ? 0 : 1);
/* unmask interrupt for used channel, enable mlb_sys_int[0] interrupt */
- dimcb_io_write(&g.dim2->ACMR0,
- readl(&g.dim2->ACMR0) | bit_mask(ch_addr));
+ writel(readl(&g.dim2->ACMR0) | bit_mask(ch_addr), &g.dim2->ACMR0);
}
static void dim2_clear_channel(u8 ch_addr)
{
/* mask interrupt for used channel, disable mlb_sys_int[0] interrupt */
- dimcb_io_write(&g.dim2->ACMR0,
- readl(&g.dim2->ACMR0) & ~bit_mask(ch_addr));
+ writel(readl(&g.dim2->ACMR0) & ~bit_mask(ch_addr), &g.dim2->ACMR0);
dim2_clear_cat(AHB_CAT, ch_addr);
dim2_clear_adt(ch_addr);
@@ -374,7 +372,7 @@ static void dim2_clear_channel(u8 ch_addr)
dim2_clear_cdt(ch_addr);
/* clear channel status bit */
- dimcb_io_write(&g.dim2->ACSR0, bit_mask(ch_addr));
+ writel(bit_mask(ch_addr), &g.dim2->ACSR0);
}
/* --
*/
@@ -518,20 +516,20 @@ static inline u16 norm_sync_buffer_size(u16 buf_size, u16
bytes_per_frame)
static void dim2_cleanup(void)
{
/* disable MediaLB */
- dimcb_io_write(&g.dim2->MLBC0, false << MLBC0_MLBEN_BIT);
+ writel(false << MLBC0_MLBEN_BIT, &g.dim2->MLBC0);
dim2_clear_ctram();
/* disable mlb_int interrupt */
- dimcb_io_write(&g.dim2->MIEN, 0);
+
[PATCH 2/3] staging: most: dim2: Remove function dimcb_io_read()
Remove function dimcb_io_read as it does nothing except call inbuilt
function readl.
Modify call sites accordingly.
Issue found with Coccinelle.
Signed-off-by: Nishka Dasgupta
---
drivers/staging/most/dim2/dim2.c | 9 -
drivers/staging/most/dim2/hal.c | 15 ---
drivers/staging/most/dim2/hal.h | 2 --
3 files changed, 8 insertions(+), 18 deletions(-)
diff --git a/drivers/staging/most/dim2/dim2.c b/drivers/staging/most/dim2/dim2.c
index 31fbc1a75b06..8d3da8e1d436 100644
--- a/drivers/staging/most/dim2/dim2.c
+++ b/drivers/staging/most/dim2/dim2.c
@@ -128,15 +128,6 @@ bool dim2_sysfs_get_state_cb(void)
return state;
}
-/**
- * dimcb_io_read - callback from HAL to read an I/O register
- * @ptr32: register address
- */
-u32 dimcb_io_read(u32 __iomem *ptr32)
-{
- return readl(ptr32);
-}
-
/**
* dimcb_io_write - callback from HAL to write value to an I/O register
* @ptr32: register address
diff --git a/drivers/staging/most/dim2/hal.c b/drivers/staging/most/dim2/hal.c
index d4d532e76147..fcf5d2a0f491 100644
--- a/drivers/staging/most/dim2/hal.c
+++ b/drivers/staging/most/dim2/hal.c
@@ -13,6 +13,7 @@
#include "reg.h"
#include
#include
+#include
/*
* Size factor for isochronous DBR buffer.
@@ -146,7 +147,7 @@ static void dim2_transfer_madr(u32 val)
dimcb_io_write(&g.dim2->MADR, val);
/* wait for transfer completion */
- while ((dimcb_io_read(&g.dim2->MCTL) & 1) != 1)
+ while ((readl(&g.dim2->MCTL) & 1) != 1)
continue;
dimcb_io_write(&g.dim2->MCTL, 0); /* clear transfer complete */
@@ -170,7 +171,7 @@ static u32 dim2_read_ctr(u32 ctr_addr, u16 mdat_idx)
{
dim2_transfer_madr(ctr_addr);
- return dimcb_io_read((&g.dim2->MDAT0) + mdat_idx);
+ return readl((&g.dim2->MDAT0) + mdat_idx);
}
static void dim2_write_ctr_mask(u32 ctr_addr, const u32 *mask, const u32
*value)
@@ -357,14 +358,14 @@ static void dim2_configure_channel(
/* unmask interrupt for used channel, enable mlb_sys_int[0] interrupt */
dimcb_io_write(&g.dim2->ACMR0,
- dimcb_io_read(&g.dim2->ACMR0) | bit_mask(ch_addr));
+ readl(&g.dim2->ACMR0) | bit_mask(ch_addr));
}
static void dim2_clear_channel(u8 ch_addr)
{
/* mask interrupt for used channel, disable mlb_sys_int[0] interrupt */
dimcb_io_write(&g.dim2->ACMR0,
- dimcb_io_read(&g.dim2->ACMR0) & ~bit_mask(ch_addr));
+ readl(&g.dim2->ACMR0) & ~bit_mask(ch_addr));
dim2_clear_cat(AHB_CAT, ch_addr);
dim2_clear_adt(ch_addr);
@@ -562,12 +563,12 @@ static bool dim2_is_mlb_locked(void)
u32 const mask0 = bit_mask(MLBC0_MLBLK_BIT);
u32 const mask1 = bit_mask(MLBC1_CLKMERR_BIT) |
bit_mask(MLBC1_LOCKERR_BIT);
- u32 const c1 = dimcb_io_read(&g.dim2->MLBC1);
+ u32 const c1 = readl(&g.dim2->MLBC1);
u32 const nda_mask = (u32)MLBC1_NDA_MASK << MLBC1_NDA_SHIFT;
dimcb_io_write(&g.dim2->MLBC1, c1 & nda_mask);
- return (dimcb_io_read(&g.dim2->MLBC1) & mask1) == 0 &&
- (dimcb_io_read(&g.dim2->MLBC0) & mask0) != 0;
+ return (readl(&g.dim2->MLBC1) & mask1) == 0 &&
+ (readl(&g.dim2->MLBC0) & mask0) != 0;
}
/* --
*/
diff --git a/drivers/staging/most/dim2/hal.h b/drivers/staging/most/dim2/hal.h
index fca6c22de8a6..d16268bd9317 100644
--- a/drivers/staging/most/dim2/hal.h
+++ b/drivers/staging/most/dim2/hal.h
@@ -97,8 +97,6 @@ bool dim_enqueue_buffer(struct dim_channel *ch, u32
buffer_addr,
bool dim_detach_buffers(struct dim_channel *ch, u16 buffers_number);
-u32 dimcb_io_read(u32 __iomem *ptr32);
-
void dimcb_io_write(u32 __iomem *ptr32, u32 value);
void dimcb_on_error(u8 error_id, const char *error_message);
--
2.19.1
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