Re: [PATCH] staging: ion: remove from the tree
On Thu, Aug 27, 2020 at 11:54:12AM -0700, John Stultz wrote: > On Thu, Aug 27, 2020 at 10:17 AM Greg Kroah-Hartman > wrote: > > On Thu, Aug 27, 2020 at 10:31:41PM +0530, Amit Pundir wrote: > > > I don't know what is the right thing to do here. I just want to > > > highlight that AOSP's audio (codec2) HAL depends on the ION system > > > heap and it will break AOSP for people who boot mainline on their > > > devices, even for just testing purpose like we do in Linaro. Right now > > > we need only 1 (Android specific out-of-tree) patch to boot AOSP with > > > mainline and Sumit is already trying to upstream that vma naming > > > patch. Removal of in-kernel ION, will just add more to that delta. > > > > As AOSP will continue to rely on ION after December of this year, all > > you are doing is postponing the inevitable a few more months. > > > > Push back on the Android team to fix up the code to not use ION, they > > know this needs to happen. > > The point though, is your main premise that no one is using this isn't true. They are using the version of ion in the Android kernel tree, yes, as it has new features that many people are relying on. The version that is currently in the kernel tree is crippled, and maybe works for some use cases, but not the majority, right? > I'm actively working with Hridya and folks on the codec2 HAL side to > transition this on the userland side: > https://android-review.googlesource.com/c/platform/frameworks/av/+/1368918/3 > > I'd like AOSP to not use ION after September (though being external I > can't promise anything), much less continuing after December. The android team has said they will be dropping ION use for the "next" Android release, which is sometime next year from what I recall. December is probably not going to happen :) > I want this migration to happen as much as anyone. But I'd prefer to > keep ION in staging until after the LTS is announced. Having both > around helps development for the transition, which helps us have a > reliable solution, which helps vendors to migrate and be able to do > comparative performance testing. I don't understand what having this in the "next" kernel helps us with here. And I would really really prefer to NOT have an outdated version of this code in a kernel tree that I am going to have to support for the next X number of years, when no one is using that version of the driver. What is this LTS fixation to keep this code around for? Who does it help? > I do appreciate that keeping it isn't free, but I also don't feel the > chaos-monkey approach here is really motivational in the way you > intend. I don't see it helping anyone to leave this around, except to cause merge issues for me, and development issues for other developers. Anyone who really wants this code, can easily revert the deletion and move on and grab the AOSP copy of the code. That's what they did when we deleted other Android features that are still relied on. Given that the "isn't free" is causing _me_ real pain, and not the actual users of this code, I am leaning toward wanting to move that pain/cost to those users, for obvious reasons. thanks, greg k-h ___ devel mailing list de...@linuxdriverproject.org http://driverdev.linuxdriverproject.org/mailman/listinfo/driverdev-devel
[PATCH v6 0/8] clk: clk-wizard: clock-wizard: Driver updates
In the thread [1] Greg suggested that we move the driver to the clk from the staging. Add patches to address the concerns regarding the fractional and set rate support in the TODO. The patch set does the following - Trivial fixes for kernel doc. - Move the driver to the clk folder - Add capability to set rate. - Add fractional support. - Add support for configurable outputs. - Make the output names unique so that multiple instances do not crib. Changes in the v3: Added the cover-letter. Add patches for rate setting and fractional support Add patches for warning. Remove the driver from staging as suggested v4: Reorder the patches. Merge the CLK_IS_BASIC patch. Add the yaml form of binding document v5: Fix a mismerge v6: Fix the yaml warning use poll timedout [1] https://spinics.net/lists/linux-driver-devel/msg117326.html Shubhrajyoti Datta (8): dt-bindings: add documentation of xilinx clocking wizard clk: clock-wizard: Add the clockwizard to clk directory clk: clock-wizard: Fix kernel-doc warning clk: clock-wizard: Add support for dynamic reconfiguration clk: clock-wizard: Add support for fractional support clk: clock-wizard: Remove the hardcoding of the clock outputs clk: clock-wizard: Update the fixed factor divisors staging: clocking-wizard: Delete the driver from the staging .../bindings/clock/xlnx,clocking-wizard.yaml | 71 +++ drivers/clk/Kconfig| 9 + drivers/clk/Makefile | 1 + drivers/clk/clk-xlnx-clock-wizard.c| 657 + drivers/staging/Kconfig| 2 - drivers/staging/Makefile | 1 - drivers/staging/clocking-wizard/Kconfig| 10 - drivers/staging/clocking-wizard/Makefile | 2 - drivers/staging/clocking-wizard/TODO | 12 - .../clocking-wizard/clk-xlnx-clock-wizard.c| 333 --- drivers/staging/clocking-wizard/dt-binding.txt | 30 - 11 files changed, 738 insertions(+), 390 deletions(-) create mode 100644 Documentation/devicetree/bindings/clock/xlnx,clocking-wizard.yaml create mode 100644 drivers/clk/clk-xlnx-clock-wizard.c delete mode 100644 drivers/staging/clocking-wizard/Kconfig delete mode 100644 drivers/staging/clocking-wizard/Makefile delete mode 100644 drivers/staging/clocking-wizard/TODO delete mode 100644 drivers/staging/clocking-wizard/clk-xlnx-clock-wizard.c delete mode 100644 drivers/staging/clocking-wizard/dt-binding.txt -- 2.1.1 ___ devel mailing list de...@linuxdriverproject.org http://driverdev.linuxdriverproject.org/mailman/listinfo/driverdev-devel
[PATCH v6 2/8] clk: clock-wizard: Add the clockwizard to clk directory
Add clocking wizard driver to clk.
Signed-off-by: Shubhrajyoti Datta
---
drivers/clk/Kconfig | 9 +
drivers/clk/Makefile| 1 +
drivers/clk/clk-xlnx-clock-wizard.c | 338
3 files changed, 348 insertions(+)
create mode 100644 drivers/clk/clk-xlnx-clock-wizard.c
diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index 4026fac..a0e29dd 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -359,6 +359,15 @@ config COMMON_CLK_FIXED_MMIO
help
Support for Memory Mapped IO Fixed clocks
+config COMMON_CLK_XLNX_CLKWZRD
+ tristate "Xilinx Clocking Wizard"
+ depends on COMMON_CLK && OF
+ help
+ Support for the Xilinx Clocking Wizard IP core clock generator.
+ Adds support for clocking wizard and compatible.
+ This driver supports the Xilinx clocking wizard programmable clock
+ synthesizer. The number of output is configurable in the design.
+
source "drivers/clk/actions/Kconfig"
source "drivers/clk/analogbits/Kconfig"
source "drivers/clk/baikal-t1/Kconfig"
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index da8fcf1..1ad6414 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -69,6 +69,7 @@ obj-$(CONFIG_ARCH_VT8500) += clk-vt8500.o
obj-$(CONFIG_COMMON_CLK_VC5) += clk-versaclock5.o
obj-$(CONFIG_COMMON_CLK_WM831X)+= clk-wm831x.o
obj-$(CONFIG_COMMON_CLK_XGENE) += clk-xgene.o
+obj-$(CONFIG_COMMON_CLK_XLNX_CLKWZRD) += clk-xlnx-clock-wizard.o
# please keep this section sorted lexicographically by directory path name
obj-y += actions/
diff --git a/drivers/clk/clk-xlnx-clock-wizard.c
b/drivers/clk/clk-xlnx-clock-wizard.c
new file mode 100644
index 000..b31524a
--- /dev/null
+++ b/drivers/clk/clk-xlnx-clock-wizard.c
@@ -0,0 +1,338 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Xilinx 'Clocking Wizard' driver
+ *
+ * Copyright (C) 2013 - 2020 Xilinx
+ *
+ * Sören Brinkmann
+ * Shubhrajyoti Datta
+ *
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define WZRD_NUM_OUTPUTS 7
+#define WZRD_ACLK_MAX_FREQ 25000UL
+
+#define WZRD_CLK_CFG_REG(n)(0x200 + 4 * (n))
+
+#define WZRD_CLKOUT0_FRAC_EN BIT(18)
+#define WZRD_CLKFBOUT_FRAC_EN BIT(26)
+
+#define WZRD_CLKFBOUT_MULT_SHIFT 8
+#define WZRD_CLKFBOUT_MULT_MASK(0xff <<
WZRD_CLKFBOUT_MULT_SHIFT)
+#define WZRD_DIVCLK_DIVIDE_SHIFT 0
+#define WZRD_DIVCLK_DIVIDE_MASK(0xff <<
WZRD_DIVCLK_DIVIDE_SHIFT)
+#define WZRD_CLKOUT_DIVIDE_SHIFT 0
+#define WZRD_CLKOUT_DIVIDE_MASK(0xff <<
WZRD_DIVCLK_DIVIDE_SHIFT)
+
+enum clk_wzrd_int_clks {
+ wzrd_clk_mul,
+ wzrd_clk_mul_div,
+ wzrd_clk_int_max
+};
+
+/**
+ * struct clk_wzrd:
+ * @clk_data: Clock data
+ * @nb:Notifier block
+ * @base: Memory base
+ * @clk_in1: Handle to input clock 'clk_in1'
+ * @axi_clk: Handle to input clock 's_axi_aclk'
+ * @clks_internal: Internal clocks
+ * @clkout:Output clocks
+ * @speed_grade: Speed grade of the device
+ * @suspended: Flag indicating power state of the device
+ */
+struct clk_wzrd {
+ struct clk_onecell_data clk_data;
+ struct notifier_block nb;
+ void __iomem *base;
+ struct clk *clk_in1;
+ struct clk *axi_clk;
+ struct clk *clks_internal[wzrd_clk_int_max];
+ struct clk *clkout[WZRD_NUM_OUTPUTS];
+ unsigned int speed_grade;
+ bool suspended;
+};
+
+#define to_clk_wzrd(_nb) container_of(_nb, struct clk_wzrd, nb)
+
+/* maximum frequencies for input/output clocks per speed grade */
+static const unsigned long clk_wzrd_max_freq[] = {
+ 8UL,
+ 93300UL,
+ 106600UL
+};
+
+static int clk_wzrd_clk_notifier(struct notifier_block *nb, unsigned long
event,
+void *data)
+{
+ unsigned long max;
+ struct clk_notifier_data *ndata = data;
+ struct clk_wzrd *clk_wzrd = to_clk_wzrd(nb);
+
+ if (clk_wzrd->suspended)
+ return NOTIFY_OK;
+
+ if (ndata->clk == clk_wzrd->clk_in1)
+ max = clk_wzrd_max_freq[clk_wzrd->speed_grade - 1];
+ else if (ndata->clk == clk_wzrd->axi_clk)
+ max = WZRD_ACLK_MAX_FREQ;
+ else
+ return NOTIFY_DONE; /* should never happen */
+
+ switch (event) {
+ case PRE_RATE_CHANGE:
+ if (ndata->new_rate > max)
+ return NOTIFY_BAD;
+ return NOTIFY_OK;
+ case POST_RATE_CHANGE:
+ case ABORT_RATE_CHANGE:
+ default:
+ return NOTIFY_DONE;
+ }
+}
+
+static int __maybe_unused clk_wzrd_suspend(struct device *dev)
+{
+ struct clk_wzrd *clk_wzrd = dev_get_drvdata(dev);
+
+
[PATCH v6 3/8] clk: clock-wizard: Fix kernel-doc warning
Update description for the clocking wizard structure
Signed-off-by: Shubhrajyoti Datta
---
drivers/clk/clk-xlnx-clock-wizard.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/clk-xlnx-clock-wizard.c
b/drivers/clk/clk-xlnx-clock-wizard.c
index b31524a..d6577c8 100644
--- a/drivers/clk/clk-xlnx-clock-wizard.c
+++ b/drivers/clk/clk-xlnx-clock-wizard.c
@@ -40,7 +40,8 @@ enum clk_wzrd_int_clks {
};
/**
- * struct clk_wzrd:
+ * struct clk_wzrd - Clock wizard private data structure
+ *
* @clk_data: Clock data
* @nb:Notifier block
* @base: Memory base
--
2.1.1
___
devel mailing list
de...@linuxdriverproject.org
http://driverdev.linuxdriverproject.org/mailman/listinfo/driverdev-devel
[PATCH v6 5/8] clk: clock-wizard: Add support for fractional support
Currently the set rate granularity is to integral divisors.
Add support for the fractional divisors.
Only the first output0 is fractional in the hardware.
Signed-off-by: Shubhrajyoti Datta
---
v6:
remove unnecessary typecast
remove unnecessary locks
use polled timeout
drivers/clk/clk-xlnx-clock-wizard.c | 166 +---
1 file changed, 153 insertions(+), 13 deletions(-)
diff --git a/drivers/clk/clk-xlnx-clock-wizard.c
b/drivers/clk/clk-xlnx-clock-wizard.c
index 8dfcec8..1af59a4 100644
--- a/drivers/clk/clk-xlnx-clock-wizard.c
+++ b/drivers/clk/clk-xlnx-clock-wizard.c
@@ -29,20 +29,25 @@
#define WZRD_CLKFBOUT_MULT_SHIFT 8
#define WZRD_CLKFBOUT_MULT_MASK(0xff <<
WZRD_CLKFBOUT_MULT_SHIFT)
+#define WZRD_CLKFBOUT_FRAC_SHIFT 16
+#define WZRD_CLKFBOUT_FRAC_MASK(0x3ff <<
WZRD_CLKFBOUT_FRAC_SHIFT)
#define WZRD_DIVCLK_DIVIDE_SHIFT 0
#define WZRD_DIVCLK_DIVIDE_MASK(0xff <<
WZRD_DIVCLK_DIVIDE_SHIFT)
#define WZRD_CLKOUT_DIVIDE_SHIFT 0
#define WZRD_CLKOUT_DIVIDE_WIDTH 8
#define WZRD_CLKOUT_DIVIDE_MASK(0xff <<
WZRD_DIVCLK_DIVIDE_SHIFT)
+#define WZRD_CLKOUT_FRAC_SHIFT 8
+#define WZRD_CLKOUT_FRAC_MASK 0x3ff
#define WZRD_DR_MAX_INT_DIV_VALUE 255
-#define WZRD_DR_NUM_RETRIES1
#define WZRD_DR_STATUS_REG_OFFSET 0x04
#define WZRD_DR_LOCK_BIT_MASK 0x0001
#define WZRD_DR_INIT_REG_OFFSET0x25C
#define WZRD_DR_DIV_TO_PHASE_OFFSET4
#define WZRD_DR_BEGIN_DYNA_RECONF 0x03
+#define WZRD_USEC_POLL 10
+#define WZRD_TIMEOUT_POLL 1000
/* Get the mask from width */
#define div_mask(width)((1 << (width)) - 1)
@@ -52,6 +57,7 @@
enum clk_wzrd_int_clks {
wzrd_clk_mul,
wzrd_clk_mul_div,
+ wzrd_clk_mul_frac,
wzrd_clk_int_max
};
@@ -185,6 +191,134 @@ static const struct clk_ops clk_wzrd_clk_divider_ops = {
.recalc_rate = clk_wzrd_recalc_rate,
};
+static unsigned long clk_wzrd_recalc_ratef(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ unsigned int val;
+ u32 div, frac;
+ struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw);
+ void __iomem *div_addr = divider->base + divider->offset;
+
+ val = readl(div_addr);
+ div = val & div_mask(divider->width);
+ frac = (val >> WZRD_CLKOUT_FRAC_SHIFT) & WZRD_CLKOUT_FRAC_MASK;
+
+ return ((parent_rate * 1000) / ((div * 1000) + frac));
+}
+
+static int clk_wzrd_dynamic_reconfig_f(struct clk_hw *hw, unsigned long rate,
+ unsigned long parent_rate)
+{
+ int err;
+ u32 value, pre;
+ unsigned long rate_div, f, clockout0_div;
+ struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw);
+ void __iomem *div_addr = divider->base + divider->offset;
+
+ rate_div = ((parent_rate * 1000) / rate);
+ clockout0_div = rate_div / 1000;
+
+ pre = DIV_ROUND_CLOSEST((parent_rate * 1000), rate);
+ f = (u32)(pre - (clockout0_div * 1000));
+ f = f & WZRD_CLKOUT_FRAC_MASK;
+
+ value = ((f << WZRD_CLKOUT_DIVIDE_WIDTH) | (clockout0_div &
+ WZRD_CLKOUT_DIVIDE_MASK));
+
+ /* Set divisor and clear phase offset */
+ writel(value, div_addr);
+ writel(0x0, div_addr + WZRD_DR_DIV_TO_PHASE_OFFSET);
+
+ /* Check status register */
+ err= readl_poll_timeout(divider->base + WZRD_DR_STATUS_REG_OFFSET,
value,
+ value & WZRD_DR_LOCK_BIT_MASK,
+ WZRD_USEC_POLL, WZRD_TIMEOUT_POLL);
+ if (err)
+ return err;
+
+ /* Initiate reconfiguration */
+ writel(WZRD_DR_BEGIN_DYNA_RECONF,
+ divider->base + WZRD_DR_INIT_REG_OFFSET);
+
+ /* Check status register */
+ err= readl_poll_timeout(divider->base + WZRD_DR_STATUS_REG_OFFSET,
value,
+ value & WZRD_DR_LOCK_BIT_MASK,
+ WZRD_USEC_POLL, WZRD_TIMEOUT_POLL);
+
+ return err;
+}
+
+static long clk_wzrd_round_rate_f(struct clk_hw *hw, unsigned long rate,
+ unsigned long *prate)
+{
+ return rate;
+}
+
+static const struct clk_ops clk_wzrd_clk_divider_ops_f = {
+ .round_rate = clk_wzrd_round_rate_f,
+ .set_rate = clk_wzrd_dynamic_reconfig_f,
+ .recalc_rate = clk_wzrd_recalc_ratef,
+};
+
+static struct clk *clk_wzrd_register_divf(struct device *dev,
+ const char *name,
+ const char *parent_name,
+ unsigned long flags,
+ void __iomem *base, u16 offset,
+ u8 shift, u8 width,
+ u8 clk
[PATCH v6 8/8] staging: clocking-wizard: Delete the driver from the staging
Delete the driver from the staging as it is in drivers/clk.
Signed-off-by: Shubhrajyoti Datta
Acked-by: Greg Kroah-Hartman
---
drivers/staging/Kconfig| 2 -
drivers/staging/Makefile | 1 -
drivers/staging/clocking-wizard/Kconfig| 10 -
drivers/staging/clocking-wizard/Makefile | 2 -
drivers/staging/clocking-wizard/TODO | 12 -
.../clocking-wizard/clk-xlnx-clock-wizard.c| 333 -
drivers/staging/clocking-wizard/dt-binding.txt | 30 --
7 files changed, 390 deletions(-)
delete mode 100644 drivers/staging/clocking-wizard/Kconfig
delete mode 100644 drivers/staging/clocking-wizard/Makefile
delete mode 100644 drivers/staging/clocking-wizard/TODO
delete mode 100644 drivers/staging/clocking-wizard/clk-xlnx-clock-wizard.c
delete mode 100644 drivers/staging/clocking-wizard/dt-binding.txt
diff --git a/drivers/staging/Kconfig b/drivers/staging/Kconfig
index e6c831c..bae49c6 100644
--- a/drivers/staging/Kconfig
+++ b/drivers/staging/Kconfig
@@ -76,8 +76,6 @@ source "drivers/staging/gs_fpgaboot/Kconfig"
source "drivers/staging/unisys/Kconfig"
-source "drivers/staging/clocking-wizard/Kconfig"
-
source "drivers/staging/fbtft/Kconfig"
source "drivers/staging/fsl-dpaa2/Kconfig"
diff --git a/drivers/staging/Makefile b/drivers/staging/Makefile
index a3b1fd0..f5a3e57 100644
--- a/drivers/staging/Makefile
+++ b/drivers/staging/Makefile
@@ -28,7 +28,6 @@ obj-$(CONFIG_FIREWIRE_SERIAL) += fwserial/
obj-$(CONFIG_GOLDFISH) += goldfish/
obj-$(CONFIG_GS_FPGABOOT) += gs_fpgaboot/
obj-$(CONFIG_UNISYSSPAR) += unisys/
-obj-$(CONFIG_COMMON_CLK_XLNX_CLKWZRD) += clocking-wizard/
obj-$(CONFIG_FB_TFT) += fbtft/
obj-$(CONFIG_FSL_DPAA2)+= fsl-dpaa2/
obj-$(CONFIG_MOST) += most/
diff --git a/drivers/staging/clocking-wizard/Kconfig
b/drivers/staging/clocking-wizard/Kconfig
deleted file mode 100644
index 69cf514..000
--- a/drivers/staging/clocking-wizard/Kconfig
+++ /dev/null
@@ -1,10 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-#
-# Xilinx Clocking Wizard Driver
-#
-
-config COMMON_CLK_XLNX_CLKWZRD
- tristate "Xilinx Clocking Wizard"
- depends on COMMON_CLK && OF && IOMEM
- help
- Support for the Xilinx Clocking Wizard IP core clock generator.
diff --git a/drivers/staging/clocking-wizard/Makefile
b/drivers/staging/clocking-wizard/Makefile
deleted file mode 100644
index b1f9152..000
--- a/drivers/staging/clocking-wizard/Makefile
+++ /dev/null
@@ -1,2 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-obj-$(CONFIG_COMMON_CLK_XLNX_CLKWZRD) += clk-xlnx-clock-wizard.o
diff --git a/drivers/staging/clocking-wizard/TODO
b/drivers/staging/clocking-wizard/TODO
deleted file mode 100644
index ebe99db..000
--- a/drivers/staging/clocking-wizard/TODO
+++ /dev/null
@@ -1,12 +0,0 @@
-TODO:
- - support for fractional multiplier
- - support for fractional divider (output 0 only)
- - support for set_rate() operations (may benefit from Stephen Boyd's
- refactoring of the clk primitives: https://lkml.org/lkml/2014/9/5/766)
- - review arithmetic
- - overflow after multiplication?
- - maximize accuracy before divisions
-
-Patches to:
- Greg Kroah-Hartman
- Sören Brinkmann
diff --git a/drivers/staging/clocking-wizard/clk-xlnx-clock-wizard.c
b/drivers/staging/clocking-wizard/clk-xlnx-clock-wizard.c
deleted file mode 100644
index e52a64b..000
--- a/drivers/staging/clocking-wizard/clk-xlnx-clock-wizard.c
+++ /dev/null
@@ -1,333 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Xilinx 'Clocking Wizard' driver
- *
- * Copyright (C) 2013 - 2014 Xilinx
- *
- * Sören Brinkmann
- */
-
-#include
-#include
-#include
-#include
-#include
-#include
-#include
-#include
-
-#define WZRD_NUM_OUTPUTS 7
-#define WZRD_ACLK_MAX_FREQ 25000UL
-
-#define WZRD_CLK_CFG_REG(n)(0x200 + 4 * (n))
-
-#define WZRD_CLKOUT0_FRAC_EN BIT(18)
-#define WZRD_CLKFBOUT_FRAC_EN BIT(26)
-
-#define WZRD_CLKFBOUT_MULT_SHIFT 8
-#define WZRD_CLKFBOUT_MULT_MASK(0xff <<
WZRD_CLKFBOUT_MULT_SHIFT)
-#define WZRD_DIVCLK_DIVIDE_SHIFT 0
-#define WZRD_DIVCLK_DIVIDE_MASK(0xff <<
WZRD_DIVCLK_DIVIDE_SHIFT)
-#define WZRD_CLKOUT_DIVIDE_SHIFT 0
-#define WZRD_CLKOUT_DIVIDE_MASK(0xff <<
WZRD_DIVCLK_DIVIDE_SHIFT)
-
-enum clk_wzrd_int_clks {
- wzrd_clk_mul,
- wzrd_clk_mul_div,
- wzrd_clk_int_max
-};
-
-/**
- * struct clk_wzrd:
- * @clk_data: Clock data
- * @nb:Notifier block
- * @base: Memory base
- * @clk_in1: Handle to input clock 'clk_in1'
- * @axi_clk: Handle to input clock 's_axi_aclk'
- * @clks_internal: Internal clocks
- * @clkout:Output clocks
- * @speed_grade: Speed grade of the device
- * @suspended: Flag
[PATCH v6 6/8] clk: clock-wizard: Remove the hardcoding of the clock outputs
The number of output clocks are configurable in the hardware.
Currently the driver registers the maximum number of outputs.
Fix the same by registering only the outputs that are there.
Signed-off-by: Shubhrajyoti Datta
---
v4:
Assign output in this patch
drivers/clk/clk-xlnx-clock-wizard.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/clk-xlnx-clock-wizard.c
b/drivers/clk/clk-xlnx-clock-wizard.c
index 1af59a4..ded4cdd 100644
--- a/drivers/clk/clk-xlnx-clock-wizard.c
+++ b/drivers/clk/clk-xlnx-clock-wizard.c
@@ -442,6 +442,7 @@ static int clk_wzrd_probe(struct platform_device *pdev)
const char *clk_name;
struct clk_wzrd *clk_wzrd;
struct resource *mem;
+ int outputs;
struct device_node *np = pdev->dev.of_node;
clk_wzrd = devm_kzalloc(&pdev->dev, sizeof(*clk_wzrd), GFP_KERNEL);
@@ -512,6 +513,7 @@ static int clk_wzrd_probe(struct platform_device *pdev)
goto err_disable_clk;
}
+ outputs = of_property_count_strings(np, "clock-output-names");
/* register div */
reg = (readl(clk_wzrd->base + WZRD_CLK_CFG_REG(0)) &
WZRD_DIVCLK_DIVIDE_MASK) >> WZRD_DIVCLK_DIVIDE_SHIFT;
@@ -533,7 +535,7 @@ static int clk_wzrd_probe(struct platform_device *pdev)
}
/* register div per output */
- for (i = WZRD_NUM_OUTPUTS - 1; i >= 0 ; i--) {
+ for (i = outputs - 1; i >= 0 ; i--) {
const char *clkout_name;
if (of_property_read_string_index(np, "clock-output-names", i,
@@ -564,7 +566,7 @@ static int clk_wzrd_probe(struct platform_device *pdev)
if (IS_ERR(clk_wzrd->clkout[i])) {
int j;
- for (j = i + 1; j < WZRD_NUM_OUTPUTS; j++)
+ for (j = i + 1; j < outputs; j++)
clk_unregister(clk_wzrd->clkout[j]);
dev_err(&pdev->dev,
"unable to register divider clock\n");
--
2.1.1
___
devel mailing list
de...@linuxdriverproject.org
http://driverdev.linuxdriverproject.org/mailman/listinfo/driverdev-devel
[PATCH v6 1/8] dt-bindings: add documentation of xilinx clocking wizard
Add the devicetree binding for the xilinx clocking wizard.
Signed-off-by: Shubhrajyoti Datta
---
v6:
Fix a yaml warning
.../bindings/clock/xlnx,clocking-wizard.yaml | 71 ++
1 file changed, 71 insertions(+)
create mode 100644
Documentation/devicetree/bindings/clock/xlnx,clocking-wizard.yaml
diff --git a/Documentation/devicetree/bindings/clock/xlnx,clocking-wizard.yaml
b/Documentation/devicetree/bindings/clock/xlnx,clocking-wizard.yaml
new file mode 100644
index 000..ca63593
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/xlnx,clocking-wizard.yaml
@@ -0,0 +1,71 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/xlnx,clocking-wizard.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Xilinx clocking wizard
+
+maintainers:
+ - Shubhrajyoti Datta
+
+description: |
+ The clocking wizard is a soft ip clocking block of Xilinx versal. It
+ reads required input clock frequencies from the devicetree and acts as clock
+ clock output.
+
+select: false
+
+properties:
+ compatible:
+items:
+ - enum:
+ - xlnx,clocking-wizard
+ - xlnx,clocking-wizard-6.0
+
+ "#clock-cells":
+const: 1
+
+ clocks:
+description: List of clock specifiers which are external input
+ clocks to the given clock controller.
+items:
+ - description: clock input
+ - description: axi clock
+
+ clock-names:
+items:
+ - const: clk_in1
+ - const: s_axi_aclk
+
+ speed-grade:
+allOf:
+ - $ref: /schemas/types.yaml#/definitions/uint32
+ - enum: [1, 2, 3]
+description:
+ Speed grade of the device.
+maxItems: 1
+
+required:
+ - compatible
+ - "#clock-cells"
+ - clocks
+ - clock-names
+ - speed-grade
+
+additionalProperties: false
+
+examples:
+ - |
+clock-generator@4004 {
+#clock-cells = <1>;
+reg = <0x4004 0x1000>;
+compatible = "xlnx,clk-wizard-1.0";
+speed-grade = <1>;
+clock-names = "clk_in1", "s_axi_aclk";
+clocks = <&clkc 15>, <&clkc 15>;
+clock-output-names = "clk_out1", "clk_out2",
+"clk_out3", "clk_out4", "clk_out5",
+"clk_out6", "clk_out7";
+};
+...
--
2.1.1
___
devel mailing list
de...@linuxdriverproject.org
http://driverdev.linuxdriverproject.org/mailman/listinfo/driverdev-devel
[PATCH v6 4/8] clk: clock-wizard: Add support for dynamic reconfiguration
The patch adds support for dynamic reconfiguration of clock output rate.
Output clocks are registered as dividers and set rate callback function
is used for dynamic reconfiguration.
Based on the initial work from Chirag.
Signed-off-by: Chirag Parekh
Signed-off-by: Shubhrajyoti Datta
---
v6:
Remove the typecast.
use min for capping frequency.
use polled timeout
drivers/clk/clk-xlnx-clock-wizard.c | 185 ++--
1 file changed, 179 insertions(+), 6 deletions(-)
diff --git a/drivers/clk/clk-xlnx-clock-wizard.c
b/drivers/clk/clk-xlnx-clock-wizard.c
index d6577c8..8dfcec8 100644
--- a/drivers/clk/clk-xlnx-clock-wizard.c
+++ b/drivers/clk/clk-xlnx-clock-wizard.c
@@ -17,6 +17,7 @@
#include
#include
#include
+#include
#define WZRD_NUM_OUTPUTS 7
#define WZRD_ACLK_MAX_FREQ 25000UL
@@ -31,8 +32,23 @@
#define WZRD_DIVCLK_DIVIDE_SHIFT 0
#define WZRD_DIVCLK_DIVIDE_MASK(0xff <<
WZRD_DIVCLK_DIVIDE_SHIFT)
#define WZRD_CLKOUT_DIVIDE_SHIFT 0
+#define WZRD_CLKOUT_DIVIDE_WIDTH 8
#define WZRD_CLKOUT_DIVIDE_MASK(0xff <<
WZRD_DIVCLK_DIVIDE_SHIFT)
+#define WZRD_DR_MAX_INT_DIV_VALUE 255
+#define WZRD_DR_NUM_RETRIES1
+#define WZRD_DR_STATUS_REG_OFFSET 0x04
+#define WZRD_DR_LOCK_BIT_MASK 0x0001
+#define WZRD_DR_INIT_REG_OFFSET0x25C
+#define WZRD_DR_DIV_TO_PHASE_OFFSET4
+#define WZRD_DR_BEGIN_DYNA_RECONF 0x03
+
+/* Get the mask from width */
+#define div_mask(width)((1 << (width)) - 1)
+
+/* Extract divider instance from clock hardware instance */
+#define to_clk_wzrd_divider(_hw) container_of(_hw, struct clk_wzrd_divider, hw)
+
enum clk_wzrd_int_clks {
wzrd_clk_mul,
wzrd_clk_mul_div,
@@ -64,6 +80,29 @@ struct clk_wzrd {
bool suspended;
};
+/**
+ * struct clk_wzrd_divider - clock divider specific to clk_wzrd
+ *
+ * @hw:handle between common and hardware-specific interfaces
+ * @base: base address of register containing the divider
+ * @offset:offset address of register containing the divider
+ * @shift: shift to the divider bit field
+ * @width: width of the divider bit field
+ * @flags: clk_wzrd divider flags
+ * @table: array of value/divider pairs, last entry should have div = 0
+ * @lock: register lock
+ */
+struct clk_wzrd_divider {
+ struct clk_hw hw;
+ void __iomem *base;
+ u16 offset;
+ u8 shift;
+ u8 width;
+ u8 flags;
+ const struct clk_div_table *table;
+ spinlock_t *lock; /* divider lock */
+};
+
#define to_clk_wzrd(_nb) container_of(_nb, struct clk_wzrd, nb)
/* maximum frequencies for input/output clocks per speed grade */
@@ -73,6 +112,136 @@ static const unsigned long clk_wzrd_max_freq[] = {
106600UL
};
+/* spin lock variable for clk_wzrd */
+static DEFINE_SPINLOCK(clkwzrd_lock);
+
+static unsigned long clk_wzrd_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw);
+ void __iomem *div_addr = divider->base + divider->offset;
+ unsigned int val;
+
+ val = readl(div_addr) >> divider->shift;
+ val &= div_mask(divider->width);
+
+ return divider_recalc_rate(hw, parent_rate, val, divider->table,
+ divider->flags, divider->width);
+}
+
+static int clk_wzrd_dynamic_reconfig(struct clk_hw *hw, unsigned long rate,
+unsigned long parent_rate)
+{
+ int err = 0;
+ u32 value;
+ struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw);
+ void __iomem *div_addr = divider->base + divider->offset;
+
+ value = DIV_ROUND_CLOSEST(parent_rate, rate);
+
+ /* Cap the value to max */
+ min(value, (u32)WZRD_DR_MAX_INT_DIV_VALUE);
+
+ /* Set divisor and clear phase offset */
+ writel(value, div_addr);
+ writel(0x00, div_addr + WZRD_DR_DIV_TO_PHASE_OFFSET);
+
+ /* Check status register */
+ err = readl_poll_timeout(divider->base + WZRD_DR_STATUS_REG_OFFSET,
value,
+ value & WZRD_DR_LOCK_BIT_MASK,
+ WZRD_USEC_POLL, WZRD_TIMEOUT_POLL);
+ if (err)
+ return err;
+
+ /* Initiate reconfiguration */
+ writel(WZRD_DR_BEGIN_DYNA_RECONF,
+ divider->base + WZRD_DR_INIT_REG_OFFSET);
+
+ /* Check status register */
+ err = readl_poll_timeout(divider->base + WZRD_DR_STATUS_REG_OFFSET,
value,
+ value & WZRD_DR_LOCK_BIT_MASK,
+ WZRD_USEC_POLL, WZRD_TIMEOUT_POLL);
+
+ return err;
+}
+
+static long clk_wzrd_round_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long *prate)
+{
+ u8 div;
+
+ /*
+* since we don't
[PATCH v6 7/8] clk: clock-wizard: Update the fixed factor divisors
Update the fixed factor clock registration to register the divisors.
Signed-off-by: Shubhrajyoti Datta
---
drivers/clk/clk-xlnx-clock-wizard.c | 13 -
1 file changed, 8 insertions(+), 5 deletions(-)
diff --git a/drivers/clk/clk-xlnx-clock-wizard.c
b/drivers/clk/clk-xlnx-clock-wizard.c
index ded4cdd..fd69eb0 100644
--- a/drivers/clk/clk-xlnx-clock-wizard.c
+++ b/drivers/clk/clk-xlnx-clock-wizard.c
@@ -440,9 +440,11 @@ static int clk_wzrd_probe(struct platform_device *pdev)
u32 reg, reg_f, mult;
unsigned long rate;
const char *clk_name;
+ void __iomem *ctrl_reg;
struct clk_wzrd *clk_wzrd;
struct resource *mem;
int outputs;
+ unsigned long flags = 0;
struct device_node *np = pdev->dev.of_node;
clk_wzrd = devm_kzalloc(&pdev->dev, sizeof(*clk_wzrd), GFP_KERNEL);
@@ -514,16 +516,17 @@ static int clk_wzrd_probe(struct platform_device *pdev)
}
outputs = of_property_count_strings(np, "clock-output-names");
- /* register div */
- reg = (readl(clk_wzrd->base + WZRD_CLK_CFG_REG(0)) &
- WZRD_DIVCLK_DIVIDE_MASK) >> WZRD_DIVCLK_DIVIDE_SHIFT;
+ if (outputs == 1)
+ flags = CLK_SET_RATE_PARENT;
clk_name = kasprintf(GFP_KERNEL, "%s_mul_div", dev_name(&pdev->dev));
if (!clk_name) {
ret = -ENOMEM;
goto err_rm_int_clk;
}
- clk_wzrd->clks_internal[wzrd_clk_mul_div] = clk_register_fixed_factor
+ ctrl_reg = clk_wzrd->base + WZRD_CLK_CFG_REG(0);
+ /* register div */
+ clk_wzrd->clks_internal[wzrd_clk_mul_div] = clk_register_divider
(&pdev->dev, clk_name,
__clk_get_name(clk_wzrd->clks_internal[wzrd_clk_mul]),
flags, ctrl_reg, 0, 8, CLK_DIVIDER_ONE_BASED |
@@ -548,7 +551,7 @@ static int clk_wzrd_probe(struct platform_device *pdev)
if (!i)
clk_wzrd->clkout[i] = clk_wzrd_register_divf
(&pdev->dev, clkout_name,
- clk_name, 0,
+ clk_name, flags,
clk_wzrd->base, (WZRD_CLK_CFG_REG(2) + i * 12),
WZRD_CLKOUT_DIVIDE_SHIFT,
WZRD_CLKOUT_DIVIDE_WIDTH,
--
2.1.1
___
devel mailing list
de...@linuxdriverproject.org
http://driverdev.linuxdriverproject.org/mailman/listinfo/driverdev-devel
Re: [PATCH v2 28/47] staging: vchi: Get rid of vchiq_shim's message callback
Hi Nicolas, I'm working on a v2 of the bcm2835-isp support which was sent along with UNICAM v4l2 driver and some misc changes you have collected in this series. Reference to v1: https://lore.kernel.org/linux-media/20200504092611.9798-1-laurent.pinch...@ideasonboard.com/ On Mon, Jun 29, 2020 at 05:09:26PM +0200, Nicolas Saenz Julienne wrote: > As vchiq_shim's callback does nothing aside from pushing messages into > the service's queue, let's bypass it and jump directly to the service's > callbacks, letting them choose whether to use the message queue. I admit this patch caused me some pain, as after a few days chasing why the ISP got stuck in importing buffers into the VPU through the vc-sm-cma driver I realized that this patch removed a significant part of the process.. > > It turns out most services don't need to use the message queue, which > makes for simpler code in the end. > > - > - if (reason == VCHIQ_MESSAGE_AVAILABLE) > - vchiq_msg_queue_push(service->handle, header); This one '-.- I wonder if this was intentional and it is expected all services now handle the message queue (it seems so according to your commit message). Fair enough, I could add in the vc-sma-cma callback a call to vchiq_msg_queue_push() but I wonder if it wouldn't be better to do so in vchiq_core.c:parse_rx_slots(), just before calling the service's callback, so that this has not to be re-implemented in all services. What would you suggest ? And by the way I see mmal-vchiq.c:service_callback() releasing messages but never pushing them to the queue. Is this intended as well ? Thanks j ___ devel mailing list de...@linuxdriverproject.org http://driverdev.linuxdriverproject.org/mailman/listinfo/driverdev-devel
Re: [PATCH] staging: ion: remove from the tree
On Fri, Aug 28, 2020 at 1:05 AM Greg Kroah-Hartman wrote: > > On Thu, Aug 27, 2020 at 11:54:12AM -0700, John Stultz wrote: > > On Thu, Aug 27, 2020 at 10:17 AM Greg Kroah-Hartman > > wrote: > > > On Thu, Aug 27, 2020 at 10:31:41PM +0530, Amit Pundir wrote: > > > > I don't know what is the right thing to do here. I just want to > > > > highlight that AOSP's audio (codec2) HAL depends on the ION system > > > > heap and it will break AOSP for people who boot mainline on their > > > > devices, even for just testing purpose like we do in Linaro. Right now > > > > we need only 1 (Android specific out-of-tree) patch to boot AOSP with > > > > mainline and Sumit is already trying to upstream that vma naming > > > > patch. Removal of in-kernel ION, will just add more to that delta. > > > > > > As AOSP will continue to rely on ION after December of this year, all > > > you are doing is postponing the inevitable a few more months. > > > > > > Push back on the Android team to fix up the code to not use ION, they > > > know this needs to happen. > > > > The point though, is your main premise that no one is using this isn't true. > > They are using the version of ion in the Android kernel tree, yes, as it > has new features that many people are relying on. > > The version that is currently in the kernel tree is crippled, and maybe > works for some use cases, but not the majority, right? So my understanding is the Android Common Kernel tree version was mostly reworked to allow heaps as modules, and allowed heaps to have their own exporter logic (not unlike how dmabuf heaps do it). The main allocation interface is maybe slightly tweaked for out-of-tree vendor heaps, but doesn't affect the in-staging heaps. There's also a few optimizations we have skipped taking upstream. So yes, there are differences, but I don't feel your characterization is quite accurate. > > I'm actively working with Hridya and folks on the codec2 HAL side to > > transition this on the userland side: > > > > https://android-review.googlesource.com/c/platform/frameworks/av/+/1368918/3 > > > > I'd like AOSP to not use ION after September (though being external I > > can't promise anything), much less continuing after December. > > The android team has said they will be dropping ION use for the "next" > Android release, which is sometime next year from what I recall. > December is probably not going to happen :) AOSP is what the next Android release forks off of, so it needs to be fixed first. > > I want this migration to happen as much as anyone. But I'd prefer to > > keep ION in staging until after the LTS is announced. Having both > > around helps development for the transition, which helps us have a > > reliable solution, which helps vendors to migrate and be able to do > > comparative performance testing. > > I don't understand what having this in the "next" kernel helps us with > here. And I would really really prefer to NOT have an outdated version > of this code in a kernel tree that I am going to have to support for the > next X number of years, when no one is using that version of the driver. > > What is this LTS fixation to keep this code around for? Who does it > help? Vendors usually target LTS releases for their hardware bringups. Having a LTS release with both ION and DMA BUF Heaps helps them validate their old ION solution as performant, and then migrate to DMA BUF Heaps and be able to do performance comparisons holding all other things equal. > > I do appreciate that keeping it isn't free, but I also don't feel the > > chaos-monkey approach here is really motivational in the way you > > intend. > > I don't see it helping anyone to leave this around, except to cause > merge issues for me, and development issues for other developers. > > Anyone who really wants this code, can easily revert the deletion and > move on and grab the AOSP copy of the code. That's what they did when > we deleted other Android features that are still relied on. > > Given that the "isn't free" is causing _me_ real pain, and not the > actual users of this code, I am leaning toward wanting to move that > pain/cost to those users, for obvious reasons. Sure. Again, I do understand the desire to remove it, and it's your right to do so. Keeping the code for an extra year in LTS (over 5.4) is a cost, so I understand if you drop it. But I'll ask that you make that judgement clear as the main motivator/rationale of the commit message, rather than flippantly pretending it's not being used, and that everyone agrees it has no usefulness to keep around (especially after we've had this conversation a few times already this year). thanks -john ___ devel mailing list de...@linuxdriverproject.org http://driverdev.linuxdriverproject.org/mailman/listinfo/driverdev-devel
Re: [PATCH v6 1/8] dt-bindings: add documentation of xilinx clocking wizard
On Fri, Aug 28, 2020 at 07:09:49PM +0530, Shubhrajyoti Datta wrote:
> Add the devicetree binding for the xilinx clocking wizard.
>
> Signed-off-by: Shubhrajyoti Datta
> ---
> v6:
> Fix a yaml warning
>
> .../bindings/clock/xlnx,clocking-wizard.yaml | 71
> ++
> 1 file changed, 71 insertions(+)
> create mode 100644
> Documentation/devicetree/bindings/clock/xlnx,clocking-wizard.yaml
>
> diff --git
> a/Documentation/devicetree/bindings/clock/xlnx,clocking-wizard.yaml
> b/Documentation/devicetree/bindings/clock/xlnx,clocking-wizard.yaml
> new file mode 100644
> index 000..ca63593
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/xlnx,clocking-wizard.yaml
> @@ -0,0 +1,71 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/clock/xlnx,clocking-wizard.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Xilinx clocking wizard
> +
> +maintainers:
> + - Shubhrajyoti Datta
> +
> +description: |
> + The clocking wizard is a soft ip clocking block of Xilinx versal. It
> + reads required input clock frequencies from the devicetree and acts as
> clock
> + clock output.
> +
> +select: false
> +
> +properties:
> + compatible:
> +items:
> + - enum:
You can drop 'items' since there is only 1.
> + - xlnx,clocking-wizard
> + - xlnx,clocking-wizard-6.0
> +
> + "#clock-cells":
> +const: 1
> +
> + clocks:
> +description: List of clock specifiers which are external input
> + clocks to the given clock controller.
Drop this. That's every 'clocks' property.
> +items:
> + - description: clock input
> + - description: axi clock
> +
> + clock-names:
> +items:
> + - const: clk_in1
> + - const: s_axi_aclk
> +
> + speed-grade:
Needs a vendor prefix.
> +allOf:
You can remove the 'allOf'.
> + - $ref: /schemas/types.yaml#/definitions/uint32
> + - enum: [1, 2, 3]
> +description:
> + Speed grade of the device.
> +maxItems: 1
Drop this. A 'uint32' is always 1 item.
> +
> +required:
> + - compatible
> + - "#clock-cells"
> + - clocks
> + - clock-names
> + - speed-grade
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> +clock-generator@4004 {
> +#clock-cells = <1>;
> +reg = <0x4004 0x1000>;
> +compatible = "xlnx,clk-wizard-1.0";
Doesn't match the schema.
> +speed-grade = <1>;
> +clock-names = "clk_in1", "s_axi_aclk";
> +clocks = <&clkc 15>, <&clkc 15>;
> +clock-output-names = "clk_out1", "clk_out2",
> +"clk_out3", "clk_out4", "clk_out5",
> +"clk_out6", "clk_out7";
> +};
> +...
> --
> 2.1.1
>
___
devel mailing list
de...@linuxdriverproject.org
http://driverdev.linuxdriverproject.org/mailman/listinfo/driverdev-devel
The Project
Hello,
My name is Ms. Reem Ebrahim Al-Hashimi, I am the "Minister of state and
Petroleum" also "Minister of
State for International Cooperation" in UAE. I write to you on behalf of my
other "three (3)
colleagues" who has approved me to solicit for your "partnership in claiming of
{us$47=Million}"
from a Financial Home in Cambodia on their behalf and for our "Mutual Benefits".
The Fund {us$47=Million} is our share from the (Over-invoiced) Oil/Gas deal
with Cambodian/Vietnam
Government within 2013/2014, however, We don't want our government to know
about the fund. If this
proposal interests you, let me know, by sending me an email and I will send to
you detailed
information on how this business would be successfully transacted. Be informed
that nobody knows
about the secret of this fund except us, and we know how to carry out the
entire transaction. So I
am compelled to ask, that you will stand on our behalf and receive this fund
into any account that
is solely controlled by you.
We will compensate you with 30% of the total amount involved as gratification
for being our partner
in this transaction. Reply to my private email as stated:
honreemebrahimal-hash...@yandex.com
Regards,
Ms. Reem Ebrahim Al-Hashimi.
___
devel mailing list
de...@linuxdriverproject.org
http://driverdev.linuxdriverproject.org/mailman/listinfo/driverdev-devel
[staging:staging-testing] BUILD SUCCESS cc34073c6248e9cec801bf690d1455f264d12357
tree/branch: https://git.kernel.org/pub/scm/linux/kernel/git/gregkh/staging.git staging-testing branch HEAD: cc34073c6248e9cec801bf690d1455f264d12357 staging: emxx_udc: Fix passing of NULL to dma_alloc_coherent() elapsed time: 723m configs tested: 87 configs skipped: 8 The following configs have been built successfully. More configs may be tested in the coming days. arm defconfig arm64allyesconfig arm64 defconfig arm allyesconfig arm allmodconfig x86_64 allyesconfig m68k m5208evb_defconfig m68kmvme147_defconfig openriscor1ksim_defconfig sh se7722_defconfig pariscgeneric-64bit_defconfig mips rs90_defconfig m68k bvme6000_defconfig powerpc mpc866_ads_defconfig powerpc pq2fads_defconfig m68k apollo_defconfig m68k allyesconfig armqcom_defconfig mips maltasmvp_eva_defconfig nios2allyesconfig nios2alldefconfig microblazenommu_defconfig mipsmalta_kvm_guest_defconfig mips cavium_octeon_defconfig arc nps_defconfig arm spear13xx_defconfig arcnsim_700_defconfig mips rb532_defconfig sh lboxre2_defconfig ia64 allmodconfig ia64defconfig ia64 allyesconfig m68k allmodconfig m68kdefconfig nios2 defconfig arc allyesconfig nds32 allnoconfig c6x allyesconfig nds32 defconfig cskydefconfig alpha defconfig alphaallyesconfig xtensa allyesconfig h8300allyesconfig arc defconfig sh allmodconfig parisc defconfig s390 allyesconfig parisc allyesconfig s390defconfig i386 allyesconfig sparcallyesconfig sparc defconfig i386defconfig mips allyesconfig mips allmodconfig powerpc defconfig powerpc allyesconfig powerpc allmodconfig powerpc allnoconfig i386 randconfig-a002-20200828 i386 randconfig-a005-20200828 i386 randconfig-a003-20200828 i386 randconfig-a004-20200828 i386 randconfig-a001-20200828 i386 randconfig-a006-20200828 x86_64 randconfig-a015-20200828 x86_64 randconfig-a012-20200828 x86_64 randconfig-a016-20200828 x86_64 randconfig-a014-20200828 x86_64 randconfig-a011-20200828 x86_64 randconfig-a013-20200828 i386 randconfig-a013-20200828 i386 randconfig-a012-20200828 i386 randconfig-a011-20200828 i386 randconfig-a016-20200828 i386 randconfig-a014-20200828 i386 randconfig-a015-20200828 riscvallyesconfig riscv allnoconfig riscv defconfig riscvallmodconfig x86_64 rhel x86_64rhel-7.6-kselftests x86_64 defconfig x86_64 rhel-8.3 x86_64 kexec --- 0-DAY CI Kernel Test Service, Intel Corporation https://lists.01.org/hyperkitty/list/kbuild-...@lists.01.org ___ devel mailing list de...@linuxdriverproject.org http://driverdev.linuxdriverproject.org/mailman/listinfo/driverdev-devel
[driver-core:driver-core-linus] BUILD SUCCESS 40b8b826a6998639dd1c26f0e127f18371e1058d
tree/branch: https://git.kernel.org/pub/scm/linux/kernel/git/gregkh/driver-core.git driver-core-linus branch HEAD: 40b8b826a6998639dd1c26f0e127f18371e1058d kobject: Restore old behaviour of kobject_del(NULL) elapsed time: 723m configs tested: 85 configs skipped: 6 The following configs have been built successfully. More configs may be tested in the coming days. arm defconfig arm64allyesconfig arm64 defconfig arm allyesconfig arm allmodconfig arm cm_x300_defconfig arcnsim_700_defconfig armmmp2_defconfig armcerfcube_defconfig mipsvocore2_defconfig sh rts7751r2dplus_defconfig powerpc allnoconfig arm axm55xx_defconfig sh alldefconfig mips fuloong2e_defconfig arc nsimosci_hs_smp_defconfig arm cns3420vb_defconfig s390 debug_defconfig alphaalldefconfig m68k m5208evb_defconfig arm sama5_defconfig nds32alldefconfig arm corgi_defconfig m68k m5275evb_defconfig armmvebu_v7_defconfig ia64 allmodconfig ia64defconfig ia64 allyesconfig m68k allmodconfig m68kdefconfig m68k allyesconfig nds32 defconfig nios2allyesconfig cskydefconfig alpha defconfig alphaallyesconfig xtensa allyesconfig h8300allyesconfig arc defconfig sh allmodconfig nios2 defconfig arc allyesconfig nds32 allnoconfig c6x allyesconfig parisc defconfig s390 allyesconfig parisc allyesconfig s390defconfig i386 allyesconfig sparcallyesconfig sparc defconfig i386defconfig mips allyesconfig mips allmodconfig powerpc allyesconfig powerpc allmodconfig powerpc defconfig i386 randconfig-a002-20200828 i386 randconfig-a005-20200828 i386 randconfig-a003-20200828 i386 randconfig-a004-20200828 i386 randconfig-a001-20200828 i386 randconfig-a006-20200828 x86_64 randconfig-a015-20200828 x86_64 randconfig-a012-20200828 x86_64 randconfig-a016-20200828 x86_64 randconfig-a014-20200828 x86_64 randconfig-a011-20200828 x86_64 randconfig-a013-20200828 i386 randconfig-a013-20200828 i386 randconfig-a012-20200828 i386 randconfig-a011-20200828 i386 randconfig-a016-20200828 i386 randconfig-a014-20200828 i386 randconfig-a015-20200828 riscvallyesconfig riscv allnoconfig riscv defconfig riscvallmodconfig x86_64 rhel x86_64 allyesconfig x86_64rhel-7.6-kselftests x86_64 defconfig x86_64 rhel-8.3 x86_64 kexec --- 0-DAY CI Kernel Test Service, Intel Corporation https://lists.01.org/hyperkitty/list/kbuild-...@lists.01.org ___ devel mailing list de...@linuxdriverproject.org http://driverdev.linuxdriverproject.org/mailman/listinfo/driverdev-devel
[PATCH] Staging: rtl8723bs: os_dep: fixed some coding style issues
Fixed some coding style issues.
Signed-off-by: Ross Schmidt
---
drivers/staging/rtl8723bs/os_dep/sdio_intf.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/staging/rtl8723bs/os_dep/sdio_intf.c
b/drivers/staging/rtl8723bs/os_dep/sdio_intf.c
index f1e2829a19a7..2b2f4505b98b 100644
--- a/drivers/staging/rtl8723bs/os_dep/sdio_intf.c
+++ b/drivers/staging/rtl8723bs/os_dep/sdio_intf.c
@@ -121,6 +121,7 @@ extern unsigned int oob_irq;
static irqreturn_t gpio_hostwakeup_irq_thread(int irq, void *data)
{
struct adapter *padapter = data;
+
DBG_871X_LEVEL(_drv_always_, "gpio_hostwakeup_irq_thread\n");
/* Disable interrupt before calling handler */
/* disable_irq_nosync(oob_irq); */
@@ -131,6 +132,7 @@ static irqreturn_t gpio_hostwakeup_irq_thread(int irq, void
*data)
static u8 gpio_hostwakeup_alloc_irq(struct adapter *padapter)
{
int err;
+
if (oob_irq == 0) {
DBG_871X("oob_irq ZERO!\n");
return _FAIL;
--
2.26.2
___
devel mailing list
de...@linuxdriverproject.org
http://driverdev.linuxdriverproject.org/mailman/listinfo/driverdev-devel
