[edk2] [Patch] Makefile: Enable arch X64 build

[Jiaxin Wu]

This patch is used to support arch X64 build. The
ARCH can be either IA32 or X64. Adapt these two
directives to your need.

Cc: Fu Siyuan 
Cc: Zhang Lubo 
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jiaxin Wu 
---
 Makefile | 25 ++---
 1 file changed, 18 insertions(+), 7 deletions(-)

diff --git a/Makefile b/Makefile
index ea567ba..85a68ec 100644
--- a/Makefile
+++ b/Makefile
@@ -1,8 +1,8 @@
 #/*++
 #
-# Copyright (c) 2006, Intel Corporation
 
+# Copyright (c) 2006 - 2016, Intel Corporation 

 # All rights reserved. This program and the accompanying materials 
 
 # are licensed and made available under the terms and conditions of the BSD 
License 
 # which accompanies this distribution.  The full text of the license may be 
found at
 # http://opensource.org/licenses/bsd-license.php   
 
 #  

@@ -20,36 +20,47 @@
 
 
 #
 #WINPCAP_DIR is the directory that contains the WinPcap developer's package
 #The TARGET can be either DEBUG or RELEASE. Adapt these two directives to your 
need
+#The ARCH can be either IA32 or X64. Adapt these two directives to your need
 #
 WINPCAP_DIR = ".\WpdPack"
 TARGET  = DEBUG
+ARCH= IA32
+
+#
+#WINPCAP_LIBPATH is the directory that contains the WinPcap developer's library
+#
+!IF "$(ARCH)" == "IA32"
+WINPCAP_LIB = ".\WpdPack\Lib"
+!ELSE
+WINPCAP_LIB = ".\WpdPack\Lib\x64"
+!ENDIF
 
 #
 #Change the output directory and compile parameters according to the TARGET.
 #
 !IF "$(TARGET)" == "DEBUG"
-OUTPUT_DIR  = Debug
+OUTPUT_DIR  = Debug_$(ARCH)
 C_DEFINES   = /D "WIN32" /D "SNPNT32IO_EXPORTS"
-C_FLAGS = /Od /FD /MTd /Fo"Debug/" /Fd"Debug/vc70" /W3 /c /Wp64 /ZI /TC 
-LINK_FLAGS  = /DLL /DEBUG /PDB:"Debug/SnpNt32Io.pdb"
+C_FLAGS = /Od /FD /MTd /Fo"$(OUTPUT_DIR)/" /Fd"$(OUTPUT_DIR)/vc70" /W3 /c 
/Wp64 /ZI /TC 
+LINK_FLAGS  = /DLL /DEBUG /PDB:"$(OUTPUT_DIR)/SnpNt32Io.pdb"
 !ELSE
-OUTPUT_DIR  = Release
+OUTPUT_DIR  = Release_$(ARCH)
 C_DEFINES   = /D "WIN32" /D "NDEBUG" /D "SNPNT32IO_EXPORTS" 
-C_FLAGS = /O2 /FD /MT /GS /Fo"Release/" /Fd"Release/vc70" /W3 /c /Wp64 /Zi 
/TC 
+C_FLAGS = /O2 /FD /MT /GS /Fo"$(OUTPUT_DIR)/" /Fd"$(OUTPUT_DIR)/vc70" /W3 
/c /Wp64 /Zi /TC 
 LINK_FLAGS  = /DLL
 !ENDIF
 
 
 #
 #Main section to build the SnpNt32Io.DLL. The "-" before command prevents the
 #nmake to exit when the command returns an error 
 #
 SnpNt32Io.DLL : SnpNt32Io.obj
- link $(LINK_FLAGS) /IMPLIB:"$(OUTPUT_DIR)/SnpNt32Io.lib" 
/LIBPATH:$(WINPCAP_DIR)\Lib\
+ link $(LINK_FLAGS) /IMPLIB:"$(OUTPUT_DIR)/SnpNt32Io.lib" 
/LIBPATH:$(WINPCAP_LIB)\
  /OUT:"$(OUTPUT_DIR)/SnpNt32Io.dll" wpcap.lib packet.lib 
$(OUTPUT_DIR)/SnpNt32Io.obj
   
 SnpNt32Io.obj : src\SnpNt32Io.c
  - md $(OUTPUT_DIR)
  cl   /I $(WINPCAP_DIR)\Include $(C_DEFINES) $(C_FLAGS) src\SnpNt32Io.c
-- 
1.9.5.msysgit.1

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[edk2] [PATCH v2] SecurityPkg: Fix TPM 1.2 SelfTest command bug.

[Derek Lin]

Specify command response length.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Derek Lin 

---
Changes in v2:
  Fix patch message.
---
 SecurityPkg/Library/Tpm12CommandLib/Tpm12SelfTest.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/SecurityPkg/Library/Tpm12CommandLib/Tpm12SelfTest.c 
b/SecurityPkg/Library/Tpm12CommandLib/Tpm12SelfTest.c
index cd08d19..8e232ee 100644
--- a/SecurityPkg/Library/Tpm12CommandLib/Tpm12SelfTest.c
+++ b/SecurityPkg/Library/Tpm12CommandLib/Tpm12SelfTest.c
@@ -2,6 +2,7 @@
   Implement TPM1.2 NV Self Test related commands.
 
 Copyright (c) 2016, Intel Corporation. All rights reserved. 
+(C) Copyright 2016 Hewlett Packard Enterprise Development LP
 This program and the accompanying materials
 are licensed and made available under the terms and conditions of the BSD 
License
 which accompanies this distribution.  The full text of the license may be 
found at
@@ -42,5 +43,6 @@ Tpm12ContinueSelfTest (
   Command.tag   = SwapBytes16 (TPM_TAG_RQU_COMMAND);
   Command.paramSize = SwapBytes32 (sizeof (Command));
   Command.ordinal   = SwapBytes32 (TPM_ORD_ContinueSelfTest);
+  Length = sizeof (Response);
   return Tpm12SubmitCommand (sizeof (Command), (UINT8 *)&Command, &Length, 
(UINT8 *)&Response);
 }
-- 
2.6.0.windows.1

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Re: [edk2] Update UDK2014 to UDK2015 leads to setup page slow

[wang xiaofeng]

HI Liming,
 Sorry, Set gEfiMdePkgTokenSpaceGuid.PcdMaximumLinkedListLength to 0 with 
PcdsFixedAtBuild can also solve this issue, previous test result is wrong.








At 2016-03-09 15:21:37, "wang xiaofeng"  wrote:
>Hi Liming,
>Thanks for your helpful information! Set 
> gEfiMdePkgTokenSpaceGuid.PcdMaximumLinkedListLength to 0 cannot solve this 
> issue, but I tried to use release mode and the issue disappears. This issue 
> only occurs in debug mode.
>My plan is waiting your fix for the issue you found. Most probably the two 
>issues have the same root cause, or your fix can help us solve part of the 
>problem .
>
>
>
>
>
>
>
>
>At 2016-03-09 11:21:42, "Gao, Liming"  wrote:
>>Xiaofeng:
>>  We find the similar issue in DEBUG tip when DEBUG log is enabled. 
>> AllocatePool() service will be slower than before. The updated memory 
>> allocation algorithm brings the long free pool list and cause AllocatePool() 
>> service slow. I am still investigating it. The temp solution is to disable 
>> link list check by set gEfiMdePkgTokenSpaceGuid.PcdMaximumLinkedListLength 
>> to 0 in platform DSC file. Could you see whether this way works or not? If 
>> it works, your issue should be same to ours. If not, your issue may be 
>> different. 
>>
>>Thanks
>>Liming
>>> -Original Message-
>>> From: edk2-devel [mailto:edk2-devel-boun...@lists.01.org] On Behalf Of
>>> wang xiaofeng
>>> Sent: Wednesday, March 09, 2016 10:36 AM
>>> To: Dong, Eric; edk2-devel@lists.01.org
>>> Subject: [edk2] Update UDK2014 to UDK2015 leads to setup page slow
>>> 
>>> Hi Edk2 developers,
>>>After upate to UDK2015 from UDk2014, the Uiapp setup shows very slow.
>>> the following is our issue and debug information. Anyone meet similar issue
>>> before?
>>> 
>>> 
>>> Issue symptom:
>>> 
>>> 1, System draw the Front Page cost about 2 second. We can see the frame/
>>> menu block/ help block draw one by one. Other submenu has same slowly
>>> display when enter it.
>>> 
>>> Normally those are instantaneous  work .
>>> 
>>> 2, Change the highlight item in one page meet about half-second delay
>>> response.
>>> 
>>> 3, In Data and time page. We can see the scan line to update the time 
>>> display
>>> from top-left to bottom-right.
>>> 
>>> 4, In shell environment, "drivers" command can show title part normally, but
>>> it display the number of driver with a visible slow speed. "PCI" command 
>>> still
>>> has normal behave.
>>> 
>>> 
>>> 
>>> 
>>> Debug step:
>>> 
>>> 1, Doubt that call back function hook to the form will case this issue .Try 
>>> to
>>> remove the callback function for all the form.
>>> 
>>> Issue still happened.
>>> 
>>> 2. Because the setup has may loop invoke, Try to fixed a single delay point 
>>> for
>>> more debug.
>>> 
>>> In "DisplayPageFrame" when try to clear the screen for First Form display ,
>>> there is about 1-2 second single delay point inside
>>> 
>>> ClearLines (0, gScreenDimensions.RightColumn, 0,
>>> gScreenDimensions.BottomRow, KEYHELP_BACKGROUND);
>>> 
>>> Trace the string passed to clear screen in this routing .The string is same 
>>> with
>>> the UDK2014 normal case. This can preliminary exclusion the string analysis
>>> issue and special font issue.
>>> 
>>> 3,  Deep debug, Delay is happened in "PrintInternal" try to invoke "Out-
>>> >OutputString(XX)".
>>> 
>>> This Out is point to system table  conout , There is only one
>>> SimpleTextOutput  "GraphicsConsoleController" in consplitter list in our
>>> project.
>>> 
>>>  And the GOP protocol install  optrom in both UDK2014 and UDK2015 are
>>> the same one. BTW, The logo display and post information display has no
>>> delay symptom.
>>> 
>>> 4, There is  three "Out->OutputString(XX)" invoke "PrintInternal", 
>>> String
>>> is display by first two after remove the CHAR type. the last invoke is used 
>>> for
>>> display space to meet the request display size.
>>> 
>>> If we don't do this work. Symptom 2 Will have a great improvement.
>>> ___
>>> edk2-devel mailing list
>>> edk2-devel@lists.01.org
>>> https://lists.01.org/mailman/listinfo/edk2-devel
>>___
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Re: [edk2] Update UDK2014 to UDK2015 leads to setup page slow

[wang xiaofeng]

Hi Liming,
Thanks for your helpful information! Set 
gEfiMdePkgTokenSpaceGuid.PcdMaximumLinkedListLength to 0 cannot solve this 
issue, but I tried to use release mode and the issue disappears. This issue 
only occurs in debug mode.
My plan is waiting your fix for the issue you found. Most probably the two 
issues have the same root cause, or your fix can help us solve part of the 
problem .








At 2016-03-09 11:21:42, "Gao, Liming"  wrote:
>Xiaofeng:
>  We find the similar issue in DEBUG tip when DEBUG log is enabled. 
> AllocatePool() service will be slower than before. The updated memory 
> allocation algorithm brings the long free pool list and cause AllocatePool() 
> service slow. I am still investigating it. The temp solution is to disable 
> link list check by set gEfiMdePkgTokenSpaceGuid.PcdMaximumLinkedListLength to 
> 0 in platform DSC file. Could you see whether this way works or not? If it 
> works, your issue should be same to ours. If not, your issue may be 
> different. 
>
>Thanks
>Liming
>> -Original Message-
>> From: edk2-devel [mailto:edk2-devel-boun...@lists.01.org] On Behalf Of
>> wang xiaofeng
>> Sent: Wednesday, March 09, 2016 10:36 AM
>> To: Dong, Eric; edk2-devel@lists.01.org
>> Subject: [edk2] Update UDK2014 to UDK2015 leads to setup page slow
>> 
>> Hi Edk2 developers,
>>After upate to UDK2015 from UDk2014, the Uiapp setup shows very slow.
>> the following is our issue and debug information. Anyone meet similar issue
>> before?
>> 
>> 
>> Issue symptom:
>> 
>> 1, System draw the Front Page cost about 2 second. We can see the frame/
>> menu block/ help block draw one by one. Other submenu has same slowly
>> display when enter it.
>> 
>> Normally those are instantaneous  work .
>> 
>> 2, Change the highlight item in one page meet about half-second delay
>> response.
>> 
>> 3, In Data and time page. We can see the scan line to update the time display
>> from top-left to bottom-right.
>> 
>> 4, In shell environment, "drivers" command can show title part normally, but
>> it display the number of driver with a visible slow speed. "PCI" command 
>> still
>> has normal behave.
>> 
>> 
>> 
>> 
>> Debug step:
>> 
>> 1, Doubt that call back function hook to the form will case this issue .Try 
>> to
>> remove the callback function for all the form.
>> 
>> Issue still happened.
>> 
>> 2. Because the setup has may loop invoke, Try to fixed a single delay point 
>> for
>> more debug.
>> 
>> In "DisplayPageFrame" when try to clear the screen for First Form display ,
>> there is about 1-2 second single delay point inside
>> 
>> ClearLines (0, gScreenDimensions.RightColumn, 0,
>> gScreenDimensions.BottomRow, KEYHELP_BACKGROUND);
>> 
>> Trace the string passed to clear screen in this routing .The string is same 
>> with
>> the UDK2014 normal case. This can preliminary exclusion the string analysis
>> issue and special font issue.
>> 
>> 3,  Deep debug, Delay is happened in "PrintInternal" try to invoke "Out-
>> >OutputString(XX)".
>> 
>> This Out is point to system table  conout , There is only one
>> SimpleTextOutput  "GraphicsConsoleController" in consplitter list in our
>> project.
>> 
>>  And the GOP protocol install  optrom in both UDK2014 and UDK2015 are
>> the same one. BTW, The logo display and post information display has no
>> delay symptom.
>> 
>> 4, There is  three "Out->OutputString(XX)" invoke "PrintInternal", String
>> is display by first two after remove the CHAR type. the last invoke is used 
>> for
>> display space to meet the request display size.
>> 
>> If we don't do this work. Symptom 2 Will have a great improvement.
>> ___
>> edk2-devel mailing list
>> edk2-devel@lists.01.org
>> https://lists.01.org/mailman/listinfo/edk2-devel
>___
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[edk2] [PATCH] SecurityPkg: Fix TPM 1.2 SelfTest command bug. Specify command response length.

[Derek Lin]

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Derek Lin 
---
 SecurityPkg/Library/Tpm12CommandLib/Tpm12SelfTest.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/SecurityPkg/Library/Tpm12CommandLib/Tpm12SelfTest.c 
b/SecurityPkg/Library/Tpm12CommandLib/Tpm12SelfTest.c
index cd08d19..8e232ee 100644
--- a/SecurityPkg/Library/Tpm12CommandLib/Tpm12SelfTest.c
+++ b/SecurityPkg/Library/Tpm12CommandLib/Tpm12SelfTest.c
@@ -2,6 +2,7 @@
   Implement TPM1.2 NV Self Test related commands.
 
 Copyright (c) 2016, Intel Corporation. All rights reserved. 
+(C) Copyright 2016 Hewlett Packard Enterprise Development LP
 This program and the accompanying materials
 are licensed and made available under the terms and conditions of the BSD 
License
 which accompanies this distribution.  The full text of the license may be 
found at
@@ -42,5 +43,6 @@ Tpm12ContinueSelfTest (
   Command.tag   = SwapBytes16 (TPM_TAG_RQU_COMMAND);
   Command.paramSize = SwapBytes32 (sizeof (Command));
   Command.ordinal   = SwapBytes32 (TPM_ORD_ContinueSelfTest);
+  Length = sizeof (Response);
   return Tpm12SubmitCommand (sizeof (Command), (UINT8 *)&Command, &Length, 
(UINT8 *)&Response);
 }
-- 
2.6.0.windows.1

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[edk2] [patch] NetworkPkg: Refine the code of shell app under networkPkg.

[Zhang Lubo]

refine the code of ifconfig6 and ping6 application.

Cc: Fu Siyuan 
Cc: Wu Jiaxin 
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Zhang Lubo 
---
 NetworkPkg/Application/IfConfig6/IfConfig6.c | 5 +
 NetworkPkg/Application/IfConfig6/IfConfig6.h | 5 -
 NetworkPkg/Application/Ping6/Ping6.c | 5 +
 NetworkPkg/Application/Ping6/Ping6.h | 5 -
 4 files changed, 10 insertions(+), 10 deletions(-)

diff --git a/NetworkPkg/Application/IfConfig6/IfConfig6.c 
b/NetworkPkg/Application/IfConfig6/IfConfig6.c
index 8bd6243..48c3be3 100644
--- a/NetworkPkg/Application/IfConfig6/IfConfig6.c
+++ b/NetworkPkg/Application/IfConfig6/IfConfig6.c
@@ -26,10 +26,15 @@
 #include 
 #include 
 
 #include "IfConfig6.h"
 
+//
+// String token ID of ifconfig6 command help message text.
+//
+GLOBAL_REMOVE_IF_UNREFERENCED EFI_STRING_ID mStringIfconfig6HelpTokenId = 
STRING_TOKEN (STR_IFCONFIG6_HELP);
+
 EFI_HII_HANDLE  mHiiHandle;
 
 SHELL_PARAM_ITEMmIfConfig6CheckList[] = {
   {
 L"-b",
diff --git a/NetworkPkg/Application/IfConfig6/IfConfig6.h 
b/NetworkPkg/Application/IfConfig6/IfConfig6.h
index 53b6d72..f748971 100644
--- a/NetworkPkg/Application/IfConfig6/IfConfig6.h
+++ b/NetworkPkg/Application/IfConfig6/IfConfig6.h
@@ -14,15 +14,10 @@
 **/
 
 #ifndef _IFCONFIG6_H_
 #define _IFCONFIG6_H_
 
-//
-// String token ID of ifconfig6 command help message text.
-//
-GLOBAL_REMOVE_IF_UNREFERENCED EFI_STRING_ID mStringIfconfig6HelpTokenId = 
STRING_TOKEN (STR_IFCONFIG6_HELP);
-
 enum {
   IfConfig6OpList = 1,
   IfConfig6OpSet  = 2,
   IfConfig6OpClear= 3
 };
diff --git a/NetworkPkg/Application/Ping6/Ping6.c 
b/NetworkPkg/Application/Ping6/Ping6.c
index f1685f7..55314e5 100644
--- a/NetworkPkg/Application/Ping6/Ping6.c
+++ b/NetworkPkg/Application/Ping6/Ping6.c
@@ -28,10 +28,15 @@
 #include 
 #include 
 
 #include "Ping6.h"
 
+//
+// String token ID of Ping6 command help message text.
+//
+GLOBAL_REMOVE_IF_UNREFERENCED EFI_STRING_ID mStringPing6HelpToken = 
STRING_TOKEN (STR_PING6_HELP);
+
 SHELL_PARAM_ITEMPing6ParamList[] = {
   {
 L"-l",
 TypeValue
   },
diff --git a/NetworkPkg/Application/Ping6/Ping6.h 
b/NetworkPkg/Application/Ping6/Ping6.h
index 4660b0e..6f590af 100644
--- a/NetworkPkg/Application/Ping6/Ping6.h
+++ b/NetworkPkg/Application/Ping6/Ping6.h
@@ -20,15 +20,10 @@
 #define PING6_MAX_SEND_NUMBER  1
 #define PING6_MAX_BUFFER_SIZE  32768
 #define PING6_ONE_SECOND   1000
 
 //
-// String token ID of Ping6 command help message text.
-//
-GLOBAL_REMOVE_IF_UNREFERENCED EFI_STRING_ID mStringPing6HelpToken = 
STRING_TOKEN (STR_PING6_HELP);
-
-//
 // A similar amount of time that passes in femtoseconds
 // for each increment of TimerValue. It is for NT32 only.
 //
 #define NTTIMERPERIOD358049
 
-- 
1.9.5.msysgit.1

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Re: [edk2] [Patch] BaseTools: Change source files to DOS format.

[Zhu, Yonghong]

Reviewed-by: Yonghong Zhu 

Best Regards,
Zhu Yonghong


-Original Message-
From: edk2-devel [mailto:edk2-devel-boun...@lists.01.org] On Behalf Of Yonghong 
Zhu
Sent: Wednesday, March 09, 2016 10:16 AM
To: edk2-devel@lists.01.org
Cc: Gao, Liming 
Subject: [edk2] [Patch] BaseTools: Change source files to DOS format.

From: Liming Gao 

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Liming Gao 
---
 BaseTools/Source/C/BootSectImage/bootsectimage.c  | 14 +++---
 BaseTools/Source/C/EfiLdrImage/EfiLdrImage.c  | 18 +-
 BaseTools/Source/C/Split/Split.c  | 14 +++---
 BaseTools/Source/C/VfrCompile/VfrCompiler.cpp |  8 
 BaseTools/Source/C/VfrCompile/VfrCompiler.h   |  4 ++--
 BaseTools/Source/C/VolInfo/VolInfo.c  | 12 ++--
 BaseTools/Source/Python/BPDG/BPDG.py  |  6 +++---
 BaseTools/Source/Python/BPDG/StringTable.py   | 14 +++---
 BaseTools/Source/Python/Ecc/Ecc.py| 10 +-
 BaseTools/Source/Python/UPT/Logger/StringTable.py |  6 +++---
 BaseTools/Source/Python/UPT/UPT.py|  4 ++--
 11 files changed, 55 insertions(+), 55 deletions(-)

diff --git a/BaseTools/Source/C/BootSectImage/bootsectimage.c 
b/BaseTools/Source/C/BootSectImage/bootsectimage.c
index 453a463..4f876ae 100644
--- a/BaseTools/Source/C/BootSectImage/bootsectimage.c
+++ b/BaseTools/Source/C/BootSectImage/bootsectimage.c
@@ -4,7 +4,7 @@ Abstract:
   Patch the BPB information in boot sector image file.
   Patch the MBR code in MBR image file.
 
-Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.
+Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.
 This program and the accompanying materials  
 are licensed and made available under the terms and conditions of the BSD 
License 
 which accompanies this distribution.  The full text of the license may be 
found at
@@ -33,8 +33,8 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER 
EXPRESS OR IMPLIED.
 //
 // Utility version information
 //
-#define UTILITY_MAJOR_VERSION 1
-#define UTILITY_MINOR_VERSION 0
+#define UTILITY_MAJOR_VERSION 1
+#define UTILITY_MINOR_VERSION 0
 
 void
 Version (
@@ -56,7 +56,7 @@ Returns:
 
 --*/
 {
-  printf ("%s Version %d.%d Build %s\n", UTILITY_NAME, UTILITY_MAJOR_VERSION, 
UTILITY_MINOR_VERSION, __BUILD_VERSION);
+  printf ("%s Version %d.%d Build %s\n", UTILITY_NAME, 
+ UTILITY_MAJOR_VERSION, UTILITY_MINOR_VERSION, __BUILD_VERSION);
 }
 
 void
@@ -79,9 +79,9 @@ Returns:
 --*/
 {
   Version();
-  printf ("Copyright (c) 1999-2016 Intel Corporation. All rights reserved.\n");
-  printf ("\n  The BootSectImage tool prints information or patch destination 
file by source\n");
-  printf ("  file for BIOS Parameter Block (BPB) or Master Boot Record 
(MBR).\n");
+  printf ("Copyright (c) 1999-2016 Intel Corporation. All rights 
+ reserved.\n");  printf ("\n  The BootSectImage tool prints information 
+ or patch destination file by source\n");  printf ("  file for BIOS 
+ Parameter Block (BPB) or Master Boot Record (MBR).\n");
   printf ("\nUsage: \n\
BootSectImage\n\
  [-f, --force force patch even if the FAT type of SrcImage and DstImage 
mismatch]\n\ diff --git a/BaseTools/Source/C/EfiLdrImage/EfiLdrImage.c 
b/BaseTools/Source/C/EfiLdrImage/EfiLdrImage.c
index 7961867..88cc345 100644
--- a/BaseTools/Source/C/EfiLdrImage/EfiLdrImage.c
+++ b/BaseTools/Source/C/EfiLdrImage/EfiLdrImage.c
@@ -6,7 +6,7 @@ FILE := EFILDR_HEADER
  +
 The order of EFILDR_IMAGE is same as the order of placing PeImageFileContent.
   
-Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.
+Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.
 This program and the accompanying materials  
 are licensed and made available under the terms and conditions of the BSD 
License 
 which accompanies this distribution.  The full text of the license may be 
found at
@@ -51,8 +51,8 @@ typedef struct {
 //
 // Utility version information
 //
-#define UTILITY_MAJOR_VERSION 1
-#define UTILITY_MINOR_VERSION 0
+#define UTILITY_MAJOR_VERSION 1
+#define UTILITY_MINOR_VERSION 0
 
 void
 Version (
@@ -74,8 +74,8 @@ Returns:
 
 --*/
 {
-  printf ("%s Version %d.%d Build %s\n", UTILITY_NAME, UTILITY_MAJOR_VERSION, 
UTILITY_MINOR_VERSION, __BUILD_VERSION);
-  exit (0);
+  printf ("%s Version %d.%d Build %s\n", UTILITY_NAME, 
+ UTILITY_MAJOR_VERSION, UTILITY_MINOR_VERSION, __BUILD_VERSION);  exit 
+ (0);
 }
 
 VOID
@@ -84,9 +84,9 @@ Usage (
   )
 {
   printf ("Usage: EfiLdrImage -o OutImage LoaderImage PeImage1 PeImage2 ... 
PeImageN\n");
-  printf ("%s Version %d.%d Build %s\n", UTILITY_NAME, UTILITY_MAJOR_VERSION, 
UTILITY_MINOR_VERSION, __BUILD_VERSION);
-  printf ("Copyright (c) 1999-2016 Intel Corporation. All rights reserved.\n");
-  printf ("\n  The EfiLdrImage tool is used to combine PE file

Re: [edk2] EDK2 Setup & Configuration Issue

[Jim Slaughter]

Looks like that did.Jim S.
 

On Tuesday, March 8, 2016 4:43 PM, "Carsey, Jaben"  
wrote:
 

 #yiv2666485428 #yiv2666485428 -- _filtered #yiv2666485428 
{font-family:Helvetica;panose-1:2 11 6 4 2 2 2 2 2 4;} _filtered #yiv2666485428 
{panose-1:2 4 5 3 5 4 6 3 2 4;} _filtered #yiv2666485428 
{font-family:Calibri;panose-1:2 15 5 2 2 2 4 3 2 4;}#yiv2666485428 
#yiv2666485428 p.yiv2666485428MsoNormal, #yiv2666485428 
li.yiv2666485428MsoNormal, #yiv2666485428 div.yiv2666485428MsoNormal 
{margin:0in;margin-bottom:.0001pt;font-size:12.0pt;}#yiv2666485428 a:link, 
#yiv2666485428 span.yiv2666485428MsoHyperlink 
{color:blue;text-decoration:underline;}#yiv2666485428 a:visited, #yiv2666485428 
span.yiv2666485428MsoHyperlinkFollowed 
{color:purple;text-decoration:underline;}#yiv2666485428 
span.yiv2666485428EmailStyle17 {color:#1F497D;}#yiv2666485428 
.yiv2666485428MsoChpDefault {font-size:10.0pt;} _filtered #yiv2666485428 
{margin:1.0in 1.0in 1.0in 1.0in;}#yiv2666485428 div.yiv2666485428WordSection1 
{}#yiv2666485428 BaseTools and Conf should be one directory up I think.    
From: Jim Slaughter [mailto:jwslau...@yahoo.com]
Sent: Tuesday, March 08, 2016 4:19 PM
To: Carsey, Jaben ; Gao, Liming ; 
Tian, Feng ; edk2-devel@lists.01.org
Subject: Re: [edk2] EDK2 Setup & Configuration Issue
Importance: High    Windows Environment:    edketup:     
C:\edk2\BaseTools(Windows)>edksetup
'C:\edk2\BaseTools' is not recognized as an internal or external command,
operable program or batch file. !!! WARNING !!! CYGWIN_HOME not found, gcc 
build may not be used !!! C:\edk2\BaseTools(Windows)>    A dir of this:    
C:\edk2\BaseTools(Windows)>dir
 Volume in drive C is OSDisk
 Volume Serial Number is CE0F-B385  Directory of C:\edk2\BaseTools(Windows) 
03/08/2016  03:17 PM      .
03/08/2016  03:17 PM      ..
03/08/2016  03:17 PM      BaseTools
03/08/2016  03:17 PM      Conf
03/08/2016  03:17 PM 4,202 edksetup.bat
   1 File(s)  4,202 bytes
   4 Dir(s)  941,196,587,008 bytes free C:\edk2\BaseTools(Windows)> 
   Jim S.          On Tuesday, March 8, 2016 2:27 PM, "Carsey, Jaben" 
 wrote:    Jim,

You need to download or build the BaseTools that are used during the build.

Have you done that?

-Jaben

> -Original Message-
> From: edk2-devel [mailto:edk2-devel-boun...@lists.01.org] On Behalf Of Jim
> Slaughter
> Sent: Tuesday, March 08, 2016 2:21 PM
> To: Gao, Liming ; Tian, Feng ;
> edk2-devel@lists.01.org
> Subject: Re: [edk2] EDK2 Setup & Configuration Issue
> 
> Hello Liming:
> I am confused.I originally downloaded edk2-master and unzipped.This has one
> of the packages I am interested in building, embeddedpkg. This is where the
> directory is missing.
> I have since downloaded 2014 and 2015, all in separate directories, from
> sourceforge.The file structure looks different? I am after the Ffs code which 
> I
> think appears in embeddedpkg. I searched for the function
> FfsFindNextVolumne() and it is not located in 2014 or 2015. The function is in
> edk2-master.
> What is wrong? Am I not downloading the correct zip files?
> Jim S.
> 
> 
>    On Thursday, March 3, 2016 8:21 PM, "Gao, Liming"
>  wrote:
> 
> 
>  #yiv2782034757 #yiv2782034757 -- _filtered #yiv2782034757 {font-
> family:Helvetica;panose-1:2 11 6 4 2 2 2 2 2 4;} _filtered #yiv2782034757
> {font-family:SimSun;panose-1:2 1 6 0 3 1 1 1 1 1;} _filtered #yiv2782034757
> {panose-1:2 4 5 3 5 4 6 3 2 4;} _filtered #yiv2782034757 {font-
> family:Calibri;panose-1:2 15 5 2 2 2 4 3 2 4;} _filtered #yiv2782034757
> {panose-1:2 1 6 0 3 1 1 1 1 1;}#yiv2782034757 #yiv2782034757
> p.yiv2782034757MsoNormal, #yiv2782034757 li.yiv2782034757MsoNormal,
> #yiv2782034757 div.yiv2782034757MsoNormal {margin:0in;margin-
> bottom:.0001pt;font-size:12.0pt;}#yiv2782034757 a:link, #yiv2782034757
> span.yiv2782034757MsoHyperlink {color:blue;text-
> decoration:underline;}#yiv2782034757 a:visited, #yiv2782034757
> span.yiv2782034757MsoHyperlinkFollowed {color:purple;text-
> decoration:underline;}#yiv2782034757 span.yiv2782034757EmailStyle17
> {color:#1F497D;}#yiv2782034757 .yiv2782034757MsoChpDefault {font-
> size:10.0pt;} _filtered #yiv2782034757 {margin:1.0in 1.0in 1.0in
> 1.0in;}#yiv2782034757 div.yiv2782034757WordSection1 {}#yiv2782034757
> Jim:   Yes. GitHub Edk2 project has not included BaseTools Binary. You need to
> download it from this linkhttps://github.com/tianocore/edk2-BaseTools-
> win32.git.      Or, you download full source code from UDK release
> http://www.tianocore.org/udk/udk2015/   Thanks Liming From: Jim Slaughter
> [mailto:jwslau...@yahoo.com]
> Sent: Friday, March 04, 2016 11:26 AM
> To: Gao, Liming; Tian, Feng; edk2-devel@lists.01.org
> Subject: Re: [edk2] EDK2 Setup & Configuration Issue    Hello,    I downloaded
> edk2 again, and its the 2014 stable version. The directory is still not
> there:    Z:\edk2\edk2-master>dir basetools\bin\win32
>  Volume in drive Z is vxbox
>  Volume Serial Number is 009A-

[edk2] [patch] SecurityPkg: Add Tpm2 prefix to lib to avoid conflict.

[Jiewen Yao]

Tpm2Ptp.c is library, but it miss Tpm2 prefix for
IsPtpPresence() and GetPtpInterface(). There might
be risk as name symbol conflict. This patch adds Tpm2
prefix for them.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: "Yao, Jiewen" 
Cc: "Zhang, Chao B" 
Tested-by: "Wu, Hao A" 

---
 SecurityPkg/Library/Tpm2DeviceLibDTpm/Tpm2Ptp.c | 18 +-
 1 file changed, 9 insertions(+), 9 deletions(-)

diff --git a/SecurityPkg/Library/Tpm2DeviceLibDTpm/Tpm2Ptp.c 
b/SecurityPkg/Library/Tpm2DeviceLibDTpm/Tpm2Ptp.c
index a627bbd..ddd4bd0 100644
--- a/SecurityPkg/Library/Tpm2DeviceLibDTpm/Tpm2Ptp.c
+++ b/SecurityPkg/Library/Tpm2DeviceLibDTpm/Tpm2Ptp.c
@@ -1,7 +1,7 @@
 /** @file
   PTP (Platform TPM Profile) CRB (Command Response Buffer) interface used by 
dTPM2.0 library.
 
-Copyright (c) 2015, Intel Corporation. All rights reserved.
+Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.
 This program and the accompanying materials
 are licensed and made available under the terms and conditions of the BSD 
License
 which accompanies this distribution.  The full text of the license may be 
found at
@@ -52,7 +52,7 @@ typedef enum {
   @retvalFALSE   TPM PTP is not found.
 **/
 BOOLEAN
-IsPtpPresence (
+Tpm2IsPtpPresence (
   IN VOID *Reg
   )
 {
@@ -117,7 +117,7 @@ PtpCrbRequestUseTpm (
 {
   EFI_STATUSStatus;
 
-  if (!IsPtpPresence (CrbReg)) {
+  if (!Tpm2IsPtpPresence (CrbReg)) {
 return EFI_NOT_FOUND;
   }
 
@@ -353,14 +353,14 @@ TisPcRequestUseTpm (
   @return PTP interface type.
 **/
 PTP_INTERFACE_TYPE
-GetPtpInterface (
+Tpm2GetPtpInterface (
   IN VOID *Register
   )
 {
   PTP_CRB_INTERFACE_IDENTIFIER  InterfaceId;
   PTP_FIFO_INTERFACE_CAPABILITY InterfaceCapability;
 
-  if (!IsPtpPresence (Register)) {
+  if (!Tpm2IsPtpPresence (Register)) {
 return PtpInterfaceMax;
   }
   //
@@ -401,7 +401,7 @@ DumpPtpInfo (
   UINT8 Rid;
   PTP_INTERFACE_TYPEPtpInterface;
 
-  if (!IsPtpPresence (Register)) {
+  if (!Tpm2IsPtpPresence (Register)) {
 return ;
   }
 
@@ -440,7 +440,7 @@ DumpPtpInfo (
   Vid = 0x;
   Did = 0x;
   Rid = 0xFF;
-  PtpInterface = GetPtpInterface (Register);
+  PtpInterface = Tpm2GetPtpInterface (Register);
   DEBUG ((EFI_D_INFO, "PtpInterface - %x\n", PtpInterface));
   switch (PtpInterface) {
   case PtpInterfaceCrb:
@@ -485,7 +485,7 @@ DTpm2SubmitCommand (
 {
   PTP_INTERFACE_TYPE  PtpInterface;
 
-  PtpInterface = GetPtpInterface ((VOID *) (UINTN) PcdGet64 
(PcdTpmBaseAddress));
+  PtpInterface = Tpm2GetPtpInterface ((VOID *) (UINTN) PcdGet64 
(PcdTpmBaseAddress));
   switch (PtpInterface) {
   case PtpInterfaceCrb:
 return PtpCrbTpmCommand (
@@ -524,7 +524,7 @@ DTpm2RequestUseTpm (
 {
   PTP_INTERFACE_TYPE  PtpInterface;
 
-  PtpInterface = GetPtpInterface ((VOID *) (UINTN) PcdGet64 
(PcdTpmBaseAddress));
+  PtpInterface = Tpm2GetPtpInterface ((VOID *) (UINTN) PcdGet64 
(PcdTpmBaseAddress));
   switch (PtpInterface) {
   case PtpInterfaceCrb:
 return PtpCrbRequestUseTpm ((PTP_CRB_REGISTERS_PTR) (UINTN) PcdGet64 
(PcdTpmBaseAddress));
-- 
1.9.5.msysgit.0

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Re: [edk2] [patch] MdeModulePkg: Add missing pcd description to MdeModulePkg.uni

[Qiu, Shumin]

Reviewed-by: Qiu Shumin 

-Original Message-
From: Bi, Dandan 
Sent: Wednesday, March 09, 2016 12:37 PM
To: edk2-devel@lists.01.org
Cc: Qiu, Shumin; Dong, Eric
Subject: [patch] MdeModulePkg: Add missing pcd description to MdeModulePkg.uni

Since PcdHiiOsRuntimeSupport has added in the MdeModulePkg.dec file, now add 
the usage information in the uni file.

Cc: Qiu Shumin 
Cc: Eric Dong 
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Dandan Bi 
---
 MdeModulePkg/MdeModulePkg.uni | 8 
 1 file changed, 8 insertions(+)

diff --git a/MdeModulePkg/MdeModulePkg.uni b/MdeModulePkg/MdeModulePkg.uni 
index 257a5d6..9e62f27 100644
--- a/MdeModulePkg/MdeModulePkg.uni
+++ b/MdeModulePkg/MdeModulePkg.uni
@@ -924,5 +924,13 @@

  "BIT 2 - EFI_ACPI_TABLE_VERSION_2_0.\n"

  "BIT 3 - EFI_ACPI_TABLE_VERSION_3_0.\n"

  "BIT 4 - EFI_ACPI_TABLE_VERSION_4_0.\n"

  "BIT 5 - EFI_ACPI_TABLE_VERSION_5_0."
 
+#string STR_gEfiMdeModulePkgTokenSpaceGuid_PcdHiiOsRuntimeSupport_PROMPT  
#language en-US "Enable export HII data and configuration to be used in OS 
runtime."
+
+#string STR_gEfiMdeModulePkgTokenSpaceGuid_PcdHiiOsRuntimeSupport_HELP  
#language en-US "Indicates if HII data and configuration has been 
exported.\n"
+   
 "Add this PCD mainly consider the use case of simulator. This PCD 
maybe set to FALSE for\n"
+   
 "simulator platform because the performance cost for this feature.\n"
+   
 "TRUE  - Export HII data and configuration data.\n"
+   
 "FALSE - Does not export HII data and configuration."
+
--
1.9.5.msysgit.1

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[edk2] [patch] MdeModulePkg: Add missing pcd description to MdeModulePkg.uni

[Dandan Bi]

Since PcdHiiOsRuntimeSupport has added in the MdeModulePkg.dec file,
now add the usage information in the uni file.

Cc: Qiu Shumin 
Cc: Eric Dong 
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Dandan Bi 
---
 MdeModulePkg/MdeModulePkg.uni | 8 
 1 file changed, 8 insertions(+)

diff --git a/MdeModulePkg/MdeModulePkg.uni b/MdeModulePkg/MdeModulePkg.uni
index 257a5d6..9e62f27 100644
--- a/MdeModulePkg/MdeModulePkg.uni
+++ b/MdeModulePkg/MdeModulePkg.uni
@@ -924,5 +924,13 @@

  "BIT 2 - EFI_ACPI_TABLE_VERSION_2_0.\n"

  "BIT 3 - EFI_ACPI_TABLE_VERSION_3_0.\n"

  "BIT 4 - EFI_ACPI_TABLE_VERSION_4_0.\n"

  "BIT 5 - EFI_ACPI_TABLE_VERSION_5_0."
 
+#string STR_gEfiMdeModulePkgTokenSpaceGuid_PcdHiiOsRuntimeSupport_PROMPT  
#language en-US "Enable export HII data and configuration to be used in OS 
runtime."
+
+#string STR_gEfiMdeModulePkgTokenSpaceGuid_PcdHiiOsRuntimeSupport_HELP  
#language en-US "Indicates if HII data and configuration has been 
exported.\n"
+   
 "Add this PCD mainly consider the use case of simulator. This PCD 
maybe set to FALSE for\n"
+   
 "simulator platform because the performance cost for this feature.\n"
+   
 "TRUE  - Export HII data and configuration data.\n"
+   
 "FALSE - Does not export HII data and configuration."
+
-- 
1.9.5.msysgit.1

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Re: [edk2] Update UDK2014 to UDK2015 leads to setup page slow

[Gao, Liming]

Xiaofeng:
  We find the similar issue in DEBUG tip when DEBUG log is enabled. 
AllocatePool() service will be slower than before. The updated memory 
allocation algorithm brings the long free pool list and cause AllocatePool() 
service slow. I am still investigating it. The temp solution is to disable link 
list check by set gEfiMdePkgTokenSpaceGuid.PcdMaximumLinkedListLength to 0 in 
platform DSC file. Could you see whether this way works or not? If it works, 
your issue should be same to ours. If not, your issue may be different. 

Thanks
Liming
> -Original Message-
> From: edk2-devel [mailto:edk2-devel-boun...@lists.01.org] On Behalf Of
> wang xiaofeng
> Sent: Wednesday, March 09, 2016 10:36 AM
> To: Dong, Eric; edk2-devel@lists.01.org
> Subject: [edk2] Update UDK2014 to UDK2015 leads to setup page slow
> 
> Hi Edk2 developers,
>After upate to UDK2015 from UDk2014, the Uiapp setup shows very slow.
> the following is our issue and debug information. Anyone meet similar issue
> before?
> 
> 
> Issue symptom:
> 
> 1, System draw the Front Page cost about 2 second. We can see the frame/
> menu block/ help block draw one by one. Other submenu has same slowly
> display when enter it.
> 
> Normally those are instantaneous  work .
> 
> 2, Change the highlight item in one page meet about half-second delay
> response.
> 
> 3, In Data and time page. We can see the scan line to update the time display
> from top-left to bottom-right.
> 
> 4, In shell environment, "drivers" command can show title part normally, but
> it display the number of driver with a visible slow speed. "PCI" command still
> has normal behave.
> 
> 
> 
> 
> Debug step:
> 
> 1, Doubt that call back function hook to the form will case this issue .Try to
> remove the callback function for all the form.
> 
> Issue still happened.
> 
> 2. Because the setup has may loop invoke, Try to fixed a single delay point 
> for
> more debug.
> 
> In "DisplayPageFrame" when try to clear the screen for First Form display ,
> there is about 1-2 second single delay point inside
> 
> ClearLines (0, gScreenDimensions.RightColumn, 0,
> gScreenDimensions.BottomRow, KEYHELP_BACKGROUND);
> 
> Trace the string passed to clear screen in this routing .The string is same 
> with
> the UDK2014 normal case. This can preliminary exclusion the string analysis
> issue and special font issue.
> 
> 3,  Deep debug, Delay is happened in "PrintInternal" try to invoke "Out-
> >OutputString(XX)".
> 
> This Out is point to system table  conout , There is only one
> SimpleTextOutput  "GraphicsConsoleController" in consplitter list in our
> project.
> 
>  And the GOP protocol install  optrom in both UDK2014 and UDK2015 are
> the same one. BTW, The logo display and post information display has no
> delay symptom.
> 
> 4, There is  three "Out->OutputString(XX)" invoke "PrintInternal", String
> is display by first two after remove the CHAR type. the last invoke is used 
> for
> display space to meet the request display size.
> 
> If we don't do this work. Symptom 2 Will have a great improvement.
> ___
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> edk2-devel@lists.01.org
> https://lists.01.org/mailman/listinfo/edk2-devel
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Re: [edk2] [Patch] UefiCpuPkg/Application/Cpuid: Remove unnecessary code check

[Kinney, Michael D]

Reviewed-by: Michael Kinney 


> -Original Message-
> From: Fan, Jeff
> Sent: Tuesday, March 8, 2016 6:17 PM
> To: edk2-devel@lists.01.org
> Cc: Qiu, Shumin ; Kinney, Michael D 
> 
> Subject: [Patch] UefiCpuPkg/Application/Cpuid: Remove unnecessary code check
> 
> gMaximumBasicFunction is set to CPUID_SIGNATURE as below, so removed the 
> compare code.
> UINT32  gMaximumBasicFunction = CPUID_SIGNATURE;
> 
> Cc: Qiu Shumin 
> Cc: Michael Kinney 
> Contributed-under: TianoCore Contribution Agreement 1.0
> Signed-off-by: Jeff Fan 
> ---
>  UefiCpuPkg/Application/Cpuid/Cpuid.c | 4 
>  1 file changed, 4 deletions(-)
> 
> diff --git a/UefiCpuPkg/Application/Cpuid/Cpuid.c
> b/UefiCpuPkg/Application/Cpuid/Cpuid.c
> index f5268cd..b0624e1 100644
> --- a/UefiCpuPkg/Application/Cpuid/Cpuid.c
> +++ b/UefiCpuPkg/Application/Cpuid/Cpuid.c
> @@ -179,10 +179,6 @@ CpuidSignature (
>UINT32 Edx;
>CHAR8  Signature[13];
> 
> -  if (CPUID_SIGNATURE > gMaximumBasicFunction) {
> -return;
> -  }
> -
>AsmCpuid (CPUID_SIGNATURE, &Eax, &Ebx, &Ecx, &Edx);
> 
>Print (L"CPUID_SIGNATURE (Leaf %08x)\n", CPUID_SIGNATURE);
> --
> 1.9.5.msysgit.0

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Re: [edk2] [Patch] UefiCpuPkg/Application/Cpuid: Add check for gMaximumBasicFunction

[Kinney, Michael D]

Reviewed-by: Michael Kinney 

> -Original Message-
> From: Fan, Jeff
> Sent: Tuesday, March 8, 2016 6:17 PM
> To: edk2-devel@lists.01.org
> Cc: Qiu, Shumin ; Kinney, Michael D 
> 
> Subject: [Patch] UefiCpuPkg/Application/Cpuid: Add check for 
> gMaximumBasicFunction
> 
> Add check for gMaximumBasicFunction in CpuidVersionInfo () back.
> 
> Cc: Qiu Shumin 
> Cc: Michael Kinney 
> Contributed-under: TianoCore Contribution Agreement 1.0
> Signed-off-by: Jeff Fan 
> ---
>  UefiCpuPkg/Application/Cpuid/Cpuid.c | 4 
>  1 file changed, 4 insertions(+)
> 
> diff --git a/UefiCpuPkg/Application/Cpuid/Cpuid.c
> b/UefiCpuPkg/Application/Cpuid/Cpuid.c
> index 371df66..f5268cd 100644
> --- a/UefiCpuPkg/Application/Cpuid/Cpuid.c
> +++ b/UefiCpuPkg/Application/Cpuid/Cpuid.c
> @@ -213,6 +213,10 @@ CpuidVersionInfo (
>UINT32  DisplayFamily;
>UINT32  DisplayModel;
> 
> +  if (CPUID_VERSION_INFO > gMaximumBasicFunction) {
> +return;
> +  }
> +
>AsmCpuid (CPUID_VERSION_INFO, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, 
> &Edx.Uint32);
> 
>Print (L"CPUID_VERSION_INFO (Leaf %08x)\n", CPUID_VERSION_INFO);
> --
> 1.9.5.msysgit.0

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[edk2] [Patch 21/21] UefiCpuPkg/Include: Add top level MSR include file

[Michael Kinney]

Add top level MSR include file that includes the Architecural MSR
include file and all family specific MSR files from the Msr
subdirectory

Intel(R) 64 and IA-32 Architectures Software Developer's
Manual, Volume 3, December 2015, Chapter 35
Model-Specific-Registers (MSR).

Cc: Jeff Fan 
Cc: Jiewen Yao 
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Michael Kinney 
---
 UefiCpuPkg/Include/Register/Msr.h | 48 +++
 1 file changed, 48 insertions(+)
 create mode 100644 UefiCpuPkg/Include/Register/Msr.h

diff --git a/UefiCpuPkg/Include/Register/Msr.h 
b/UefiCpuPkg/Include/Register/Msr.h
new file mode 100644
index 000..c0ee995
--- /dev/null
+++ b/UefiCpuPkg/Include/Register/Msr.h
@@ -0,0 +1,48 @@
+/** @file
+  MSR Defintions.
+
+  Provides defines for Machine Specific Registers(MSR) indexes. Data structures
+  are provided for MSRs that contain one or more bit fields.  If the MSR value
+  returned is a single 32-bit or 64-bit value, then a data structure is not
+  provided for that MSR.
+
+  Copyright (c) 2016, Intel Corporation. All rights reserved.
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD 
License
+  which accompanies this distribution.  The full text of the license may be 
found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+  @par Specification Reference:
+  Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,
+  December 2015, Chapter 35 Model-Specific-Registers (MSR), Chapter 35.
+
+**/
+
+#ifndef __MSR_H__
+#define __MSR_H__
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#endif
-- 
2.6.3.windows.1

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[edk2] [Patch 19/21] UefiCpuPkg/Include: Add P6 MSR include file

[Michael Kinney]

Add P6 MSRs from:
Intel(R) 64 and IA-32 Architectures Software Developer's
Manual, Volume 3, December 2015, Chapter 35
Model-Specific-Registers (MSR), Section 35-19.

Cc: Jeff Fan 
Cc: Jiewen Yao 
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Michael Kinney 
---
 UefiCpuPkg/Include/Register/Msr/P6Msr.h | 1608 +++
 1 file changed, 1608 insertions(+)
 create mode 100644 UefiCpuPkg/Include/Register/Msr/P6Msr.h

diff --git a/UefiCpuPkg/Include/Register/Msr/P6Msr.h 
b/UefiCpuPkg/Include/Register/Msr/P6Msr.h
new file mode 100644
index 000..4f82de1
--- /dev/null
+++ b/UefiCpuPkg/Include/Register/Msr/P6Msr.h
@@ -0,0 +1,1608 @@
+/** @file
+  MSR Defintions for P6 Family Processors.
+
+  Provides defines for Machine Specific Registers(MSR) indexes. Data structures
+  are provided for MSRs that contain one or more bit fields.  If the MSR value
+  returned is a single 32-bit or 64-bit value, then a data structure is not
+  provided for that MSR.
+
+  Copyright (c) 2016, Intel Corporation. All rights reserved.
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD 
License
+  which accompanies this distribution.  The full text of the license may be 
found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+  @par Specification Reference:
+  Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,
+  December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-19.
+
+**/
+
+#ifndef __P6_MSR_H__
+#define __P6_MSR_H__
+
+#include 
+
+/**
+  See Section 35.20, "MSRs in Pentium Processors.".
+
+  @param  ECX  MSR_P6_P5_MC_ADDR (0x)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  Example usage
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_P6_P5_MC_ADDR);
+  AsmWriteMsr64 (MSR_P6_P5_MC_ADDR, Msr);
+  @endcode
+**/
+#define MSR_P6_P5_MC_ADDR0x
+
+
+/**
+  See Section 35.20, "MSRs in Pentium Processors.".
+
+  @param  ECX  MSR_P6_P5_MC_TYPE (0x0001)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  Example usage
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_P6_P5_MC_TYPE);
+  AsmWriteMsr64 (MSR_P6_P5_MC_TYPE, Msr);
+  @endcode
+**/
+#define MSR_P6_P5_MC_TYPE0x0001
+
+
+/**
+  See Section 17.14, "Time-Stamp Counter.".
+
+  @param  ECX  MSR_P6_TSC (0x0010)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  Example usage
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_P6_TSC);
+  AsmWriteMsr64 (MSR_P6_TSC, Msr);
+  @endcode
+**/
+#define MSR_P6_TSC   0x0010
+
+
+/**
+  Platform ID (R)  The operating system can use this MSR to determine "slot"
+  information for the processor and the proper microcode update to load.
+
+  @param  ECX  MSR_P6_IA32_PLATFORM_ID (0x0017)
+  @param  EAX  Lower 32-bits of MSR value.
+   Described by the type MSR_P6_IA32_PLATFORM_ID_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+   Described by the type MSR_P6_IA32_PLATFORM_ID_REGISTER.
+
+  Example usage
+  @code
+  MSR_P6_IA32_PLATFORM_ID_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_P6_IA32_PLATFORM_ID);
+  @endcode
+**/
+#define MSR_P6_IA32_PLATFORM_ID  0x0017
+
+/**
+  MSR information returned for MSR index #MSR_P6_IA32_PLATFORM_ID
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+UINT32  Reserved1:32;
+UINT32  Reserved2:18;
+///
+/// [Bits 52:50] Platform Id (R) Contains information concerning the
+/// intended platform for the processor.
+///
+///  52 51 50
+///   0  0  0  Processor Flag 0.
+///   0  0  1  Processor Flag 1
+///   0  1  0  Processor Flag 2
+///   0  1  1  Processor Flag 3
+///   1  0  0  Processor Flag 4
+///   1  0  1  Processor Flag 5
+///   1  1  0  Processor Flag 6
+///   1  1  1  Processor Flag 7
+///
+UINT32  PlatformId:3;
+///
+/// [Bits 56:53] L2 Cache Latency Read.
+///
+UINT32  L2CacheLatencyRead:4;
+UINT32  Reserved3:3;
+///
+/// [Bit 60] Clock Frequency Ratio Read.
+///
+UINT32  ClockFrequencyRatioRead:1;
+UINT32  Reserved4:3;
+  } Bits;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_P6_IA32_PLATFORM_ID_REGISTER;
+
+
+/**
+  Section 10.4.4, "Local APIC Status and Location.".
+
+  @param  ECX  MSR_P6_APIC_BASE (0x001B)
+  @param  EAX  Lower 32-bits of MSR value.
+   Described by the type MSR_P6_APIC_BASE_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+   Described by the type MSR_P6_APIC_BASE_REGISTER.

[edk2] [Patch 20/21] UefiCpuPkg/Include: Add Pentium MSR include file

[Michael Kinney]

Add Pentium MSRs from:
Intel(R) 64 and IA-32 Architectures Software Developer's
Manual, Volume 3, December 2015, Chapter 35
Model-Specific-Registers (MSR), Section 35-20.

Cc: Jeff Fan 
Cc: Jiewen Yao 
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Michael Kinney 
---
 UefiCpuPkg/Include/Register/Msr/PentiumMsr.h | 121 +++
 1 file changed, 121 insertions(+)
 create mode 100644 UefiCpuPkg/Include/Register/Msr/PentiumMsr.h

diff --git a/UefiCpuPkg/Include/Register/Msr/PentiumMsr.h 
b/UefiCpuPkg/Include/Register/Msr/PentiumMsr.h
new file mode 100644
index 000..f0105d2
--- /dev/null
+++ b/UefiCpuPkg/Include/Register/Msr/PentiumMsr.h
@@ -0,0 +1,121 @@
+/** @file
+  MSR Defintions for Pentium Processors.
+
+  Provides defines for Machine Specific Registers(MSR) indexes. Data structures
+  are provided for MSRs that contain one or more bit fields.  If the MSR value
+  returned is a single 32-bit or 64-bit value, then a data structure is not
+  provided for that MSR.
+
+  Copyright (c) 2016, Intel Corporation. All rights reserved.
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD 
License
+  which accompanies this distribution.  The full text of the license may be 
found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+  @par Specification Reference:
+  Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,
+  December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-20.
+
+**/
+
+#ifndef __PENTIUM_MSR_H__
+#define __PENTIUM_MSR_H__
+
+#include 
+
+/**
+  See Section 15.10.2, "Pentium Processor Machine-Check Exception Handling.".
+
+  @param  ECX  MSR_PENTIUM_P5_MC_ADDR (0x)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  Example usage
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_PENTIUM_P5_MC_ADDR);
+  AsmWriteMsr64 (MSR_PENTIUM_P5_MC_ADDR, Msr);
+  @endcode
+**/
+#define MSR_PENTIUM_P5_MC_ADDR   0x
+
+
+/**
+  See Section 15.10.2, "Pentium Processor Machine-Check Exception Handling.".
+
+  @param  ECX  MSR_PENTIUM_P5_MC_TYPE (0x0001)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  Example usage
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_PENTIUM_P5_MC_TYPE);
+  AsmWriteMsr64 (MSR_PENTIUM_P5_MC_TYPE, Msr);
+  @endcode
+**/
+#define MSR_PENTIUM_P5_MC_TYPE   0x0001
+
+
+/**
+  See Section 17.14, "Time-Stamp Counter.".
+
+  @param  ECX  MSR_PENTIUM_TSC (0x0010)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  Example usage
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_PENTIUM_TSC);
+  AsmWriteMsr64 (MSR_PENTIUM_TSC, Msr);
+  @endcode
+**/
+#define MSR_PENTIUM_TSC  0x0010
+
+
+/**
+  See Section 18.20.1, "Control and Event Select Register (CESR).".
+
+  @param  ECX  MSR_PENTIUM_CESR (0x0011)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  Example usage
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_PENTIUM_CESR);
+  AsmWriteMsr64 (MSR_PENTIUM_CESR, Msr);
+  @endcode
+**/
+#define MSR_PENTIUM_CESR 0x0011
+
+
+/**
+  Section 18.20.3, "Events Counted.".
+
+  @param  ECX  MSR_PENTIUM_CTRn
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  Example usage
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_PENTIUM_CTR0);
+  AsmWriteMsr64 (MSR_PENTIUM_CTR0, Msr);
+  @endcode
+  @{
+**/
+#define MSR_PENTIUM_CTR0 0x0012
+#define MSR_PENTIUM_CTR1 0x0013
+/// @}
+
+#endif
-- 
2.6.3.windows.1

___
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[edk2] [Patch 03/21] UefiCpuPkg/Include: Add Atom MSR include file

[Michael Kinney]

Add Atom MSRs from:
Intel(R) 64 and IA-32 Architectures Software Developer's
Manual, Volume 3, December 2015, Chapter 35
Model-Specific-Registers (MSR), Section 35-3.

Cc: Jeff Fan 
Cc: Jiewen Yao 
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Michael Kinney 
---
 UefiCpuPkg/Include/Register/Msr/AtomMsr.h | 896 ++
 1 file changed, 896 insertions(+)
 create mode 100644 UefiCpuPkg/Include/Register/Msr/AtomMsr.h

diff --git a/UefiCpuPkg/Include/Register/Msr/AtomMsr.h 
b/UefiCpuPkg/Include/Register/Msr/AtomMsr.h
new file mode 100644
index 000..5b13a95
--- /dev/null
+++ b/UefiCpuPkg/Include/Register/Msr/AtomMsr.h
@@ -0,0 +1,896 @@
+/** @file
+  MSR Defintions for the Intel(R) Atom(TM) Processor Family.
+
+  Provides defines for Machine Specific Registers(MSR) indexes. Data structures
+  are provided for MSRs that contain one or more bit fields.  If the MSR value
+  returned is a single 32-bit or 64-bit value, then a data structure is not
+  provided for that MSR.
+
+  Copyright (c) 2016, Intel Corporation. All rights reserved.
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD 
License
+  which accompanies this distribution.  The full text of the license may be 
found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+  @par Specification Reference:
+  Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,
+  December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-3.
+
+**/
+
+#ifndef __ATOM_MSR_H__
+#define __ATOM_MSR_H__
+
+#include 
+
+/**
+  Shared. Model Specific Platform ID (R).
+
+  @param  ECX  MSR_ATOM_PLATFORM_ID (0x0017)
+  @param  EAX  Lower 32-bits of MSR value.
+   Described by the type MSR_ATOM_PLATFORM_ID_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+   Described by the type MSR_ATOM_PLATFORM_ID_REGISTER.
+
+  Example usage
+  @code
+  MSR_ATOM_PLATFORM_ID_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_ATOM_PLATFORM_ID);
+  @endcode
+**/
+#define MSR_ATOM_PLATFORM_ID 0x0017
+
+/**
+  MSR information returned for MSR index #MSR_ATOM_PLATFORM_ID
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+UINT32  Reserved1:8;
+///
+/// [Bits 12:8] Maximum Qualified Ratio (R)  The maximum allowed bus ratio.
+///
+UINT32  MaximumQualifiedRatio:5;
+UINT32  Reserved2:19;
+UINT32  Reserved3:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_ATOM_PLATFORM_ID_REGISTER;
+
+
+/**
+  Shared. Processor Hard Power-On Configuration (R/W) Enables and disables
+  processor features; (R) indicates current processor configuration.
+
+  @param  ECX  MSR_ATOM_EBL_CR_POWERON (0x002A)
+  @param  EAX  Lower 32-bits of MSR value.
+   Described by the type MSR_ATOM_EBL_CR_POWERON_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+   Described by the type MSR_ATOM_EBL_CR_POWERON_REGISTER.
+
+  Example usage
+  @code
+  MSR_ATOM_EBL_CR_POWERON_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_ATOM_EBL_CR_POWERON);
+  AsmWriteMsr64 (MSR_ATOM_EBL_CR_POWERON, Msr.Uint64);
+  @endcode
+**/
+#define MSR_ATOM_EBL_CR_POWERON  0x002A
+
+/**
+  MSR information returned for MSR index #MSR_ATOM_EBL_CR_POWERON
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+UINT32  Reserved1:1;
+///
+/// [Bit 1] Data Error Checking Enable (R/W) 1 = Enabled; 0 = Disabled
+/// Always 0.
+///
+UINT32  DataErrorCheckingEnable:1;
+///
+/// [Bit 2] Response Error Checking Enable (R/W) 1 = Enabled; 0 = Disabled
+/// Always 0.
+///
+UINT32  ResponseErrorCheckingEnable:1;
+///
+/// [Bit 3] AERR# Drive Enable (R/W)  1 = Enabled; 0 = Disabled Always 0.
+///
+UINT32  AERR_DriveEnable:1;
+///
+/// [Bit 4] BERR# Enable for initiator bus requests (R/W) 1 = Enabled; 0 =
+/// Disabled Always 0.
+///
+UINT32  BERR_Enable:1;
+UINT32  Reserved2:1;
+UINT32  Reserved3:1;
+///
+/// [Bit 7] BINIT# Driver Enable (R/W) 1 = Enabled; 0 = Disabled Always 0.
+///
+UINT32  BINIT_DriverEnable:1;
+UINT32  Reserved4:1;
+///
+/// [Bit 9] Execute BIST (R/O) 1 = Enabled; 0 = Disabled.
+///
+UINT32  ExecuteBIST:1;
+///
+/// [Bit 10] AERR# Observation Enabled (R/O) 1 = Enabled; 0 = Disabled
+/// Always 0.
+///
+UINT32  AERR_ObservationEnabled:1;
+UINT32  Reserved5:1;
+///
+/// [Bit 12] BINIT# Observation Enabled (R/O) 1 = Enabled; 0 = Disabled
+/// Always 0.
+///
+UINT32  BINIT_ObservationEnabled:1;
+  

[edk2] [Patch 13/21] UefiCpuPkg/Include: Add Xeon Processor D MSR include file

[Michael Kinney]

Add Xeon Processor D MSRs from:
Intel(R) 64 and IA-32 Architectures Software Developer's
Manual, Volume 3, December 2015, Chapter 35
Model-Specific-Registers (MSR), Section 35-13.

Cc: Jeff Fan 
Cc: Jiewen Yao 
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Michael Kinney 
---
 UefiCpuPkg/Include/Register/Msr/XeonDMsr.h | 1431 
 1 file changed, 1431 insertions(+)
 create mode 100644 UefiCpuPkg/Include/Register/Msr/XeonDMsr.h

diff --git a/UefiCpuPkg/Include/Register/Msr/XeonDMsr.h 
b/UefiCpuPkg/Include/Register/Msr/XeonDMsr.h
new file mode 100644
index 000..3940b44
--- /dev/null
+++ b/UefiCpuPkg/Include/Register/Msr/XeonDMsr.h
@@ -0,0 +1,1431 @@
+/** @file
+  MSR Defintions for Intel(R) Xeon(R) Processor D product Family.
+
+  Provides defines for Machine Specific Registers(MSR) indexes. Data structures
+  are provided for MSRs that contain one or more bit fields.  If the MSR value
+  returned is a single 32-bit or 64-bit value, then a data structure is not
+  provided for that MSR.
+
+  Copyright (c) 2016, Intel Corporation. All rights reserved.
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD 
License
+  which accompanies this distribution.  The full text of the license may be 
found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+  @par Specification Reference:
+  Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,
+  December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-13.
+
+**/
+
+#ifndef __XEON_D_MSR_H__
+#define __XEON_D_MSR_H__
+
+#include 
+
+/**
+  Package. Protected Processor Inventory Number Enable Control (R/W).
+
+  @param  ECX  MSR_XEON_D_PPIN_CTL (0x004E)
+  @param  EAX  Lower 32-bits of MSR value.
+   Described by the type MSR_XEON_D_PPIN_CTL_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+   Described by the type MSR_XEON_D_PPIN_CTL_REGISTER.
+
+  Example usage
+  @code
+  MSR_XEON_D_PPIN_CTL_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_PPIN_CTL);
+  AsmWriteMsr64 (MSR_XEON_D_PPIN_CTL, Msr.Uint64);
+  @endcode
+**/
+#define MSR_XEON_D_PPIN_CTL  0x004E
+
+/**
+  MSR information returned for MSR index #MSR_XEON_D_PPIN_CTL
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+///
+/// [Bit 0] LockOut (R/WO) See Table 35-21.
+///
+UINT32  LockOut:1;
+///
+/// [Bit 1] Enable_PPIN (R/W) See Table 35-21.
+///
+UINT32  Enable_PPIN:1;
+UINT32  Reserved1:30;
+UINT32  Reserved2:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_XEON_D_PPIN_CTL_REGISTER;
+
+
+/**
+  Package. Protected Processor Inventory Number (R/O). Protected Processor
+  Inventory Number (R/O) See Table 35-21.
+
+  @param  ECX  MSR_XEON_D_PPIN (0x004F)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  Example usage
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_XEON_D_PPIN);
+  @endcode
+**/
+#define MSR_XEON_D_PPIN  0x004F
+
+
+/**
+  Package. See http://biosbits.org.
+
+  @param  ECX  MSR_XEON_D_PLATFORM_INFO (0x00CE)
+  @param  EAX  Lower 32-bits of MSR value.
+   Described by the type MSR_XEON_D_PLATFORM_INFO_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+   Described by the type MSR_XEON_D_PLATFORM_INFO_REGISTER.
+
+  Example usage
+  @code
+  MSR_XEON_D_PLATFORM_INFO_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_PLATFORM_INFO);
+  AsmWriteMsr64 (MSR_XEON_D_PLATFORM_INFO, Msr.Uint64);
+  @endcode
+**/
+#define MSR_XEON_D_PLATFORM_INFO 0x00CE
+
+/**
+  MSR information returned for MSR index #MSR_XEON_D_PLATFORM_INFO
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+UINT32  Reserved1:8;
+///
+/// [Bits 15:8] Package. Maximum Non-Turbo Ratio (R/O) See Table 35-21.
+///
+UINT32  MaximumNonTurboRatio:8;
+UINT32  Reserved2:7;
+///
+/// [Bit 23] Package. PPIN_CAP (R/O) See Table 35-21.
+///
+UINT32  PPIN_CAP:1;
+UINT32  Reserved3:4;
+///
+/// [Bit 28] Package. Programmable Ratio Limit for Turbo Mode (R/O) See
+/// Table 35-21.
+///
+UINT32  RatioLimit:1;
+///
+/// [Bit 29] Package. Programmable TDP Limit for Turbo Mode (R/O) See
+/// Table 35-21.
+///
+UINT32  TDPLimit:1;
+///
+/// [Bit 30] Package. Programmable TJ OFFSET (R/O) See Table 35-21.
+///
+UINT32  TJOFFSET:1;
+UINT32  Reserved4:1;
+UINT32  Reserved5:8;
+///
+/// [Bits 47:40] Package. Maximum Efficiency Rati

[edk2] [Patch 06/21] UefiCpuPkg/Include: Add Xeon 5600 MSR include file

[Michael Kinney]

Add Xeon 5600 MSRs from:
Intel(R) 64 and IA-32 Architectures Software Developer's
Manual, Volume 3, December 2015, Chapter 35
Model-Specific-Registers (MSR), Section 35-6.

Cc: Jeff Fan 
Cc: Jiewen Yao 
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Michael Kinney 
---
 UefiCpuPkg/Include/Register/Msr/Xeon5600Msr.h | 182 ++
 1 file changed, 182 insertions(+)
 create mode 100644 UefiCpuPkg/Include/Register/Msr/Xeon5600Msr.h

diff --git a/UefiCpuPkg/Include/Register/Msr/Xeon5600Msr.h 
b/UefiCpuPkg/Include/Register/Msr/Xeon5600Msr.h
new file mode 100644
index 000..1aa30b3
--- /dev/null
+++ b/UefiCpuPkg/Include/Register/Msr/Xeon5600Msr.h
@@ -0,0 +1,182 @@
+/** @file
+  MSR Defintions for Intel(R) Xeon(R) Processor Series 5600.
+
+  Provides defines for Machine Specific Registers(MSR) indexes. Data structures
+  are provided for MSRs that contain one or more bit fields.  If the MSR value
+  returned is a single 32-bit or 64-bit value, then a data structure is not
+  provided for that MSR.
+
+  Copyright (c) 2016, Intel Corporation. All rights reserved.
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD 
License
+  which accompanies this distribution.  The full text of the license may be 
found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+  @par Specification Reference:
+  Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,
+  December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-6.
+
+**/
+
+#ifndef __XEON_5600_MSR_H__
+#define __XEON_5600_MSR_H__
+
+#include 
+
+/**
+  Core. AES Configuration (RW-L) Privileged post-BIOS agent must provide a #GP
+  handler to handle unsuccessful read of this MSR.
+
+  @param  ECX  MSR_XEON_5600_FEATURE_CONFIG (0x013C)
+  @param  EAX  Lower 32-bits of MSR value.
+   Described by the type MSR_XEON_5600_FEATURE_CONFIG_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+   Described by the type MSR_XEON_5600_FEATURE_CONFIG_REGISTER.
+
+  Example usage
+  @code
+  MSR_XEON_5600_FEATURE_CONFIG_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_XEON_5600_FEATURE_CONFIG);
+  AsmWriteMsr64 (MSR_XEON_5600_FEATURE_CONFIG, Msr.Uint64);
+  @endcode
+**/
+#define MSR_XEON_5600_FEATURE_CONFIG 0x013C
+
+/**
+  MSR information returned for MSR index #MSR_XEON_5600_FEATURE_CONFIG
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+///
+/// [Bits 1:0] AES Configuration (RW-L)  Upon a successful read of this
+/// MSR, the configuration of AES instruction set availability is as
+/// follows: 11b: AES instructions are not available until next RESET.
+/// otherwise, AES instructions are available. Note, AES instruction set
+/// is not available if read is unsuccessful. If the configuration is not
+/// 01b, AES instruction can be mis-configured if a privileged agent
+/// unintentionally writes 11b.
+///
+UINT32  AESConfiguration:2;
+UINT32  Reserved1:30;
+UINT32  Reserved2:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_XEON_5600_FEATURE_CONFIG_REGISTER;
+
+
+/**
+  Thread. Offcore Response Event Select Register (R/W).
+
+  @param  ECX  MSR_XEON_5600_OFFCORE_RSP_1 (0x01A7)
+  @param  EAX  Lower 32-bits of MSR value.
+   Described by the type MSR_XEON_5600_OFFCORE_RSP_1_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+   Described by the type MSR_XEON_5600_OFFCORE_RSP_1_REGISTER.
+
+  Example usage
+  @code
+  MSR_XEON_5600_OFFCORE_RSP_1_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_XEON_5600_OFFCORE_RSP_1);
+  AsmWriteMsr64 (MSR_XEON_5600_OFFCORE_RSP_1, Msr.Uint64);
+  @endcode
+**/
+#define MSR_XEON_5600_OFFCORE_RSP_1  0x01A7
+
+/**
+  MSR information returned for MSR index #MSR_XEON_5600_OFFCORE_RSP_1
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+///
+/// [Bits 7:0] Package. Maximum Ratio Limit for 1C Maximum turbo ratio
+/// limit of 1 core active.
+///
+UINT32  Maximum1C:8;
+///
+/// [Bits 15:8] Package. Maximum Ratio Limit for 2C Maximum turbo ratio
+/// limit of 2 core active.
+///
+UINT32  Maximum2C:8;
+///
+/// [Bits 23:16] Package. Maximum Ratio Limit for 3C Maximum turbo ratio
+/// limit of 3 core active.
+///
+UINT32  Maximum3C:8;
+///
+/// [Bits 31:24] Package. Maximum Ratio Limit for 4C Maximum turbo ratio
+/// limit of 4 core active.
+///
+UINT32  Maximum4C:8;
+///
+/// [Bits 39:32] Package. Maximum Ratio Limit for 5C Maximum turbo ratio
+/// limit of 

[edk2] [Patch 10/21] UefiCpuPkg/Include: Add Haswell MSR include file

[Michael Kinney]

Add Haswell MSRs from:
Intel(R) 64 and IA-32 Architectures Software Developer's
Manual, Volume 3, December 2015, Chapter 35
Model-Specific-Registers (MSR), Section 35-10.

Cc: Jeff Fan 
Cc: Jiewen Yao 
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Michael Kinney 
---
 UefiCpuPkg/Include/Register/Msr/HaswellMsr.h | 2575 ++
 1 file changed, 2575 insertions(+)
 create mode 100644 UefiCpuPkg/Include/Register/Msr/HaswellMsr.h

diff --git a/UefiCpuPkg/Include/Register/Msr/HaswellMsr.h 
b/UefiCpuPkg/Include/Register/Msr/HaswellMsr.h
new file mode 100644
index 000..b763585
--- /dev/null
+++ b/UefiCpuPkg/Include/Register/Msr/HaswellMsr.h
@@ -0,0 +1,2575 @@
+/** @file
+  MSR Defintions for Intel processors based on the Haswell microarchitecture.
+
+  Provides defines for Machine Specific Registers(MSR) indexes. Data structures
+  are provided for MSRs that contain one or more bit fields.  If the MSR value
+  returned is a single 32-bit or 64-bit value, then a data structure is not
+  provided for that MSR.
+
+  Copyright (c) 2016, Intel Corporation. All rights reserved.
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD 
License
+  which accompanies this distribution.  The full text of the license may be 
found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+  @par Specification Reference:
+  Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,
+  December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-10.
+
+**/
+
+#ifndef __HASWELL_MSR_H__
+#define __HASWELL_MSR_H__
+
+#include 
+
+/**
+  Package.
+
+  @param  ECX  MSR_HASWELL_PLATFORM_INFO (0x00CE)
+  @param  EAX  Lower 32-bits of MSR value.
+   Described by the type MSR_HASWELL_PLATFORM_INFO_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+   Described by the type MSR_HASWELL_PLATFORM_INFO_REGISTER.
+
+  Example usage
+  @code
+  MSR_HASWELL_PLATFORM_INFO_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_PLATFORM_INFO);
+  AsmWriteMsr64 (MSR_HASWELL_PLATFORM_INFO, Msr.Uint64);
+  @endcode
+**/
+#define MSR_HASWELL_PLATFORM_INFO0x00CE
+
+/**
+  MSR information returned for MSR index #MSR_HASWELL_PLATFORM_INFO
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+UINT32  Reserved1:8;
+///
+/// [Bits 15:8] Package. Maximum Non-Turbo Ratio (R/O)  The is the ratio
+/// of the frequency that invariant TSC runs at. Frequency = ratio * 100
+/// MHz.
+///
+UINT32  MaximumNonTurboRatio:8;
+UINT32  Reserved2:12;
+///
+/// [Bit 28] Package. Programmable Ratio Limit for Turbo Mode (R/O)  When
+/// set to 1, indicates that Programmable Ratio Limits for Turbo mode is
+/// enabled, and when set to 0, indicates Programmable Ratio Limits for
+/// Turbo mode is disabled.
+///
+UINT32  RatioLimit:1;
+///
+/// [Bit 29] Package. Programmable TDP Limit for Turbo Mode (R/O)  When
+/// set to 1, indicates that TDP Limits for Turbo mode are programmable,
+/// and when set to 0, indicates TDP Limit for Turbo mode is not
+/// programmable.
+///
+UINT32  TDPLimit:1;
+UINT32  Reserved3:2;
+///
+/// [Bit 32] Package. Low Power Mode Support (LPM) (R/O)  When set to 1,
+/// indicates that LPM is supported, and when set to 0, indicates LPM is
+/// not supported.
+///
+UINT32  LowPowerModeSupport:1;
+///
+/// [Bits 34:33] Package. Number of ConfigTDP Levels (R/O) 00: Only Base
+/// TDP level available. 01: One additional TDP level available. 02: Two
+/// additional TDP level available. 11: Reserved.
+///
+UINT32  ConfigTDPLevels:2;
+UINT32  Reserved4:5;
+///
+/// [Bits 47:40] Package. Maximum Efficiency Ratio (R/O)  The is the
+/// minimum ratio (maximum efficiency) that the processor can operates, in
+/// units of 100MHz.
+///
+UINT32  MaximumEfficiencyRatio:8;
+///
+/// [Bits 55:48] Package. Minimum Operating Ratio (R/O) Contains the
+/// minimum supported operating ratio in units of 100 MHz.
+///
+UINT32  MinimumOperatingRatio:8;
+UINT32  Reserved5:8;
+  } Bits;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_HASWELL_PLATFORM_INFO_REGISTER;
+
+
+/**
+  THREAD. Performance Event Select for Counter n (R/W) Supports all fields
+  described inTable 35-2 and the fields below.
+
+  @param  ECX  MSR_HASWELL_IA32_PERFEVTSELn
+  @param  EAX  Lower 32-bits of MSR value.
+   Described by the type MSR_HASWELL_IA32_PERFEVTSEL_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+   Described by the type MSR_HASWELL_IA32_PERFEVTSEL_REGISTER.
+
+  Example usag

[edk2] [Patch 15/21] UefiCpuPkg/Include: Add Xeon Phi MSR include file

[Michael Kinney]

Add Xeon Phi MSRs from:
Intel(R) 64 and IA-32 Architectures Software Developer's
Manual, Volume 3, December 2015, Chapter 35
Model-Specific-Registers (MSR), Section 35-15.

Cc: Jeff Fan 
Cc: Jiewen Yao 
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Michael Kinney 
---
 UefiCpuPkg/Include/Register/Msr/XeonPhiMsr.h | 1462 ++
 1 file changed, 1462 insertions(+)
 create mode 100644 UefiCpuPkg/Include/Register/Msr/XeonPhiMsr.h

diff --git a/UefiCpuPkg/Include/Register/Msr/XeonPhiMsr.h 
b/UefiCpuPkg/Include/Register/Msr/XeonPhiMsr.h
new file mode 100644
index 000..9ff60c2
--- /dev/null
+++ b/UefiCpuPkg/Include/Register/Msr/XeonPhiMsr.h
@@ -0,0 +1,1462 @@
+/** @file
+  MSR Defintions for Intel(R) Xeon(R) Phi(TM) processor Family.
+
+  Provides defines for Machine Specific Registers(MSR) indexes. Data structures
+  are provided for MSRs that contain one or more bit fields.  If the MSR value
+  returned is a single 32-bit or 64-bit value, then a data structure is not
+  provided for that MSR.
+
+  Copyright (c) 2016, Intel Corporation. All rights reserved.
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD 
License
+  which accompanies this distribution.  The full text of the license may be 
found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+  @par Specification Reference:
+  Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,
+  December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-15.
+
+**/
+
+#ifndef __XEON_PHI_MSR_H__
+#define __XEON_PHI_MSR_H__
+
+#include 
+
+/**
+  Thread. SMI Counter (R/O).
+
+  @param  ECX  MSR_XEON_PHI_SMI_COUNT (0x0034)
+  @param  EAX  Lower 32-bits of MSR value.
+   Described by the type MSR_XEON_PHI_SMI_COUNT_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+   Described by the type MSR_XEON_PHI_SMI_COUNT_REGISTER.
+
+  Example usage
+  @code
+  MSR_XEON_PHI_SMI_COUNT_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_SMI_COUNT);
+  @endcode
+**/
+#define MSR_XEON_PHI_SMI_COUNT   0x0034
+
+/**
+  MSR information returned for MSR index #MSR_XEON_PHI_SMI_COUNT
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+///
+/// [Bits 31:0] SMI Count (R/O).
+///
+UINT32  SMICount:32;
+UINT32  Reserved:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_XEON_PHI_SMI_COUNT_REGISTER;
+
+
+/**
+  Package. See http://biosbits.org.
+
+  @param  ECX  MSR_XEON_PHI_PLATFORM_INFO (0x00CE)
+  @param  EAX  Lower 32-bits of MSR value.
+   Described by the type MSR_XEON_PHI_PLATFORM_INFO_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+   Described by the type MSR_XEON_PHI_PLATFORM_INFO_REGISTER.
+
+  Example usage
+  @code
+  MSR_XEON_PHI_PLATFORM_INFO_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_PLATFORM_INFO);
+  AsmWriteMsr64 (MSR_XEON_PHI_PLATFORM_INFO, Msr.Uint64);
+  @endcode
+**/
+#define MSR_XEON_PHI_PLATFORM_INFO   0x00CE
+
+/**
+  MSR information returned for MSR index #MSR_XEON_PHI_PLATFORM_INFO
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+UINT32  Reserved1:8;
+///
+/// [Bits 15:8] Package. Maximum Non-Turbo Ratio (R/O)  The is the ratio
+/// of the frequency that invariant TSC runs at. Frequency = ratio * 100
+/// MHz.
+///
+UINT32  MaximumNonTurboRatio:8;
+UINT32  Reserved2:12;
+///
+/// [Bit 28] Package. Programmable Ratio Limit for Turbo Mode (R/O)  When
+/// set to 1, indicates that Programmable Ratio Limits for Turbo mode is
+/// enabled, and when set to 0, indicates Programmable Ratio Limits for
+/// Turbo mode is disabled.
+///
+UINT32  RatioLimit:1;
+///
+/// [Bit 29] Package. Programmable TDP Limit for Turbo Mode (R/O)  When
+/// set to 1, indicates that TDP Limits for Turbo mode are programmable,
+/// and when set to 0, indicates TDP Limit for Turbo mode is not
+/// programmable.
+///
+UINT32  TDPLimit:1;
+UINT32  Reserved3:2;
+UINT32  Reserved4:8;
+///
+/// [Bits 47:40] Package. Maximum Efficiency Ratio (R/O)  The is the
+/// minimum ratio (maximum efficiency) that the processor can operates, in
+/// units of 100MHz.
+///
+UINT32  MaximumEfficiencyRatio:8;
+UINT32  Reserved5:16;
+  } Bits;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_XEON_PHI_PLATFORM_INFO_REGISTER;
+
+
+/**
+  Module. C-State Configuration Control (R/W).
+
+  @param  ECX  MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL (0x00E2)
+

[edk2] [Patch 08/21] UefiCpuPkg/Include: Add Sandy Bridge MSR include file

[Michael Kinney]

Add Sandy Bridge MSRs from:
Intel(R) 64 and IA-32 Architectures Software Developer's
Manual, Volume 3, December 2015, Chapter 35
Model-Specific-Registers (MSR), Section 35-8.

Cc: Jeff Fan 
Cc: Jiewen Yao 
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Michael Kinney 
---
 UefiCpuPkg/Include/Register/Msr/SandyBridgeMsr.h | 4739 ++
 1 file changed, 4739 insertions(+)
 create mode 100644 UefiCpuPkg/Include/Register/Msr/SandyBridgeMsr.h

diff --git a/UefiCpuPkg/Include/Register/Msr/SandyBridgeMsr.h 
b/UefiCpuPkg/Include/Register/Msr/SandyBridgeMsr.h
new file mode 100644
index 000..9e99c2c
--- /dev/null
+++ b/UefiCpuPkg/Include/Register/Msr/SandyBridgeMsr.h
@@ -0,0 +1,4739 @@
+/** @file
+  MSR Defintions for Intel processors based on the Sandy Bridge 
microarchitecture.
+
+  Provides defines for Machine Specific Registers(MSR) indexes. Data structures
+  are provided for MSRs that contain one or more bit fields.  If the MSR value
+  returned is a single 32-bit or 64-bit value, then a data structure is not
+  provided for that MSR.
+
+  Copyright (c) 2016, Intel Corporation. All rights reserved.
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD 
License
+  which accompanies this distribution.  The full text of the license may be 
found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+  @par Specification Reference:
+  Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,
+  December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-8.
+
+**/
+
+#ifndef __SANDY_BRIDGE_MSR_H__
+#define __SANDY_BRIDGE_MSR_H__
+
+#include 
+
+/**
+  Thread. SMI Counter (R/O).
+
+  @param  ECX  MSR_SANDY_BRIDGE_SMI_COUNT (0x0034)
+  @param  EAX  Lower 32-bits of MSR value.
+   Described by the type MSR_SANDY_BRIDGE_SMI_COUNT_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+   Described by the type MSR_SANDY_BRIDGE_SMI_COUNT_REGISTER.
+
+  Example usage
+  @code
+  MSR_SANDY_BRIDGE_SMI_COUNT_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_SMI_COUNT);
+  @endcode
+**/
+#define MSR_SANDY_BRIDGE_SMI_COUNT   0x0034
+
+/**
+  MSR information returned for MSR index #MSR_SANDY_BRIDGE_SMI_COUNT
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+///
+/// [Bits 31:0] SMI Count (R/O) Count SMIs.
+///
+UINT32  SMICount:32;
+UINT32  Reserved:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_SANDY_BRIDGE_SMI_COUNT_REGISTER;
+
+
+/**
+  Package. See http://biosbits.org.
+
+  @param  ECX  MSR_SANDY_BRIDGE_PLATFORM_INFO (0x00CE)
+  @param  EAX  Lower 32-bits of MSR value.
+   Described by the type MSR_SANDY_BRIDGE_PLATFORM_INFO_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+   Described by the type MSR_SANDY_BRIDGE_PLATFORM_INFO_REGISTER.
+
+  Example usage
+  @code
+  MSR_SANDY_BRIDGE_PLATFORM_INFO_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_PLATFORM_INFO);
+  AsmWriteMsr64 (MSR_SANDY_BRIDGE_PLATFORM_INFO, Msr.Uint64);
+  @endcode
+**/
+#define MSR_SANDY_BRIDGE_PLATFORM_INFO   0x00CE
+
+/**
+  MSR information returned for MSR index #MSR_SANDY_BRIDGE_PLATFORM_INFO
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+UINT32  Reserved1:8;
+///
+/// [Bits 15:8] Package. Maximum Non-Turbo Ratio (R/O)  The is the ratio
+/// of the frequency that invariant TSC runs at. Frequency = ratio * 100
+/// MHz.
+///
+UINT32  MaximumNonTurboRatio:8;
+UINT32  Reserved2:12;
+///
+/// [Bit 28] Package. Programmable Ratio Limit for Turbo Mode (R/O)  When
+/// set to 1, indicates that Programmable Ratio Limits for Turbo mode is
+/// enabled, and when set to 0, indicates Programmable Ratio Limits for
+/// Turbo mode is disabled.
+///
+UINT32  RatioLimit:1;
+///
+/// [Bit 29] Package. Programmable TDP Limit for Turbo Mode (R/O)  When
+/// set to 1, indicates that TDP Limits for Turbo mode are programmable,
+/// and when set to 0, indicates TDP Limit for Turbo mode is not
+/// programmable.
+///
+UINT32  TDPLimit:1;
+UINT32  Reserved3:2;
+UINT32  Reserved4:8;
+///
+/// [Bits 47:40] Package. Maximum Efficiency Ratio (R/O)  The is the
+/// minimum ratio (maximum efficiency) that the processor can operates, in
+/// units of 100MHz.
+///
+UINT32  MaximumEfficiencyRatio:8;
+UINT32  Reserved5:16;
+  } Bits;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_SANDY_BRIDGE_PLATFORM_INFO_REGISTER;
+
+
+/**

[edk2] [Patch 12/21] UefiCpuPkg/Include: Add Broadwell MSR include file

[Michael Kinney]

Add Broadwell MSRs from:
Intel(R) 64 and IA-32 Architectures Software Developer's
Manual, Volume 3, December 2015, Chapter 35
Model-Specific-Registers (MSR), Section 35-12.

Cc: Jeff Fan 
Cc: Jiewen Yao 
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Michael Kinney 
---
 UefiCpuPkg/Include/Register/Msr/BroadwellMsr.h | 306 +
 1 file changed, 306 insertions(+)
 create mode 100644 UefiCpuPkg/Include/Register/Msr/BroadwellMsr.h

diff --git a/UefiCpuPkg/Include/Register/Msr/BroadwellMsr.h 
b/UefiCpuPkg/Include/Register/Msr/BroadwellMsr.h
new file mode 100644
index 000..44fe290
--- /dev/null
+++ b/UefiCpuPkg/Include/Register/Msr/BroadwellMsr.h
@@ -0,0 +1,306 @@
+/** @file
+  MSR Defintions for Intel processors based on the Broadwell microarchitecture.
+
+  Provides defines for Machine Specific Registers(MSR) indexes. Data structures
+  are provided for MSRs that contain one or more bit fields.  If the MSR value
+  returned is a single 32-bit or 64-bit value, then a data structure is not
+  provided for that MSR.
+
+  Copyright (c) 2016, Intel Corporation. All rights reserved.
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD 
License
+  which accompanies this distribution.  The full text of the license may be 
found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+  @par Specification Reference:
+  Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,
+  December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-12.
+
+**/
+
+#ifndef __BROADWELL_MSR_H__
+#define __BROADWELL_MSR_H__
+
+#include 
+
+/**
+  Thread. See Table 35-2. See Section 18.4.2, "Global Counter Control
+  Facilities.".
+
+  @param  ECX  MSR_BROADWELL_IA32_PERF_GLOBAL_STAUS (0x038E)
+  @param  EAX  Lower 32-bits of MSR value.
+   Described by the type 
MSR_BROADWELL_IA32_PERF_GLOBAL_STAUS_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+   Described by the type 
MSR_BROADWELL_IA32_PERF_GLOBAL_STAUS_REGISTER.
+
+  Example usage
+  @code
+  MSR_BROADWELL_IA32_PERF_GLOBAL_STAUS_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_BROADWELL_IA32_PERF_GLOBAL_STAUS);
+  AsmWriteMsr64 (MSR_BROADWELL_IA32_PERF_GLOBAL_STAUS, Msr.Uint64);
+  @endcode
+**/
+#define MSR_BROADWELL_IA32_PERF_GLOBAL_STAUS 0x038E
+
+/**
+  MSR information returned for MSR index #MSR_BROADWELL_IA32_PERF_GLOBAL_STAUS
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+///
+/// [Bit 0] Ovf_PMC0.
+///
+UINT32  Ovf_PMC0:1;
+///
+/// [Bit 1] Ovf_PMC1.
+///
+UINT32  Ovf_PMC1:1;
+///
+/// [Bit 2] Ovf_PMC2.
+///
+UINT32  Ovf_PMC2:1;
+///
+/// [Bit 3] Ovf_PMC3.
+///
+UINT32  Ovf_PMC3:1;
+UINT32  Reserved1:28;
+///
+/// [Bit 32] Ovf_FixedCtr0.
+///
+UINT32  Ovf_FixedCtr0:1;
+///
+/// [Bit 33] Ovf_FixedCtr1.
+///
+UINT32  Ovf_FixedCtr1:1;
+///
+/// [Bit 34] Ovf_FixedCtr2.
+///
+UINT32  Ovf_FixedCtr2:1;
+UINT32  Reserved2:20;
+///
+/// [Bit 55] Trace_ToPA_PMI. See Section 36.2.4.2, "Table of Physical
+/// Addresses (ToPA).".
+///
+UINT32  Trace_ToPA_PMI:1;
+UINT32  Reserved3:5;
+///
+/// [Bit 61] Ovf_Uncore.
+///
+UINT32  Ovf_Uncore:1;
+///
+/// [Bit 62] Ovf_BufDSSAVE.
+///
+UINT32  OvfBuf:1;
+///
+/// [Bit 63] CondChgd.
+///
+UINT32  CondChgd:1;
+  } Bits;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_BROADWELL_IA32_PERF_GLOBAL_STAUS_REGISTER;
+
+
+/**
+  Package. Uncore C-box 17 perfmon box wide status.
+
+  @param  ECX  MSR_BROADWELL_C17_PMON_BOX_STATUS (0x0F17)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  Example usage
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_BROADWELL_C17_PMON_BOX_STATUS);
+  AsmWriteMsr64 (MSR_BROADWELL_C17_PMON_BOX_STATUS, Msr);
+  @endcode
+**/
+#define MSR_BROADWELL_C17_PMON_BOX_STATUS0x0F17
+
+
+/**
+  Package. Uncore C-box 17 perfmon counter n.
+
+  @param  ECX  MSR_BROADWELL_C17_PMON_CTRn
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  Example usage
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_BROADWELL_C17_PMON_CTR0);
+  AsmWriteMsr64 (MSR_BROADWELL_C17_PMON_CTR0, Msr);
+  @endcode
+  @{
+**/
+#define MSR_BROADWELL_C17_PMON_CTR0  0x0F18
+#define MSR_BROADWELL_C17_PMON_CTR1  0x0F19
+#define MSR_BROADWELL_C17_PMON_CTR2  0x0F1A
+#define MSR_BROADWELL_C17_PMON_CTR3  0x0F1B
+/// @}
+
+
+/**
+  Core. C-State Configuration Control (R/W) Note: C-state values are processor
+  

[edk2] [Patch 14/21] UefiCpuPkg/Include: Add Skylake MSR include file

[Michael Kinney]

Add Skylake MSRs from:
Intel(R) 64 and IA-32 Architectures Software Developer's
Manual, Volume 3, December 2015, Chapter 35
Model-Specific-Registers (MSR), Section 35-14.

Cc: Jeff Fan 
Cc: Jiewen Yao 
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Michael Kinney 
---
 UefiCpuPkg/Include/Register/Msr/SkylakeMsr.h | 1008 ++
 1 file changed, 1008 insertions(+)
 create mode 100644 UefiCpuPkg/Include/Register/Msr/SkylakeMsr.h

diff --git a/UefiCpuPkg/Include/Register/Msr/SkylakeMsr.h 
b/UefiCpuPkg/Include/Register/Msr/SkylakeMsr.h
new file mode 100644
index 000..f2643be
--- /dev/null
+++ b/UefiCpuPkg/Include/Register/Msr/SkylakeMsr.h
@@ -0,0 +1,1008 @@
+/** @file
+  MSR Defintions for Intel processors based on the Skylake microarchitecture.
+
+  Provides defines for Machine Specific Registers(MSR) indexes. Data structures
+  are provided for MSRs that contain one or more bit fields.  If the MSR value
+  returned is a single 32-bit or 64-bit value, then a data structure is not
+  provided for that MSR.
+
+  Copyright (c) 2016, Intel Corporation. All rights reserved.
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD 
License
+  which accompanies this distribution.  The full text of the license may be 
found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+  @par Specification Reference:
+  Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,
+  December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-14.
+
+**/
+
+#ifndef __SKYLAKE_MSR_H__
+#define __SKYLAKE_MSR_H__
+
+#include 
+
+/**
+  Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0,
+  RW if MSR_PLATFORM_INFO.[28] = 1.
+
+  @param  ECX  MSR_SKYLAKE_TURBO_RATIO_LIMIT (0x01AD)
+  @param  EAX  Lower 32-bits of MSR value.
+   Described by the type MSR_SKYLAKE_TURBO_RATIO_LIMIT_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+   Described by the type MSR_SKYLAKE_TURBO_RATIO_LIMIT_REGISTER.
+
+  Example usage
+  @code
+  MSR_SKYLAKE_TURBO_RATIO_LIMIT_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_TURBO_RATIO_LIMIT);
+  @endcode
+**/
+#define MSR_SKYLAKE_TURBO_RATIO_LIMIT0x01AD
+
+/**
+  MSR information returned for MSR index #MSR_SKYLAKE_TURBO_RATIO_LIMIT
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+///
+/// [Bits 7:0] Package. Maximum Ratio Limit for 1C Maximum turbo ratio
+/// limit of 1 core active.
+///
+UINT32  Maximum1C:8;
+///
+/// [Bits 15:8] Package. Maximum Ratio Limit for 2C Maximum turbo ratio
+/// limit of 2 core active.
+///
+UINT32  Maximum2C:8;
+///
+/// [Bits 23:16] Package. Maximum Ratio Limit for 3C Maximum turbo ratio
+/// limit of 3 core active.
+///
+UINT32  Maximum3C:8;
+///
+/// [Bits 31:24] Package. Maximum Ratio Limit for 4C Maximum turbo ratio
+/// limit of 4 core active.
+///
+UINT32  Maximum4C:8;
+UINT32  Reserved:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_SKYLAKE_TURBO_RATIO_LIMIT_REGISTER;
+
+
+/**
+  Thread. Last Branch Record Stack TOS (R/W)  Contains an index (bits 0-4)
+  that points to the MSR containing the most recent branch record.
+
+  @param  ECX  MSR_SKYLAKE_LASTBRANCH_TOS (0x01C9)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  Example usage
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_SKYLAKE_LASTBRANCH_TOS);
+  AsmWriteMsr64 (MSR_SKYLAKE_LASTBRANCH_TOS, Msr);
+  @endcode
+**/
+#define MSR_SKYLAKE_LASTBRANCH_TOS   0x01C9
+
+
+/**
+  Package. Lower 64 Bit OwnerEpoch Component of SGX Key (RO). Low 64 bits of
+  an 128-bit external entropy value for key derivation of an enclave.
+
+  @param  ECX  MSR_SKYLAKE_SGXOWNER0 (0x0300)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  Example usage
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_SKYLAKE_SGXOWNER0);
+  @endcode
+**/
+#define MSR_SKYLAKE_SGXOWNER00x0300
+
+
+/**
+  Package. Upper 64 Bit OwnerEpoch Component of SGX Key (RO). Upper 64 bits of
+  an 128-bit external entropy value for key derivation of an enclave.
+
+  @param  ECX  MSR_SKYLAKE_SGXOWNER1 (0x0301)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  Example usage
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_SKYLAKE_SGXOWNER1);
+  @endcode
+**/
+#define MSR_SKYLAKE_SGXOWNER10x0301
+
+
+/**
+  See Table 35-2. See Section 18.2.2.3, "Full-Width 

[edk2] [Patch 16/21] UefiCpuPkg/Include: Add Pentium 4 MSR include file

[Michael Kinney]

Add Pentium 4 MSRs from:
Intel(R) 64 and IA-32 Architectures Software Developer's
Manual, Volume 3, December 2015, Chapter 35
Model-Specific-Registers (MSR), Section 35-16.

Cc: Jeff Fan 
Cc: Jiewen Yao 
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Michael Kinney 
---
 UefiCpuPkg/Include/Register/Msr/Pentium4Msr.h | 2568 +
 1 file changed, 2568 insertions(+)
 create mode 100644 UefiCpuPkg/Include/Register/Msr/Pentium4Msr.h

diff --git a/UefiCpuPkg/Include/Register/Msr/Pentium4Msr.h 
b/UefiCpuPkg/Include/Register/Msr/Pentium4Msr.h
new file mode 100644
index 000..ad641ec
--- /dev/null
+++ b/UefiCpuPkg/Include/Register/Msr/Pentium4Msr.h
@@ -0,0 +1,2568 @@
+/** @file
+  MSR Defintions for Pentium(R) 4 Processors.
+
+  Provides defines for Machine Specific Registers(MSR) indexes. Data structures
+  are provided for MSRs that contain one or more bit fields.  If the MSR value
+  returned is a single 32-bit or 64-bit value, then a data structure is not
+  provided for that MSR.
+
+  Copyright (c) 2016, Intel Corporation. All rights reserved.
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD 
License
+  which accompanies this distribution.  The full text of the license may be 
found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+  @par Specification Reference:
+  Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,
+  December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-16.
+
+**/
+
+#ifndef __PENTIUM_4_MSR_H__
+#define __PENTIUM_4_MSR_H__
+
+#include 
+
+/**
+  3, 4, 6. Shared. See Section 8.10.5, "Monitor/Mwait Address Range
+  Determination.".
+
+  @param  ECX  MSR_PENTIUM_4_IA32_MONITOR_FILTER_LINE_SIZE (0x0006)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  Example usage
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_PENTIUM_4_IA32_MONITOR_FILTER_LINE_SIZE);
+  AsmWriteMsr64 (MSR_PENTIUM_4_IA32_MONITOR_FILTER_LINE_SIZE, Msr);
+  @endcode
+**/
+#define MSR_PENTIUM_4_IA32_MONITOR_FILTER_LINE_SIZE 0x0006
+
+
+/**
+  0, 1, 2, 3, 4, 6. Shared. Processor Hard Power-On Configuration (R/W)
+  Enables and disables processor features; (R) indicates current processor
+  configuration.
+
+  @param  ECX  MSR_PENTIUM_4_EBC_HARD_POWERON (0x002A)
+  @param  EAX  Lower 32-bits of MSR value.
+   Described by the type MSR_PENTIUM_4_EBC_HARD_POWERON_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+   Described by the type MSR_PENTIUM_4_EBC_HARD_POWERON_REGISTER.
+
+  Example usage
+  @code
+  MSR_PENTIUM_4_EBC_HARD_POWERON_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_PENTIUM_4_EBC_HARD_POWERON);
+  AsmWriteMsr64 (MSR_PENTIUM_4_EBC_HARD_POWERON, Msr.Uint64);
+  @endcode
+**/
+#define MSR_PENTIUM_4_EBC_HARD_POWERON   0x002A
+
+/**
+  MSR information returned for MSR index #MSR_PENTIUM_4_EBC_HARD_POWERON
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+///
+/// [Bit 0] Output Tri-state Enabled (R) Indicates whether tri-state
+/// output is enabled (1) or disabled (0) as set by the strapping of SMI#.
+/// The value in this bit is written on the deassertion of RESET#; the bit
+/// is set to 1 when the address bus signal is asserted.
+///
+UINT32  OutputTriStateEnabled:1;
+///
+/// [Bit 1] Execute BIST (R)  Indicates whether the execution of the BIST
+/// is enabled (1) or disabled (0) as set by the strapping of INIT#. The
+/// value in this bit is written on the deassertion of RESET#; the bit is
+/// set to 1 when the address bus signal is asserted.
+///
+UINT32  ExecuteBIST:1;
+///
+/// [Bit 2] In Order Queue Depth (R) Indicates whether the in order queue
+/// depth for the system bus is 1 (1) or up to 12 (0) as set by the
+/// strapping of A7#. The value in this bit is written on the deassertion
+/// of RESET#; the bit is set to 1 when the address bus signal is asserted.
+///
+UINT32  InOrderQueueDepth:1;
+///
+/// [Bit 3] MCERR# Observation Disabled (R) Indicates whether MCERR#
+/// observation is enabled (0) or disabled (1) as determined by the
+/// strapping of A9#. The value in this bit is written on the deassertion
+/// of RESET#; the bit is set to 1 when the address bus signal is asserted.
+///
+UINT32  MCERR_ObservationDisabled:1;
+///
+/// [Bit 4] BINIT# Observation Enabled (R) Indicates whether BINIT#
+/// observation is enabled (0) or disabled (1) as determined by the
+/// strapping of A10#. The value in this bit is written on the deassertion
+/// of RESET#; the bit is set to 1 when the address bus signal is asserted.
+///
+ 

[edk2] [Patch 09/21] UefiCpuPkg/Include: Add Ivy Bridge MSR include file

[Michael Kinney]

Add Ivy Bridge MSRs from:
Intel(R) 64 and IA-32 Architectures Software Developer's
Manual, Volume 3, December 2015, Chapter 35
Model-Specific-Registers (MSR), Section 35-9.

Cc: Jeff Fan 
Cc: Jiewen Yao 
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Michael Kinney 
---
 UefiCpuPkg/Include/Register/Msr/IvyBridgeMsr.h | 2830 
 1 file changed, 2830 insertions(+)
 create mode 100644 UefiCpuPkg/Include/Register/Msr/IvyBridgeMsr.h

diff --git a/UefiCpuPkg/Include/Register/Msr/IvyBridgeMsr.h 
b/UefiCpuPkg/Include/Register/Msr/IvyBridgeMsr.h
new file mode 100644
index 000..615d480
--- /dev/null
+++ b/UefiCpuPkg/Include/Register/Msr/IvyBridgeMsr.h
@@ -0,0 +1,2830 @@
+/** @file
+  MSR Defintions for Intel processors based on the Ivy Bridge 
microarchitecture.
+
+  Provides defines for Machine Specific Registers(MSR) indexes. Data structures
+  are provided for MSRs that contain one or more bit fields.  If the MSR value
+  returned is a single 32-bit or 64-bit value, then a data structure is not
+  provided for that MSR.
+
+  Copyright (c) 2016, Intel Corporation. All rights reserved.
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD 
License
+  which accompanies this distribution.  The full text of the license may be 
found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+  @par Specification Reference:
+  Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,
+  December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-9.
+
+**/
+
+#ifndef __IVY_BRIDGE_MSR_H__
+#define __IVY_BRIDGE_MSR_H__
+
+#include 
+
+/**
+  Package. See http://biosbits.org.
+
+  @param  ECX  MSR_IVY_BRIDGE_PLATFORM_INFO (0x00CE)
+  @param  EAX  Lower 32-bits of MSR value.
+   Described by the type MSR_IVY_BRIDGE_PLATFORM_INFO_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+   Described by the type MSR_IVY_BRIDGE_PLATFORM_INFO_REGISTER.
+
+  Example usage
+  @code
+  MSR_IVY_BRIDGE_PLATFORM_INFO_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_PLATFORM_INFO);
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_PLATFORM_INFO, Msr.Uint64);
+  @endcode
+**/
+#define MSR_IVY_BRIDGE_PLATFORM_INFO 0x00CE
+
+/**
+  MSR information returned for MSR index #MSR_IVY_BRIDGE_PLATFORM_INFO
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+UINT32  Reserved1:8;
+///
+/// [Bits 15:8] Package. Maximum Non-Turbo Ratio (R/O)  The is the ratio
+/// of the frequency that invariant TSC runs at. Frequency = ratio * 100
+/// MHz.
+///
+UINT32  MaximumNonTurboRatio:8;
+UINT32  Reserved2:12;
+///
+/// [Bit 28] Package. Programmable Ratio Limit for Turbo Mode (R/O)  When
+/// set to 1, indicates that Programmable Ratio Limits for Turbo mode is
+/// enabled, and when set to 0, indicates Programmable Ratio Limits for
+/// Turbo mode is disabled.
+///
+UINT32  RatioLimit:1;
+///
+/// [Bit 29] Package. Programmable TDP Limit for Turbo Mode (R/O)  When
+/// set to 1, indicates that TDP Limits for Turbo mode are programmable,
+/// and when set to 0, indicates TDP Limit for Turbo mode is not
+/// programmable.
+///
+UINT32  TDPLimit:1;
+UINT32  Reserved3:2;
+///
+/// [Bit 32] Package. Low Power Mode Support (LPM) (R/O)  When set to 1,
+/// indicates that LPM is supported, and when set to 0, indicates LPM is
+/// not supported.
+///
+UINT32  LowPowerModeSupport:1;
+///
+/// [Bits 34:33] Package. Number of ConfigTDP Levels (R/O) 00: Only Base
+/// TDP level available. 01: One additional TDP level available. 02: Two
+/// additional TDP level available. 11: Reserved.
+///
+UINT32  ConfigTDPLevels:2;
+UINT32  Reserved4:5;
+///
+/// [Bits 47:40] Package. Maximum Efficiency Ratio (R/O)  The is the
+/// minimum ratio (maximum efficiency) that the processor can operates, in
+/// units of 100MHz.
+///
+UINT32  MaximumEfficiencyRatio:8;
+///
+/// [Bits 55:48] Package. Minimum Operating Ratio (R/O) Contains the
+/// minimum supported operating ratio in units of 100 MHz.
+///
+UINT32  MinimumOperatingRatio:8;
+UINT32  Reserved5:8;
+  } Bits;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_IVY_BRIDGE_PLATFORM_INFO_REGISTER;
+
+
+/**
+  Core. C-State Configuration Control (R/W)  Note: C-state values are
+  processor specific C-state code names, unrelated to MWAIT extension C-state
+  parameters or ACPI C-States. See http://biosbits.org.
+
+  @param  ECX  MSR_IVY_BRIDGE_PKG_CST_CONFIG_CONTROL (0x00E2)
+  @param  EAX  Lower 32-bits of MSR value.
+   Described by the type 
M

[edk2] [Patch 18/21] UefiCpuPkg/Include: Add Pentium M MSR include file

[Michael Kinney]

Add Pentium M MSRs from:
Intel(R) 64 and IA-32 Architectures Software Developer's
Manual, Volume 3, December 2015, Chapter 35
Model-Specific-Registers (MSR), Section 35-18.

Cc: Jeff Fan 
Cc: Jiewen Yao 
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Michael Kinney 
---
 UefiCpuPkg/Include/Register/Msr/PentiumMMsr.h | 638 ++
 1 file changed, 638 insertions(+)
 create mode 100644 UefiCpuPkg/Include/Register/Msr/PentiumMMsr.h

diff --git a/UefiCpuPkg/Include/Register/Msr/PentiumMMsr.h 
b/UefiCpuPkg/Include/Register/Msr/PentiumMMsr.h
new file mode 100644
index 000..cffec6b
--- /dev/null
+++ b/UefiCpuPkg/Include/Register/Msr/PentiumMMsr.h
@@ -0,0 +1,638 @@
+/** @file
+  MSR Defintions for Pentium M Processors.
+
+  Provides defines for Machine Specific Registers(MSR) indexes. Data structures
+  are provided for MSRs that contain one or more bit fields.  If the MSR value
+  returned is a single 32-bit or 64-bit value, then a data structure is not
+  provided for that MSR.
+
+  Copyright (c) 2016, Intel Corporation. All rights reserved.
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD 
License
+  which accompanies this distribution.  The full text of the license may be 
found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+  @par Specification Reference:
+  Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,
+  December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-18.
+
+**/
+
+#ifndef __PENTIUM_M_MSR_H__
+#define __PENTIUM_M_MSR_H__
+
+#include 
+
+/**
+  See Section 35.20, "MSRs in Pentium Processors.".
+
+  @param  ECX  MSR_PENTIUM_M_P5_MC_ADDR (0x)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  Example usage
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_PENTIUM_M_P5_MC_ADDR);
+  AsmWriteMsr64 (MSR_PENTIUM_M_P5_MC_ADDR, Msr);
+  @endcode
+**/
+#define MSR_PENTIUM_M_P5_MC_ADDR 0x
+
+
+/**
+  See Section 35.20, "MSRs in Pentium Processors.".
+
+  @param  ECX  MSR_PENTIUM_M_P5_MC_TYPE (0x0001)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  Example usage
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_PENTIUM_M_P5_MC_TYPE);
+  AsmWriteMsr64 (MSR_PENTIUM_M_P5_MC_TYPE, Msr);
+  @endcode
+**/
+#define MSR_PENTIUM_M_P5_MC_TYPE 0x0001
+
+
+/**
+  Processor Hard Power-On Configuration (R/W) Enables and disables processor
+  features. (R) Indicates current processor configuration.
+
+  @param  ECX  MSR_PENTIUM_M_EBL_CR_POWERON (0x002A)
+  @param  EAX  Lower 32-bits of MSR value.
+   Described by the type MSR_PENTIUM_M_EBL_CR_POWERON_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+   Described by the type MSR_PENTIUM_M_EBL_CR_POWERON_REGISTER.
+
+  Example usage
+  @code
+  MSR_PENTIUM_M_EBL_CR_POWERON_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_PENTIUM_M_EBL_CR_POWERON);
+  AsmWriteMsr64 (MSR_PENTIUM_M_EBL_CR_POWERON, Msr.Uint64);
+  @endcode
+**/
+#define MSR_PENTIUM_M_EBL_CR_POWERON 0x002A
+
+/**
+  MSR information returned for MSR index #MSR_PENTIUM_M_EBL_CR_POWERON
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+UINT32  Reserved1:1;
+///
+/// [Bit 1] Data Error Checking Enable (R) 0 = Disabled Always 0 on the
+/// Pentium M processor.
+///
+UINT32  DataErrorCheckingEnable:1;
+///
+/// [Bit 2] Response Error Checking Enable (R) 0 = Disabled Always 0 on
+/// the Pentium M processor.
+///
+UINT32  ResponseErrorCheckingEnable:1;
+///
+/// [Bit 3] MCERR# Drive Enable (R)  0 = Disabled Always 0 on the Pentium
+/// M processor.
+///
+UINT32  MCERR_DriveEnable:1;
+///
+/// [Bit 4] Address Parity Enable (R) 0 = Disabled Always 0 on the Pentium
+/// M processor.
+///
+UINT32  AddressParityEnable:1;
+UINT32  Reserved2:2;
+///
+/// [Bit 7] BINIT# Driver Enable (R) 1 = Enabled; 0 = Disabled Always 0 on
+/// the Pentium M processor.
+///
+UINT32  BINIT_DriverEnable:1;
+///
+/// [Bit 8] Output Tri-state Enabled (R/O) 1 = Enabled; 0 = Disabled.
+///
+UINT32  OutputTriStateEnable:1;
+///
+/// [Bit 9] Execute BIST (R/O) 1 = Enabled; 0 = Disabled.
+///
+UINT32  ExecuteBIST:1;
+///
+/// [Bit 10] MCERR# Observation Enabled (R/O) 1 = Enabled; 0 = Disabled
+/// Always 0 on the Pentium M processor.
+///
+UINT32  MCERR_ObservationEnabled:1;
+UINT32  Reserved3:1;
+///
+/// [Bit 12] BINIT# Observation Enabled (R/O) 1 = Enabled; 0 = Disabled
+/// Always 0 on the Pentium M processor.
+///
+UINT32

[edk2] [Patch 17/21] UefiCpuPkg/Include: Add Core Solo/Duo MSR include file

[Michael Kinney]

Add Core Solo/Duo MSRs from:
Intel(R) 64 and IA-32 Architectures Software Developer's
Manual, Volume 3, December 2015, Chapter 35
Model-Specific-Registers (MSR), Section 35-17.

Cc: Jeff Fan 
Cc: Jiewen Yao 
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Michael Kinney 
---
 UefiCpuPkg/Include/Register/Msr/CoreMsr.h | 1074 +
 1 file changed, 1074 insertions(+)
 create mode 100644 UefiCpuPkg/Include/Register/Msr/CoreMsr.h

diff --git a/UefiCpuPkg/Include/Register/Msr/CoreMsr.h 
b/UefiCpuPkg/Include/Register/Msr/CoreMsr.h
new file mode 100644
index 000..1f2660b
--- /dev/null
+++ b/UefiCpuPkg/Include/Register/Msr/CoreMsr.h
@@ -0,0 +1,1074 @@
+/** @file
+  MSR Defintions for Intel Core Solo and Intel Core Duo Processors.
+
+  Provides defines for Machine Specific Registers(MSR) indexes. Data structures
+  are provided for MSRs that contain one or more bit fields.  If the MSR value
+  returned is a single 32-bit or 64-bit value, then a data structure is not
+  provided for that MSR.
+
+  Copyright (c) 2016, Intel Corporation. All rights reserved.
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD 
License
+  which accompanies this distribution.  The full text of the license may be 
found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+  @par Specification Reference:
+  Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,
+  December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-17.
+
+**/
+
+#ifndef __CORE_MSR_H__
+#define __CORE_MSR_H__
+
+#include 
+
+/**
+  Unique. See Section 35.20, "MSRs in Pentium Processors," and see Table 35-2.
+
+  @param  ECX  MSR_CORE_P5_MC_ADDR (0x)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  Example usage
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_CORE_P5_MC_ADDR);
+  AsmWriteMsr64 (MSR_CORE_P5_MC_ADDR, Msr);
+  @endcode
+**/
+#define MSR_CORE_P5_MC_ADDR  0x
+
+
+/**
+  Unique. See Section 35.20, "MSRs in Pentium Processors," and see Table 35-2.
+
+  @param  ECX  MSR_CORE_P5_MC_TYPE (0x0001)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  Example usage
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_CORE_P5_MC_TYPE);
+  AsmWriteMsr64 (MSR_CORE_P5_MC_TYPE, Msr);
+  @endcode
+**/
+#define MSR_CORE_P5_MC_TYPE  0x0001
+
+
+/**
+  Shared. Processor Hard Power-On Configuration (R/W) Enables and disables
+  processor features; (R) indicates current processor configuration.
+
+  @param  ECX  MSR_CORE_EBL_CR_POWERON (0x002A)
+  @param  EAX  Lower 32-bits of MSR value.
+   Described by the type MSR_CORE_EBL_CR_POWERON_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+   Described by the type MSR_CORE_EBL_CR_POWERON_REGISTER.
+
+  Example usage
+  @code
+  MSR_CORE_EBL_CR_POWERON_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_CORE_EBL_CR_POWERON);
+  AsmWriteMsr64 (MSR_CORE_EBL_CR_POWERON, Msr.Uint64);
+  @endcode
+**/
+#define MSR_CORE_EBL_CR_POWERON  0x002A
+
+/**
+  MSR information returned for MSR index #MSR_CORE_EBL_CR_POWERON
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+UINT32  Reserved1:1;
+///
+/// [Bit 1] Data Error Checking Enable (R/W) 1 = Enabled; 0 = Disabled
+/// Note: Not all processor implements R/W.
+///
+UINT32  DataErrorCheckingEnable:1;
+///
+/// [Bit 2] Response Error Checking Enable (R/W) 1 = Enabled; 0 = Disabled
+/// Note: Not all processor implements R/W.
+///
+UINT32  ResponseErrorCheckingEnable:1;
+///
+/// [Bit 3] MCERR# Drive Enable (R/W)  1 = Enabled; 0 = Disabled Note: Not
+/// all processor implements R/W.
+///
+UINT32  MCERR_DriveEnable:1;
+///
+/// [Bit 4] Address Parity Enable (R/W) 1 = Enabled; 0 = Disabled Note:
+/// Not all processor implements R/W.
+///
+UINT32  AddressParityEnable:1;
+UINT32  Reserved2:2;
+///
+/// [Bit 7] BINIT# Driver Enable (R/W) 1 = Enabled; 0 = Disabled Note: Not
+/// all processor implements R/W.
+///
+UINT32  BINIT_DriverEnable:1;
+///
+/// [Bit 8] Output Tri-state Enabled (R/O) 1 = Enabled; 0 = Disabled.
+///
+UINT32  OutputTriStateEnable:1;
+///
+/// [Bit 9] Execute BIST (R/O) 1 = Enabled; 0 = Disabled.
+///
+UINT32  ExecuteBIST:1;
+///
+/// [Bit 10] MCERR# Observation Enabled (R/O) 1 = Enabled; 0 = Disabled.
+///
+UINT32  MCERR_ObservationEnabled:1;
+UINT32  Reserved3:1;
+///
+/// [Bit 12] BINIT# Observation Enabled (R/O) 1 = Enabled; 0 = Disabled.
+///
+UINT32  BINIT_Obs

[edk2] [Patch 07/21] UefiCpuPkg/Include: Add Xeon E7 MSR include file

[Michael Kinney]

Add Xeon E7 MSRs from:
Intel(R) 64 and IA-32 Architectures Software Developer's
Manual, Volume 3, December 2015, Chapter 35
Model-Specific-Registers (MSR), Section 35-7.

Cc: Jeff Fan 
Cc: Jiewen Yao 
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Michael Kinney 
---
 UefiCpuPkg/Include/Register/Msr/XeonE7Msr.h | 254 
 1 file changed, 254 insertions(+)
 create mode 100644 UefiCpuPkg/Include/Register/Msr/XeonE7Msr.h

diff --git a/UefiCpuPkg/Include/Register/Msr/XeonE7Msr.h 
b/UefiCpuPkg/Include/Register/Msr/XeonE7Msr.h
new file mode 100644
index 000..423c111
--- /dev/null
+++ b/UefiCpuPkg/Include/Register/Msr/XeonE7Msr.h
@@ -0,0 +1,254 @@
+/** @file
+  MSR Defintions for Intel(R) Xeon(R) Processor E7 Family.
+
+  Provides defines for Machine Specific Registers(MSR) indexes. Data structures
+  are provided for MSRs that contain one or more bit fields.  If the MSR value
+  returned is a single 32-bit or 64-bit value, then a data structure is not
+  provided for that MSR.
+
+  Copyright (c) 2016, Intel Corporation. All rights reserved.
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD 
License
+  which accompanies this distribution.  The full text of the license may be 
found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+  @par Specification Reference:
+  Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,
+  December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-7.
+
+**/
+
+#ifndef __XEON_E7_MSR_H__
+#define __XEON_E7_MSR_H__
+
+#include 
+
+/**
+  Package. Reserved Attempt to read/write will cause #UD.
+
+  @param  ECX  MSR_XEON_E7_TURBO_RATIO_LIMIT (0x01AD)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  Example usage
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_XEON_E7_TURBO_RATIO_LIMIT);
+  AsmWriteMsr64 (MSR_XEON_E7_TURBO_RATIO_LIMIT, Msr);
+  @endcode
+**/
+#define MSR_XEON_E7_TURBO_RATIO_LIMIT0x01AD
+
+
+/**
+  Package. Uncore C-box 8 perfmon local box control MSR.
+
+  @param  ECX  MSR_XEON_E7_C8_PMON_BOX_CTRL (0x0F40)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  Example usage
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_XEON_E7_C8_PMON_BOX_CTRL);
+  AsmWriteMsr64 (MSR_XEON_E7_C8_PMON_BOX_CTRL, Msr);
+  @endcode
+**/
+#define MSR_XEON_E7_C8_PMON_BOX_CTRL 0x0F40
+
+
+/**
+  Package. Uncore C-box 8 perfmon local box status MSR.
+
+  @param  ECX  MSR_XEON_E7_C8_PMON_BOX_STATUS (0x0F41)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  Example usage
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_XEON_E7_C8_PMON_BOX_STATUS);
+  AsmWriteMsr64 (MSR_XEON_E7_C8_PMON_BOX_STATUS, Msr);
+  @endcode
+**/
+#define MSR_XEON_E7_C8_PMON_BOX_STATUS   0x0F41
+
+
+/**
+  Package. Uncore C-box 8 perfmon local box overflow control MSR.
+
+  @param  ECX  MSR_XEON_E7_C8_PMON_BOX_OVF_CTRL (0x0F42)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  Example usage
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_XEON_E7_C8_PMON_BOX_OVF_CTRL);
+  AsmWriteMsr64 (MSR_XEON_E7_C8_PMON_BOX_OVF_CTRL, Msr);
+  @endcode
+**/
+#define MSR_XEON_E7_C8_PMON_BOX_OVF_CTRL 0x0F42
+
+
+/**
+  Package. Uncore C-box 8 perfmon event select MSR.
+
+  @param  ECX  MSR_XEON_E7_C8_PMON_EVNT_SELn
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  Example usage
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_XEON_E7_C8_PMON_EVNT_SEL0);
+  AsmWriteMsr64 (MSR_XEON_E7_C8_PMON_EVNT_SEL0, Msr);
+  @endcode
+  @{
+**/
+#define MSR_XEON_E7_C8_PMON_EVNT_SEL00x0F50
+#define MSR_XEON_E7_C8_PMON_EVNT_SEL10x0F52
+#define MSR_XEON_E7_C8_PMON_EVNT_SEL20x0F54
+#define MSR_XEON_E7_C8_PMON_EVNT_SEL30x0F56
+#define MSR_XEON_E7_C8_PMON_EVNT_SEL40x0F58
+#define MSR_XEON_E7_C8_PMON_EVNT_SEL50x0F5A
+/// @}
+
+
+/**
+  Package. Uncore C-box 8 perfmon counter MSR.
+
+  @param  ECX  MSR_XEON_E7_C8_PMON_CTRn
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  Example usage
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_XEON_E7_C8_PMON_CTR0);
+  AsmWriteMsr64 (MSR_XEON_E7_C8_PMON_CTR0, Msr);
+  @endcode
+  @{
+**/
+#define MSR_XEON_E7_C8_PMON_CTR0 0x0F51
+#define MSR_XEON_E7_C8_PMON_CTR1 0x0F53
+#define MSR_XEON_E7_C8_PMON_CTR2 0x0F55
+#define MSR_XEON_E7_C8_PMON_CTR3 0x0F57
+#define MSR_XEON_E7_C8_PMON_CTR4

[edk2] [Patch 02/21] UefiCpuPkg/Include: Add Core 2 MSR include file

[Michael Kinney]

Add Core 2 MSRs from:
Intel(R) 64 and IA-32 Architectures Software Developer's
Manual, Volume 3, December 2015, Chapter 35
Model-Specific-Registers (MSR), Section 35-2.

Cc: Jeff Fan 
Cc: Jiewen Yao 
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Michael Kinney 
---
 UefiCpuPkg/Include/Register/Msr/Core2Msr.h | 1343 
 1 file changed, 1343 insertions(+)
 create mode 100644 UefiCpuPkg/Include/Register/Msr/Core2Msr.h

diff --git a/UefiCpuPkg/Include/Register/Msr/Core2Msr.h 
b/UefiCpuPkg/Include/Register/Msr/Core2Msr.h
new file mode 100644
index 000..b1bd58b
--- /dev/null
+++ b/UefiCpuPkg/Include/Register/Msr/Core2Msr.h
@@ -0,0 +1,1343 @@
+/** @file
+   MSR Defintions for the Intel(R) Core(TM) 2 Processor Family.
+
+  Provides defines for Machine Specific Registers(MSR) indexes. Data structures
+  are provided for MSRs that contain one or more bit fields.  If the MSR value
+  returned is a single 32-bit or 64-bit value, then a data structure is not
+  provided for that MSR.
+
+  Copyright (c) 2016, Intel Corporation. All rights reserved.
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD 
License
+  which accompanies this distribution.  The full text of the license may be 
found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+  @par Specification Reference:
+  Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,
+  December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-2.
+
+**/
+
+#ifndef __CORE2_MSR_H__
+#define __CORE2_MSR_H__
+
+#include 
+
+/**
+  Shared. Model Specific Platform ID (R).
+
+  @param  ECX  MSR_CORE2_PLATFORM_ID (0x0017)
+  @param  EAX  Lower 32-bits of MSR value.
+   Described by the type MSR_CORE2_PLATFORM_ID_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+   Described by the type MSR_CORE2_PLATFORM_ID_REGISTER.
+
+  Example usage
+  @code
+  MSR_CORE2_PLATFORM_ID_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_CORE2_PLATFORM_ID);
+  @endcode
+**/
+#define MSR_CORE2_PLATFORM_ID0x0017
+
+/**
+  MSR information returned for MSR index #MSR_CORE2_PLATFORM_ID
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+UINT32  Reserved1:8;
+///
+/// [Bits 12:8] Maximum Qualified Ratio (R)  The maximum allowed bus ratio.
+///
+UINT32  MaximumQualifiedRatio:5;
+UINT32  Reserved2:19;
+UINT32  Reserved3:18;
+///
+/// [Bits 52:50] See Table 35-2.
+///
+UINT32  PlatformId:3;
+UINT32  Reserved4:11;
+  } Bits;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_CORE2_PLATFORM_ID_REGISTER;
+
+
+/**
+  Shared. Processor Hard Power-On Configuration (R/W) Enables and disables
+  processor features; (R) indicates current processor configuration.
+
+  @param  ECX  MSR_CORE2_EBL_CR_POWERON (0x002A)
+  @param  EAX  Lower 32-bits of MSR value.
+   Described by the type MSR_CORE2_EBL_CR_POWERON_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+   Described by the type MSR_CORE2_EBL_CR_POWERON_REGISTER.
+
+  Example usage
+  @code
+  MSR_CORE2_EBL_CR_POWERON_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_CORE2_EBL_CR_POWERON);
+  AsmWriteMsr64 (MSR_CORE2_EBL_CR_POWERON, Msr.Uint64);
+  @endcode
+**/
+#define MSR_CORE2_EBL_CR_POWERON 0x002A
+
+/**
+  MSR information returned for MSR index #MSR_CORE2_EBL_CR_POWERON
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+UINT32  Reserved1:1;
+///
+/// [Bit 1] Data Error Checking Enable (R/W) 1 = Enabled; 0 = Disabled
+/// Note: Not all processor implements R/W.
+///
+UINT32  DataErrorCheckingEnable:1;
+///
+/// [Bit 2] Response Error Checking Enable (R/W) 1 = Enabled; 0 = Disabled
+/// Note: Not all processor implements R/W.
+///
+UINT32  ResponseErrorCheckingEnable:1;
+///
+/// [Bit 3] MCERR# Drive Enable (R/W)  1 = Enabled; 0 = Disabled Note: Not
+/// all processor implements R/W.
+///
+UINT32  MCERR_DriveEnable:1;
+///
+/// [Bit 4] Address Parity Enable (R/W) 1 = Enabled; 0 = Disabled Note:
+/// Not all processor implements R/W.
+///
+UINT32  AddressParityEnable:1;
+UINT32  Reserved2:1;
+UINT32  Reserved3:1;
+///
+/// [Bit 7] BINIT# Driver Enable (R/W) 1 = Enabled; 0 = Disabled Note: Not
+/// all processor implements R/W.
+///
+UINT32  BINIT_DriverEnable:1;
+///
+/// [Bit 8] Output Tri-state Enabled (R/O) 1 = Enabled; 0 = Disabled.
+///
+UINT32  OutputTriStateEnable:1;
+///
+/// [Bit 9] Execute BIST (R/O) 1 = Enabled; 0 = Disabled.
+///
+UINT32  ExecuteBIST:1;
+///

[edk2] [Patch 00/21] UefiCpuPkg/Include: Add MSR include files

[Michael Kinney]

Add include files for Architectural MSRs and family specific 
MSRs described in section 35.1 to 35.20 of the 
Intel(R) 64 and IA-32 Architectures Software Developer's
Manual, Volume 3, December 2015, Chapter 35
Model-Specific-Registers (MSR).

These files can also be pulled and reviewd from:

https://github.com/mdkinney/edk2/tree/Msr

These includes files are not being used by any modules or 
libraries yet, so adding these .h files should not have any
impact on any build.  

I have tested that these include files do not cause any
build failures when used in UefiCPuPkg/Application/Cpuid.

These include files are being added so the defines and 
REGISTER structures can be used clean up IA32/X64 CPU 
modules and libraries that access MSRs.

Cc: Jeff Fan 
Cc: Jiewen Yao 
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Michael Kinney 

Michael Kinney (21):
  UefiCpuPkg/Include: Add Architectural MSR include file
  UefiCpuPkg/Include: Add Core 2 MSR include file
  UefiCpuPkg/Include: Add Atom MSR include file
  UefiCpuPkg/Include: Add Silvermont MSR include file
  UefiCpuPkg/Include: Add Nehalem MSR include file
  UefiCpuPkg/Include: Add Xeon 5600 MSR include file
  UefiCpuPkg/Include: Add Xeon E7 MSR include file
  UefiCpuPkg/Include: Add Sandy Bridge MSR include file
  UefiCpuPkg/Include: Add Ivy Bridge MSR include file
  UefiCpuPkg/Include: Add Haswell MSR include file
  UefiCpuPkg/Include: Add Haswell-E MSR include file
  UefiCpuPkg/Include: Add Broadwell MSR include file
  UefiCpuPkg/Include: Add Xeon Processor D MSR include file
  UefiCpuPkg/Include: Add Skylake MSR include file
  UefiCpuPkg/Include: Add Xeon Phi MSR include file
  UefiCpuPkg/Include: Add Pentium 4 MSR include file
  UefiCpuPkg/Include: Add Core Solo/Duo MSR include file
  UefiCpuPkg/Include: Add Pentium M MSR include file
  UefiCpuPkg/Include: Add P6 MSR include file
  UefiCpuPkg/Include: Add Pentium MSR include file
  UefiCpuPkg/Include: Add top level MSR include file

 UefiCpuPkg/Include/Register/ArchitecturalMsr.h   | 5801 +
 UefiCpuPkg/Include/Register/Msr.h|   48 +
 UefiCpuPkg/Include/Register/Msr/AtomMsr.h|  896 +++
 UefiCpuPkg/Include/Register/Msr/BroadwellMsr.h   |  306 +
 UefiCpuPkg/Include/Register/Msr/Core2Msr.h   | 1343 
 UefiCpuPkg/Include/Register/Msr/CoreMsr.h| 1074 
 UefiCpuPkg/Include/Register/Msr/HaswellEMsr.h| 5955 ++
 UefiCpuPkg/Include/Register/Msr/HaswellMsr.h | 2575 
 UefiCpuPkg/Include/Register/Msr/IvyBridgeMsr.h   | 2830 +
 UefiCpuPkg/Include/Register/Msr/NehalemMsr.h | 7214 ++
 UefiCpuPkg/Include/Register/Msr/P6Msr.h  | 1608 +
 UefiCpuPkg/Include/Register/Msr/Pentium4Msr.h| 2568 
 UefiCpuPkg/Include/Register/Msr/PentiumMMsr.h|  638 ++
 UefiCpuPkg/Include/Register/Msr/PentiumMsr.h |  121 +
 UefiCpuPkg/Include/Register/Msr/SandyBridgeMsr.h | 4739 ++
 UefiCpuPkg/Include/Register/Msr/SilvermontMsr.h  | 1486 +
 UefiCpuPkg/Include/Register/Msr/SkylakeMsr.h | 1008 +++
 UefiCpuPkg/Include/Register/Msr/Xeon5600Msr.h|  182 +
 UefiCpuPkg/Include/Register/Msr/XeonDMsr.h   | 1431 +
 UefiCpuPkg/Include/Register/Msr/XeonE7Msr.h  |  254 +
 UefiCpuPkg/Include/Register/Msr/XeonPhiMsr.h | 1462 +
 21 files changed, 43539 insertions(+)
 create mode 100644 UefiCpuPkg/Include/Register/ArchitecturalMsr.h
 create mode 100644 UefiCpuPkg/Include/Register/Msr.h
 create mode 100644 UefiCpuPkg/Include/Register/Msr/AtomMsr.h
 create mode 100644 UefiCpuPkg/Include/Register/Msr/BroadwellMsr.h
 create mode 100644 UefiCpuPkg/Include/Register/Msr/Core2Msr.h
 create mode 100644 UefiCpuPkg/Include/Register/Msr/CoreMsr.h
 create mode 100644 UefiCpuPkg/Include/Register/Msr/HaswellEMsr.h
 create mode 100644 UefiCpuPkg/Include/Register/Msr/HaswellMsr.h
 create mode 100644 UefiCpuPkg/Include/Register/Msr/IvyBridgeMsr.h
 create mode 100644 UefiCpuPkg/Include/Register/Msr/NehalemMsr.h
 create mode 100644 UefiCpuPkg/Include/Register/Msr/P6Msr.h
 create mode 100644 UefiCpuPkg/Include/Register/Msr/Pentium4Msr.h
 create mode 100644 UefiCpuPkg/Include/Register/Msr/PentiumMMsr.h
 create mode 100644 UefiCpuPkg/Include/Register/Msr/PentiumMsr.h
 create mode 100644 UefiCpuPkg/Include/Register/Msr/SandyBridgeMsr.h
 create mode 100644 UefiCpuPkg/Include/Register/Msr/SilvermontMsr.h
 create mode 100644 UefiCpuPkg/Include/Register/Msr/SkylakeMsr.h
 create mode 100644 UefiCpuPkg/Include/Register/Msr/Xeon5600Msr.h
 create mode 100644 UefiCpuPkg/Include/Register/Msr/XeonDMsr.h
 create mode 100644 UefiCpuPkg/Include/Register/Msr/XeonE7Msr.h
 create mode 100644 UefiCpuPkg/Include/Register/Msr/XeonPhiMsr.h

-- 
2.6.3.windows.1

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[edk2] [Patch 04/21] UefiCpuPkg/Include: Add Silvermont MSR include file

[Michael Kinney]

Add Silvermont MSRs from:
Intel(R) 64 and IA-32 Architectures Software Developer's
Manual, Volume 3, December 2015, Chapter 35
Model-Specific-Registers (MSR), Section 35-4.

Cc: Jeff Fan 
Cc: Jiewen Yao 
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Michael Kinney 
---
 UefiCpuPkg/Include/Register/Msr/SilvermontMsr.h | 1486 +++
 1 file changed, 1486 insertions(+)
 create mode 100644 UefiCpuPkg/Include/Register/Msr/SilvermontMsr.h

diff --git a/UefiCpuPkg/Include/Register/Msr/SilvermontMsr.h 
b/UefiCpuPkg/Include/Register/Msr/SilvermontMsr.h
new file mode 100644
index 000..71fb123
--- /dev/null
+++ b/UefiCpuPkg/Include/Register/Msr/SilvermontMsr.h
@@ -0,0 +1,1486 @@
+/** @file
+  MSR Defintions for Intel processors based on the Silvermont 
microarchitecture.
+
+  Provides defines for Machine Specific Registers(MSR) indexes. Data structures
+  are provided for MSRs that contain one or more bit fields.  If the MSR value
+  returned is a single 32-bit or 64-bit value, then a data structure is not
+  provided for that MSR.
+
+  Copyright (c) 2016, Intel Corporation. All rights reserved.
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD 
License
+  which accompanies this distribution.  The full text of the license may be 
found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+  @par Specification Reference:
+  Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,
+  December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-4.
+
+**/
+
+#ifndef __SILVERMONT_MSR_H__
+#define __SILVERMONT_MSR_H__
+
+#include 
+
+/**
+  Shared. Model Specific Platform ID (R).
+
+  @param  ECX  MSR_SILVERMONT_PLATFORM_ID (0x0017)
+  @param  EAX  Lower 32-bits of MSR value.
+   Described by the type MSR_SILVERMONT_PLATFORM_ID_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+   Described by the type MSR_SILVERMONT_PLATFORM_ID_REGISTER.
+
+  Example usage
+  @code
+  MSR_SILVERMONT_PLATFORM_ID_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_PLATFORM_ID);
+  @endcode
+**/
+#define MSR_SILVERMONT_PLATFORM_ID   0x0017
+
+/**
+  MSR information returned for MSR index #MSR_SILVERMONT_PLATFORM_ID
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+UINT32  Reserved1:8;
+///
+/// [Bits 12:8] Maximum Qualified Ratio (R)  The maximum allowed bus ratio.
+///
+UINT32  MaximumQualifiedRatio:5;
+UINT32  Reserved2:19;
+UINT32  Reserved3:18;
+///
+/// [Bits 52:50] See Table 35-2.
+///
+UINT32  PlatformId:3;
+UINT32  Reserved4:11;
+  } Bits;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_SILVERMONT_PLATFORM_ID_REGISTER;
+
+
+/**
+  Shared. Processor Hard Power-On Configuration (R/W) Enables and disables
+  processor features; (R) indicates current processor configuration.
+
+  @param  ECX  MSR_SILVERMONT_EBL_CR_POWERON (0x002A)
+  @param  EAX  Lower 32-bits of MSR value.
+   Described by the type MSR_SILVERMONT_EBL_CR_POWERON_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+   Described by the type MSR_SILVERMONT_EBL_CR_POWERON_REGISTER.
+
+  Example usage
+  @code
+  MSR_SILVERMONT_EBL_CR_POWERON_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_EBL_CR_POWERON);
+  AsmWriteMsr64 (MSR_SILVERMONT_EBL_CR_POWERON, Msr.Uint64);
+  @endcode
+**/
+#define MSR_SILVERMONT_EBL_CR_POWERON0x002A
+
+/**
+  MSR information returned for MSR index #MSR_SILVERMONT_EBL_CR_POWERON
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+UINT32  Reserved1:1;
+///
+/// [Bit 1] Data Error Checking Enable (R/W) 1 = Enabled; 0 = Disabled
+/// Always 0.
+///
+UINT32  DataErrorCheckingEnable:1;
+///
+/// [Bit 2] Response Error Checking Enable (R/W) 1 = Enabled; 0 = Disabled
+/// Always 0.
+///
+UINT32  ResponseErrorCheckingEnable:1;
+///
+/// [Bit 3] AERR# Drive Enable (R/W)  1 = Enabled; 0 = Disabled Always 0.
+///
+UINT32  AERR_DriveEnable:1;
+///
+/// [Bit 4] BERR# Enable for initiator bus requests (R/W) 1 = Enabled; 0 =
+/// Disabled Always 0.
+///
+UINT32  BERR_Enable:1;
+UINT32  Reserved2:1;
+UINT32  Reserved3:1;
+///
+/// [Bit 7] BINIT# Driver Enable (R/W) 1 = Enabled; 0 = Disabled Always 0.
+///
+UINT32  BINIT_DriverEnable:1;
+UINT32  Reserved4:1;
+///
+/// [Bit 9] Execute BIST (R/O) 1 = Enabled; 0 = Disabled.
+///
+UINT32  ExecuteBIST:1;
+///
+/// [Bit 10] AERR# Observation Enabled (R/O) 1 = Enabled; 0 = Disabled
+/// Always 0.
+///
+UINT32  AERR_ObservationEnabled:1

[edk2] Update UDK2014 to UDK2015 leads to setup page slow

[wang xiaofeng]

Hi Edk2 developers,
   After upate to UDK2015 from UDk2014, the Uiapp setup shows very slow. the 
following is our issue and debug information. Anyone meet similar issue before?
 

Issue symptom:

1, System draw the Front Page cost about 2 second. We can see the frame/ menu 
block/ help block draw one by one. Other submenu has same slowly display when 
enter it.

Normally those are instantaneous  work .

2, Change the highlight item in one page meet about half-second delay response.

3, In Data and time page. We can see the scan line to update the time display 
from top-left to bottom-right.

4, In shell environment, “drivers” command can show title part normally, but it 
display the number of driver with a visible slow speed. ”PCI” command still has 
normal behave.




Debug step:

1, Doubt that call back function hook to the form will case this issue .Try to 
remove the callback function for all the form.

Issue still happened.

2. Because the setup has may loop invoke, Try to fixed a single delay point for 
more debug.

In “DisplayPageFrame” when try to clear the screen for First Form display , 
there is about 1-2 second single delay point inside

ClearLines (0, gScreenDimensions.RightColumn, 0, gScreenDimensions.BottomRow, 
KEYHELP_BACKGROUND);  

Trace the string passed to clear screen in this routing .The string is same 
with the UDK2014 normal case. This can preliminary exclusion the string 
analysis issue and special font issue.

3,  Deep debug, Delay is happened in “PrintInternal” try to invoke 
”Out->OutputString(XX)”.

This Out is point to system table  conout , There is only one SimpleTextOutput  
“GraphicsConsoleController” in consplitter list in our project.

 And the GOP protocol install  optrom in both UDK2014 and UDK2015 are the 
same one. BTW, The logo display and post information display has no delay 
symptom.

4, There is  three ”Out->OutputString(XX)” invoke “PrintInternal”, String 
is display by first two after remove the CHAR type. the last invoke is used for 
display space to meet the request display size.

If we don’t do this work. Symptom 2 Will have a great improvement.
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Re: [edk2] [Patch] UefiCpuPkg/Application/Cpuid: Remove unnecessary code check

[Qiu, Shumin]

Reviewed-by: Qiu Shumin 

-Original Message-
From: Fan, Jeff 
Sent: Wednesday, March 09, 2016 10:17 AM
To: edk2-devel@lists.01.org
Cc: Qiu, Shumin; Kinney, Michael D
Subject: [Patch] UefiCpuPkg/Application/Cpuid: Remove unnecessary code check

gMaximumBasicFunction is set to CPUID_SIGNATURE as below, so removed the 
compare code.
UINT32  gMaximumBasicFunction = CPUID_SIGNATURE;

Cc: Qiu Shumin 
Cc: Michael Kinney 
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan 
---
 UefiCpuPkg/Application/Cpuid/Cpuid.c | 4 
 1 file changed, 4 deletions(-)

diff --git a/UefiCpuPkg/Application/Cpuid/Cpuid.c 
b/UefiCpuPkg/Application/Cpuid/Cpuid.c
index f5268cd..b0624e1 100644
--- a/UefiCpuPkg/Application/Cpuid/Cpuid.c
+++ b/UefiCpuPkg/Application/Cpuid/Cpuid.c
@@ -179,10 +179,6 @@ CpuidSignature (
   UINT32 Edx;
   CHAR8  Signature[13];
 
-  if (CPUID_SIGNATURE > gMaximumBasicFunction) {
-return;
-  }
-
   AsmCpuid (CPUID_SIGNATURE, &Eax, &Ebx, &Ecx, &Edx);
 
   Print (L"CPUID_SIGNATURE (Leaf %08x)\n", CPUID_SIGNATURE);
-- 
1.9.5.msysgit.0

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Re: [edk2] [Patch] UefiCpuPkg/Application/Cpuid: Add check for gMaximumBasicFunction

[Qiu, Shumin]

Reviewed-by: Qiu Shumin 

-Original Message-
From: Fan, Jeff 
Sent: Wednesday, March 09, 2016 10:17 AM
To: edk2-devel@lists.01.org
Cc: Qiu, Shumin; Kinney, Michael D
Subject: [Patch] UefiCpuPkg/Application/Cpuid: Add check for 
gMaximumBasicFunction

Add check for gMaximumBasicFunction in CpuidVersionInfo () back.

Cc: Qiu Shumin 
Cc: Michael Kinney 
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan 
---
 UefiCpuPkg/Application/Cpuid/Cpuid.c | 4 
 1 file changed, 4 insertions(+)

diff --git a/UefiCpuPkg/Application/Cpuid/Cpuid.c 
b/UefiCpuPkg/Application/Cpuid/Cpuid.c
index 371df66..f5268cd 100644
--- a/UefiCpuPkg/Application/Cpuid/Cpuid.c
+++ b/UefiCpuPkg/Application/Cpuid/Cpuid.c
@@ -213,6 +213,10 @@ CpuidVersionInfo (
   UINT32  DisplayFamily;
   UINT32  DisplayModel;
 
+  if (CPUID_VERSION_INFO > gMaximumBasicFunction) {
+return;
+  }
+
   AsmCpuid (CPUID_VERSION_INFO, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, 
&Edx.Uint32);
 
   Print (L"CPUID_VERSION_INFO (Leaf %08x)\n", CPUID_VERSION_INFO);
-- 
1.9.5.msysgit.0

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[edk2] [Patch] UefiCpuPkg/Application/Cpuid: Remove unnecessary code check

[Jeff Fan]

gMaximumBasicFunction is set to CPUID_SIGNATURE as below, so removed the 
compare code.
UINT32  gMaximumBasicFunction = CPUID_SIGNATURE;

Cc: Qiu Shumin 
Cc: Michael Kinney 
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan 
---
 UefiCpuPkg/Application/Cpuid/Cpuid.c | 4 
 1 file changed, 4 deletions(-)

diff --git a/UefiCpuPkg/Application/Cpuid/Cpuid.c 
b/UefiCpuPkg/Application/Cpuid/Cpuid.c
index f5268cd..b0624e1 100644
--- a/UefiCpuPkg/Application/Cpuid/Cpuid.c
+++ b/UefiCpuPkg/Application/Cpuid/Cpuid.c
@@ -179,10 +179,6 @@ CpuidSignature (
   UINT32 Edx;
   CHAR8  Signature[13];
 
-  if (CPUID_SIGNATURE > gMaximumBasicFunction) {
-return;
-  }
-
   AsmCpuid (CPUID_SIGNATURE, &Eax, &Ebx, &Ecx, &Edx);
 
   Print (L"CPUID_SIGNATURE (Leaf %08x)\n", CPUID_SIGNATURE);
-- 
1.9.5.msysgit.0

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[edk2] [Patch] UefiCpuPkg/Application/Cpuid: Add check for gMaximumBasicFunction

[Jeff Fan]

Add check for gMaximumBasicFunction in CpuidVersionInfo () back.

Cc: Qiu Shumin 
Cc: Michael Kinney 
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan 
---
 UefiCpuPkg/Application/Cpuid/Cpuid.c | 4 
 1 file changed, 4 insertions(+)

diff --git a/UefiCpuPkg/Application/Cpuid/Cpuid.c 
b/UefiCpuPkg/Application/Cpuid/Cpuid.c
index 371df66..f5268cd 100644
--- a/UefiCpuPkg/Application/Cpuid/Cpuid.c
+++ b/UefiCpuPkg/Application/Cpuid/Cpuid.c
@@ -213,6 +213,10 @@ CpuidVersionInfo (
   UINT32  DisplayFamily;
   UINT32  DisplayModel;
 
+  if (CPUID_VERSION_INFO > gMaximumBasicFunction) {
+return;
+  }
+
   AsmCpuid (CPUID_VERSION_INFO, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, 
&Edx.Uint32);
 
   Print (L"CPUID_VERSION_INFO (Leaf %08x)\n", CPUID_VERSION_INFO);
-- 
1.9.5.msysgit.0

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[edk2] [Patch] BaseTools: Change source files to DOS format.

[Yonghong Zhu]

From: Liming Gao 

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Liming Gao 
---
 BaseTools/Source/C/BootSectImage/bootsectimage.c  | 14 +++---
 BaseTools/Source/C/EfiLdrImage/EfiLdrImage.c  | 18 +-
 BaseTools/Source/C/Split/Split.c  | 14 +++---
 BaseTools/Source/C/VfrCompile/VfrCompiler.cpp |  8 
 BaseTools/Source/C/VfrCompile/VfrCompiler.h   |  4 ++--
 BaseTools/Source/C/VolInfo/VolInfo.c  | 12 ++--
 BaseTools/Source/Python/BPDG/BPDG.py  |  6 +++---
 BaseTools/Source/Python/BPDG/StringTable.py   | 14 +++---
 BaseTools/Source/Python/Ecc/Ecc.py| 10 +-
 BaseTools/Source/Python/UPT/Logger/StringTable.py |  6 +++---
 BaseTools/Source/Python/UPT/UPT.py|  4 ++--
 11 files changed, 55 insertions(+), 55 deletions(-)

diff --git a/BaseTools/Source/C/BootSectImage/bootsectimage.c 
b/BaseTools/Source/C/BootSectImage/bootsectimage.c
index 453a463..4f876ae 100644
--- a/BaseTools/Source/C/BootSectImage/bootsectimage.c
+++ b/BaseTools/Source/C/BootSectImage/bootsectimage.c
@@ -4,7 +4,7 @@ Abstract:
   Patch the BPB information in boot sector image file.
   Patch the MBR code in MBR image file.
 
-Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.
+Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.
 This program and the accompanying materials  
 are licensed and made available under the terms and conditions of the BSD 
License 
 which accompanies this distribution.  The full text of the license may be 
found at
@@ -33,8 +33,8 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER 
EXPRESS OR IMPLIED.
 //
 // Utility version information
 //
-#define UTILITY_MAJOR_VERSION 1
-#define UTILITY_MINOR_VERSION 0
+#define UTILITY_MAJOR_VERSION 1
+#define UTILITY_MINOR_VERSION 0
 
 void
 Version (
@@ -56,7 +56,7 @@ Returns:
 
 --*/
 {
-  printf ("%s Version %d.%d Build %s\n", UTILITY_NAME, UTILITY_MAJOR_VERSION, 
UTILITY_MINOR_VERSION, __BUILD_VERSION);
+  printf ("%s Version %d.%d Build %s\n", UTILITY_NAME, UTILITY_MAJOR_VERSION, 
UTILITY_MINOR_VERSION, __BUILD_VERSION);
 }
 
 void
@@ -79,9 +79,9 @@ Returns:
 --*/
 {
   Version();
-  printf ("Copyright (c) 1999-2016 Intel Corporation. All rights reserved.\n");
-  printf ("\n  The BootSectImage tool prints information or patch destination 
file by source\n");
-  printf ("  file for BIOS Parameter Block (BPB) or Master Boot Record 
(MBR).\n");
+  printf ("Copyright (c) 1999-2016 Intel Corporation. All rights reserved.\n");
+  printf ("\n  The BootSectImage tool prints information or patch destination 
file by source\n");
+  printf ("  file for BIOS Parameter Block (BPB) or Master Boot Record 
(MBR).\n");
   printf ("\nUsage: \n\
BootSectImage\n\
  [-f, --force force patch even if the FAT type of SrcImage and DstImage 
mismatch]\n\
diff --git a/BaseTools/Source/C/EfiLdrImage/EfiLdrImage.c 
b/BaseTools/Source/C/EfiLdrImage/EfiLdrImage.c
index 7961867..88cc345 100644
--- a/BaseTools/Source/C/EfiLdrImage/EfiLdrImage.c
+++ b/BaseTools/Source/C/EfiLdrImage/EfiLdrImage.c
@@ -6,7 +6,7 @@ FILE := EFILDR_HEADER
  +
 The order of EFILDR_IMAGE is same as the order of placing PeImageFileContent.
   
-Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.
+Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.
 This program and the accompanying materials  
 are licensed and made available under the terms and conditions of the BSD 
License 
 which accompanies this distribution.  The full text of the license may be 
found at
@@ -51,8 +51,8 @@ typedef struct {
 //
 // Utility version information
 //
-#define UTILITY_MAJOR_VERSION 1
-#define UTILITY_MINOR_VERSION 0
+#define UTILITY_MAJOR_VERSION 1
+#define UTILITY_MINOR_VERSION 0
 
 void
 Version (
@@ -74,8 +74,8 @@ Returns:
 
 --*/
 {
-  printf ("%s Version %d.%d Build %s\n", UTILITY_NAME, UTILITY_MAJOR_VERSION, 
UTILITY_MINOR_VERSION, __BUILD_VERSION);
-  exit (0);
+  printf ("%s Version %d.%d Build %s\n", UTILITY_NAME, UTILITY_MAJOR_VERSION, 
UTILITY_MINOR_VERSION, __BUILD_VERSION);
+  exit (0);
 }
 
 VOID
@@ -84,9 +84,9 @@ Usage (
   )
 {
   printf ("Usage: EfiLdrImage -o OutImage LoaderImage PeImage1 PeImage2 ... 
PeImageN\n");
-  printf ("%s Version %d.%d Build %s\n", UTILITY_NAME, UTILITY_MAJOR_VERSION, 
UTILITY_MINOR_VERSION, __BUILD_VERSION);
-  printf ("Copyright (c) 1999-2016 Intel Corporation. All rights reserved.\n");
-  printf ("\n  The EfiLdrImage tool is used to combine PE files into EFILDR 
image with Efi loader header.\n");
+  printf ("%s Version %d.%d Build %s\n", UTILITY_NAME, UTILITY_MAJOR_VERSION, 
UTILITY_MINOR_VERSION, __BUILD_VERSION);
+  printf ("Copyright (c) 1999-2016 Intel Corporation. All rights reserved.\n");
+  printf ("\n  The EfiLdrImage tool is used to combine PE files into EFILDR 
imag

Re: [edk2] [Patch] NetworkPkg: Fix IpsecConfig GCC build failure issue

[Fu, Siyuan]

Reviewed-by: Fu Siyuan 

> -Original Message-
> From: Wu, Jiaxin
> Sent: Wednesday, March 9, 2016 8:59 AM
> To: edk2-devel@lists.01.org
> Cc: Fu, Siyuan ; Zhang, Lubo 
> Subject: [Patch] NetworkPkg: Fix IpsecConfig GCC build failure issue
> 
> This issue is caused by the string token ID for help message,
> which is defined in the internal head file.
> This head file is used for reference more than once. So,
> multiple definition for the string token ID error will be
> enrolled.
> 
> Cc: Fu Siyuan 
> Cc: Zhang Lubo 
> Contributed-under: TianoCore Contribution Agreement 1.0
> Signed-off-by: Jiaxin Wu 
> ---
>  NetworkPkg/Application/IpsecConfig/IpSecConfig.c | 7 ++-
>  NetworkPkg/Application/IpsecConfig/IpSecConfig.h | 7 +--
>  2 files changed, 7 insertions(+), 7 deletions(-)
> 
> diff --git a/NetworkPkg/Application/IpsecConfig/IpSecConfig.c
> b/NetworkPkg/Application/IpsecConfig/IpSecConfig.c
> index ff895bc..274f582 100644
> --- a/NetworkPkg/Application/IpsecConfig/IpSecConfig.c
> +++ b/NetworkPkg/Application/IpsecConfig/IpSecConfig.c
> @@ -1,9 +1,9 @@
>  /** @file
>The main process for IpSecConfig application.
> 
> -  Copyright (c) 2009 - 2011, Intel Corporation. All rights reserved.
> +  Copyright (c) 2009 - 2016, Intel Corporation. All rights reserved.
> 
>This program and the accompanying materials
>are licensed and made available under the terms and conditions of the BSD
> License
>which accompanies this distribution.  The full text of the license may be
> found at
>http://opensource.org/licenses/bsd-license.php.
> @@ -24,10 +24,15 @@
>  #include "PolicyEntryOperation.h"
>  #include "Delete.h"
>  #include "Helper.h"
> 
>  //
> +// String token ID of IpSecConfig command help message text.
> +//
> +GLOBAL_REMOVE_IF_UNREFERENCED EFI_STRING_ID
> mStringIpSecHelpTokenId = STRING_TOKEN (STR_IPSEC_CONFIG_HELP);
> +
> +//
>  // Used for ShellCommandLineParseEx only
>  // and to ensure user inputs are in valid format
>  //
>  SHELL_PARAM_ITEMmIpSecConfigParamList[] = {
>{ L"-p",TypeValue },
> diff --git a/NetworkPkg/Application/IpsecConfig/IpSecConfig.h
> b/NetworkPkg/Application/IpsecConfig/IpSecConfig.h
> index 244926f..8ebc599 100644
> --- a/NetworkPkg/Application/IpsecConfig/IpSecConfig.h
> +++ b/NetworkPkg/Application/IpsecConfig/IpSecConfig.h
> @@ -1,9 +1,9 @@
>  /** @file
>The internal structure and function declaration in IpSecConfig application.
> 
> -  Copyright (c) 2009 - 2011, Intel Corporation. All rights reserved.
> +  Copyright (c) 2009 - 2016, Intel Corporation. All rights reserved.
> 
>This program and the accompanying materials
>are licensed and made available under the terms and conditions of the BSD
> License
>which accompanies this distribution.  The full text of the license may be
> found at
>http://opensource.org/licenses/bsd-license.php.
> @@ -25,15 +25,10 @@
>  #include 
>  #include 
> 
>  #include 
> 
> -//
> -// String token ID of VConfig command help message text.
> -//
> -GLOBAL_REMOVE_IF_UNREFERENCED EFI_STRING_ID
> mStringIpSecHelpTokenId = STRING_TOKEN (STR_IPSEC_CONFIG_HELP);
> -
>  #define ARRAY_SIZE(x) (sizeof(x) / sizeof(x[0]))
> 
>  #define IPSECCONFIG_STATUS_NAMEL"IpSecStatus"
> 
>  #define BIT(x)   (UINT32) (1 << (x))
> --
> 1.9.5.msysgit.1

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Re: [edk2] [Patch] NetworkPkg: Fix IpsecConfig GCC build failure issue

[Zhang, Lubo]

Reviewed-by: Zhang, Lubo 

-Original Message-
From: Wu, Jiaxin 
Sent: Wednesday, March 09, 2016 8:59 AM
To: edk2-devel@lists.01.org
Cc: Fu, Siyuan ; Zhang, Lubo 
Subject: [Patch] NetworkPkg: Fix IpsecConfig GCC build failure issue

This issue is caused by the string token ID for help message, which is defined 
in the internal head file.
This head file is used for reference more than once. So, multiple definition 
for the string token ID error will be enrolled.

Cc: Fu Siyuan 
Cc: Zhang Lubo 
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jiaxin Wu 
---
 NetworkPkg/Application/IpsecConfig/IpSecConfig.c | 7 ++-  
NetworkPkg/Application/IpsecConfig/IpSecConfig.h | 7 +--
 2 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/NetworkPkg/Application/IpsecConfig/IpSecConfig.c 
b/NetworkPkg/Application/IpsecConfig/IpSecConfig.c
index ff895bc..274f582 100644
--- a/NetworkPkg/Application/IpsecConfig/IpSecConfig.c
+++ b/NetworkPkg/Application/IpsecConfig/IpSecConfig.c
@@ -1,9 +1,9 @@
 /** @file
   The main process for IpSecConfig application.
 
-  Copyright (c) 2009 - 2011, Intel Corporation. All rights reserved.
+  Copyright (c) 2009 - 2016, Intel Corporation. All rights 
+ reserved.
 
   This program and the accompanying materials
   are licensed and made available under the terms and conditions of the BSD 
License
   which accompanies this distribution.  The full text of the license may be 
found at
   http://opensource.org/licenses/bsd-license.php.
@@ -24,10 +24,15 @@
 #include "PolicyEntryOperation.h"
 #include "Delete.h"
 #include "Helper.h"
 
 //
+// String token ID of IpSecConfig command help message text.
+//
+GLOBAL_REMOVE_IF_UNREFERENCED EFI_STRING_ID mStringIpSecHelpTokenId = 
+STRING_TOKEN (STR_IPSEC_CONFIG_HELP);
+
+//
 // Used for ShellCommandLineParseEx only  // and to ensure user inputs are in 
valid format  //
 SHELL_PARAM_ITEMmIpSecConfigParamList[] = {
   { L"-p",TypeValue },
diff --git a/NetworkPkg/Application/IpsecConfig/IpSecConfig.h 
b/NetworkPkg/Application/IpsecConfig/IpSecConfig.h
index 244926f..8ebc599 100644
--- a/NetworkPkg/Application/IpsecConfig/IpSecConfig.h
+++ b/NetworkPkg/Application/IpsecConfig/IpSecConfig.h
@@ -1,9 +1,9 @@
 /** @file
   The internal structure and function declaration in IpSecConfig application.
 
-  Copyright (c) 2009 - 2011, Intel Corporation. All rights reserved.
+  Copyright (c) 2009 - 2016, Intel Corporation. All rights 
+ reserved.
 
   This program and the accompanying materials
   are licensed and made available under the terms and conditions of the BSD 
License
   which accompanies this distribution.  The full text of the license may be 
found at
   http://opensource.org/licenses/bsd-license.php.
@@ -25,15 +25,10 @@
 #include   #include 
 
 #include 
 
-//
-// String token ID of VConfig command help message text.
-//
-GLOBAL_REMOVE_IF_UNREFERENCED EFI_STRING_ID mStringIpSecHelpTokenId = 
STRING_TOKEN (STR_IPSEC_CONFIG_HELP);
-
 #define ARRAY_SIZE(x) (sizeof(x) / sizeof(x[0]))
 
 #define IPSECCONFIG_STATUS_NAMEL"IpSecStatus"
 
 #define BIT(x)   (UINT32) (1 << (x))
--
1.9.5.msysgit.1

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Re: [edk2] [Patch] NetworkPkg: Fix IpsecConfig GCC build failure issue

[Gao, Liming]

Reviewed-by: Liming Gao 

> -Original Message-
> From: edk2-devel [mailto:edk2-devel-boun...@lists.01.org] On Behalf Of
> Jiaxin Wu
> Sent: Wednesday, March 09, 2016 8:59 AM
> To: edk2-devel@lists.01.org
> Cc: Zhang, Lubo; Fu, Siyuan
> Subject: [edk2] [Patch] NetworkPkg: Fix IpsecConfig GCC build failure issue
> 
> This issue is caused by the string token ID for help message,
> which is defined in the internal head file.
> This head file is used for reference more than once. So,
> multiple definition for the string token ID error will be
> enrolled.
> 
> Cc: Fu Siyuan 
> Cc: Zhang Lubo 
> Contributed-under: TianoCore Contribution Agreement 1.0
> Signed-off-by: Jiaxin Wu 
> ---
>  NetworkPkg/Application/IpsecConfig/IpSecConfig.c | 7 ++-
>  NetworkPkg/Application/IpsecConfig/IpSecConfig.h | 7 +--
>  2 files changed, 7 insertions(+), 7 deletions(-)
> 
> diff --git a/NetworkPkg/Application/IpsecConfig/IpSecConfig.c
> b/NetworkPkg/Application/IpsecConfig/IpSecConfig.c
> index ff895bc..274f582 100644
> --- a/NetworkPkg/Application/IpsecConfig/IpSecConfig.c
> +++ b/NetworkPkg/Application/IpsecConfig/IpSecConfig.c
> @@ -1,9 +1,9 @@
>  /** @file
>The main process for IpSecConfig application.
> 
> -  Copyright (c) 2009 - 2011, Intel Corporation. All rights reserved.
> +  Copyright (c) 2009 - 2016, Intel Corporation. All rights reserved.
> 
>This program and the accompanying materials
>are licensed and made available under the terms and conditions of the BSD
> License
>which accompanies this distribution.  The full text of the license may be
> found at
>http://opensource.org/licenses/bsd-license.php.
> @@ -24,10 +24,15 @@
>  #include "PolicyEntryOperation.h"
>  #include "Delete.h"
>  #include "Helper.h"
> 
>  //
> +// String token ID of IpSecConfig command help message text.
> +//
> +GLOBAL_REMOVE_IF_UNREFERENCED EFI_STRING_ID
> mStringIpSecHelpTokenId = STRING_TOKEN (STR_IPSEC_CONFIG_HELP);
> +
> +//
>  // Used for ShellCommandLineParseEx only
>  // and to ensure user inputs are in valid format
>  //
>  SHELL_PARAM_ITEMmIpSecConfigParamList[] = {
>{ L"-p",TypeValue },
> diff --git a/NetworkPkg/Application/IpsecConfig/IpSecConfig.h
> b/NetworkPkg/Application/IpsecConfig/IpSecConfig.h
> index 244926f..8ebc599 100644
> --- a/NetworkPkg/Application/IpsecConfig/IpSecConfig.h
> +++ b/NetworkPkg/Application/IpsecConfig/IpSecConfig.h
> @@ -1,9 +1,9 @@
>  /** @file
>The internal structure and function declaration in IpSecConfig application.
> 
> -  Copyright (c) 2009 - 2011, Intel Corporation. All rights reserved.
> +  Copyright (c) 2009 - 2016, Intel Corporation. All rights reserved.
> 
>This program and the accompanying materials
>are licensed and made available under the terms and conditions of the BSD
> License
>which accompanies this distribution.  The full text of the license may be
> found at
>http://opensource.org/licenses/bsd-license.php.
> @@ -25,15 +25,10 @@
>  #include 
>  #include 
> 
>  #include 
> 
> -//
> -// String token ID of VConfig command help message text.
> -//
> -GLOBAL_REMOVE_IF_UNREFERENCED EFI_STRING_ID
> mStringIpSecHelpTokenId = STRING_TOKEN (STR_IPSEC_CONFIG_HELP);
> -
>  #define ARRAY_SIZE(x) (sizeof(x) / sizeof(x[0]))
> 
>  #define IPSECCONFIG_STATUS_NAMEL"IpSecStatus"
> 
>  #define BIT(x)   (UINT32) (1 << (x))
> --
> 1.9.5.msysgit.1
> 
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Re: [edk2] OpenSSL 1.1 status, and a worked example of why you should *NEVER* rebase

[Ard Biesheuvel]

On 9 March 2016 at 07:53, David Woodhouse  wrote:
> On Wed, 2016-03-09 at 07:49 +0700, Ard Biesheuvel wrote:
>>
>> I agree that they should be allowed, but i share the concern that
>> merging puts the burden of fixing up conflicts on the maintainer
>> rather than the contributor, who is arguably in a worse position to
>> assess any potential problems on a seemingly clean merge, especially
>> since merges are much more forgiving than rebases.
>
> For a not-yet-proficient maintainer to ask a submitter to perform the
> merge for themselves, or to verify the result of a merge, seems
> reasonable.
>

So that means merging master into the topic branch before merging the
topic branch into master?

>> On top of that, the current crop of Tianocore committers is not
>> entirely on top of things yet as fas as git is concerned, and having
>> non-linear history just because someone couldn't be bothered to do a
>> pull beforehand should also be avoided imo.
>
> Nah, history that is trivially non-linear is fine. There's absolutely
> no harm in it. Even for backporting to SVN it's easy enough; you just
> take a line through it which represents the state of the upstream tree
> at any given time. Thus collapsing the merge commits into a single SVN
> commit. But nobody cares because that's no worse than what SVN made
> people do anyway.
>

I am not saying there is anything wrong with it, but linear history is
inherently simpler to understand while browsing through the commit
history imo
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[edk2] [Patch] NetworkPkg: Fix IpsecConfig GCC build failure issue

[Jiaxin Wu]

This issue is caused by the string token ID for help message,
which is defined in the internal head file.
This head file is used for reference more than once. So,
multiple definition for the string token ID error will be
enrolled.

Cc: Fu Siyuan 
Cc: Zhang Lubo 
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jiaxin Wu 
---
 NetworkPkg/Application/IpsecConfig/IpSecConfig.c | 7 ++-
 NetworkPkg/Application/IpsecConfig/IpSecConfig.h | 7 +--
 2 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/NetworkPkg/Application/IpsecConfig/IpSecConfig.c 
b/NetworkPkg/Application/IpsecConfig/IpSecConfig.c
index ff895bc..274f582 100644
--- a/NetworkPkg/Application/IpsecConfig/IpSecConfig.c
+++ b/NetworkPkg/Application/IpsecConfig/IpSecConfig.c
@@ -1,9 +1,9 @@
 /** @file
   The main process for IpSecConfig application.
 
-  Copyright (c) 2009 - 2011, Intel Corporation. All rights reserved.
+  Copyright (c) 2009 - 2016, Intel Corporation. All rights reserved.
 
   This program and the accompanying materials
   are licensed and made available under the terms and conditions of the BSD 
License
   which accompanies this distribution.  The full text of the license may be 
found at
   http://opensource.org/licenses/bsd-license.php.
@@ -24,10 +24,15 @@
 #include "PolicyEntryOperation.h"
 #include "Delete.h"
 #include "Helper.h"
 
 //
+// String token ID of IpSecConfig command help message text.
+//
+GLOBAL_REMOVE_IF_UNREFERENCED EFI_STRING_ID mStringIpSecHelpTokenId = 
STRING_TOKEN (STR_IPSEC_CONFIG_HELP);
+
+//
 // Used for ShellCommandLineParseEx only
 // and to ensure user inputs are in valid format
 //
 SHELL_PARAM_ITEMmIpSecConfigParamList[] = {
   { L"-p",TypeValue },
diff --git a/NetworkPkg/Application/IpsecConfig/IpSecConfig.h 
b/NetworkPkg/Application/IpsecConfig/IpSecConfig.h
index 244926f..8ebc599 100644
--- a/NetworkPkg/Application/IpsecConfig/IpSecConfig.h
+++ b/NetworkPkg/Application/IpsecConfig/IpSecConfig.h
@@ -1,9 +1,9 @@
 /** @file
   The internal structure and function declaration in IpSecConfig application.
 
-  Copyright (c) 2009 - 2011, Intel Corporation. All rights reserved.
+  Copyright (c) 2009 - 2016, Intel Corporation. All rights reserved.
 
   This program and the accompanying materials
   are licensed and made available under the terms and conditions of the BSD 
License
   which accompanies this distribution.  The full text of the license may be 
found at
   http://opensource.org/licenses/bsd-license.php.
@@ -25,15 +25,10 @@
 #include 
 #include 
 
 #include 
 
-//
-// String token ID of VConfig command help message text.
-//
-GLOBAL_REMOVE_IF_UNREFERENCED EFI_STRING_ID mStringIpSecHelpTokenId = 
STRING_TOKEN (STR_IPSEC_CONFIG_HELP);
-
 #define ARRAY_SIZE(x) (sizeof(x) / sizeof(x[0]))
 
 #define IPSECCONFIG_STATUS_NAMEL"IpSecStatus"
 
 #define BIT(x)   (UINT32) (1 << (x))
-- 
1.9.5.msysgit.1

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Re: [edk2] OpenSSL 1.1 status, and a worked example of why you should *NEVER* rebase

[David Woodhouse]

On Wed, 2016-03-09 at 07:49 +0700, Ard Biesheuvel wrote:
> 
> I agree that they should be allowed, but i share the concern that
> merging puts the burden of fixing up conflicts on the maintainer
> rather than the contributor, who is arguably in a worse position to
> assess any potential problems on a seemingly clean merge, especially
> since merges are much more forgiving than rebases.

For a not-yet-proficient maintainer to ask a submitter to perform the
merge for themselves, or to verify the result of a merge, seems
reasonable.

> On top of that, the current crop of Tianocore committers is not
> entirely on top of things yet as fas as git is concerned, and having
> non-linear history just because someone couldn't be bothered to do a
> pull beforehand should also be avoided imo.

Nah, history that is trivially non-linear is fine. There's absolutely
no harm in it. Even for backporting to SVN it's easy enough; you just
take a line through it which represents the state of the upstream tree
at any given time. Thus collapsing the merge commits into a single SVN
commit. But nobody cares because that's no worse than what SVN made
people do anyway.

-- 
dwmw2



smime.p7s
Description: S/MIME cryptographic signature
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Re: [edk2] OpenSSL 1.1 status, and a worked example of why you should *NEVER* rebase

[Ard Biesheuvel]

On 9 March 2016 at 01:17, Laszlo Ersek  wrote:
> On 03/08/16 19:09, David Woodhouse wrote:
>> On Tue, 2016-03-08 at 19:00 +0100, Laszlo Ersek wrote:
>
>>> Or do you recommend that contributors be *allowed* to email pull
>>> requests (alongside their patches), and if they do, their pull requests
>>> be merged correctly?
>>
>> Exactly this. They should be *allowed*, and for large submissions it
>> should be *recommended* but not mandatory.
>
> ACK
>
> (Modulo consensus from other edk2 maintainers, of course.)
>

I agree that they should be allowed, but i share the concern that
merging puts the burden of fixing up conflicts on the maintainer
rather than the contributor, who is arguably in a worse position to
assess any potential problems on a seemingly clean merge, especially
since merges are much more forgiving than rebases.

On top of that, the current crop of Tianocore committers is not
entirely on top of things yet as fas as git is concerned, and having
non-linear history just because someone couldn't be bothered to do a
pull beforehand should also be avoided imo.

-- 
Ard.
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Re: [edk2] [PATCH v6] MdePkg: Add UEFI2.6 HII Image Ex and Image Decoder protocol definition.

[Dong, Eric]

Reviewed-by: Eric Dong 


Feng,

Please help to check in this code.

Thanks,
Eric

> -Original Message-
> From: edk2-devel [mailto:edk2-devel-boun...@lists.01.org] On Behalf Of Cecil 
> Sheng
> Sent: Tuesday, March 08, 2016 3:56 PM
> To: edk2-devel@lists.01.org
> Cc: Cecil Sheng
> Subject: [edk2] [PATCH v6] MdePkg: Add UEFI2.6 HII Image Ex and Image Decoder 
> protocol definition.
> 
> Add the definition for the new UEFI 2.6 EFI_HII_IMAGE_EX_PROTOCOL and 
> EFI_IMAGE_DECODER_PROTOCOL.
> 
> Contributed-under: TianoCore Contribution Agreement 1.0
> Signed-off-by: Cecil Sheng 
> Reviewed-by: Samer El-Haj-Mahmoud 
> Reviewed-by: Abner Chang 
> ---
>  MdePkg/Include/Protocol/HiiImageEx.h   | 245 
> +
>  MdePkg/Include/Protocol/ImageDecoder.h | 192 ++
>  MdePkg/MdePkg.dec  |  14 ++
>  3 files changed, 451 insertions(+)
>  create mode 100644 MdePkg/Include/Protocol/HiiImageEx.h
>  create mode 100644 MdePkg/Include/Protocol/ImageDecoder.h
> 
> diff --git a/MdePkg/Include/Protocol/HiiImageEx.h 
> b/MdePkg/Include/Protocol/HiiImageEx.h
> new file mode 100644
> index 000..9393a53
> --- /dev/null
> +++ b/MdePkg/Include/Protocol/HiiImageEx.h
> @@ -0,0 +1,245 @@
> +/** @file
> +  Protocol which allows access to the images in the images database.
> +
> +(C) Copyright 2016 Hewlett Packard Enterprise Development LP
> +
> +This program and the accompanying materials are licensed and made available 
> under
> +the terms and conditions of the BSD License that accompanies this 
> distribution.
> +The full text of the license may be found at
> +http://opensource.org/licenses/bsd-license.php.
> +
> +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +
> +**/
> +
> +#ifndef EFI_HII_IMAGE_EX_H
> +#define EFI_HII_IMAGE_EX_H
> +
> +#include 
> +
> +//
> +// Global ID for the Hii Image Ex Protocol.
> +//
> +#define EFI_HII_IMAGE_EX_PROTOCOL_GUID \
> +  {0x1a1241e6, 0x8f19, 0x41a9,  { 0xbc, 0xe, 0xe8, 0xef, 0x39, 0xe0, 0x65, 
> 0x46 }}
> +
> +typedef struct _EFI_HII_IMAGE_EX_PROTOCOL EFI_HII_IMAGE_EX_PROTOCOL;
> +
> +/**
> +  The prototype of this extension function is the same with 
> EFI_HII_IMAGE_PROTOCOL.NewImage().
> +  Same with EFI_HII_IMAGE_PROTOCOL.NewImage().This protocol invokes
> +EFI_HII_IMAGE_PROTOCOL.NewImage() implicitly.
> +
> +  @param  This   A pointer to the EFI_HII_IMAGE_EX_PROTOCOL 
> instance.
> +  @param  PackageListHandle of the package list where this image 
> will
> + be added.
> +  @param  ImageIdOn return, contains the new image id, which 
> is
> + unique within PackageList.
> +  @param  Image  Points to the image.
> +
> +  @retval EFI_SUCCESSThe new image was added successfully.
> +  @retval EFI_NOT_FOUND  The specified PackageList could not be 
> found in
> + database.
> +  @retval EFI_OUT_OF_RESOURCES   Could not add the image due to lack of 
> resources.
> +  @retval EFI_INVALID_PARAMETER  Image is NULL or ImageId is NULL.
> +
> +**/
> +typedef
> +EFI_STATUS
> +(EFIAPI *EFI_HII_NEW_IMAGE_EX)(
> +  IN CONST  EFI_HII_IMAGE_EX_PROTOCOL  *This,
> +  INEFI_HII_HANDLE  PackageList,
> +  OUT   EFI_IMAGE_ID*ImageId,
> +  IN CONST  EFI_IMAGE_INPUT *Image
> +  );
> +
> +/**
> +  Return the information about the image, associated with the package list.
> +  The prototype of this extension function is the same with 
> EFI_HII_IMAGE_PROTOCOL.GetImage().
> +  Same with EFI_HII_IMAGE_PROTOCOL.SetImage(),this protocol invokes 
> EFI_HII_IMAGE_PROTOCOL.SetImage() implicitly.
> +
> +  @param  This   A pointer to the EFI_HII_IMAGE_EX_PROTOCOL 
> instance.
> +  @param  PackageListHandle of the package list where this image 
> will
> + be searched.
> +  @param  ImageIdThe image's id,, which is unique within
> + PackageList.
> +  @param  Image  Points to the image.
> +
> +  @retval EFI_SUCCESSThe new image was returned successfully.
> +  @retval EFI_NOT_FOUND  The image specified by ImageId is not in the
> + database. The specified PackageList is not 
> in
> + the database.
> +  @retval EFI_BUFFER_TOO_SMALL   The buffer specified by ImageSize is too 
> small to
> + hold the image.
> +  @retval EFI_INVALID_PARAMETER  The Image or ImageSize was NULL.
> +  @retval EFI_OUT_OF_RESOURCES   The bitmap could not be retrieved because 
> there
> + was not enough memory.
> +
> +**/
> +typedef
> +EFI_STATUS
> +(EFIAPI *EFI_HII_GET_IMAGE_EX)(
> +  IN CONST  EF

Re: [edk2] EDK2 Setup & Configuration Issue

[Carsey, Jaben]

BaseTools and Conf should be one directory up I think.

From: Jim Slaughter [mailto:jwslau...@yahoo.com]
Sent: Tuesday, March 08, 2016 4:19 PM
To: Carsey, Jaben ; Gao, Liming ; 
Tian, Feng ; edk2-devel@lists.01.org
Subject: Re: [edk2] EDK2 Setup & Configuration Issue
Importance: High

Windows Environment:

edketup:

C:\edk2\BaseTools(Windows)>edksetup
'C:\edk2\BaseTools' is not recognized as an internal or external command,
operable program or batch file.
!!! WARNING !!! CYGWIN_HOME not found, gcc build may not be used !!!
C:\edk2\BaseTools(Windows)>

A dir of this:

C:\edk2\BaseTools(Windows)>dir
 Volume in drive C is OSDisk
 Volume Serial Number is CE0F-B385
 Directory of C:\edk2\BaseTools(Windows)
03/08/2016  03:17 PM  .
03/08/2016  03:17 PM  ..
03/08/2016  03:17 PM  BaseTools
03/08/2016  03:17 PM  Conf
03/08/2016  03:17 PM 4,202 edksetup.bat
   1 File(s)  4,202 bytes
   4 Dir(s)  941,196,587,008 bytes free
C:\edk2\BaseTools(Windows)>

Jim S.



On Tuesday, March 8, 2016 2:27 PM, "Carsey, Jaben" 
mailto:jaben.car...@intel.com>> wrote:

Jim,

You need to download or build the BaseTools that are used during the build.

Have you done that?

-Jaben

> -Original Message-
> From: edk2-devel 
> [mailto:edk2-devel-boun...@lists.01.org]
>  On Behalf Of Jim
> Slaughter
> Sent: Tuesday, March 08, 2016 2:21 PM
> To: Gao, Liming mailto:liming@intel.com>>; Tian, 
> Feng mailto:feng.t...@intel.com>>;
> edk2-devel@lists.01.org
> Subject: Re: [edk2] EDK2 Setup & Configuration Issue
>
> Hello Liming:
> I am confused.I originally downloaded edk2-master and unzipped.This has one
> of the packages I am interested in building, embeddedpkg. This is where the
> directory is missing.
> I have since downloaded 2014 and 2015, all in separate directories, from
> sourceforge.The file structure looks different? I am after the Ffs code which 
> I
> think appears in embeddedpkg. I searched for the function
> FfsFindNextVolumne() and it is not located in 2014 or 2015. The function is in
> edk2-master.
> What is wrong? Am I not downloading the correct zip files?
> Jim S.
>
>
>On Thursday, March 3, 2016 8:21 PM, "Gao, Liming"
> mailto:liming@intel.com>> wrote:
>
>
>  #yiv2782034757 #yiv2782034757 -- _filtered #yiv2782034757 {font-
> family:Helvetica;panose-1:2 11 6 4 2 2 2 2 2 4;} _filtered #yiv2782034757
> {font-family:SimSun;panose-1:2 1 6 0 3 1 1 1 1 1;} _filtered #yiv2782034757
> {panose-1:2 4 5 3 5 4 6 3 2 4;} _filtered #yiv2782034757 {font-
> family:Calibri;panose-1:2 15 5 2 2 2 4 3 2 4;} _filtered #yiv2782034757
> {panose-1:2 1 6 0 3 1 1 1 1 1;}#yiv2782034757 #yiv2782034757
> p.yiv2782034757MsoNormal, #yiv2782034757 li.yiv2782034757MsoNormal,
> #yiv2782034757 div.yiv2782034757MsoNormal {margin:0in;margin-
> bottom:.0001pt;font-size:12.0pt;}#yiv2782034757 a:link, #yiv2782034757
> span.yiv2782034757MsoHyperlink {color:blue;text-
> decoration:underline;}#yiv2782034757 a:visited, #yiv2782034757
> span.yiv2782034757MsoHyperlinkFollowed {color:purple;text-
> decoration:underline;}#yiv2782034757 span.yiv2782034757EmailStyle17
> {color:#1F497D;}#yiv2782034757 .yiv2782034757MsoChpDefault {font-
> size:10.0pt;} _filtered #yiv2782034757 {margin:1.0in 1.0in 1.0in
> 1.0in;}#yiv2782034757 div.yiv2782034757WordSection1 {}#yiv2782034757
> Jim:   Yes. GitHub Edk2 project has not included BaseTools Binary. You need to
> download it from this linkhttps://github.com/tianocore/edk2-BaseTools-
> win32.git.  Or, you download full source code from UDK release
> http://www.tianocore.org/udk/udk2015/   Thanks Liming From: Jim Slaughter
> [mailto:jwslau...@yahoo.com]
> Sent: Friday, March 04, 2016 11:26 AM
> To: Gao, Liming; Tian, Feng; 
> edk2-devel@lists.01.org
> Subject: Re: [edk2] EDK2 Setup & Configuration IssueHello,I downloaded
> edk2 again, and its the 2014 stable version. The directory is still not
> there:Z:\edk2\edk2-master>dir basetools\bin\win32
>  Volume in drive Z is vxbox
>  Volume Serial Number is 009A-9A03  Directory of Z:\edk2\edk2-
> master\basetools\bin File Not Found Z:\edk2\edk2-master>dir basetools\bin\
>  Volume in drive Z is vxbox
>  Volume Serial Number is 009A-9A03  Directory of Z:\edk2\edk2-
> master\basetools\bin 12/30/2015  02:28 PM  .
> 12/30/2015  02:29 PM  ..
> 12/30/2015  02:28 PM  Darwin-i386
> 12/30/2015  02:28 PM69 externals.txt
> 12/30/2015  02:28 PM  CYGWIN_NT-5.1-i686
>1 File(s) 69 bytes
>4 Dir(s)  321,086,816,256 bytes free Z:\edk2\edk2-master>
> Not
> sure how to proceed?Jim S.   On Wednesday, March 2, 2016 8:08 PM,
> "Gao, Liming" mailto:liming@intel.com>> wrote:
> If you download them to other
> place, please configure EDK_TOOLS_BIN

Re: [edk2] EDK2 Setup & Configuration Issue

[Jim Slaughter]

Windows Environment:
edketup: 
C:\edk2\BaseTools(Windows)>edksetup
'C:\edk2\BaseTools' is not recognized as an internal or external command,
operable program or batch file.!!! WARNING !!! CYGWIN_HOME not found, gcc build 
may not be used !!!C:\edk2\BaseTools(Windows)>
A dir of this:
C:\edk2\BaseTools(Windows)>dir
 Volume in drive C is OSDisk
 Volume Serial Number is CE0F-B385 Directory of 
C:\edk2\BaseTools(Windows)03/08/2016  03:17 PM      .
03/08/2016  03:17 PM      ..
03/08/2016  03:17 PM      BaseTools
03/08/2016  03:17 PM      Conf
03/08/2016  03:17 PM 4,202 edksetup.bat
   1 File(s)  4,202 bytes
   4 Dir(s)  941,196,587,008 bytes freeC:\edk2\BaseTools(Windows)>
Jim S.

 

On Tuesday, March 8, 2016 2:27 PM, "Carsey, Jaben"  
wrote:
 

 Jim,

You need to download or build the BaseTools that are used during the build.

Have you done that?

-Jaben

> -Original Message-
> From: edk2-devel [mailto:edk2-devel-boun...@lists.01.org] On Behalf Of Jim
> Slaughter
> Sent: Tuesday, March 08, 2016 2:21 PM
> To: Gao, Liming ; Tian, Feng ;
> edk2-devel@lists.01.org
> Subject: Re: [edk2] EDK2 Setup & Configuration Issue
> 
> Hello Liming:
> I am confused.I originally downloaded edk2-master and unzipped.This has one
> of the packages I am interested in building, embeddedpkg. This is where the
> directory is missing.
> I have since downloaded 2014 and 2015, all in separate directories, from
> sourceforge.The file structure looks different? I am after the Ffs code which 
> I
> think appears in embeddedpkg. I searched for the function
> FfsFindNextVolumne() and it is not located in 2014 or 2015. The function is in
> edk2-master.
> What is wrong? Am I not downloading the correct zip files?
> Jim S.
> 
> 
>    On Thursday, March 3, 2016 8:21 PM, "Gao, Liming"
>  wrote:
> 
> 
>  #yiv2782034757 #yiv2782034757 -- _filtered #yiv2782034757 {font-
> family:Helvetica;panose-1:2 11 6 4 2 2 2 2 2 4;} _filtered #yiv2782034757
> {font-family:SimSun;panose-1:2 1 6 0 3 1 1 1 1 1;} _filtered #yiv2782034757
> {panose-1:2 4 5 3 5 4 6 3 2 4;} _filtered #yiv2782034757 {font-
> family:Calibri;panose-1:2 15 5 2 2 2 4 3 2 4;} _filtered #yiv2782034757
> {panose-1:2 1 6 0 3 1 1 1 1 1;}#yiv2782034757 #yiv2782034757
> p.yiv2782034757MsoNormal, #yiv2782034757 li.yiv2782034757MsoNormal,
> #yiv2782034757 div.yiv2782034757MsoNormal {margin:0in;margin-
> bottom:.0001pt;font-size:12.0pt;}#yiv2782034757 a:link, #yiv2782034757
> span.yiv2782034757MsoHyperlink {color:blue;text-
> decoration:underline;}#yiv2782034757 a:visited, #yiv2782034757
> span.yiv2782034757MsoHyperlinkFollowed {color:purple;text-
> decoration:underline;}#yiv2782034757 span.yiv2782034757EmailStyle17
> {color:#1F497D;}#yiv2782034757 .yiv2782034757MsoChpDefault {font-
> size:10.0pt;} _filtered #yiv2782034757 {margin:1.0in 1.0in 1.0in
> 1.0in;}#yiv2782034757 div.yiv2782034757WordSection1 {}#yiv2782034757
> Jim:   Yes. GitHub Edk2 project has not included BaseTools Binary. You need to
> download it from this linkhttps://github.com/tianocore/edk2-BaseTools-
> win32.git.      Or, you download full source code from UDK release
> http://www.tianocore.org/udk/udk2015/   Thanks Liming From: Jim Slaughter
> [mailto:jwslau...@yahoo.com]
> Sent: Friday, March 04, 2016 11:26 AM
> To: Gao, Liming; Tian, Feng; edk2-devel@lists.01.org
> Subject: Re: [edk2] EDK2 Setup & Configuration Issue    Hello,    I downloaded
> edk2 again, and its the 2014 stable version. The directory is still not
> there:    Z:\edk2\edk2-master>dir basetools\bin\win32
>  Volume in drive Z is vxbox
>  Volume Serial Number is 009A-9A03  Directory of Z:\edk2\edk2-
> master\basetools\bin File Not Found Z:\edk2\edk2-master>dir basetools\bin\
>  Volume in drive Z is vxbox
>  Volume Serial Number is 009A-9A03  Directory of Z:\edk2\edk2-
> master\basetools\bin 12/30/2015  02:28 PM      .
> 12/30/2015  02:29 PM      ..
> 12/30/2015  02:28 PM      Darwin-i386
> 12/30/2015  02:28 PM    69 externals.txt
> 12/30/2015  02:28 PM      CYGWIN_NT-5.1-i686
>    1 File(s) 69 bytes
>    4 Dir(s)  321,086,816,256 bytes free Z:\edk2\edk2-master>    
> Not
> sure how to proceed?    Jim S.       On Wednesday, March 2, 2016 8:08 PM,
> "Gao, Liming"  wrote:    If you download them to other
> place, please configure EDK_TOOLS_BIN env to point to it.
> 
> Here is wiki
> https://github.com/tianocore/tianocore.github.io/wiki/SourceForge-to-
> Github-Quick-Start.
> 
> > -Original Message-
> > From: edk2-devel [mailto:edk2-devel-boun...@lists.01.org] On Behalf Of
> > Tian, Feng
> > Sent: Thursday, March 03, 2016 11:31 AM
> > To: Jim Slaughter; edk2-devel@lists.01.org
> > Cc: Tian, Feng
> > Subject: Re: [edk2] EDK2 Setup & Configuration Issue
> >
> > Git https://github.com/tianocore/edk2-BaseTools-win32.git
> > Svn mirror https://svn.code.sf.net/p/edk2-toolbinaries/code/trunk/Win32
> >
> >

Re: [edk2] OpenSSL 1.1 status, and a worked example of why you should *NEVER* rebase

[David Woodhouse]

On Wed, 2016-03-09 at 00:05 +0100, Laszlo Ersek wrote:
> (1) The submitter is himself/herself responsible for picking up review
> tags, and then for posting a final (fully reviewed) PULL that can be
> merged without *any* kind of rebase by the pulling maintainer.
> 
> Corollary: since the first submission never has any reviews, the first
> submission should never be a PULL.

If submissions *require* review, the first submission isn't intended to
be merged anyway. So it's meaningless to say *either* that the first
submission is to be merged by applying patches, *or* that it's to be
merged as a pull. This is fairly much a non-sequitur.

> It seems to me that the extra trust for a pull request is needed because
> it's possible to post patches to the list (for review) that *differ*
> from the commits that *actually* lead up to the hash that is presented
> in the pull request. An attacker can prepare two patch sets, an innocent
> and a malicious one; post one series for review, but include the final
> commit hash of the other series in the pull request.
>
> Whereas when the maintainer applies patches from the list (i.e., at that
> point: from his own mailbox) directly, then the maintainer can be
> (reasonably) sure that those are exactly the patches the community
> reviewed (not counting mailbox break-ins etc).

Nonsense. If I go through seven rounds of posting patches to the list,
and I gather a series of acks from the first six but you apply the
seventh, you have *no* good reason to believe that my final submission
doesn't contain the trojan horse. You have to *look* before you apply
it.

And it's *just* the same if my final submission is actually in the form
of a pull request. Sure, the signed tag means you know it comes from
*me*, which can be achieved by signed email too (like this one). But
you still have to trust *me* just the same.

Or actually do a final review on the code you're actually *merging*.
Whether it be in email patches or in a pull request, that's just the
same.

Really, from the trust point of view there is *not* a difference
between pull requests and patches. Look at what you merge, or trust the
submitter. It's as simple as that.

> ... So, I dunno what to do about this. I trust you, but I wouldn't want
> to open up the possibility of *any* maintainer pulling from *any*
> contributor.
>
> * How about an alternative.
> 
> (a) Contributors are encouraged to name the fork-off point (commit hash)
> of their topic branch, from which they post their patches.
> 
> (b) For a large series, the maintainer is expected to apply the patches
> on a local, temporary branch, forked off of exactly the named commit of
> the master branch. Review tags are also added on this branch.
> 
> (c) Maintainer merges topic into master locally.
> 
> (d) Maintainer pushes the merge commit to his or her personal repo.
> 
> (e) Submitter fetches maintainer's personal repo, and confirms (in
> email, stating the hash of the merge commit) that it's fine.
> 
> (f) Maintainer pushes the merge commit (and its dependencies of course)
> to upstream master.
> 
> Now, steps (d) and (e) add a round-trip that can make the merge commit
> prepared in step (c) obsolete, by the time the confirmation arrives. So
> perhaps we can drop (d) and (e).
> 
> The point is, your history would be precisely reconstructed, and you
> could get to say the final OK.

No, this is pointless complexity.

Again, just *look* at what you merge. Whether it means a proper read
through the seventh round of patches, or actually looking at the
contents of a pull request, there's *no* difference.

> * There is another alternative. You should become an official
> co-maintainer of CryptoPkg (using your Intel email address), and then
> you could push your merges directly, after review. As I said, I trust
> you, but I don't trust a setup where any maintainer can pull from any
> contributor.

That's a band-aid for the one issue. I'm trying to make things better
for *everyone*.

-- 
dwmw2



smime.p7s
Description: S/MIME cryptographic signature
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Re: [edk2] [PATCH 1/9] edksetup.sh: Create the Conf directory if necessary

[Andrew Fish]

> On Mar 6, 2016, at 11:55 PM, Gao, Liming  wrote:
> 
> Andrew:
>  Now, Build tool will report error message if Conf directory or build 
> configuration file is not found. It can detect the wrong setting when user 
> specifies Conf by mistake. 
> 

I guess we could add an argument that enable/disables the behavior changes?

Thanks,

Andrew Fish

> Thanks
> Liming
>> -Original Message-
>> From: edk2-devel [mailto:edk2-devel-boun...@lists.01.org] On Behalf Of
>> Andrew Fish
>> Sent: Saturday, March 05, 2016 2:51 AM
>> To: Leahy, Leroy P
>> Cc: Justen, Jordan L; edk2-devel@lists.01.org; Bjorge, Erik C
>> Subject: Re: [edk2] [PATCH 1/9] edksetup.sh: Create the Conf directory if
>> necessary
>> 
>> 
>>> On Mar 4, 2016, at 8:54 AM, Lee Leahy  wrote:
>>> 
>>> Edit the shell script to determine if the Conf directory is present.  If
>>> not then create the Conf directory.
>>> 
>>> Contributed-under: TianoCore Contribution Agreement 1.0
>>> Signed-off-by: Lee Leahy 
>>> ---
>>> edksetup.sh | 4 
>>> 1 file changed, 4 insertions(+)
>>> 
>>> diff --git a/edksetup.sh b/edksetup.sh
>>> index 57368b5..d89ef9d 100755
>>> --- a/edksetup.sh
>>> +++ b/edksetup.sh
>>> @@ -72,6 +72,10 @@ function SetWorkspace()
>>> 
>>> function SetupEnv()
>>> {
>>> +  if [ ! -d "$WORKSPACE/Conf" ]
>>> +  then
>>> +mkdir $WORKSPACE/Conf
>>> +  fi
>> 
>> This comment is not related to this patch.
>> 
>> What is the process to propose a change to the edk2 build specification?
>> 
>> I think the creation of Conf/ if it does not exist should be moved to 
>> build.py
>> (build.exe). The copy of the *.template files to Conf/*.txt could also be
>> moved into build.py.
>> 
>> The reason I advocate this is we have started using the build --
>> conf=CONFDIRECTORY flag, and we point CONFDIRECTORY to the build
>> output directory. This enables building different platforms in parallel. It 
>> also
>> makes it possible to write a top level GNUmakefile and not have to call any
>> shell scripts to build. Basically the top level makefile can do a `export
>> WORKSPACE, export EDK_TOOLS_PATH, export PATH` and it is possible to
>> avoid calling any scripts to setup the environment.
>> 
>> Thus moving the Conf/ processing to build.py (build.exe) makes it more
>> convenient to use the --conf flag, and helps make the setup scripts less
>> complex.
>> 
>> Thanks,
>> 
>> Andrew Fish
>> 
>> 
>>>  if [ -n "$EDK_TOOLS_PATH" ]
>>>  then
>>>. $EDK_TOOLS_PATH/BuildEnv $*
>>> --
>>> 1.9.1
>>> 
>>> ___
>>> edk2-devel mailing list
>>> edk2-devel@lists.01.org
>>> https://lists.01.org/mailman/listinfo/edk2-devel
>> 
>> ___
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>> edk2-devel@lists.01.org
>> https://lists.01.org/mailman/listinfo/edk2-devel
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Re: [edk2] OpenSSL 1.1 status, and a worked example of why you should *NEVER* rebase

[Laszlo Ersek]

On 03/08/16 19:09, David Woodhouse wrote:
> On Tue, 2016-03-08 at 19:00 +0100, Laszlo Ersek wrote:

>> Or do you recommend that contributors be *allowed* to email pull
>> requests (alongside their patches), and if they do, their pull requests
>> be merged correctly?
> 
> Exactly this. They should be *allowed*, and for large submissions it
> should be *recommended* but not mandatory.

I found this:

http://wiki.qemu.org/Contribute/SubmitAPullRequest

The parts I find especially interesting are:

(1) The submitter is himself/herself responsible for picking up review
tags, and then for posting a final (fully reviewed) PULL that can be
merged without *any* kind of rebase by the pulling maintainer.

Corollary: since the first submission never has any reviews, the first
submission should never be a PULL.

(2) "All pull requests must be signed. [...] Key signing requires
meeting another community member *in person* so please make appropriate
arrangements."

Also, quoting Documentation/SubmittingPatches from Linux:

"Note, however, that pulling patches from a developer requires a higher
degree of trust than taking patches from a mailing list. As a result,
many subsystem maintainers are reluctant to take pull requests,
especially from new, unknown developers. [...] Some maintainers
(including Linus) want to see pull requests from signed commits; that
increases their confidence that the request actually came from you.
Linus, in particular, will not pull from public hosting sites like
GitHub in the absence of a signed tag."

Further links:
- https://lists.gnu.org/archive/html/qemu-devel/2014-09/msg00136.html
-
https://www.kernel.org/pub/software/scm/git/docs/howto/using-signed-tag-in-pull-request.html

It seems to me that the extra trust for a pull request is needed because
it's possible to post patches to the list (for review) that *differ*
from the commits that *actually* lead up to the hash that is presented
in the pull request. An attacker can prepare two patch sets, an innocent
and a malicious one; post one series for review, but include the final
commit hash of the other series in the pull request.

Whereas when the maintainer applies patches from the list (i.e., at that
point: from his own mailbox) directly, then the maintainer can be
(reasonably) sure that those are exactly the patches the community
reviewed (not counting mailbox break-ins etc).

Requesting the pull of a signed tag does not prevent the attack, but it
does ensure one thing: non-repudiation. Which in turn explains why
signed tags *only* work if people meet *in person* at key signing parties.

... So, I dunno what to do about this. I trust you, but I wouldn't want
to open up the possibility of *any* maintainer pulling from *any*
contributor.

* How about an alternative.

(a) Contributors are encouraged to name the fork-off point (commit hash)
of their topic branch, from which they post their patches.

(b) For a large series, the maintainer is expected to apply the patches
on a local, temporary branch, forked off of exactly the named commit of
the master branch. Review tags are also added on this branch.

(c) Maintainer merges topic into master locally.

(d) Maintainer pushes the merge commit to his or her personal repo.

(e) Submitter fetches maintainer's personal repo, and confirms (in
email, stating the hash of the merge commit) that it's fine.

(f) Maintainer pushes the merge commit (and its dependencies of course)
to upstream master.

Now, steps (d) and (e) add a round-trip that can make the merge commit
prepared in step (c) obsolete, by the time the confirmation arrives. So
perhaps we can drop (d) and (e).

The point is, your history would be precisely reconstructed, and you
could get to say the final OK.

* There is another alternative. You should become an official
co-maintainer of CryptoPkg (using your Intel email address), and then
you could push your merges directly, after review. As I said, I trust
you, but I don't trust a setup where any maintainer can pull from any
contributor.

This would still depend on the maintainers to approve of a non-linear
git history.

Thanks
Laszlo

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Re: [edk2] EDK2 Setup & Configuration Issue

[Carsey, Jaben]

Jim,

You need to download or build the BaseTools that are used during the build.

Have you done that?

-Jaben

> -Original Message-
> From: edk2-devel [mailto:edk2-devel-boun...@lists.01.org] On Behalf Of Jim
> Slaughter
> Sent: Tuesday, March 08, 2016 2:21 PM
> To: Gao, Liming ; Tian, Feng ;
> edk2-devel@lists.01.org
> Subject: Re: [edk2] EDK2 Setup & Configuration Issue
> 
> Hello Liming:
> I am confused.I originally downloaded edk2-master and unzipped.This has one
> of the packages I am interested in building, embeddedpkg. This is where the
> directory is missing.
> I have since downloaded 2014 and 2015, all in separate directories, from
> sourceforge.The file structure looks different? I am after the Ffs code which 
> I
> think appears in embeddedpkg. I searched for the function
> FfsFindNextVolumne() and it is not located in 2014 or 2015. The function is in
> edk2-master.
> What is wrong? Am I not downloading the correct zip files?
> Jim S.
> 
> 
> On Thursday, March 3, 2016 8:21 PM, "Gao, Liming"
>  wrote:
> 
> 
>  #yiv2782034757 #yiv2782034757 -- _filtered #yiv2782034757 {font-
> family:Helvetica;panose-1:2 11 6 4 2 2 2 2 2 4;} _filtered #yiv2782034757
> {font-family:SimSun;panose-1:2 1 6 0 3 1 1 1 1 1;} _filtered #yiv2782034757
> {panose-1:2 4 5 3 5 4 6 3 2 4;} _filtered #yiv2782034757 {font-
> family:Calibri;panose-1:2 15 5 2 2 2 4 3 2 4;} _filtered #yiv2782034757
> {panose-1:2 1 6 0 3 1 1 1 1 1;}#yiv2782034757 #yiv2782034757
> p.yiv2782034757MsoNormal, #yiv2782034757 li.yiv2782034757MsoNormal,
> #yiv2782034757 div.yiv2782034757MsoNormal {margin:0in;margin-
> bottom:.0001pt;font-size:12.0pt;}#yiv2782034757 a:link, #yiv2782034757
> span.yiv2782034757MsoHyperlink {color:blue;text-
> decoration:underline;}#yiv2782034757 a:visited, #yiv2782034757
> span.yiv2782034757MsoHyperlinkFollowed {color:purple;text-
> decoration:underline;}#yiv2782034757 span.yiv2782034757EmailStyle17
> {color:#1F497D;}#yiv2782034757 .yiv2782034757MsoChpDefault {font-
> size:10.0pt;} _filtered #yiv2782034757 {margin:1.0in 1.0in 1.0in
> 1.0in;}#yiv2782034757 div.yiv2782034757WordSection1 {}#yiv2782034757
> Jim:   Yes. GitHub Edk2 project has not included BaseTools Binary. You need to
> download it from this linkhttps://github.com/tianocore/edk2-BaseTools-
> win32.git.      Or, you download full source code from UDK release
> http://www.tianocore.org/udk/udk2015/    Thanks Liming From: Jim Slaughter
> [mailto:jwslau...@yahoo.com]
> Sent: Friday, March 04, 2016 11:26 AM
> To: Gao, Liming; Tian, Feng; edk2-devel@lists.01.org
> Subject: Re: [edk2] EDK2 Setup & Configuration Issue    Hello,    I downloaded
> edk2 again, and its the 2014 stable version. The directory is still not
> there:    Z:\edk2\edk2-master>dir basetools\bin\win32
>  Volume in drive Z is vxbox
>  Volume Serial Number is 009A-9A03  Directory of Z:\edk2\edk2-
> master\basetools\bin File Not Found Z:\edk2\edk2-master>dir basetools\bin\
>  Volume in drive Z is vxbox
>  Volume Serial Number is 009A-9A03  Directory of Z:\edk2\edk2-
> master\basetools\bin 12/30/2015  02:28 PM      .
> 12/30/2015  02:29 PM      ..
> 12/30/2015  02:28 PM      Darwin-i386
> 12/30/2015  02:28 PM    69 externals.txt
> 12/30/2015  02:28 PM      CYGWIN_NT-5.1-i686
>    1 File(s) 69 bytes
>    4 Dir(s)  321,086,816,256 bytes free Z:\edk2\edk2-master>    
> Not
> sure how to proceed?    Jim S.       On Wednesday, March 2, 2016 8:08 PM,
> "Gao, Liming"  wrote:    If you download them to other
> place, please configure EDK_TOOLS_BIN env to point to it.
> 
> Here is wiki
> https://github.com/tianocore/tianocore.github.io/wiki/SourceForge-to-
> Github-Quick-Start.
> 
> > -Original Message-
> > From: edk2-devel [mailto:edk2-devel-boun...@lists.01.org] On Behalf Of
> > Tian, Feng
> > Sent: Thursday, March 03, 2016 11:31 AM
> > To: Jim Slaughter; edk2-devel@lists.01.org
> > Cc: Tian, Feng
> > Subject: Re: [edk2] EDK2 Setup & Configuration Issue
> >
> > Git https://github.com/tianocore/edk2-BaseTools-win32.git
> > Svn mirror https://svn.code.sf.net/p/edk2-toolbinaries/code/trunk/Win32
> >
> > Please download it to BaseTools\Bin\Win32 directory.
> >
> > Thanks
> > Feng
> >
> > -Original Message-
> > From: edk2-devel [mailto:edk2-devel-boun...@lists.01.org] On Behalf Of
> > Jim Slaughter
> > Sent: Thursday, March 3, 2016 11:18 AM
> > To: edk2-devel@lists.01.org
> > Subject: [edk2] EDK2 Setup & Configuration Issue
> >
> >  New to this mail group and EDK2.
> > I loaded edk2 from sourceforge. Need to build EmbeddedPkg.
> > I ran edksetup.bat from the command window and got the following
> > messages:
> > Z:\edk2\edk2-master>edksetup
> > !!! ERROR !!! Cannot find BaseTools Bin Win32!!!
> > Please check the directory Z:\edk2\edk2-master\BaseTools\Bin\Win32
> > Or configure EDK_TOOLS_BIN env to point Win32 directory.
> >
> > !!! WARNING !!! No CYGWIN_HOME set, gcc build may not be used !!!
> > Z:\edk2\edk

Re: [edk2] EDK2 Setup & Configuration Issue

[Jim Slaughter]

Hello Liming:
I am confused.I originally downloaded edk2-master and unzipped.This has one of 
the packages I am interested in building, embeddedpkg. This is where the 
directory is missing.
I have since downloaded 2014 and 2015, all in separate directories, from 
sourceforge.The file structure looks different? I am after the Ffs code which I 
think appears in embeddedpkg. I searched for the function FfsFindNextVolumne() 
and it is not located in 2014 or 2015. The function is in edk2-master.
What is wrong? Am I not downloading the correct zip files?
Jim S.
 

On Thursday, March 3, 2016 8:21 PM, "Gao, Liming"  
wrote:
 

 #yiv2782034757 #yiv2782034757 -- _filtered #yiv2782034757 
{font-family:Helvetica;panose-1:2 11 6 4 2 2 2 2 2 4;} _filtered #yiv2782034757 
{font-family:SimSun;panose-1:2 1 6 0 3 1 1 1 1 1;} _filtered #yiv2782034757 
{panose-1:2 4 5 3 5 4 6 3 2 4;} _filtered #yiv2782034757 
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{panose-1:2 1 6 0 3 1 1 1 1 1;}#yiv2782034757 #yiv2782034757 
p.yiv2782034757MsoNormal, #yiv2782034757 li.yiv2782034757MsoNormal, 
#yiv2782034757 div.yiv2782034757MsoNormal 
{margin:0in;margin-bottom:.0001pt;font-size:12.0pt;}#yiv2782034757 a:link, 
#yiv2782034757 span.yiv2782034757MsoHyperlink 
{color:blue;text-decoration:underline;}#yiv2782034757 a:visited, #yiv2782034757 
span.yiv2782034757MsoHyperlinkFollowed 
{color:purple;text-decoration:underline;}#yiv2782034757 
span.yiv2782034757EmailStyle17 {color:#1F497D;}#yiv2782034757 
.yiv2782034757MsoChpDefault {font-size:10.0pt;} _filtered #yiv2782034757 
{margin:1.0in 1.0in 1.0in 1.0in;}#yiv2782034757 div.yiv2782034757WordSection1 
{}#yiv2782034757 Jim:   Yes. GitHub Edk2 project has not included BaseTools 
Binary. You need to download it from this 
linkhttps://github.com/tianocore/edk2-BaseTools-win32.git.      Or, you 
download full source code from UDK release 
http://www.tianocore.org/udk/udk2015/    Thanks Liming From: Jim Slaughter 
[mailto:jwslau...@yahoo.com]
Sent: Friday, March 04, 2016 11:26 AM
To: Gao, Liming; Tian, Feng; edk2-devel@lists.01.org
Subject: Re: [edk2] EDK2 Setup & Configuration Issue    Hello,    I downloaded 
edk2 again, and its the 2014 stable version. The directory is still not there:  
  Z:\edk2\edk2-master>dir basetools\bin\win32
 Volume in drive Z is vxbox
 Volume Serial Number is 009A-9A03  Directory of 
Z:\edk2\edk2-master\basetools\bin File Not Found Z:\edk2\edk2-master>dir 
basetools\bin\
 Volume in drive Z is vxbox
 Volume Serial Number is 009A-9A03  Directory of 
Z:\edk2\edk2-master\basetools\bin 12/30/2015  02:28 PM      .
12/30/2015  02:29 PM      ..
12/30/2015  02:28 PM      Darwin-i386
12/30/2015  02:28 PM    69 externals.txt
12/30/2015  02:28 PM      CYGWIN_NT-5.1-i686
   1 File(s) 69 bytes
   4 Dir(s)  321,086,816,256 bytes free Z:\edk2\edk2-master>    Not 
sure how to proceed?    Jim S.       On Wednesday, March 2, 2016 8:08 PM, "Gao, 
Liming"  wrote:    If you download them to other place, 
please configure EDK_TOOLS_BIN env to point to it.

Here is wiki 
https://github.com/tianocore/tianocore.github.io/wiki/SourceForge-to-Github-Quick-Start.

> -Original Message-
> From: edk2-devel [mailto:edk2-devel-boun...@lists.01.org] On Behalf Of
> Tian, Feng
> Sent: Thursday, March 03, 2016 11:31 AM
> To: Jim Slaughter; edk2-devel@lists.01.org
> Cc: Tian, Feng
> Subject: Re: [edk2] EDK2 Setup & Configuration Issue
> 
> Git https://github.com/tianocore/edk2-BaseTools-win32.git
> Svn mirror https://svn.code.sf.net/p/edk2-toolbinaries/code/trunk/Win32
> 
> Please download it to BaseTools\Bin\Win32 directory.
> 
> Thanks
> Feng
> 
> -Original Message-
> From: edk2-devel [mailto:edk2-devel-boun...@lists.01.org] On Behalf Of
> Jim Slaughter
> Sent: Thursday, March 3, 2016 11:18 AM
> To: edk2-devel@lists.01.org
> Subject: [edk2] EDK2 Setup & Configuration Issue
> 
>  New to this mail group and EDK2.
> I loaded edk2 from sourceforge. Need to build EmbeddedPkg.
> I ran edksetup.bat from the command window and got the following
> messages:
> Z:\edk2\edk2-master>edksetup
> !!! ERROR !!! Cannot find BaseTools Bin Win32!!!
> Please check the directory Z:\edk2\edk2-master\BaseTools\Bin\Win32
> Or configure EDK_TOOLS_BIN env to point Win32 directory.
> 
> !!! WARNING !!! No CYGWIN_HOME set, gcc build may not be used !!!
> Z:\edk2\edk2-master>
> There is no Win32 directory? Did I not get something loaded? How do I
> proceed?
> Jim Slaughter
> ___
> edk2-devel mailing list
> edk2-devel@lists.01.org
> https://lists.01.org/mailman/listinfo/edk2-devel 
> ___
> edk2-devel mailing list
> edk2-devel@lists.01.org
> https://lists.01.org/mailman/listinfo/edk2-devel    

  
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Re: [edk2] [PATCH 3/3] BaseTools ConvertMasmToNasm: Support Python 3

[Carsey, Jaben]

> -Original Message-
> From: Justen, Jordan L
> Sent: Tuesday, March 08, 2016 11:37 AM
> To: Carsey, Jaben 
> Cc: edk2-devel@lists.01.org; Gao, Liming ; Bjorge, Erik
> C 
> Subject: Re: [edk2] [PATCH 3/3] BaseTools ConvertMasmToNasm: Support
> Python 3
> Importance: High
> 
> On 2016-03-08 06:22:28, Carsey, Jaben wrote:
> >
> >
> > > On Mar 7, 2016, at 7:16 PM, Jordan Justen 
> wrote:
> > >
> > > The script is updated to support both python 2.7 and python 3.
> > >
> > > Contributed-under: TianoCore Contribution Agreement 1.0
> > > Signed-off-by: Jordan Justen 
> > > Cc: Yonghong Zhu 
> > > Cc: Liming Gao 
> > > Cc: Erik Bjorge 
> > > ---
> > > BaseTools/Scripts/ConvertMasmToNasm.py | 87 ++---
> -
> > > 1 file changed, 46 insertions(+), 41 deletions(-)
> > >
> > > diff --git a/BaseTools/Scripts/ConvertMasmToNasm.py
> b/BaseTools/Scripts/ConvertMasmToNasm.py
> > > index 8288972..98e1fac 100755
> > > --- a/BaseTools/Scripts/ConvertMasmToNasm.py
> > > +++ b/BaseTools/Scripts/ConvertMasmToNasm.py
> > > @@ -12,15 +12,18 @@
> > > #  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER
> EXPRESS OR IMPLIED.
> > > #
> > >
> > > +from __future__ import print_function
> > > +
> > > #
> > > # Import Modules
> > > #
> > > import argparse
> > > +import io
> > > import os.path
> > > import re
> > > -import StringIO
> > > import subprocess
> > > import sys
> > > +from io import open
> >
> > Why import all of io, then import some again?
> >
> 
> This allows the code to call the function as open(), rather than
> io.open(). I can update all the calls to io.open() pretty easily
> instead.
> 
> -Jordan

I initially thought that you already edited most of the open() calls, but I see 
that is not true.  I'd say change to io.open, but not sure if it's important.

-Jaben

> 
> > >
> > >
> > > class UnsupportedConversion(Exception):
> > > @@ -152,12 +155,12 @@ class CommonUtils:
> > > (stdout, stderr) = p.communicate(pipeIn)
> > > if checkExitCode:
> > > if p.returncode != 0:
> > > -print 'command:', ' '.join(cmd)
> > > -print 'stdout:', stdout
> > > -print 'stderr:', stderr
> > > -print 'return:', p.returncode
> > > +print('command:', ' '.join(cmd))
> > > +print('stdout:', stdout)
> > > +print('stderr:', stderr)
> > > +print('return:', p.returncode)
> > > assert p.returncode == 0
> > > -return stdout
> > > +return stdout.decode('utf-8', 'ignore')
> > >
> > > def FileUpdated(self, path):
> > > if not self.git or not self.gitdir:
> > > @@ -181,7 +184,7 @@ class CommonUtils:
> > > return
> > >
> > > if not self.args.quiet:
> > > -print 'Committing: Conversion of', dst
> > > +print('Committing: Conversion of', dst)
> > >
> > > prefix = ' '.join(filter(lambda a: a, [pkg, module]))
> > > message = ''
> > > @@ -195,6 +198,7 @@ class CommonUtils:
> > > message += 'Contributed-under: TianoCore Contribution Agreement
> 1.0\n'
> > > assert(self.gitemail is not None)
> > > message += 'Signed-off-by: %s\n' % self.gitemail
> > > +message = message.encode('utf-8', 'ignore')
> > >
> > > cmd = ('git', 'commit', '-F', '-')
> > > self.RunAndCaptureOutput(cmd, pipeIn=message)
> > > @@ -226,21 +230,20 @@ class ConvertAsmFile(CommonUtils):
> > >
> > > self.inputFileBase = os.path.basename(self.inputFilename)
> > > self.outputFileBase = os.path.basename(self.outputFilename)
> > > -if self.outputFilename == '-' and not self.diff:
> > > -self.output = sys.stdout
> > > -else:
> > > -self.output = StringIO.StringIO()
> > > +self.output = io.BytesIO()
> > > if not self.args.quiet:
> > > dirpath, src = os.path.split(self.inputFilename)
> > > dirpath = self.RootRelative(dirpath)
> > > dst = os.path.basename(self.outputFilename)
> > > -print 'Converting:', dirpath, src, '->', dst
> > > +print('Converting:', dirpath, src, '->', dst)
> > > lines = open(self.inputFilename).readlines()
> > > self.Convert(lines)
> > > -if self.outputFilename == '-':
> > > -if self.diff:
> > > -sys.stdout.write(self.output.getvalue())
> > > -self.output.close()
> > > +if self.outputFilename == '-' and not self.diff:
> > > +output_data = self.output.getvalue()
> > > +if sys.version_info >= (3, 0):
> > > +output_data = output_data.decode('utf-8', 'ignore')
> > > +sys.stdout.write(output_data)
> > > +self.output.close()
> > > else:
> > > f = open(self.outputFilename, 'wb')
> > > f.write(self.output.getvalue())
> > > @@ -521,18 +524,18 @@ class Conv

Re: [edk2] [PATCH 1/3] BaseTools ConvertMasmToNasm: Set gitemail when git is not found

[Laszlo Ersek]

On 03/08/16 21:03, Jordan Justen wrote:
> On 2016-03-08 11:44:46, Laszlo Ersek wrote:
>> On 03/08/16 20:31, Jordan Justen wrote:
>>> On 2016-03-08 03:25:06, Laszlo Ersek wrote:
 On 03/08/16 04:15, Jordan Justen wrote:
> Fixes: https://github.com/tianocore/edk2/issues/63
> Contributed-under: TianoCore Contribution Agreement 1.0
> Signed-off-by: Jordan Justen 
> Cc: Yonghong Zhu 
> Cc: Liming Gao 
> Cc: Michael Kinney 
> ---
>  BaseTools/Scripts/ConvertMasmToNasm.py | 4 +++-
>  1 file changed, 3 insertions(+), 1 deletion(-)

 Can you add some explanation to the commit message? At the moment it
 doesn't tell me anything (and not much even after looking at issue #63).

 Just a suggestion. If you agree, it can be done when you commit the patch.

>>>
>>> Good point. How is this for an updated commit message?
>>>
>>> ===
>>>
>>> BaseTools ConvertMasmToNasm: Fix running script outside of a git tree
>>>
>>> The script previously would hit an exception if it was run outside of
>>> a git tree. This caused issues for users of the script if they are not
>>
>> s/are/were/?
>>
> 
> In this case they still are not using git.

Sure, but you also wrote "caused". I thought the tenses of those two
should match. I'm not a native speaker though -- sorry.

> 
>>> using git.
>>>
>>> The exception looked like:
>>>
>>> edk2/BaseTools/Scripts/ConvertMasmToNasm.py Version 0.01
>>> Traceback (most recent call last):
>>>   File "edk2/BaseTools/Scripts/ConvertMasmToNasm.py", line 986, in 
>>> ConvertAsmApp()
>>>   File "edk2/BaseTools/Scripts/ConvertMasmToNasm.py", line 984, in __init__
>>> ConvertAsmFile(src, dst, self)
>>>   File "edk2/BaseTools/Scripts/ConvertMasmToNasm.py", line 209, in __init__
>>> CommonUtils.__init__(self, clone)
>>>   File "edk2/BaseTools/Scripts/ConvertMasmToNasm.py", line 69, in __init__
>>> self.gitemail = clone.gitemail
>>> AttributeError: ConvertAsmApp instance has no attribute 'gitemail'
>>>
>>> Fixes: https://github.com/tianocore/edk2/issues/63
>>> Contributed-under: TianoCore Contribution Agreement 1.0
>>> Signed-off-by: Jordan Justen 
>>> Cc: Yonghong Zhu 
>>> Cc: Liming Gao 
>>> Cc: Michael Kinney 
>>>
>>> ===
>>
>> Much better, but I still feel dumb. (It's your fault, you know. :))
>>
>> Can you please mention why the script uses git if it is invoked in a git
>> tree? (Sorry if it should be obvious from someplace else.)
>>
> 
> The script can be used with a --git parameter which will automatically
> generate commits. (Similar to the ones that you pushed for me.)
> 
> The script can also be used in other modes which aren't so closely
> tied to git. For example, to just convert a single file.
> 
> For example, someone may not be using git, and they want to use the
> script to convert their MASM source code to NASM.

Makes sense. I thought I had run the script with --help; turns out I
hadn't. The help output explains the git dependency. I agree the commit
message you proposed is detailed enough.

Acked-by: Laszlo Ersek 

Thanks
Laszlo

> -Jordan
> 
>>
>>
>>>

> diff --git a/BaseTools/Scripts/ConvertMasmToNasm.py 
> b/BaseTools/Scripts/ConvertMasmToNasm.py
> index 7ad0bd2..2f0dd4f 100755
> --- a/BaseTools/Scripts/ConvertMasmToNasm.py
> +++ b/BaseTools/Scripts/ConvertMasmToNasm.py
> @@ -1,7 +1,7 @@
>  # @file ConvertMasmToNasm.py
>  # This script assists with conversion of MASM assembly syntax to NASM
>  #
> -#  Copyright (c) 2007 - 2014, Intel Corporation. All rights reserved.
> +#  Copyright (c) 2007 - 2016, Intel Corporation. All rights reserved.
>  #
>  #  This program and the accompanying materials
>  #  are licensed and made available under the terms and conditions of the 
> BSD License
> @@ -127,6 +127,7 @@ class CommonUtils:
>  while True:
>  path = os.path.split(lastpath)[0]
>  if path == lastpath:
> +self.gitemail = None
>  return
>  candidate = os.path.join(path, '.git')
>  if os.path.isdir(candidate):
> @@ -197,6 +198,7 @@ class CommonUtils:
>  message += '%s to %s\n' % (src, dst)
>  message += '\n'
>  message += 'Contributed-under: TianoCore Contribution Agreement 
> 1.0\n'
> +assert(self.gitemail is not None)
>  message += 'Signed-off-by: %s\n' % self.gitemail
>  
>  cmd = ('git', 'commit', '-F', '-')
>

>>

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Re: [edk2] [PATCH 1/3] BaseTools ConvertMasmToNasm: Set gitemail when git is not found

[Jordan Justen]

On 2016-03-08 11:44:46, Laszlo Ersek wrote:
> On 03/08/16 20:31, Jordan Justen wrote:
> > On 2016-03-08 03:25:06, Laszlo Ersek wrote:
> >> On 03/08/16 04:15, Jordan Justen wrote:
> >>> Fixes: https://github.com/tianocore/edk2/issues/63
> >>> Contributed-under: TianoCore Contribution Agreement 1.0
> >>> Signed-off-by: Jordan Justen 
> >>> Cc: Yonghong Zhu 
> >>> Cc: Liming Gao 
> >>> Cc: Michael Kinney 
> >>> ---
> >>>  BaseTools/Scripts/ConvertMasmToNasm.py | 4 +++-
> >>>  1 file changed, 3 insertions(+), 1 deletion(-)
> >>
> >> Can you add some explanation to the commit message? At the moment it
> >> doesn't tell me anything (and not much even after looking at issue #63).
> >>
> >> Just a suggestion. If you agree, it can be done when you commit the patch.
> >>
> > 
> > Good point. How is this for an updated commit message?
> > 
> > ===
> > 
> > BaseTools ConvertMasmToNasm: Fix running script outside of a git tree
> > 
> > The script previously would hit an exception if it was run outside of
> > a git tree. This caused issues for users of the script if they are not
> 
> s/are/were/?
> 

In this case they still are not using git.

> > using git.
> > 
> > The exception looked like:
> > 
> > edk2/BaseTools/Scripts/ConvertMasmToNasm.py Version 0.01
> > Traceback (most recent call last):
> >   File "edk2/BaseTools/Scripts/ConvertMasmToNasm.py", line 986, in 
> > ConvertAsmApp()
> >   File "edk2/BaseTools/Scripts/ConvertMasmToNasm.py", line 984, in __init__
> > ConvertAsmFile(src, dst, self)
> >   File "edk2/BaseTools/Scripts/ConvertMasmToNasm.py", line 209, in __init__
> > CommonUtils.__init__(self, clone)
> >   File "edk2/BaseTools/Scripts/ConvertMasmToNasm.py", line 69, in __init__
> > self.gitemail = clone.gitemail
> > AttributeError: ConvertAsmApp instance has no attribute 'gitemail'
> > 
> > Fixes: https://github.com/tianocore/edk2/issues/63
> > Contributed-under: TianoCore Contribution Agreement 1.0
> > Signed-off-by: Jordan Justen 
> > Cc: Yonghong Zhu 
> > Cc: Liming Gao 
> > Cc: Michael Kinney 
> > 
> > ===
> 
> Much better, but I still feel dumb. (It's your fault, you know. :))
> 
> Can you please mention why the script uses git if it is invoked in a git
> tree? (Sorry if it should be obvious from someplace else.)
> 

The script can be used with a --git parameter which will automatically
generate commits. (Similar to the ones that you pushed for me.)

The script can also be used in other modes which aren't so closely
tied to git. For example, to just convert a single file.

For example, someone may not be using git, and they want to use the
script to convert their MASM source code to NASM.

-Jordan

> 
> 
> > 
> >>
> >>> diff --git a/BaseTools/Scripts/ConvertMasmToNasm.py 
> >>> b/BaseTools/Scripts/ConvertMasmToNasm.py
> >>> index 7ad0bd2..2f0dd4f 100755
> >>> --- a/BaseTools/Scripts/ConvertMasmToNasm.py
> >>> +++ b/BaseTools/Scripts/ConvertMasmToNasm.py
> >>> @@ -1,7 +1,7 @@
> >>>  # @file ConvertMasmToNasm.py
> >>>  # This script assists with conversion of MASM assembly syntax to NASM
> >>>  #
> >>> -#  Copyright (c) 2007 - 2014, Intel Corporation. All rights reserved.
> >>> +#  Copyright (c) 2007 - 2016, Intel Corporation. All rights reserved.
> >>>  #
> >>>  #  This program and the accompanying materials
> >>>  #  are licensed and made available under the terms and conditions of the 
> >>> BSD License
> >>> @@ -127,6 +127,7 @@ class CommonUtils:
> >>>  while True:
> >>>  path = os.path.split(lastpath)[0]
> >>>  if path == lastpath:
> >>> +self.gitemail = None
> >>>  return
> >>>  candidate = os.path.join(path, '.git')
> >>>  if os.path.isdir(candidate):
> >>> @@ -197,6 +198,7 @@ class CommonUtils:
> >>>  message += '%s to %s\n' % (src, dst)
> >>>  message += '\n'
> >>>  message += 'Contributed-under: TianoCore Contribution Agreement 
> >>> 1.0\n'
> >>> +assert(self.gitemail is not None)
> >>>  message += 'Signed-off-by: %s\n' % self.gitemail
> >>>  
> >>>  cmd = ('git', 'commit', '-F', '-')
> >>>
> >>
> 
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Re: [edk2] [PATCH 1/3] BaseTools ConvertMasmToNasm: Set gitemail when git is not found

[Laszlo Ersek]

On 03/08/16 20:31, Jordan Justen wrote:
> On 2016-03-08 03:25:06, Laszlo Ersek wrote:
>> On 03/08/16 04:15, Jordan Justen wrote:
>>> Fixes: https://github.com/tianocore/edk2/issues/63
>>> Contributed-under: TianoCore Contribution Agreement 1.0
>>> Signed-off-by: Jordan Justen 
>>> Cc: Yonghong Zhu 
>>> Cc: Liming Gao 
>>> Cc: Michael Kinney 
>>> ---
>>>  BaseTools/Scripts/ConvertMasmToNasm.py | 4 +++-
>>>  1 file changed, 3 insertions(+), 1 deletion(-)
>>
>> Can you add some explanation to the commit message? At the moment it
>> doesn't tell me anything (and not much even after looking at issue #63).
>>
>> Just a suggestion. If you agree, it can be done when you commit the patch.
>>
> 
> Good point. How is this for an updated commit message?
> 
> ===
> 
> BaseTools ConvertMasmToNasm: Fix running script outside of a git tree
> 
> The script previously would hit an exception if it was run outside of
> a git tree. This caused issues for users of the script if they are not

s/are/were/?

> using git.
> 
> The exception looked like:
> 
> edk2/BaseTools/Scripts/ConvertMasmToNasm.py Version 0.01
> Traceback (most recent call last):
>   File "edk2/BaseTools/Scripts/ConvertMasmToNasm.py", line 986, in 
> ConvertAsmApp()
>   File "edk2/BaseTools/Scripts/ConvertMasmToNasm.py", line 984, in __init__
> ConvertAsmFile(src, dst, self)
>   File "edk2/BaseTools/Scripts/ConvertMasmToNasm.py", line 209, in __init__
> CommonUtils.__init__(self, clone)
>   File "edk2/BaseTools/Scripts/ConvertMasmToNasm.py", line 69, in __init__
> self.gitemail = clone.gitemail
> AttributeError: ConvertAsmApp instance has no attribute 'gitemail'
> 
> Fixes: https://github.com/tianocore/edk2/issues/63
> Contributed-under: TianoCore Contribution Agreement 1.0
> Signed-off-by: Jordan Justen 
> Cc: Yonghong Zhu 
> Cc: Liming Gao 
> Cc: Michael Kinney 
> 
> ===

Much better, but I still feel dumb. (It's your fault, you know. :))

Can you please mention why the script uses git if it is invoked in a git
tree? (Sorry if it should be obvious from someplace else.)

Thanks!
Laszlo


> 
>>
>>> diff --git a/BaseTools/Scripts/ConvertMasmToNasm.py 
>>> b/BaseTools/Scripts/ConvertMasmToNasm.py
>>> index 7ad0bd2..2f0dd4f 100755
>>> --- a/BaseTools/Scripts/ConvertMasmToNasm.py
>>> +++ b/BaseTools/Scripts/ConvertMasmToNasm.py
>>> @@ -1,7 +1,7 @@
>>>  # @file ConvertMasmToNasm.py
>>>  # This script assists with conversion of MASM assembly syntax to NASM
>>>  #
>>> -#  Copyright (c) 2007 - 2014, Intel Corporation. All rights reserved.
>>> +#  Copyright (c) 2007 - 2016, Intel Corporation. All rights reserved.
>>>  #
>>>  #  This program and the accompanying materials
>>>  #  are licensed and made available under the terms and conditions of the 
>>> BSD License
>>> @@ -127,6 +127,7 @@ class CommonUtils:
>>>  while True:
>>>  path = os.path.split(lastpath)[0]
>>>  if path == lastpath:
>>> +self.gitemail = None
>>>  return
>>>  candidate = os.path.join(path, '.git')
>>>  if os.path.isdir(candidate):
>>> @@ -197,6 +198,7 @@ class CommonUtils:
>>>  message += '%s to %s\n' % (src, dst)
>>>  message += '\n'
>>>  message += 'Contributed-under: TianoCore Contribution Agreement 
>>> 1.0\n'
>>> +assert(self.gitemail is not None)
>>>  message += 'Signed-off-by: %s\n' % self.gitemail
>>>  
>>>  cmd = ('git', 'commit', '-F', '-')
>>>
>>

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Re: [edk2] [PATCH 3/3] BaseTools ConvertMasmToNasm: Support Python 3

[Jordan Justen]

On 2016-03-08 06:22:28, Carsey, Jaben wrote:
> 
> 
> > On Mar 7, 2016, at 7:16 PM, Jordan Justen  wrote:
> > 
> > The script is updated to support both python 2.7 and python 3.
> > 
> > Contributed-under: TianoCore Contribution Agreement 1.0
> > Signed-off-by: Jordan Justen 
> > Cc: Yonghong Zhu 
> > Cc: Liming Gao 
> > Cc: Erik Bjorge 
> > ---
> > BaseTools/Scripts/ConvertMasmToNasm.py | 87 
> > ++
> > 1 file changed, 46 insertions(+), 41 deletions(-)
> > 
> > diff --git a/BaseTools/Scripts/ConvertMasmToNasm.py 
> > b/BaseTools/Scripts/ConvertMasmToNasm.py
> > index 8288972..98e1fac 100755
> > --- a/BaseTools/Scripts/ConvertMasmToNasm.py
> > +++ b/BaseTools/Scripts/ConvertMasmToNasm.py
> > @@ -12,15 +12,18 @@
> > #  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR 
> > IMPLIED.
> > #
> > 
> > +from __future__ import print_function
> > +
> > #
> > # Import Modules
> > #
> > import argparse
> > +import io
> > import os.path
> > import re
> > -import StringIO
> > import subprocess
> > import sys
> > +from io import open
> 
> Why import all of io, then import some again?
> 

This allows the code to call the function as open(), rather than
io.open(). I can update all the calls to io.open() pretty easily
instead.

-Jordan

> > 
> > 
> > class UnsupportedConversion(Exception):
> > @@ -152,12 +155,12 @@ class CommonUtils:
> > (stdout, stderr) = p.communicate(pipeIn)
> > if checkExitCode:
> > if p.returncode != 0:
> > -print 'command:', ' '.join(cmd)
> > -print 'stdout:', stdout
> > -print 'stderr:', stderr
> > -print 'return:', p.returncode
> > +print('command:', ' '.join(cmd))
> > +print('stdout:', stdout)
> > +print('stderr:', stderr)
> > +print('return:', p.returncode)
> > assert p.returncode == 0
> > -return stdout
> > +return stdout.decode('utf-8', 'ignore')
> > 
> > def FileUpdated(self, path):
> > if not self.git or not self.gitdir:
> > @@ -181,7 +184,7 @@ class CommonUtils:
> > return
> > 
> > if not self.args.quiet:
> > -print 'Committing: Conversion of', dst
> > +print('Committing: Conversion of', dst)
> > 
> > prefix = ' '.join(filter(lambda a: a, [pkg, module]))
> > message = ''
> > @@ -195,6 +198,7 @@ class CommonUtils:
> > message += 'Contributed-under: TianoCore Contribution Agreement 
> > 1.0\n'
> > assert(self.gitemail is not None)
> > message += 'Signed-off-by: %s\n' % self.gitemail
> > +message = message.encode('utf-8', 'ignore')
> > 
> > cmd = ('git', 'commit', '-F', '-')
> > self.RunAndCaptureOutput(cmd, pipeIn=message)
> > @@ -226,21 +230,20 @@ class ConvertAsmFile(CommonUtils):
> > 
> > self.inputFileBase = os.path.basename(self.inputFilename)
> > self.outputFileBase = os.path.basename(self.outputFilename)
> > -if self.outputFilename == '-' and not self.diff:
> > -self.output = sys.stdout
> > -else:
> > -self.output = StringIO.StringIO()
> > +self.output = io.BytesIO()
> > if not self.args.quiet:
> > dirpath, src = os.path.split(self.inputFilename)
> > dirpath = self.RootRelative(dirpath)
> > dst = os.path.basename(self.outputFilename)
> > -print 'Converting:', dirpath, src, '->', dst
> > +print('Converting:', dirpath, src, '->', dst)
> > lines = open(self.inputFilename).readlines()
> > self.Convert(lines)
> > -if self.outputFilename == '-':
> > -if self.diff:
> > -sys.stdout.write(self.output.getvalue())
> > -self.output.close()
> > +if self.outputFilename == '-' and not self.diff:
> > +output_data = self.output.getvalue()
> > +if sys.version_info >= (3, 0):
> > +output_data = output_data.decode('utf-8', 'ignore')
> > +sys.stdout.write(output_data)
> > +self.output.close()
> > else:
> > f = open(self.outputFilename, 'wb')
> > f.write(self.output.getvalue())
> > @@ -521,18 +524,18 @@ class ConvertAsmFile(CommonUtils):
> > return '.%d' % count
> > 
> > def EmitString(self, string):
> > -self.output.write(string)
> > +self.output.write(string.encode('utf-8', 'ignore'))
> > 
> > def EmitLineWithDiff(self, old, new):
> > newLine = (self.indent + new).rstrip()
> > if self.diff:
> > if old is None:
> > -print '+%s' % newLine
> > +print('+%s' % newLine)
> > elif newLine != old:
> > -print '-%s' % old
> > -print '+%s' % newLine
> > +print('-%s' % old)
> > +print('+%s' % newLine)
> >

Re: [edk2] [PATCH 1/3] BaseTools ConvertMasmToNasm: Set gitemail when git is not found

[Jordan Justen]

On 2016-03-08 03:25:06, Laszlo Ersek wrote:
> On 03/08/16 04:15, Jordan Justen wrote:
> > Fixes: https://github.com/tianocore/edk2/issues/63
> > Contributed-under: TianoCore Contribution Agreement 1.0
> > Signed-off-by: Jordan Justen 
> > Cc: Yonghong Zhu 
> > Cc: Liming Gao 
> > Cc: Michael Kinney 
> > ---
> >  BaseTools/Scripts/ConvertMasmToNasm.py | 4 +++-
> >  1 file changed, 3 insertions(+), 1 deletion(-)
> 
> Can you add some explanation to the commit message? At the moment it
> doesn't tell me anything (and not much even after looking at issue #63).
> 
> Just a suggestion. If you agree, it can be done when you commit the patch.
> 

Good point. How is this for an updated commit message?

===

BaseTools ConvertMasmToNasm: Fix running script outside of a git tree

The script previously would hit an exception if it was run outside of
a git tree. This caused issues for users of the script if they are not
using git.

The exception looked like:

edk2/BaseTools/Scripts/ConvertMasmToNasm.py Version 0.01
Traceback (most recent call last):
  File "edk2/BaseTools/Scripts/ConvertMasmToNasm.py", line 986, in 
ConvertAsmApp()
  File "edk2/BaseTools/Scripts/ConvertMasmToNasm.py", line 984, in __init__
ConvertAsmFile(src, dst, self)
  File "edk2/BaseTools/Scripts/ConvertMasmToNasm.py", line 209, in __init__
CommonUtils.__init__(self, clone)
  File "edk2/BaseTools/Scripts/ConvertMasmToNasm.py", line 69, in __init__
self.gitemail = clone.gitemail
AttributeError: ConvertAsmApp instance has no attribute 'gitemail'

Fixes: https://github.com/tianocore/edk2/issues/63
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jordan Justen 
Cc: Yonghong Zhu 
Cc: Liming Gao 
Cc: Michael Kinney 

===

> 
> > diff --git a/BaseTools/Scripts/ConvertMasmToNasm.py 
> > b/BaseTools/Scripts/ConvertMasmToNasm.py
> > index 7ad0bd2..2f0dd4f 100755
> > --- a/BaseTools/Scripts/ConvertMasmToNasm.py
> > +++ b/BaseTools/Scripts/ConvertMasmToNasm.py
> > @@ -1,7 +1,7 @@
> >  # @file ConvertMasmToNasm.py
> >  # This script assists with conversion of MASM assembly syntax to NASM
> >  #
> > -#  Copyright (c) 2007 - 2014, Intel Corporation. All rights reserved.
> > +#  Copyright (c) 2007 - 2016, Intel Corporation. All rights reserved.
> >  #
> >  #  This program and the accompanying materials
> >  #  are licensed and made available under the terms and conditions of the 
> > BSD License
> > @@ -127,6 +127,7 @@ class CommonUtils:
> >  while True:
> >  path = os.path.split(lastpath)[0]
> >  if path == lastpath:
> > +self.gitemail = None
> >  return
> >  candidate = os.path.join(path, '.git')
> >  if os.path.isdir(candidate):
> > @@ -197,6 +198,7 @@ class CommonUtils:
> >  message += '%s to %s\n' % (src, dst)
> >  message += '\n'
> >  message += 'Contributed-under: TianoCore Contribution Agreement 
> > 1.0\n'
> > +assert(self.gitemail is not None)
> >  message += 'Signed-off-by: %s\n' % self.gitemail
> >  
> >  cmd = ('git', 'commit', '-F', '-')
> > 
> 
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Re: [edk2] OpenSSL 1.1 status, and a worked example of why you should *NEVER* rebase

[Laszlo Ersek]

On 03/08/16 19:09, David Woodhouse wrote:
> On Tue, 2016-03-08 at 19:00 +0100, Laszlo Ersek wrote:

>> Or do you recommend that contributors be *allowed* to email pull
>> requests (alongside their patches), and if they do, their pull requests
>> be merged correctly?
> 
> Exactly this. They should be *allowed*, and for large submissions it
> should be *recommended* but not mandatory.

ACK

(Modulo consensus from other edk2 maintainers, of course.)

Thanks
Laszlo
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Re: [edk2] OpenSSL 1.1 status, and a worked example of why you should *NEVER* rebase

[David Woodhouse]

On Tue, 2016-03-08 at 19:00 +0100, Laszlo Ersek wrote:
> It is not about the branch that linus pulls from the subsystem
> maintainer.
> 
> It is about the patches that the subsystem maintainer picks up from
> emails of individual contributors.
> 
> Let me quote Linus's email back at you:

The better part to quote, I suspect, is :

    People can (and probably should) rebase their _private_ trees 
    (their own work). That's a _cleanup_. But never other peoples 
    code. That's a "destroy history"

> But we're not talking about the handling of pull requests. We're talking
> about patches that contributors send in email. Most individual
> contributors send patches in email *only*. This covers Linux (to my
> knowledge), QEMU (definitely), libvirt (I believe), and edk2.
> 
> Is your recommendation to *require* contirbutors to email pull requests,
> alongside their patches (which is "my" requirement)? 

Absolutely not. Especially for single patches, it doesn't make sense to
*require* a pull request. It's large submissions, especially new
features which interact with other things that might be in flux, and
especially where the new submission involves a large series of commits,
where pull requests are better.

And even then, if the submitter *chooses* to send their work as email
patches instead of a pull request — despite that being not such a good
idea — it should still be accepted as such.

That's OK. That history *is* correct — the submitter chose to use
email, and in doing so their work *was* broken from day 1 (in the cases
where it goes wrong).


> Or do you recommend that contributors be *allowed* to email pull
> requests (alongside their patches), and if they do, their pull requests
> be merged correctly?

Exactly this. They should be *allowed*, and for large submissions it
should be *recommended* but not mandatory.

-- 
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Re: [edk2] OpenSSL 1.1 status, and a worked example of why you should *NEVER* rebase

[Laszlo Ersek]

On 03/08/16 18:30, Jordan Justen wrote:

> At the subsystem level, I think even the kernel often relies on rebase
> along with format-patch/am to bring in patches rather than merges.

My point exactly.

> I don't think anyone has ruled out considering using merges once
> everyone is more comfortable with git.

My point exactly.

> Anyway, I'll brace for your cluebat pummeling. :)

My point exactly :)

Laszlo
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Re: [edk2] OpenSSL 1.1 status, and a worked example of why you should *NEVER* rebase

[Laszlo Ersek]

On 03/08/16 18:34, David Woodhouse wrote:
> On Tue, 2016-03-08 at 18:24 +0100, Laszlo Ersek wrote:
>> Here again I can only point to people who I consider my betters -- are
>> you suggesting that the QEMU workflow and the Linux workflow are utterly
>> wrong?
> 
> It is not "the Linux workflow". Linus will *eat* you if you rebase
> trees which you ask him to pull.
> 
> See http://www.mail-archive.com/dri-devel@lists.sourceforge.net/msg39091.html

I don't know how to formulate this any clearer than I did before.

It is not about the branch that linus pulls from the subsystem maintainer.

It is about the patches that the subsystem maintainer picks up from
emails of individual contributors.

Let me quote Linus's email back at you:

>   Notice that this really is about other peoples _history_, not about
>   other peoples _code_. If they sent stuff to you as an emailed patch,
>   and you applied it with "git am -s", then it's their code, but it's
>   _your_ history.
>
>   So you can go wild on the "git rebase" thing on it, even though you
>   didn't write the code, as long as the commit itself is your private
>   one.

It is not surprising that Linus will satisfy his appetite for
person-meat with a pull-requestor if said requestor rebases a branch
pending a pull. The commit to be pulled could even completely disappear
from the repo to pull from, if an aggressive git garbage collection
occurs after the rebase. The branch ref moves to a different commit hash
(due to the rebase), the old tip commit becomes dangling, and the gc
reaps it. Understandable.

But we're not talking about the handling of pull requests. We're talking
about patches that contributors send in email. Most individual
contributors send patches in email *only*. This covers Linux (to my
knowledge), QEMU (definitely), libvirt (I believe), and edk2.

Is your recommendation to *require* contirbutors to email pull requests,
alongside their patches (which is "my" requirement)? I think that would
go too far.

Or do you recommend that contributors be *allowed* to email pull
requests (alongside their patches), and if they do, their pull requests
be merged correctly? I'm fine with this if the Intel leadership / edk2
maintainers reaches a consensus that we don't insist on a linear history
any longer.

Thanks
Laszlo

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Re: [edk2] OpenSSL 1.1 status, and a worked example of why you should *NEVER* rebase

[David Woodhouse]

On Tue, 2016-03-08 at 09:30 -0800, Jordan Justen wrote:
> It sounds like the issue was a lack or gap in testing after the
> rebase.
> 
> I don't see that possibility going away just because you instead used
> merge. Especially if you consider resolving merge conflicts or other
> subtle errors that can creep in during a merge. (3a01358bdb03)

Right. The possibility of error doesn't go away. But the point is that
the history is preserved, and you can work out what happened. Instead
of ending up with a series of commits that apparently *never* worked.

> I've worked on projects that generally rebase, and still regularly
> have patchsets larger than 50 patches contributed.

I've worked on projects that don't use version control at all. Or which
use SVN. That doesn't make it a good idea.

> EDK II has been forced to live in the rebase mindset for years due to
> svn, and rebasing has not been a problem for us either.

The point in moving to git was to make things better. :)

> At the subsystem level, I think even the kernel often relies on rebase
> along with format-patch/am to bring in patches rather than merges.

As I said, don't let that get close to Linus or he'll eat you.

> So I disagree with the statement that rebase should *NEVER* be used.
> 
> For EDK II, we decided to start with a rebase model as it was a
> smaller step (conceptually) from svn. I'm not sure what happened in
> your rebase, but I think issues with this model will be no more
> frequent than issues with merges.
> 
> I don't think anyone has ruled out considering using merges once
> everyone is more comfortable with git.

Shouldn't we just switch to a proper usage model in one hit instead of
prolonging the pain?

That means fixing the CRLF thing ASAP too.

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Re: [edk2] OpenSSL 1.1 status, and a worked example of why you should *NEVER* rebase

[David Woodhouse]

On Tue, 2016-03-08 at 18:24 +0100, Laszlo Ersek wrote:
> Here again I can only point to people who I consider my betters -- are
> you suggesting that the QEMU workflow and the Linux workflow are utterly
> wrong?

It is not "the Linux workflow". Linus will *eat* you if you rebase
trees which you ask him to pull.

See http://www.mail-archive.com/dri-devel@lists.sourceforge.net/msg39091.html

-- 
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Re: [edk2] OpenSSL 1.1 status, and a worked example of why you should *NEVER* rebase

[Jordan Justen]

On 2016-03-08 04:12:32, David Woodhouse wrote:
> As of yesterday, *all* my patches had been merged into OpenSSL HEAD, in
> preparation for the OpenSSL 1.1 Beta 1 release this week.
> 
> There is only one more patch outstanding in my OpenSSL git tree.
> 
> Do those statements seem self-contradictory to you? Well, they're not
> quite. The patches *were* merged, but one was then reverted because it
> was utterly hosed and broke the build for fairly much *everyone* except
> the UEFI target. Bad dwmw2. No biscuit.
> 
> Why was it so broken? Well, it wasn't because I'm a *complete* muppet —
> it was correct when I first committed it, and I *tested* it in a native
> Linux build at that point too, as well as within the EDK2 build:
> http://git.infradead.org/users/dwmw2/openssl.git/commitdiff/929ae044cf7
> 
> However, a subsequent change in the upstream tree affected my patch:
> http://git.infradead.org/users/dwmw2/openssl.git/commitdiff/8731a4fcd#patch7
> 
> At some point I stupidly did a 'git pull --rebase' or something else
> that you should never do. In rebasing, I then failed to correctly fix
> up the changes, leaving it broken. I did a quick smoke-test rebuild
> (under EDK2 only, it seems) of the rebased tree, but didn't spot the
> error.
> 

It sounds like the issue was a lack or gap in testing after the
rebase.

I don't see that possibility going away just because you instead used
merge. Especially if you consider resolving merge conflicts or other
subtle errors that can creep in during a merge. (3a01358bdb03)

> Now, you can point out that this involved user error on my part when I
> did the rebase — but there are a number of problems with putting it
> down to that alone:
> 
> Firstly, it's a *predictable* error. You are *never* paying as much
> attention (to each and every commit) when you rebase, as when you
> create them in the first place. A process should not introduce
> *predictable* user errors.
> 
> In fact, although in *this* case it needed user error, there are cases
> where the tools *will* handle the merge automatically, but the code is
> still broken — you're not handling a new enum value that someone else
> has added in the upstream you're rebasing onto, or something like that.
> So the patch *applies* OK, but doesn't work. Or works most of the time
> but has broken corner cases.
> 
> And the most important thing is that when this happens during a rebase,
> the history — which is the single most important thing that a version
> control system exists to preserve! — is lost. When the breakage is
> discovered, there's no way to go back and see "it works  and then
> the merge  was broken". You just end up with a false history in
> which a given commit *never* worked.
> 
> Now, this one is a trivial (and recent) example, and it's easy enough
> to sort out and even *find* the original commit in my local tree which
> was subsequently discarded in the rebase. I'm using it because it was
> *me* who screwed up, and I can rant at length about the *practice* of
> rebasing, without making some other poor sod feel bad. We all screw up.
> The point is to use the tools to help us *cope*.
> 
> Although *this* one was simple, it *does* happen that more complex
> submissions also end up broken even by the time they are merged. And
> when that happens, if the tools are being used *properly*, you can
> *see* that it actually worked on the commit just *before* it was
> merged, and it was broken in the merge. And you can look for the cause
> — what changed in the upstream, between the version that the work was
> based on, and the tree it was merged into.
> 
> This isn't a purely theoretical concern. I've *done* this. And I've
> done it as a third party with little familiarity with the specific code
> in question, a *long* time after it was merged. Because it was only a
> relatively esoteric corner case that was broken, so nobody noticed —
> the kind of thing you think about while you're *writing* the code, and
> never again. Especially not while rebasing.
> 
> (Which is also an argument for decent unit tests, mind you, but that's
> a different rant and one on which I'm even *more* hypocritical.)
> 
> So please, DO NOT REBASE submissions onto the latest master. Use the
> tools properly as they were designed to be used — put any non-trivial
> work into a tree and send it as a pull request. Sure, send the patches
> to the list for review *too*, but that shouldn't be how they actually
> get in.
> 

I've worked on projects that generally rebase, and still regularly
have patchsets larger than 50 patches contributed.

EDK II has been forced to live in the rebase mindset for years due to
svn, and rebasing has not been a problem for us either.

At the subsystem level, I think even the kernel often relies on rebase
along with format-patch/am to bring in patches rather than merges.

So I disagree with the statement that rebase should *NEVER* be used.

For EDK II, we decided to start with a rebase model as it was a
smaller ste

Re: [edk2] OpenSSL 1.1 status, and a worked example of why you should *NEVER* rebase

[Laszlo Ersek]

On 03/08/16 17:23, David Woodhouse wrote:
> On Tue, 2016-03-08 at 14:44 +0100, Laszlo Ersek wrote:
>>
>> Using git is one thing, designing a workflow is another thing. Many
>> workflows exist. Some of them are not exclusively merge based (QEMU,
>> various subsystems of Linux), where sub-maintainers rebase and
>> occasionally rework patches that they queue for their next pull
>> request.
> 
> Ah, right.
> 
> This "break your history by rebasing" workflow is so utterly wrong that
> it didn't actually occur to me that it might have been *mandated*. I
> assumed it was just a mistake by people who were not really familiar
> with the tools and how to use them correctly.

Here again I can only point to people who I consider my betters -- are
you suggesting that the QEMU workflow and the Linux workflow are utterly
wrong? As I said, QEMU sub-maintainers and (some) Linux sub-maintainers
keep *queues* of patches. Unstable branches with patches they apply and
rebase. Are they all mistaken?

> I thought I might need to overcome some resistance from those who can't
> drag themselves out of the 20th century mindset of version control with
> purely linear history, and needed to be shown the *reasons* why we
> should actually do things properly. But I didn't expect there'd be a
> mandate to do it wrong.

I don't recall any mandate. I recall looking for examples and finding
QEMU and Linux real quick. Their lowest levels of patch flow don't
differ from ours; individual contributors practically never send pull
requests. They send patches.

> Do you have a reason to believe that there *is* such a mandate, rather
> than a simple error? If so, I'll go and apply the cluebat there in a
> more targeted fashion :)

I think you should demonstrate one of the following:

- Our (well, "my") interpretation of the lowest levels of patch flow in
  QEMU and Linux is wrong.
- Or, QEMU and Linux sub-maintainers are mistaken, and it's our fault
  to have followed their example.

Should we invite some of these maintainers to this discussion?

Thanks
Laszlo
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Re: [edk2] OpenSSL 1.1 status, and a worked example of why you should *NEVER* rebase

[David Woodhouse]

On Tue, 2016-03-08 at 14:44 +0100, Laszlo Ersek wrote:
> 
> Using git is one thing, designing a workflow is another thing. Many
> workflows exist. Some of them are not exclusively merge based (QEMU,
> various subsystems of Linux), where sub-maintainers rebase and
> occasionally rework patches that they queue for their next pull
> request.

Ah, right.

This "break your history by rebasing" workflow is so utterly wrong that
it didn't actually occur to me that it might have been *mandated*. I
assumed it was just a mistake by people who were not really familiar
with the tools and how to use them correctly.

I thought I might need to overcome some resistance from those who can't
drag themselves out of the 20th century mindset of version control with
purely linear history, and needed to be shown the *reasons* why we
should actually do things properly. But I didn't expect there'd be a
mandate to do it wrong.

Do you have a reason to believe that there *is* such a mandate, rather
than a simple error? If so, I'll go and apply the cluebat there in a
more targeted fashion :)

-- 
David WoodhouseOpen Source Technology Centre
david.woodho...@intel.com  Intel Corporation



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Re: [edk2] [PATCH v2 0/6] OvmfPkg: enable PCIe on Q35

[Laszlo Ersek]

On 03/08/16 16:26, Gabriel L. Somlo wrote:
> On Tue, Mar 08, 2016 at 03:19:58PM +0100, Laszlo Ersek wrote:
>> Version 2 of .
>>
>> News for v2: following Gerd's advice, I inserted a new patch (as #2),
>> and reworked parts of patch #3. The changes are marked in detail on
>> those patches.
>>
>> Review & testing feedback: Jordan should please review patches #2 and
>> #3, and Gabriel and Michał should please retest the series in their
>> usual environments. I also ran my own routine, successfully.
> 
> Same as before (on top of Reza's remaining osx specific patches I've
> been rebasing, on q35, spanning osx 10.[9,10,11]):
> 
> Tested-by: Gabriel Somlo 
> 
> Cheers,
> --Gabriel

Thanks Gabriel, much appreciated!
Laszlo

>> Public branch: .
>>
>> Cc: Gabriel Somlo 
>> Cc: Gerd Hoffmann 
>> Cc: Jordan Justen 
>> Cc: Marcel Apfelbaum 
>> Cc: Michał Zegan 
>>
>> Thanks
>> Laszlo
>>
>> Laszlo Ersek (6):
>>   OvmfPkg: IndustryStandard/Q35MchIch9.h: add PCIEXBAR macros
>>   OvmfPkg: PlatformPei: lower the 32-bit PCI MMIO base to 2GB on Q35
>>   OvmfPkg: PlatformPei: enable PCIEXBAR (aka MMCONFIG / ECAM) on Q35
>>   OvmfPkg: add DxePciLibI440FxQ35
>>   OvmfPkg: match PCI config access to machine type (if not
>> USE_OLD_PCI_HOST)
>>   OvmfPkg: PciHostBridgeLib: permit access to the full extended config
>> space
>>
>>  OvmfPkg/OvmfPkgIa32.dsc 
>>   |  29 
>>  OvmfPkg/OvmfPkgIa32X64.dsc  
>>   |  29 
>>  OvmfPkg/OvmfPkgX64.dsc  
>>   |  29 
>>  OvmfPkg/Library/DxePciLibI440FxQ35/DxePciLibI440FxQ35.inf   
>>   |  47 ++
>>  OvmfPkg/Library/PciHostBridgeLib/PciHostBridgeLib.inf   
>>   |   1 +
>>  OvmfPkg/PlatformPei/PlatformPei.inf 
>>   |   3 +
>>  OvmfPkg/Include/IndustryStandard/Q35MchIch9.h   
>>   |   8 +
>>  {MdePkg/Library/BasePciLibCf8 => 
>> OvmfPkg/Library/DxePciLibI440FxQ35}/PciLib.c | 161 +++-
>>  OvmfPkg/Library/PciHostBridgeLib/PciHostBridgeLib.c 
>>   |   4 +-
>>  OvmfPkg/PlatformPei/Platform.c  
>>   |  82 +-
>>  10 files changed, 352 insertions(+), 41 deletions(-)
>>  create mode 100644 OvmfPkg/Library/DxePciLibI440FxQ35/DxePciLibI440FxQ35.inf
>>  copy {MdePkg/Library/BasePciLibCf8 => 
>> OvmfPkg/Library/DxePciLibI440FxQ35}/PciLib.c (85%)
>>
>> -- 
>> 1.8.3.1
>>

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Re: [edk2] [PATCH v2 0/6] OvmfPkg: enable PCIe on Q35

[Gabriel L. Somlo]

On Tue, Mar 08, 2016 at 03:19:58PM +0100, Laszlo Ersek wrote:
> Version 2 of .
> 
> News for v2: following Gerd's advice, I inserted a new patch (as #2),
> and reworked parts of patch #3. The changes are marked in detail on
> those patches.
> 
> Review & testing feedback: Jordan should please review patches #2 and
> #3, and Gabriel and Michał should please retest the series in their
> usual environments. I also ran my own routine, successfully.

Same as before (on top of Reza's remaining osx specific patches I've
been rebasing, on q35, spanning osx 10.[9,10,11]):

Tested-by: Gabriel Somlo 

Cheers,
--Gabriel

> Public branch: .
> 
> Cc: Gabriel Somlo 
> Cc: Gerd Hoffmann 
> Cc: Jordan Justen 
> Cc: Marcel Apfelbaum 
> Cc: Michał Zegan 
> 
> Thanks
> Laszlo
> 
> Laszlo Ersek (6):
>   OvmfPkg: IndustryStandard/Q35MchIch9.h: add PCIEXBAR macros
>   OvmfPkg: PlatformPei: lower the 32-bit PCI MMIO base to 2GB on Q35
>   OvmfPkg: PlatformPei: enable PCIEXBAR (aka MMCONFIG / ECAM) on Q35
>   OvmfPkg: add DxePciLibI440FxQ35
>   OvmfPkg: match PCI config access to machine type (if not
> USE_OLD_PCI_HOST)
>   OvmfPkg: PciHostBridgeLib: permit access to the full extended config
> space
> 
>  OvmfPkg/OvmfPkgIa32.dsc  
>  |  29 
>  OvmfPkg/OvmfPkgIa32X64.dsc   
>  |  29 
>  OvmfPkg/OvmfPkgX64.dsc   
>  |  29 
>  OvmfPkg/Library/DxePciLibI440FxQ35/DxePciLibI440FxQ35.inf
>  |  47 ++
>  OvmfPkg/Library/PciHostBridgeLib/PciHostBridgeLib.inf
>  |   1 +
>  OvmfPkg/PlatformPei/PlatformPei.inf  
>  |   3 +
>  OvmfPkg/Include/IndustryStandard/Q35MchIch9.h
>  |   8 +
>  {MdePkg/Library/BasePciLibCf8 => 
> OvmfPkg/Library/DxePciLibI440FxQ35}/PciLib.c | 161 +++-
>  OvmfPkg/Library/PciHostBridgeLib/PciHostBridgeLib.c  
>  |   4 +-
>  OvmfPkg/PlatformPei/Platform.c   
>  |  82 +-
>  10 files changed, 352 insertions(+), 41 deletions(-)
>  create mode 100644 OvmfPkg/Library/DxePciLibI440FxQ35/DxePciLibI440FxQ35.inf
>  copy {MdePkg/Library/BasePciLibCf8 => 
> OvmfPkg/Library/DxePciLibI440FxQ35}/PciLib.c (85%)
> 
> -- 
> 1.8.3.1
> 
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Re: [edk2] [PATCH 3/3] BaseTools ConvertMasmToNasm: Support Python 3

[Carsey, Jaben]

> On Mar 7, 2016, at 7:16 PM, Jordan Justen  wrote:
> 
> The script is updated to support both python 2.7 and python 3.
> 
> Contributed-under: TianoCore Contribution Agreement 1.0
> Signed-off-by: Jordan Justen 
> Cc: Yonghong Zhu 
> Cc: Liming Gao 
> Cc: Erik Bjorge 
> ---
> BaseTools/Scripts/ConvertMasmToNasm.py | 87 ++
> 1 file changed, 46 insertions(+), 41 deletions(-)
> 
> diff --git a/BaseTools/Scripts/ConvertMasmToNasm.py 
> b/BaseTools/Scripts/ConvertMasmToNasm.py
> index 8288972..98e1fac 100755
> --- a/BaseTools/Scripts/ConvertMasmToNasm.py
> +++ b/BaseTools/Scripts/ConvertMasmToNasm.py
> @@ -12,15 +12,18 @@
> #  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR 
> IMPLIED.
> #
> 
> +from __future__ import print_function
> +
> #
> # Import Modules
> #
> import argparse
> +import io
> import os.path
> import re
> -import StringIO
> import subprocess
> import sys
> +from io import open

Why import all of io, then import some again?

> 
> 
> class UnsupportedConversion(Exception):
> @@ -152,12 +155,12 @@ class CommonUtils:
> (stdout, stderr) = p.communicate(pipeIn)
> if checkExitCode:
> if p.returncode != 0:
> -print 'command:', ' '.join(cmd)
> -print 'stdout:', stdout
> -print 'stderr:', stderr
> -print 'return:', p.returncode
> +print('command:', ' '.join(cmd))
> +print('stdout:', stdout)
> +print('stderr:', stderr)
> +print('return:', p.returncode)
> assert p.returncode == 0
> -return stdout
> +return stdout.decode('utf-8', 'ignore')
> 
> def FileUpdated(self, path):
> if not self.git or not self.gitdir:
> @@ -181,7 +184,7 @@ class CommonUtils:
> return
> 
> if not self.args.quiet:
> -print 'Committing: Conversion of', dst
> +print('Committing: Conversion of', dst)
> 
> prefix = ' '.join(filter(lambda a: a, [pkg, module]))
> message = ''
> @@ -195,6 +198,7 @@ class CommonUtils:
> message += 'Contributed-under: TianoCore Contribution Agreement 1.0\n'
> assert(self.gitemail is not None)
> message += 'Signed-off-by: %s\n' % self.gitemail
> +message = message.encode('utf-8', 'ignore')
> 
> cmd = ('git', 'commit', '-F', '-')
> self.RunAndCaptureOutput(cmd, pipeIn=message)
> @@ -226,21 +230,20 @@ class ConvertAsmFile(CommonUtils):
> 
> self.inputFileBase = os.path.basename(self.inputFilename)
> self.outputFileBase = os.path.basename(self.outputFilename)
> -if self.outputFilename == '-' and not self.diff:
> -self.output = sys.stdout
> -else:
> -self.output = StringIO.StringIO()
> +self.output = io.BytesIO()
> if not self.args.quiet:
> dirpath, src = os.path.split(self.inputFilename)
> dirpath = self.RootRelative(dirpath)
> dst = os.path.basename(self.outputFilename)
> -print 'Converting:', dirpath, src, '->', dst
> +print('Converting:', dirpath, src, '->', dst)
> lines = open(self.inputFilename).readlines()
> self.Convert(lines)
> -if self.outputFilename == '-':
> -if self.diff:
> -sys.stdout.write(self.output.getvalue())
> -self.output.close()
> +if self.outputFilename == '-' and not self.diff:
> +output_data = self.output.getvalue()
> +if sys.version_info >= (3, 0):
> +output_data = output_data.decode('utf-8', 'ignore')
> +sys.stdout.write(output_data)
> +self.output.close()
> else:
> f = open(self.outputFilename, 'wb')
> f.write(self.output.getvalue())
> @@ -521,18 +524,18 @@ class ConvertAsmFile(CommonUtils):
> return '.%d' % count
> 
> def EmitString(self, string):
> -self.output.write(string)
> +self.output.write(string.encode('utf-8', 'ignore'))
> 
> def EmitLineWithDiff(self, old, new):
> newLine = (self.indent + new).rstrip()
> if self.diff:
> if old is None:
> -print '+%s' % newLine
> +print('+%s' % newLine)
> elif newLine != old:
> -print '-%s' % old
> -print '+%s' % newLine
> +print('-%s' % old)
> +print('+%s' % newLine)
> else:
> -print '', newLine
> +print('', newLine)
> if newLine != '':
> self.newAsmEmptyLineCount = 0
> self.EmitString(newLine + '\r\n')
> @@ -565,7 +568,7 @@ class ConvertAsmFile(CommonUtils):
> if emitNewLine:
> self.EmitLine(newLine.rstrip())
> elif self.diff:
> -print '-%s' % self.originalLine
> +print('-%s' % self.originalLine)
> 
> 

[edk2] [PATCH v2 0/6] OvmfPkg: enable PCIe on Q35

[Laszlo Ersek]

Version 2 of .

News for v2: following Gerd's advice, I inserted a new patch (as #2),
and reworked parts of patch #3. The changes are marked in detail on
those patches.

Review & testing feedback: Jordan should please review patches #2 and
#3, and Gabriel and Michał should please retest the series in their
usual environments. I also ran my own routine, successfully.

Public branch: .

Cc: Gabriel Somlo 
Cc: Gerd Hoffmann 
Cc: Jordan Justen 
Cc: Marcel Apfelbaum 
Cc: Michał Zegan 

Thanks
Laszlo

Laszlo Ersek (6):
  OvmfPkg: IndustryStandard/Q35MchIch9.h: add PCIEXBAR macros
  OvmfPkg: PlatformPei: lower the 32-bit PCI MMIO base to 2GB on Q35
  OvmfPkg: PlatformPei: enable PCIEXBAR (aka MMCONFIG / ECAM) on Q35
  OvmfPkg: add DxePciLibI440FxQ35
  OvmfPkg: match PCI config access to machine type (if not
USE_OLD_PCI_HOST)
  OvmfPkg: PciHostBridgeLib: permit access to the full extended config
space

 OvmfPkg/OvmfPkgIa32.dsc   
|  29 
 OvmfPkg/OvmfPkgIa32X64.dsc
|  29 
 OvmfPkg/OvmfPkgX64.dsc
|  29 
 OvmfPkg/Library/DxePciLibI440FxQ35/DxePciLibI440FxQ35.inf 
|  47 ++
 OvmfPkg/Library/PciHostBridgeLib/PciHostBridgeLib.inf 
|   1 +
 OvmfPkg/PlatformPei/PlatformPei.inf   
|   3 +
 OvmfPkg/Include/IndustryStandard/Q35MchIch9.h 
|   8 +
 {MdePkg/Library/BasePciLibCf8 => OvmfPkg/Library/DxePciLibI440FxQ35}/PciLib.c 
| 161 +++-
 OvmfPkg/Library/PciHostBridgeLib/PciHostBridgeLib.c   
|   4 +-
 OvmfPkg/PlatformPei/Platform.c
|  82 +-
 10 files changed, 352 insertions(+), 41 deletions(-)
 create mode 100644 OvmfPkg/Library/DxePciLibI440FxQ35/DxePciLibI440FxQ35.inf
 copy {MdePkg/Library/BasePciLibCf8 => 
OvmfPkg/Library/DxePciLibI440FxQ35}/PciLib.c (85%)

-- 
1.8.3.1

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[edk2] [PATCH v2 6/6] OvmfPkg: PciHostBridgeLib: permit access to the full extended config space

[Laszlo Ersek]

By now OVMF makes MdeModulePkg/Bus/Pci/PciHostBridgeDxe go through
MMCONFIG (when running on Q35). Enable the driver to address each B/D/F's
config space up to and including offset 0xFFF.

Cc: Gabriel Somlo 
Cc: Gerd Hoffmann 
Cc: Jordan Justen 
Cc: Marcel Apfelbaum 
Cc: Michał Zegan 
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Laszlo Ersek 
Reviewed-by: Jordan Justen 
---
 OvmfPkg/Library/PciHostBridgeLib/PciHostBridgeLib.inf | 1 +
 OvmfPkg/Library/PciHostBridgeLib/PciHostBridgeLib.c   | 4 +++-
 2 files changed, 4 insertions(+), 1 deletion(-)

diff --git a/OvmfPkg/Library/PciHostBridgeLib/PciHostBridgeLib.inf 
b/OvmfPkg/Library/PciHostBridgeLib/PciHostBridgeLib.inf
index 5467fff8aa15..bbec74645c83 100644
--- a/OvmfPkg/Library/PciHostBridgeLib/PciHostBridgeLib.inf
+++ b/OvmfPkg/Library/PciHostBridgeLib/PciHostBridgeLib.inf
@@ -51,3 +51,4 @@ [Pcd]
   gUefiOvmfPkgTokenSpaceGuid.PcdPciIoSize
   gUefiOvmfPkgTokenSpaceGuid.PcdPciMmio32Base
   gUefiOvmfPkgTokenSpaceGuid.PcdPciMmio32Size
+  gUefiOvmfPkgTokenSpaceGuid.PcdOvmfHostBridgePciDevId
diff --git a/OvmfPkg/Library/PciHostBridgeLib/PciHostBridgeLib.c 
b/OvmfPkg/Library/PciHostBridgeLib/PciHostBridgeLib.c
index 582e87dd9ac0..3e02778492a8 100644
--- a/OvmfPkg/Library/PciHostBridgeLib/PciHostBridgeLib.c
+++ b/OvmfPkg/Library/PciHostBridgeLib/PciHostBridgeLib.c
@@ -16,6 +16,7 @@
 #include 
 
 #include 
+#include 
 
 #include 
 #include 
@@ -139,7 +140,8 @@ InitRootBridge (
   RootBus->Mem.Limit = PcdGet64 (PcdPciMmio32Base) +
(PcdGet64 (PcdPciMmio32Size) - 1);
 
-  RootBus->NoExtendedConfigSpace = TRUE;
+  RootBus->NoExtendedConfigSpace = (PcdGet16 (PcdOvmfHostBridgePciDevId) !=
+INTEL_Q35_MCH_DEVICE_ID);
 
   DevicePath = AllocateCopyPool (sizeof mRootBridgeDevicePathTemplate,
  &mRootBridgeDevicePathTemplate);
-- 
1.8.3.1

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[edk2] [PATCH v2 5/6] OvmfPkg: match PCI config access to machine type (if not USE_OLD_PCI_HOST)

[Laszlo Ersek]

If USE_OLD_PCI_HOST is FALSE, then we switch all executable module types
supported by DxePciLibI440FxQ35 to the following library instance stack:

  BasePciSegmentLibPci  [class: PciSegmentLib]
DxePciLibI440FxQ35  [class: PciLib]
  BasePciCf8Lib [class: PciCf8Lib]
  BasePciExpressLib [class: PciExpressLib]

Every module will select 0xCF8 vs. ECAM based on the OVMF platform type
(i440fx or Q35). Notably, MdeModulePkg/Bus/Pci/PciHostBridgeDxe is among
the affected drivers.

The BasePciExpressLib instance is where the PcdPciExpressBaseAddress PCD
fills its original role.

Cc: Gabriel Somlo 
Cc: Gerd Hoffmann 
Cc: Jordan Justen 
Cc: Marcel Apfelbaum 
Cc: Michał Zegan 
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Laszlo Ersek 
Reviewed-by: Jordan Justen 
---
 OvmfPkg/OvmfPkgIa32.dsc| 21 
 OvmfPkg/OvmfPkgIa32X64.dsc | 21 
 OvmfPkg/OvmfPkgX64.dsc | 21 
 3 files changed, 63 insertions(+)

diff --git a/OvmfPkg/OvmfPkgIa32.dsc b/OvmfPkg/OvmfPkgIa32.dsc
index aae1972950ee..2635992ac7cb 100644
--- a/OvmfPkg/OvmfPkgIa32.dsc
+++ b/OvmfPkg/OvmfPkgIa32.dsc
@@ -82,6 +82,9 @@ [LibraryClasses]
   
DxeServicesTableLib|MdePkg/Library/DxeServicesTableLib/DxeServicesTableLib.inf
   
PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.inf
   PciCf8Lib|MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf
+!if $(USE_OLD_PCI_HOST) == FALSE
+  PciExpressLib|MdePkg/Library/BasePciExpressLib/BasePciExpressLib.inf
+!endif
   PciLib|MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf
   PciSegmentLib|MdePkg/Library/BasePciSegmentLibPci/BasePciSegmentLibPci.inf
   IoLib|MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf
@@ -242,6 +245,9 @@ [LibraryClasses.common.DXE_RUNTIME_DRIVER]
 !if $(SECURE_BOOT_ENABLE) == TRUE
   BaseCryptLib|CryptoPkg/Library/BaseCryptLib/RuntimeCryptLib.inf
 !endif
+!if $(USE_OLD_PCI_HOST) == FALSE
+  PciLib|OvmfPkg/Library/DxePciLibI440FxQ35/DxePciLibI440FxQ35.inf
+!endif
 
 [LibraryClasses.common.UEFI_DRIVER]
   PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf
@@ -256,6 +262,9 @@ [LibraryClasses.common.UEFI_DRIVER]
   DebugLib|OvmfPkg/Library/PlatformDebugLibIoPort/PlatformDebugLibIoPort.inf
 !endif
   UefiScsiLib|MdePkg/Library/UefiScsiLib/UefiScsiLib.inf
+!if $(USE_OLD_PCI_HOST) == FALSE
+  PciLib|OvmfPkg/Library/DxePciLibI440FxQ35/DxePciLibI440FxQ35.inf
+!endif
 
 [LibraryClasses.common.DXE_DRIVER]
   PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf
@@ -287,6 +296,9 @@ [LibraryClasses.common.DXE_DRIVER]
 !if $(SECURE_BOOT_ENABLE) == TRUE
   FileExplorerLib|MdeModulePkg/Library/FileExplorerLib/FileExplorerLib.inf
 !endif
+!if $(USE_OLD_PCI_HOST) == FALSE
+  PciLib|OvmfPkg/Library/DxePciLibI440FxQ35/DxePciLibI440FxQ35.inf
+!endif
 
 [LibraryClasses.common.UEFI_APPLICATION]
   PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf
@@ -298,6 +310,9 @@ [LibraryClasses.common.UEFI_APPLICATION]
 !else
   DebugLib|OvmfPkg/Library/PlatformDebugLibIoPort/PlatformDebugLibIoPort.inf
 !endif
+!if $(USE_OLD_PCI_HOST) == FALSE
+  PciLib|OvmfPkg/Library/DxePciLibI440FxQ35/DxePciLibI440FxQ35.inf
+!endif
 
 [LibraryClasses.common.DXE_SMM_DRIVER]
   PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf
@@ -317,6 +332,9 @@ [LibraryClasses.common.DXE_SMM_DRIVER]
   DebugAgentLib|SourceLevelDebugPkg/Library/DebugAgent/SmmDebugAgentLib.inf
 !endif
   BaseCryptLib|CryptoPkg/Library/BaseCryptLib/SmmCryptLib.inf
+!if $(USE_OLD_PCI_HOST) == FALSE
+  PciLib|OvmfPkg/Library/DxePciLibI440FxQ35/DxePciLibI440FxQ35.inf
+!endif
 
 [LibraryClasses.common.SMM_CORE]
   PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf
@@ -332,6 +350,9 @@ [LibraryClasses.common.SMM_CORE]
 !else
   DebugLib|OvmfPkg/Library/PlatformDebugLibIoPort/PlatformDebugLibIoPort.inf
 !endif
+!if $(USE_OLD_PCI_HOST) == FALSE
+  PciLib|OvmfPkg/Library/DxePciLibI440FxQ35/DxePciLibI440FxQ35.inf
+!endif
 
 

 #
diff --git a/OvmfPkg/OvmfPkgIa32X64.dsc b/OvmfPkg/OvmfPkgIa32X64.dsc
index 0422dda09fbe..e9ffcb418522 100644
--- a/OvmfPkg/OvmfPkgIa32X64.dsc
+++ b/OvmfPkg/OvmfPkgIa32X64.dsc
@@ -87,6 +87,9 @@ [LibraryClasses]
   
DxeServicesTableLib|MdePkg/Library/DxeServicesTableLib/DxeServicesTableLib.inf
   
PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.inf
   PciCf8Lib|MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf
+!if $(USE_OLD_PCI_HOST) == FALSE
+  PciExpressLib|MdePkg/Library/BasePciExpressLib/BasePciExpressLib.inf
+!endif
   PciLib|MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf
   PciSegmentLib|MdePkg/Library/BasePciSegmentLibPci/BasePciSegmentLibPci.inf
   IoLib|MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf
@@ -247,6 +250,9 @@ [LibraryClasses.common.DXE_RUNTIME_DRIVER]
 !if $(SECURE_BOOT_ENABLE) == TRUE
   BaseCryptLib|CryptoPkg/Library/BaseCryptLib/RuntimeCryptLib.inf
 !endif
+!if $(USE_OLD_PCI_HOST) == FALSE
+  PciLib|OvmfPkg/

[edk2] [PATCH v2 3/6] OvmfPkg: PlatformPei: enable PCIEXBAR (aka MMCONFIG / ECAM) on Q35

[Laszlo Ersek]

The comments in the code should speak for themselves; here we note only
two facts:

- The PCI config space writes (to the PCIEXBAR register) are performed
  using the 0xCF8 / 0xCFC IO ports, by virtue of PciLib being resolved to
  BasePciLibCf8. (This library resolution will permanently remain in place
  for the PEI phase.)

- Since PCIEXBAR counts as a chipset register, it is the responsibility of
  the firmware to reprogram it at S3 resume. Therefore
  PciExBarInitialization() is called regardless of the boot path. (Marcel
  recently posted patches for SeaBIOS that implement this.)

This patch suffices to enable PCIEXBAR (and the dependent ACPI table
generation in QEMU), for the sake of "PCIeHotplug" in the Linux guest:

  ACPI: MCFG 0x7E17F000 3C
(v01 BOCHS  BXPCMCFG 0001 BXPC 0001)
  PCI: MMCONFIG for domain  [bus 00-ff] at [mem 0x8000-0x8fff]
   (base 0x8000)
  PCI: MMCONFIG at [mem 0x8000-0x8fff] reserved in E820
  acpi PNP0A08:00: _OSC: OS supports
   [ExtendedConfig ASPM ClockPM Segments MSI]
  acpi PNP0A08:00: _OSC: OS now controls
   [PCIeHotplug PME AER PCIeCapability]

In the following patches, we'll equip the core PCI host bridge / root
bridge driver and the rest of DXE as well to utilize ECAM on Q35.

Cc: Gabriel Somlo 
Cc: Gerd Hoffmann 
Cc: Jordan Justen 
Cc: Marcel Apfelbaum 
Cc: Michał Zegan 
Ref: https://github.com/tianocore/edk2/issues/32
Ref: http://thread.gmane.org/gmane.comp.bios.coreboot.seabios/10548
Suggested-by: Marcel Apfelbaum 
Reported-by: Michał Zegan 
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Laszlo Ersek 
Reviewed-by: Marcel Apfelbaum 
---

Notes:
v2:
- move the PCIEXBAR to 2GB, raise the start of the 32-bit MMIO window to
  2GB + 256MB [Gerd]

- replace the references to SeaBIOS settings and QEMU defaults in the
  DSC files with information we know about Q35 from Gerd

- rework the computation of PciBase on the Q35 branch, so that it builds
  up from the PCIEXBAR address

- kept Marcel's R-b, beause his v1 review mostly concerned the PCI
  config accesses to PCIEXBAR
  ,
  and I didn't change that part

- didn't pick up Jordan's R-b

 OvmfPkg/OvmfPkgIa32.dsc |  8 ++
 OvmfPkg/OvmfPkgIa32X64.dsc  |  8 ++
 OvmfPkg/OvmfPkgX64.dsc  |  8 ++
 OvmfPkg/PlatformPei/PlatformPei.inf |  3 +
 OvmfPkg/PlatformPei/Platform.c  | 81 +++-
 5 files changed, 104 insertions(+), 4 deletions(-)

diff --git a/OvmfPkg/OvmfPkgIa32.dsc b/OvmfPkg/OvmfPkgIa32.dsc
index 9b603f001fe5..aae1972950ee 100644
--- a/OvmfPkg/OvmfPkgIa32.dsc
+++ b/OvmfPkg/OvmfPkgIa32.dsc
@@ -395,6 +395,14 @@ [PcdsFixedAtBuild]
   gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x2F
 !endif
 
+  # This PCD is used to set the base address of the PCI express hierarchy. It
+  # is only consulted when OVMF runs on Q35. In that case it is programmed into
+  # the PCIEXBAR register.
+  #
+  # On Q35 machine types that QEMU intends to support in the long term, QEMU
+  # never lets the RAM below 4 GB exceed 2 GB.
+  gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x8000
+
 !ifdef $(SOURCE_DEBUG_ENABLE)
   gEfiSourceLevelDebugPkgTokenSpaceGuid.PcdDebugLoadImageMethod|0x2
 !endif
diff --git a/OvmfPkg/OvmfPkgIa32X64.dsc b/OvmfPkg/OvmfPkgIa32X64.dsc
index 1d68eb95d69e..0422dda09fbe 100644
--- a/OvmfPkg/OvmfPkgIa32X64.dsc
+++ b/OvmfPkg/OvmfPkgIa32X64.dsc
@@ -400,6 +400,14 @@ [PcdsFixedAtBuild]
   gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x2F
 !endif
 
+  # This PCD is used to set the base address of the PCI express hierarchy. It
+  # is only consulted when OVMF runs on Q35. In that case it is programmed into
+  # the PCIEXBAR register.
+  #
+  # On Q35 machine types that QEMU intends to support in the long term, QEMU
+  # never lets the RAM below 4 GB exceed 2 GB.
+  gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x8000
+
 !ifdef $(SOURCE_DEBUG_ENABLE)
   gEfiSourceLevelDebugPkgTokenSpaceGuid.PcdDebugLoadImageMethod|0x2
 !endif
diff --git a/OvmfPkg/OvmfPkgX64.dsc b/OvmfPkg/OvmfPkgX64.dsc
index b971ee8bb56b..18517e337649 100644
--- a/OvmfPkg/OvmfPkgX64.dsc
+++ b/OvmfPkg/OvmfPkgX64.dsc
@@ -400,6 +400,14 @@ [PcdsFixedAtBuild]
   gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x2F
 !endif
 
+  # This PCD is used to set the base address of the PCI express hierarchy. It
+  # is only consulted when OVMF runs on Q35. In that case it is programmed into
+  # the PCIEXBAR register.
+  #
+  # On Q35 machine types that QEMU intends to support in the long term, QEMU
+  # never lets the RAM below 4 GB exceed 2 GB.
+  gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x8000
+
 !ifdef $(SOURCE_DEBUG_ENABLE)
   gEfiSourceLevelDebugPkgTokenSpaceGuid.PcdDebugLoadImageMethod|0x2
 !endif
diff --git a/OvmfPkg/PlatformPei/PlatformPei.inf 
b/OvmfPkg/Pla

[edk2] [PATCH v2 2/6] OvmfPkg: PlatformPei: lower the 32-bit PCI MMIO base to 2GB on Q35

[Laszlo Ersek]

Gerd has advised us that long term support Q35 machine types have no low
RAM above 2GB, hence we should utilize the [2GB, 3GB) gap -- that we
currently leave unused -- for MMIO. (Plus, later in this series, for the
PCIEXBAR too.)

Cc: Gabriel Somlo 
Cc: Gerd Hoffmann 
Cc: Jordan Justen 
Cc: Marcel Apfelbaum 
Cc: Michał Zegan 
Ref: https://github.com/tianocore/edk2/issues/32
Ref: http://thread.gmane.org/gmane.comp.bios.edk2.devel/8707/focus=8817
Suggested-by: Gerd Hoffmann 
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Laszlo Ersek 
---

Notes:
v2:
- new in v2

 OvmfPkg/PlatformPei/Platform.c | 7 +++
 1 file changed, 3 insertions(+), 4 deletions(-)

diff --git a/OvmfPkg/PlatformPei/Platform.c b/OvmfPkg/PlatformPei/Platform.c
index 7d0941209f25..8e4da41001e1 100644
--- a/OvmfPkg/PlatformPei/Platform.c
+++ b/OvmfPkg/PlatformPei/Platform.c
@@ -218,11 +218,10 @@ MemMapInitialization (
 TopOfLowRam = GetSystemMemorySizeBelow4gb ();
 if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {
   //
-  // A 3GB base will always fall into Q35's 32-bit PCI host aperture,
-  // regardless of the Q35 MMCONFIG BAR. Correspondingly, QEMU never lets
-  // the RAM below 4 GB exceed it.
+  // On Q35 machine types that QEMU intends to support in the long term,
+  // QEMU never lets the RAM below 4 GB exceed 2 GB.
   //
-  PciBase = BASE_2GB + BASE_1GB;
+  PciBase = BASE_2GB;
   ASSERT (TopOfLowRam <= PciBase);
 } else {
   PciBase = (TopOfLowRam < BASE_2GB) ? BASE_2GB : TopOfLowRam;
-- 
1.8.3.1


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[edk2] [PATCH v2 4/6] OvmfPkg: add DxePciLibI440FxQ35

[Laszlo Ersek]

This library is a trivial unification of the following two PciLib
instances (and the result is easily diffable against each):
- MdePkg/Library/BasePciLibCf8
- MdePkg/Library/BasePciLibPciExpress

The PCI config access method is determined in the constructor function,
from the dynamic PCD "PcdOvmfHostBridgePciDevId" that is set by
PlatformPei.

The library instance is usable in DXE phase or later modules: the PciLib
instances being unified have no firmware phase / client module type
restrictions, and here the only PCD access is made in the constructor
function. That is, even before a given client executable's entry point is
invoked.

The library instance depends on PlatformPei both for setting the PCD
mentioned above, and also for enabling MMCONFIG on Q35. PEI and earlier
phase modules are not expected to need extended config access even on Q35.

Cc: Gabriel Somlo 
Cc: Gerd Hoffmann 
Cc: Jordan Justen 
Cc: Marcel Apfelbaum 
Cc: Michał Zegan 
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Laszlo Ersek 
Reviewed-by: Jordan Justen 
---
 OvmfPkg/Library/DxePciLibI440FxQ35/DxePciLibI440FxQ35.inf 
|  47 ++
 {MdePkg/Library/BasePciLibCf8 => OvmfPkg/Library/DxePciLibI440FxQ35}/PciLib.c 
| 161 +++-
 2 files changed, 173 insertions(+), 35 deletions(-)

diff --git a/OvmfPkg/Library/DxePciLibI440FxQ35/DxePciLibI440FxQ35.inf 
b/OvmfPkg/Library/DxePciLibI440FxQ35/DxePciLibI440FxQ35.inf
new file mode 100644
index ..2bd10cc23282
--- /dev/null
+++ b/OvmfPkg/Library/DxePciLibI440FxQ35/DxePciLibI440FxQ35.inf
@@ -0,0 +1,47 @@
+## @file
+#  An instance of the PCI Library that is based on both the PCI CF8 Library and
+#  the PCI Express Library.
+#
+#  This PciLib instance caches the OVMF platform type (I440FX vs. Q35) in
+#  its entry point function, then delegates function calls to one of the
+#  PciCf8Lib or PciExpressLib "backends" as appropriate.
+#
+#  Copyright (C) 2016, Red Hat, Inc.
+#
+#  Copyright (c) 2007 - 2014, Intel Corporation. All rights reserved.
+#
+#  This program and the accompanying materials are licensed and made available
+#  under the terms and conditions of the BSD License which accompanies this
+#  distribution. The full text of the license may be found at
+#  http://opensource.org/licenses/bsd-license.php.
+#
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR
+#  IMPLIED.
+##
+
+[Defines]
+  INF_VERSION= 0x00010005
+  BASE_NAME  = DxePciLibI440FxQ35
+  FILE_GUID  = 5360bff6-3911-4495-ae3c-b02ff004b585
+  MODULE_TYPE= BASE
+  VERSION_STRING = 1.0
+  LIBRARY_CLASS  = PciLib|DXE_DRIVER DXE_RUNTIME_DRIVER 
SMM_CORE DXE_SMM_DRIVER UEFI_DRIVER UEFI_APPLICATION
+  CONSTRUCTOR= InitializeConfigAccessMethod
+
+#  VALID_ARCHITECTURES   = IA32 X64
+
+[Sources]
+  PciLib.c
+
+[Packages]
+  MdePkg/MdePkg.dec
+  OvmfPkg/OvmfPkg.dec
+
+[LibraryClasses]
+  PcdLib
+  PciCf8Lib
+  PciExpressLib
+
+[Pcd]
+  gUefiOvmfPkgTokenSpaceGuid.PcdOvmfHostBridgePciDevId
diff --git a/MdePkg/Library/BasePciLibCf8/PciLib.c 
b/OvmfPkg/Library/DxePciLibI440FxQ35/PciLib.c
similarity index 85%
copy from MdePkg/Library/BasePciLibCf8/PciLib.c
copy to OvmfPkg/Library/DxePciLibI440FxQ35/PciLib.c
index f5f21475d8bd..6c1a272973af 100644
--- a/MdePkg/Library/BasePciLibCf8/PciLib.c
+++ b/OvmfPkg/Library/DxePciLibI440FxQ35/PciLib.c
@@ -1,6 +1,14 @@
 /** @file
-  PCI Library functions that use I/O ports 0xCF8 and 0xCFC to perform
-  PCI Configuration cycles. Layers on top of one PCI CF8 Library instance.
+  PCI Library functions that use
+  (a) I/O ports 0xCF8 and 0xCFC to perform PCI Configuration cycles, layering
+  on top of one PCI CF8 Library instance; or
+  (b) PCI Library functions that use the 256 MB PCI Express MMIO window to
+  perform PCI Configuration cycles, layering on PCI Express Library.
+
+  The decision is made in the entry point function, based on the OVMF platform
+  type, and then adhered to during the lifetime of the client module.
+
+  Copyright (C) 2016, Red Hat, Inc.
 
   Copyright (c) 2006 - 2012, Intel Corporation. All rights reserved.
   This program and the accompanying materials
@@ -16,8 +24,25 @@
 
 #include 
 
+#include 
+
 #include 
 #include 
+#include 
+#include 
+
+STATIC BOOLEAN mRunningOnQ35;
+
+RETURN_STATUS
+EFIAPI
+InitializeConfigAccessMethod (
+  VOID
+  )
+{
+  mRunningOnQ35 = (PcdGet16 (PcdOvmfHostBridgePciDevId) ==
+   INTEL_Q35_MCH_DEVICE_ID);
+  return RETURN_SUCCESS;
+}
 
 /**
   Registers a PCI device so PCI configuration registers may be accessed after 
@@ -46,7 +71,9 @@ PciRegisterForRuntimeAccess (
   IN UINTN  Address
   )
 {
-  return PciCf8RegisterForRuntimeAccess (Address);
+  return mRunningOnQ35 ?
+ PciExpressRegisterForRuntimeAccess (Address) :
+ 

[edk2] [PATCH v2 1/6] OvmfPkg: IndustryStandard/Q35MchIch9.h: add PCIEXBAR macros

[Laszlo Ersek]

Section 5.1.16 ("PCIEXBAR -- PCI Express Register Range Base Address") in
Intel document #316966-002 (already referenced near the top of this header
file) describes the Q35 DRAM Controller register that configures the
memory-mapped PCI config space (also known as MMCONFIG, and ECAM /
Enhanced Configuration Access Method).

In this patch we add the macros we'll need later. We'll only support the
256 MB memory-mapped config space -- enough for buses [0, 255].

Cc: Gabriel Somlo 
Cc: Gerd Hoffmann 
Cc: Jordan Justen 
Cc: Marcel Apfelbaum 
Cc: Michał Zegan 
Ref: https://github.com/tianocore/edk2/issues/32
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Laszlo Ersek 
Reviewed-by: Marcel Apfelbaum 
Reviewed-by: Jordan Justen 
---
 OvmfPkg/Include/IndustryStandard/Q35MchIch9.h | 8 
 1 file changed, 8 insertions(+)

diff --git a/OvmfPkg/Include/IndustryStandard/Q35MchIch9.h 
b/OvmfPkg/Include/IndustryStandard/Q35MchIch9.h
index 18b34a3d4f4e..4dc2c39901c1 100644
--- a/OvmfPkg/Include/IndustryStandard/Q35MchIch9.h
+++ b/OvmfPkg/Include/IndustryStandard/Q35MchIch9.h
@@ -33,6 +33,14 @@
 #define MCH_GGC   0x52
 #define MCH_GGC_IVD BIT1
 
+#define MCH_PCIEXBAR_LOW  0x60
+#define MCH_PCIEXBAR_LOWMASK0x0FFF
+#define MCH_PCIEXBAR_BUS_FF 0
+#define MCH_PCIEXBAR_EN BIT0
+
+#define MCH_PCIEXBAR_HIGH 0x64
+#define MCH_PCIEXBAR_HIGHMASK   0xFFF0
+
 #define MCH_SMRAM 0x9D
 #define MCH_SMRAM_D_LCK BIT4
 #define MCH_SMRAM_G_SMRAME  BIT3
-- 
1.8.3.1


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Re: [edk2] [PATCH] ShellPkg: Use DOS format end of line.

[Carsey, Jaben]

Fix Intel's copyright years in the modified files. If you do that, then good. 

Reviewed-By: Jaben Carsey 

-Jaben

Sent from my iPad.

> On Mar 8, 2016, at 4:57 AM, Qiu, Shumin  wrote:
> 
> Use DOS format end of line(CR, LF).
> 
> Cc: Jaben Carsey 
> Contributed-under: TianoCore Contribution Agreement 1.0
> Signed-off-by: Qiu Shumin 
> ---
> ShellPkg/Application/Shell/ShellParametersProtocol.c | 12 ++--
> ShellPkg/Library/UefiShellDebug1CommandsLib/Pci.c| 12 ++--
> .../UefiShellDebug1CommandsLib.uni   | 12 ++--
> 3 files changed, 18 insertions(+), 18 deletions(-)
> 
> diff --git a/ShellPkg/Application/Shell/ShellParametersProtocol.c 
> b/ShellPkg/Application/Shell/ShellParametersProtocol.c
> index c638583..8ae0ea5 100644
> --- a/ShellPkg/Application/Shell/ShellParametersProtocol.c
> +++ b/ShellPkg/Application/Shell/ShellParametersProtocol.c
> @@ -1266,12 +1266,12 @@ UpdateStdInStdOutStdErr(
>   EFI_FILE_MODE_READ,
>   0);
> if (!EFI_ERROR(Status)) {
> -  if (!InUnicode) {
> -//
> -// Create the ASCII->Unicode conversion layer
> -//
> -TempHandle = CreateFileInterfaceFile(TempHandle, FALSE);
> -  }
> +  if (!InUnicode) {
> +//
> +// Create the ASCII->Unicode conversion layer
> +//
> +TempHandle = CreateFileInterfaceFile(TempHandle, FALSE);
> +  }
>   ShellParameters->StdIn = TempHandle;
>   gST->ConIn = CreateSimpleTextInOnFile(TempHandle, 
> &gST->ConsoleInHandle);
> }
> diff --git a/ShellPkg/Library/UefiShellDebug1CommandsLib/Pci.c 
> b/ShellPkg/Library/UefiShellDebug1CommandsLib/Pci.c
> index 6956963..240d7d1 100644
> --- a/ShellPkg/Library/UefiShellDebug1CommandsLib/Pci.c
> +++ b/ShellPkg/Library/UefiShellDebug1CommandsLib/Pci.c
> @@ -2,8 +2,8 @@
>   Main file for Pci shell Debug1 function.
> 
>   Copyright (c) 2005 - 2014, Intel Corporation. All rights reserved.
> -  (C) Copyright 2013-2015 Hewlett-Packard Development Company, L.P.
> -  (C) Copyright 2016 Hewlett Packard Enterprise Development LP  
> +  (C) Copyright 2013-2015 Hewlett-Packard Development Company, L.P.
> +  (C) Copyright 2016 Hewlett Packard Enterprise Development LP  
>   This program and the accompanying materials
>   are licensed and made available under the terms and conditions of the BSD 
> License
>   which accompanies this distribution.  The full text of the license may be 
> found at
> @@ -5444,10 +5444,10 @@ PrintInterpretedExtendedCompatibilityAer (
> Header->CorrectableErrorStatus,
> Header->CorrectableErrorMask,
> Header->AdvancedErrorCapabilitiesAndControl,
> -Header->HeaderLog[0],
> -Header->HeaderLog[1],
> -Header->HeaderLog[2],
> -Header->HeaderLog[3],
> +Header->HeaderLog[0],
> +Header->HeaderLog[1],
> +Header->HeaderLog[2],
> +Header->HeaderLog[3],
> Header->RootErrorCommand,
> Header->RootErrorStatus,
> Header->ErrorSourceIdentification,
> diff --git 
> a/ShellPkg/Library/UefiShellDebug1CommandsLib/UefiShellDebug1CommandsLib.uni 
> b/ShellPkg/Library/UefiShellDebug1CommandsLib/UefiShellDebug1CommandsLib.uni
> index 6206f84..7a5f5a5 100644
> --- 
> a/ShellPkg/Library/UefiShellDebug1CommandsLib/UefiShellDebug1CommandsLib.uni
> +++ 
> b/ShellPkg/Library/UefiShellDebug1CommandsLib/UefiShellDebug1CommandsLib.uni
> @@ -1,8 +1,8 @@
> // /**
> //
> // Copyright (c) 2010 - 2015, Intel Corporation. All rights reserved.
> -// (C) Copyright 2013-2015 Hewlett-Packard Development Company, L.P.
> -// (C) Copyright 2016 Hewlett Packard Enterprise Development LP
> +// (C) Copyright 2013-2015 Hewlett-Packard Development Company, L.P.
> +// (C) Copyright 2016 Hewlett Packard Enterprise Development LP
> // This program and the accompanying materials
> // are licensed and made available under the terms and conditions of the BSD 
> License
> // which accompanies this distribution. The full text of the license may be 
> found at
> @@ -317,10 +317,10 @@
>"
> CorrectableErrorStatus %08x\r\n"
>"
> CorrectableErrorMask   %08x\r\n"
>"
> AdvancedErrorCapAndControl %08x\r\n"
> -   "HeaderLog1   
>   %08x\r\n"
> -   "HeaderLog2   
>   %08x\r\n"
> -   "HeaderLog3   
>   %08x\r\n"
> -   "HeaderLog4   
>   %08x\r\n"
> +   "HeaderLog1   
>   %08x\r\n"
> +  

Re: [edk2] OpenSSL 1.1 status, and a worked example of why you should *NEVER* rebase

[Laszlo Ersek]

On 03/08/16 14:25, David Woodhouse wrote:
> On Tue, 2016-03-08 at 14:21 +0100, Laszlo Ersek wrote:
>> As soon as Intel leadership signs off on a merge-oriented workflow,
>> I'll seek to adopt it immediately.
> 
> What is this "Intel leadership" of which you speak?

The Intel leadership I speak of are the people who organized the
internal git trainings @ Intel, orchestrated the migration of individual
developers to git, and ultimately okayed the move of the project to git.
Edk2 as a project doesn't exactly look like irrelevant to Intel :), so
I'm pretty sure management was involved in the transition.

> I thought the
> direction from Intel was that we would move to git (at last).

1. Yes, it was.
2. The management I speak of are the people who the direction was from.

> Nobody made a statement that we should *NOT* use the git tools as they
> were designed to be used, and should instead do things (rebasing) that
> the git authors explicitly recommend *against*... did they?

Using git is one thing, designing a workflow is another thing. Many
workflows exist. Some of them are not exclusively merge based (QEMU,
various subsystems of Linux), where sub-maintainers rebase and
occasionally rework patches that they queue for their next pull request.
Some other workflows are not merge based at all, regardless of what the
git authors say. (This is a semi-frequent topic on reddit.com, for example.)

Given that most of the edk2 developer community are coming from an SVN
background, a linear history, at this stage of the git transition, was
deemed more comprehensible. The initial git workflow was built around
such a lineary history. Even this "lite" workflow has caused confusion
and mistakes; the developer community's git expertise needs to mature.

Please understand that I'm not personally defending the current
workflow. I'm trying to relay (to the best of my understanding) how and
why the current workflow was designed. I don't think it's fruitful if
the two of us argue -- first, I'm not the one you have to convince,
second, I don't need convincing at all.

Laszlo
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Re: [edk2] OpenSSL 1.1 status, and a worked example of why you should *NEVER* rebase

[David Woodhouse]

On Tue, 2016-03-08 at 14:21 +0100, Laszlo Ersek wrote:
> As soon as Intel leadership signs off on a merge-oriented workflow,
> I'll seek to adopt it immediately.

What is this "Intel leadership" of which you speak? I thought the
direction from Intel was that we would move to git (at last).

Nobody made a statement that we should *NOT* use the git tools as they
were designed to be used, and should instead do things (rebasing) that
the git authors explicitly recommend *against*... did they?

Jordan?

-- 
dwmw2



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Re: [edk2] OpenSSL 1.1 status, and a worked example of why you should *NEVER* rebase

[Laszlo Ersek]

On 03/08/16 13:12, David Woodhouse wrote:

> So please, DO NOT REBASE submissions onto the latest master. Use the
> tools properly as they were designed to be used — put any non-trivial
> work into a tree and send it as a pull request. Sure, send the patches
> to the list for review *too*, but that shouldn't be how they actually
> get in.

I support the idea. I have no input on the urgency of it.

As soon as Intel leadership signs off on a merge-oriented workflow, I'll
seek to adopt it immediately.

(Importantly: this shall not include *github* pull requests, only pull
requests sent to the mailing list, and the patches must also be on the
list. I think what people frequently do is, they format the series as
usual, just include the pull request (formatted with git-request-pull)
in the blurb. In such cases the PATCH subject prefix can also be
replaced with PULL, across the full series.)

Until then, we'll have to stick with the rules that we have now. (Again,
I do support the idea.)

Thanks
Laszlo
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Re: [edk2] [PATCH v6] MdeModulePkg: Increase the maximum number of PEI performance log entries

[Zeng, Star]

patch committed at 7c50b3434377cbb49ce4514ee31339000a5cadc0.

On 2016/3/8 14:32, Zeng, Star wrote:

Reviewed-by: Star Zeng 

On 2016/3/8 14:00, Cinnamon Shia wrote:

The maximum number of PEI performance log entries is 255.
Add a new PCD, PcdMaxPeiPerformanceLogEntries16, to increase the maximum
number of PEI performance log entries.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Cinnamon Shia 
Reviewed-by: Samer EL-Haj-Mahmoud 
Reviewed-by: Joseph Shifflett 
Reviewed-by: Michael Kinney 
---
  .../DxeCorePerformanceLib/DxeCorePerformanceLib.c|  5 -
  .../DxeCorePerformanceLib/DxeCorePerformanceLib.inf  |  6 --
  .../Library/PeiPerformanceLib/PeiPerformanceLib.c| 20
+++-
  .../Library/PeiPerformanceLib/PeiPerformanceLib.inf  |  6 --
  MdeModulePkg/MdeModulePkg.dec| 10 ++
  5 files changed, 37 insertions(+), 10 deletions(-)

diff --git
a/MdeModulePkg/Library/DxeCorePerformanceLib/DxeCorePerformanceLib.c
b/MdeModulePkg/Library/DxeCorePerformanceLib/DxeCorePerformanceLib.c
index 0eb8e57..c3a6d70 100644
--- a/MdeModulePkg/Library/DxeCorePerformanceLib/DxeCorePerformanceLib.c
+++ b/MdeModulePkg/Library/DxeCorePerformanceLib/DxeCorePerformanceLib.c
@@ -11,6 +11,7 @@
Performance Protocol is installed at the very beginning of DXE phase.

  Copyright (c) 2006 - 2015, Intel Corporation. All rights reserved.
+(C) Copyright 2016 Hewlett Packard Enterprise Development LP
  This program and the accompanying materials
  are licensed and made available under the terms and conditions of
the BSD License
  which accompanies this distribution.  The full text of the license
may be found at
@@ -522,7 +523,9 @@ DxeCorePerformanceLibConstructor (
);
ASSERT_EFI_ERROR (Status);

-  mMaxGaugeRecords = INIT_DXE_GAUGE_DATA_ENTRIES + PcdGet8
(PcdMaxPeiPerformanceLogEntries);
+  mMaxGaugeRecords = INIT_DXE_GAUGE_DATA_ENTRIES + (UINT16) (PcdGet16
(PcdMaxPeiPerformanceLogEntries16) != 0 ?
+ PcdGet16
(PcdMaxPeiPerformanceLogEntries16) :
+ PcdGet8
(PcdMaxPeiPerformanceLogEntries));

mGaugeData = AllocateZeroPool (sizeof (GAUGE_DATA_HEADER) +
(sizeof (GAUGE_DATA_ENTRY_EX) * mMaxGaugeRecords));
ASSERT (mGaugeData != NULL);
diff --git
a/MdeModulePkg/Library/DxeCorePerformanceLib/DxeCorePerformanceLib.inf
b/MdeModulePkg/Library/DxeCorePerformanceLib/DxeCorePerformanceLib.inf
index 5f29063..f73d0a4 100644
---
a/MdeModulePkg/Library/DxeCorePerformanceLib/DxeCorePerformanceLib.inf
+++
b/MdeModulePkg/Library/DxeCorePerformanceLib/DxeCorePerformanceLib.inf
@@ -10,6 +10,7 @@
  #  Performance and PerformanceEx Protocol are installed at the very
beginning of DXE phase.
  #
  #  Copyright (c) 2006 - 2014, Intel Corporation. All rights
reserved.
+# (C) Copyright 2016 Hewlett Packard Enterprise Development LP
  #  This program and the accompanying materials
  #  are licensed and made available under the terms and conditions of
the BSD License
  #  which accompanies this distribution.  The full text of the
license may be found at
@@ -66,5 +67,6 @@
gPerformanceExProtocolGuid

  [Pcd]
-  gEfiMdeModulePkgTokenSpaceGuid.PcdMaxPeiPerformanceLogEntries ##
CONSUMES
-  gEfiMdePkgTokenSpaceGuid.PcdPerformanceLibraryPropertyMask##
CONSUMES
+  gEfiMdeModulePkgTokenSpaceGuid.PcdMaxPeiPerformanceLogEntries   ##
CONSUMES
+  gEfiMdeModulePkgTokenSpaceGuid.PcdMaxPeiPerformanceLogEntries16 ##
CONSUMES
+  gEfiMdePkgTokenSpaceGuid.PcdPerformanceLibraryPropertyMask  ##
CONSUMES
diff --git
a/MdeModulePkg/Library/PeiPerformanceLib/PeiPerformanceLib.c
b/MdeModulePkg/Library/PeiPerformanceLib/PeiPerformanceLib.c
index 9674bbc..b3b11b9 100644
--- a/MdeModulePkg/Library/PeiPerformanceLib/PeiPerformanceLib.c
+++ b/MdeModulePkg/Library/PeiPerformanceLib/PeiPerformanceLib.c
@@ -4,10 +4,11 @@
This file implements all APIs in Performance Library class in
MdePkg. It creates
performance logging GUIDed HOB on the first performance logging
and then logs the
performance data to the GUIDed HOB. Due to the limitation of
temporary RAM, the maximum
-  number of performance logging entry is specified by
PcdMaxPeiPerformanceLogEntries.
+  number of performance logging entry is specified by
PcdMaxPeiPerformanceLogEntries or
+  PcdMaxPeiPerformanceLogEntries16.

  Copyright (c) 2006 - 2015, Intel Corporation. All rights reserved.
-(C) Copyright 2015 Hewlett Packard Enterprise Development LP
+(C) Copyright 2015-2016 Hewlett Packard Enterprise Development LP
  This program and the accompanying materials
  are licensed and made available under the terms and conditions of
the BSD License
  which accompanies this distribution.  The full text of the license
may be found at
@@ -51,10 +52,14 @@ InternalGetPerformanceHobLog (
  {
EFI_HOB_GUID_TYPE   *GuidHob;
UINTN   PeiPerformanceSize;
+  UINT16 

[edk2] [PATCH] ShellPkg: Use DOS format end of line.

[Qiu Shumin]

Use DOS format end of line(CR, LF).

Cc: Jaben Carsey 
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Qiu Shumin 
---
 ShellPkg/Application/Shell/ShellParametersProtocol.c | 12 ++--
 ShellPkg/Library/UefiShellDebug1CommandsLib/Pci.c| 12 ++--
 .../UefiShellDebug1CommandsLib.uni   | 12 ++--
 3 files changed, 18 insertions(+), 18 deletions(-)

diff --git a/ShellPkg/Application/Shell/ShellParametersProtocol.c 
b/ShellPkg/Application/Shell/ShellParametersProtocol.c
index c638583..8ae0ea5 100644
--- a/ShellPkg/Application/Shell/ShellParametersProtocol.c
+++ b/ShellPkg/Application/Shell/ShellParametersProtocol.c
@@ -1266,12 +1266,12 @@ UpdateStdInStdOutStdErr(
   EFI_FILE_MODE_READ,
   0);
 if (!EFI_ERROR(Status)) {
-  if (!InUnicode) {
-//
-// Create the ASCII->Unicode conversion layer
-//
-TempHandle = CreateFileInterfaceFile(TempHandle, FALSE);
-  }
+  if (!InUnicode) {
+//
+// Create the ASCII->Unicode conversion layer
+//
+TempHandle = CreateFileInterfaceFile(TempHandle, FALSE);
+  }
   ShellParameters->StdIn = TempHandle;
   gST->ConIn = CreateSimpleTextInOnFile(TempHandle, 
&gST->ConsoleInHandle);
 }
diff --git a/ShellPkg/Library/UefiShellDebug1CommandsLib/Pci.c 
b/ShellPkg/Library/UefiShellDebug1CommandsLib/Pci.c
index 6956963..240d7d1 100644
--- a/ShellPkg/Library/UefiShellDebug1CommandsLib/Pci.c
+++ b/ShellPkg/Library/UefiShellDebug1CommandsLib/Pci.c
@@ -2,8 +2,8 @@
   Main file for Pci shell Debug1 function.
 
   Copyright (c) 2005 - 2014, Intel Corporation. All rights reserved.
-  (C) Copyright 2013-2015 Hewlett-Packard Development Company, L.P.
-  (C) Copyright 2016 Hewlett Packard Enterprise Development LP  
+  (C) Copyright 2013-2015 Hewlett-Packard Development Company, L.P.
+  (C) Copyright 2016 Hewlett Packard Enterprise Development LP  
   This program and the accompanying materials
   are licensed and made available under the terms and conditions of the BSD 
License
   which accompanies this distribution.  The full text of the license may be 
found at
@@ -5444,10 +5444,10 @@ PrintInterpretedExtendedCompatibilityAer (
 Header->CorrectableErrorStatus,
 Header->CorrectableErrorMask,
 Header->AdvancedErrorCapabilitiesAndControl,
-Header->HeaderLog[0],
-Header->HeaderLog[1],
-Header->HeaderLog[2],
-Header->HeaderLog[3],
+Header->HeaderLog[0],
+Header->HeaderLog[1],
+Header->HeaderLog[2],
+Header->HeaderLog[3],
 Header->RootErrorCommand,
 Header->RootErrorStatus,
 Header->ErrorSourceIdentification,
diff --git 
a/ShellPkg/Library/UefiShellDebug1CommandsLib/UefiShellDebug1CommandsLib.uni 
b/ShellPkg/Library/UefiShellDebug1CommandsLib/UefiShellDebug1CommandsLib.uni
index 6206f84..7a5f5a5 100644
--- a/ShellPkg/Library/UefiShellDebug1CommandsLib/UefiShellDebug1CommandsLib.uni
+++ b/ShellPkg/Library/UefiShellDebug1CommandsLib/UefiShellDebug1CommandsLib.uni
@@ -1,8 +1,8 @@
 // /**
 //
 // Copyright (c) 2010 - 2015, Intel Corporation. All rights reserved.
-// (C) Copyright 2013-2015 Hewlett-Packard Development Company, L.P.
-// (C) Copyright 2016 Hewlett Packard Enterprise Development LP
+// (C) Copyright 2013-2015 Hewlett-Packard Development Company, L.P.
+// (C) Copyright 2016 Hewlett Packard Enterprise Development LP
 // This program and the accompanying materials
 // are licensed and made available under the terms and conditions of the BSD 
License
 // which accompanies this distribution. The full text of the license may be 
found at
@@ -317,10 +317,10 @@
"
CorrectableErrorStatus %08x\r\n"
"
CorrectableErrorMask   %08x\r\n"
"
AdvancedErrorCapAndControl %08x\r\n"
-   "HeaderLog1 
%08x\r\n"
-   "HeaderLog2 
%08x\r\n"
-   "HeaderLog3 
%08x\r\n"
-   "HeaderLog4 
%08x\r\n"
+   "HeaderLog1 
%08x\r\n"
+   "HeaderLog2 
%08x\r\n"
+   "HeaderLog3 
%08x\r\n"
+   "HeaderLog4 
%08x\r\n"
"RootErrorCommand   
%08x\r\n"
   

[edk2] OpenSSL 1.1 status, and a worked example of why you should *NEVER* rebase

[David Woodhouse]

As of yesterday, *all* my patches had been merged into OpenSSL HEAD, in
preparation for the OpenSSL 1.1 Beta 1 release this week.

There is only one more patch outstanding in my OpenSSL git tree.

Do those statements seem self-contradictory to you? Well, they're not
quite. The patches *were* merged, but one was then reverted because it
was utterly hosed and broke the build for fairly much *everyone* except
the UEFI target. Bad dwmw2. No biscuit.

Why was it so broken? Well, it wasn't because I'm a *complete* muppet —
it was correct when I first committed it, and I *tested* it in a native
Linux build at that point too, as well as within the EDK2 build:
http://git.infradead.org/users/dwmw2/openssl.git/commitdiff/929ae044cf7

However, a subsequent change in the upstream tree affected my patch:
http://git.infradead.org/users/dwmw2/openssl.git/commitdiff/8731a4fcd#patch7

At some point I stupidly did a 'git pull --rebase' or something else
that you should never do. In rebasing, I then failed to correctly fix
up the changes, leaving it broken. I did a quick smoke-test rebuild
(under EDK2 only, it seems) of the rebased tree, but didn't spot the
error.

Now, you can point out that this involved user error on my part when I
did the rebase — but there are a number of problems with putting it
down to that alone:

Firstly, it's a *predictable* error. You are *never* paying as much
attention (to each and every commit) when you rebase, as when you
create them in the first place. A process should not introduce
*predictable* user errors.

In fact, although in *this* case it needed user error, there are cases
where the tools *will* handle the merge automatically, but the code is
still broken — you're not handling a new enum value that someone else
has added in the upstream you're rebasing onto, or something like that.
So the patch *applies* OK, but doesn't work. Or works most of the time
but has broken corner cases.

And the most important thing is that when this happens during a rebase,
the history — which is the single most important thing that a version
control system exists to preserve! — is lost. When the breakage is
discovered, there's no way to go back and see "it works  and then
the merge  was broken". You just end up with a false history in
which a given commit *never* worked.

Now, this one is a trivial (and recent) example, and it's easy enough
to sort out and even *find* the original commit in my local tree which
was subsequently discarded in the rebase. I'm using it because it was
*me* who screwed up, and I can rant at length about the *practice* of
rebasing, without making some other poor sod feel bad. We all screw up.
The point is to use the tools to help us *cope*.

Although *this* one was simple, it *does* happen that more complex
submissions also end up broken even by the time they are merged. And
when that happens, if the tools are being used *properly*, you can
*see* that it actually worked on the commit just *before* it was
merged, and it was broken in the merge. And you can look for the cause
— what changed in the upstream, between the version that the work was
based on, and the tree it was merged into.

This isn't a purely theoretical concern. I've *done* this. And I've
done it as a third party with little familiarity with the specific code
in question, a *long* time after it was merged. Because it was only a
relatively esoteric corner case that was broken, so nobody noticed —
the kind of thing you think about while you're *writing* the code, and
never again. Especially not while rebasing.

(Which is also an argument for decent unit tests, mind you, but that's
a different rant and one on which I'm even *more* hypocritical.)

So please, DO NOT REBASE submissions onto the latest master. Use the
tools properly as they were designed to be used — put any non-trivial
work into a tree and send it as a pull request. Sure, send the patches
to the list for review *too*, but that shouldn't be how they actually
get in.

Note: using 'git rebase --interactive' just to add Reviewed-by: and
similar tags is acceptable. But don't actually rebase onto a different
base. Keep it where it was, and *merge* it.

-- 
David WoodhouseOpen Source Technology Centre
david.woodho...@intel.com  Intel Corporation



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Re: [edk2] [PATCH 1/3] BaseTools ConvertMasmToNasm: Set gitemail when git is not found

[Laszlo Ersek]

On 03/08/16 04:15, Jordan Justen wrote:
> Fixes: https://github.com/tianocore/edk2/issues/63
> Contributed-under: TianoCore Contribution Agreement 1.0
> Signed-off-by: Jordan Justen 
> Cc: Yonghong Zhu 
> Cc: Liming Gao 
> Cc: Michael Kinney 
> ---
>  BaseTools/Scripts/ConvertMasmToNasm.py | 4 +++-
>  1 file changed, 3 insertions(+), 1 deletion(-)

Can you add some explanation to the commit message? At the moment it
doesn't tell me anything (and not much even after looking at issue #63).

Just a suggestion. If you agree, it can be done when you commit the patch.

Thanks
Laszlo

> diff --git a/BaseTools/Scripts/ConvertMasmToNasm.py 
> b/BaseTools/Scripts/ConvertMasmToNasm.py
> index 7ad0bd2..2f0dd4f 100755
> --- a/BaseTools/Scripts/ConvertMasmToNasm.py
> +++ b/BaseTools/Scripts/ConvertMasmToNasm.py
> @@ -1,7 +1,7 @@
>  # @file ConvertMasmToNasm.py
>  # This script assists with conversion of MASM assembly syntax to NASM
>  #
> -#  Copyright (c) 2007 - 2014, Intel Corporation. All rights reserved.
> +#  Copyright (c) 2007 - 2016, Intel Corporation. All rights reserved.
>  #
>  #  This program and the accompanying materials
>  #  are licensed and made available under the terms and conditions of the BSD 
> License
> @@ -127,6 +127,7 @@ class CommonUtils:
>  while True:
>  path = os.path.split(lastpath)[0]
>  if path == lastpath:
> +self.gitemail = None
>  return
>  candidate = os.path.join(path, '.git')
>  if os.path.isdir(candidate):
> @@ -197,6 +198,7 @@ class CommonUtils:
>  message += '%s to %s\n' % (src, dst)
>  message += '\n'
>  message += 'Contributed-under: TianoCore Contribution Agreement 
> 1.0\n'
> +assert(self.gitemail is not None)
>  message += 'Signed-off-by: %s\n' % self.gitemail
>  
>  cmd = ('git', 'commit', '-F', '-')
> 

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Re: [edk2] [PATCH] OvmfPkg: Enable Network2 Commands for IPv6

[Laszlo Ersek]

On 03/08/16 10:50, Gary Lin wrote:
> Enable the network2 commands when NETWORK_IP6_ENABLE is TRUE, so we
> would have Ping6 and Ifconfig6.
> 
> Contributed-under: TianoCore Contribution Agreement 1.0
> Signed-off-by: Gary Ching-Pang Lin 
> ---
>  OvmfPkg/OvmfPkgIa32.dsc| 3 +++
>  OvmfPkg/OvmfPkgIa32X64.dsc | 3 +++
>  OvmfPkg/OvmfPkgX64.dsc | 3 +++
>  3 files changed, 9 insertions(+)

[ler...@redhat.com: added the word "Shell" to the subject]
Reviewed-by: Laszlo Ersek 

Committed as 96302b80d90e.

Thank you!
Laszlo

> diff --git a/OvmfPkg/OvmfPkgIa32.dsc b/OvmfPkg/OvmfPkgIa32.dsc
> index 2b92850..9b603f0 100644
> --- a/OvmfPkg/OvmfPkgIa32.dsc
> +++ b/OvmfPkg/OvmfPkgIa32.dsc
> @@ -686,6 +686,9 @@ [Components]
>
> NULL|ShellPkg/Library/UefiShellDebug1CommandsLib/UefiShellDebug1CommandsLib.inf
>
> NULL|ShellPkg/Library/UefiShellInstall1CommandsLib/UefiShellInstall1CommandsLib.inf
>
> NULL|ShellPkg/Library/UefiShellNetwork1CommandsLib/UefiShellNetwork1CommandsLib.inf
> +!if $(NETWORK_IP6_ENABLE) == TRUE
> +  
> NULL|ShellPkg/Library/UefiShellNetwork2CommandsLib/UefiShellNetwork2CommandsLib.inf
> +!endif
>
> NULL|ShellPkg/Library/UefiShellTftpCommandLib/UefiShellTftpCommandLib.inf
>
> HandleParsingLib|ShellPkg/Library/UefiHandleParsingLib/UefiHandleParsingLib.inf
>ShellLib|ShellPkg/Library/UefiShellLib/UefiShellLib.inf
> diff --git a/OvmfPkg/OvmfPkgIa32X64.dsc b/OvmfPkg/OvmfPkgIa32X64.dsc
> index 8d62718..1d68eb9 100644
> --- a/OvmfPkg/OvmfPkgIa32X64.dsc
> +++ b/OvmfPkg/OvmfPkgIa32X64.dsc
> @@ -693,6 +693,9 @@ [Components.X64]
>
> NULL|ShellPkg/Library/UefiShellDebug1CommandsLib/UefiShellDebug1CommandsLib.inf
>
> NULL|ShellPkg/Library/UefiShellInstall1CommandsLib/UefiShellInstall1CommandsLib.inf
>
> NULL|ShellPkg/Library/UefiShellNetwork1CommandsLib/UefiShellNetwork1CommandsLib.inf
> +!if $(NETWORK_IP6_ENABLE) == TRUE
> +  
> NULL|ShellPkg/Library/UefiShellNetwork2CommandsLib/UefiShellNetwork2CommandsLib.inf
> +!endif
>
> NULL|ShellPkg/Library/UefiShellTftpCommandLib/UefiShellTftpCommandLib.inf
>
> HandleParsingLib|ShellPkg/Library/UefiHandleParsingLib/UefiHandleParsingLib.inf
>ShellLib|ShellPkg/Library/UefiShellLib/UefiShellLib.inf
> diff --git a/OvmfPkg/OvmfPkgX64.dsc b/OvmfPkg/OvmfPkgX64.dsc
> index e3f97f1..b971ee8 100644
> --- a/OvmfPkg/OvmfPkgX64.dsc
> +++ b/OvmfPkg/OvmfPkgX64.dsc
> @@ -691,6 +691,9 @@ [Components]
>
> NULL|ShellPkg/Library/UefiShellDebug1CommandsLib/UefiShellDebug1CommandsLib.inf
>
> NULL|ShellPkg/Library/UefiShellInstall1CommandsLib/UefiShellInstall1CommandsLib.inf
>
> NULL|ShellPkg/Library/UefiShellNetwork1CommandsLib/UefiShellNetwork1CommandsLib.inf
> +!if $(NETWORK_IP6_ENABLE) == TRUE
> +  
> NULL|ShellPkg/Library/UefiShellNetwork2CommandsLib/UefiShellNetwork2CommandsLib.inf
> +!endif
>
> NULL|ShellPkg/Library/UefiShellTftpCommandLib/UefiShellTftpCommandLib.inf
>
> HandleParsingLib|ShellPkg/Library/UefiHandleParsingLib/UefiHandleParsingLib.inf
>ShellLib|ShellPkg/Library/UefiShellLib/UefiShellLib.inf
> 

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Re: [edk2] [PATCH v2 1/2] PerformancePkg/Dp_App: Support execution break

[Zeng, Star]

Series committed at 3e9de670ec3f18d0211a72d28fedb5dfce93442a and 
196ccda08fc481dae4fc97db8f2938df87801edb.


On 2016/3/7 15:09, Zeng, Star wrote:

Series: Reviewed-by: Star Zeng 

On 2016/3/7 11:23, Cinnamon Shia wrote:

Support UEFI shell execution break.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Cinnamon Shia 
---
  PerformancePkg/Dp_App/Dp.c | 36 --
  PerformancePkg/Dp_App/DpInternal.h | 27 -
  PerformancePkg/Dp_App/DpTrace.c| 62
--
  3 files changed, 99 insertions(+), 26 deletions(-)

diff --git a/PerformancePkg/Dp_App/Dp.c b/PerformancePkg/Dp_App/Dp.c
index e052216..e36a032 100644
--- a/PerformancePkg/Dp_App/Dp.c
+++ b/PerformancePkg/Dp_App/Dp.c
@@ -14,7 +14,7 @@
timer information to calculate elapsed time for each measurement.

Copyright (c) 2009 - 2015, Intel Corporation. All rights
reserved.
-  (C) Copyright 2015 Hewlett Packard Enterprise Development LP
+  (C) Copyright 2015-2016 Hewlett Packard Enterprise Development LP
This program and the accompanying materials
are licensed and made available under the terms and conditions of
the BSD License
which accompanies this distribution.  The full text of the license
may be found at
@@ -195,11 +195,11 @@ InitCumulativeData (

@param[in]  ImageHandle The image handle.
@param[in]  SystemTable The system table.
-
+
@retval EFI_SUCCESSCommand completed successfully.
@retval EFI_INVALID_PARAMETER  Command usage error.
+  @retval EFI_ABORTEDThe user aborts the operation.
@retval value  Unknown error.
-
  **/
  EFI_STATUS
  EFIAPI
@@ -443,7 +443,10 @@ InitializeDp (
  ProcessCumulative (CustomCumulativeData);
} else if (AllMode) {
  if (TraceMode) {
-  DumpAllTrace( Number2Display, ExcludeMode);
+  Status = DumpAllTrace( Number2Display, ExcludeMode);
+  if (Status == EFI_ABORTED) {
+goto Done;
+  }
  }
  if (ProfileMode) {
DumpAllProfile( Number2Display, ExcludeMode);
@@ -451,7 +454,10 @@ InitializeDp (
}
else if (RawMode) {
  if (TraceMode) {
-  DumpRawTrace( Number2Display, ExcludeMode);
+  Status = DumpRawTrace( Number2Display, ExcludeMode);
+  if (Status == EFI_ABORTED) {
+goto Done;
+  }
  }
  if (ProfileMode) {
DumpRawProfile( Number2Display, ExcludeMode);
@@ -463,11 +469,21 @@ InitializeDp (
ProcessPhases ( Ticker );
if ( ! SummaryMode) {
  Status = ProcessHandles ( ExcludeMode);
-if ( ! EFI_ERROR( Status)) {
-  ProcessPeims ( );
-  ProcessGlobal ();
-  ProcessCumulative (NULL);
+if (Status == EFI_ABORTED) {
+  goto Done;
  }
+
+Status = ProcessPeims ();
+if (Status == EFI_ABORTED) {
+  goto Done;
+}
+
+Status = ProcessGlobal ();
+if (Status == EFI_ABORTED) {
+  goto Done;
+}
+
+ProcessCumulative (NULL);
}
  }
  if (ProfileMode) {
@@ -480,6 +496,8 @@ InitializeDp (
  }
}

+Done:
+
//
// Free the memory allocate from HiiGetString
//
diff --git a/PerformancePkg/Dp_App/DpInternal.h
b/PerformancePkg/Dp_App/DpInternal.h
index 0e97e1e..53c5fb2 100644
--- a/PerformancePkg/Dp_App/DpInternal.h
+++ b/PerformancePkg/Dp_App/DpInternal.h
@@ -7,7 +7,7 @@
DpUtilities.c, DpTrace.c, and DpProfile.c are included here.

Copyright (c) 2009 - 2014, Intel Corporation. All rights
reserved.
-  (C) Copyright 2015 Hewlett Packard Enterprise Development LP
+  (C) Copyright 2015-2016 Hewlett Packard Enterprise Development LP
This program and the accompanying materials
are licensed and made available under the terms and conditions of
the BSD License
which accompanies this distribution.  The full text of the license
may be found at
@@ -215,8 +215,11 @@ GatherStatistics(
@param[in]Limit   The number of records to print.  Zero is
ALL.
@param[in]ExcludeFlag TRUE to exclude individual Cumulative
items from display.

+  @retval EFI_SUCCESS   The operation was successful.
+  @retval EFI_ABORTED   The user aborts the operation.
+  @return Othersfrom a call to
gBS->LocateHandleBuffer().
  **/
-VOID
+EFI_STATUS
  DumpAllTrace(
IN UINTN Limit,
IN BOOLEAN   ExcludeFlag
@@ -238,9 +241,11 @@ DumpAllTrace(

@param[in]Limit   The number of records to print.  Zero is
ALL.
@param[in]ExcludeFlag TRUE to exclude individual Cumulative
items from display.
-
+
+  @retval EFI_SUCCESS   The operation was successful.
+  @retval EFI_ABORTED   The user aborts the operation.
  **/
-VOID
+EFI_STATUS
  DumpRawTrac

Re: [edk2] [PATCH 1/2] OvmfPkg PciHostBridgeDxe: Convert Ia32/IoFifo.asm to NASM

[Laszlo Ersek]

On 03/08/16 04:18, Jordan Justen wrote:
> The BaseTools/Scripts/ConvertMasmToNasm.py script was used to convert
> Ia32/IoFifo.asm to Ia32/IoFifo.nasm
> 
> Contributed-under: TianoCore Contribution Agreement 1.0
> Signed-off-by: Jordan Justen 
> Cc: Laszlo Ersek 
> ---
>  OvmfPkg/PciHostBridgeDxe/Ia32/IoFifo.S | 134 
> -
>  .../Ia32/{IoFifo.asm => IoFifo.nasm}   |  30 ++---
>  OvmfPkg/PciHostBridgeDxe/PciHostBridgeDxe.inf  |   3 +-
>  3 files changed, 14 insertions(+), 153 deletions(-)
>  delete mode 100644 OvmfPkg/PciHostBridgeDxe/Ia32/IoFifo.S
>  rename OvmfPkg/PciHostBridgeDxe/Ia32/{IoFifo.asm => IoFifo.nasm} (87%)

Series
Reviewed-by: Laszlo Ersek 

Committed for your convenience as 43ca17532bd7..ace1d0517b65 :)

Laszlo

> 
> diff --git a/OvmfPkg/PciHostBridgeDxe/Ia32/IoFifo.S 
> b/OvmfPkg/PciHostBridgeDxe/Ia32/IoFifo.S
> deleted file mode 100644
> index 03a014d..000
> --- a/OvmfPkg/PciHostBridgeDxe/Ia32/IoFifo.S
> +++ /dev/null
> @@ -1,134 +0,0 @@
> -#--
> -#
> -# Copyright (c) 2006 - 2012, Intel Corporation. All rights reserved.
> -#
> -# This program and the accompanying materials are licensed and made available
> -# under the terms and conditions of the BSD License which accompanies this
> -# distribution.  The full text of the license may be found at
> -# http://opensource.org/licenses/bsd-license.php.
> -#
> -# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> -# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR 
> IMPLIED.
> -#
> -#--
> -
> -#--
> -#  VOID
> -#  EFIAPI
> -#  IoReadFifo8 (
> -#IN UINTN  Port,
> -#IN UINTN  Count,
> -#IN VOID   *Buffer
> -#);
> -#--
> -ASM_GLOBAL ASM_PFX(IoReadFifo8)
> -ASM_PFX(IoReadFifo8):
> -push%edi
> -cld
> -movw8(%esp), %dx
> -mov 12(%esp), %ecx
> -mov 16(%esp), %edi
> -rep insb
> -pop %edi
> -ret
> -
> -#--
> -#  VOID
> -#  EFIAPI
> -#  IoReadFifo16 (
> -#IN UINTN  Port,
> -#IN UINTN  Count,
> -#IN VOID   *Buffer
> -#);
> -#--
> -ASM_GLOBAL ASM_PFX(IoReadFifo16)
> -ASM_PFX(IoReadFifo16):
> -push%edi
> -cld
> -movw8(%esp), %dx
> -mov 12(%esp), %ecx
> -mov 16(%esp), %edi
> -rep insw
> -pop %edi
> -ret
> -
> -#--
> -#  VOID
> -#  EFIAPI
> -#  IoReadFifo32 (
> -#IN UINTN  Port,
> -#IN UINTN  Count,
> -#IN VOID   *Buffer
> -#);
> -#--
> -ASM_GLOBAL ASM_PFX(IoReadFifo32)
> -ASM_PFX(IoReadFifo32):
> -push%edi
> -cld
> -movw8(%esp), %dx
> -mov 12(%esp), %ecx
> -mov 16(%esp), %edi
> -rep insl
> -pop %edi
> -ret
> -
> -#--
> -#  VOID
> -#  EFIAPI
> -#  IoWriteFifo8 (
> -#IN UINTN  Port,
> -#IN UINTN  Count,
> -#IN VOID   *Buffer
> -#);
> -#--
> -ASM_GLOBAL ASM_PFX(IoWriteFifo8)
> -ASM_PFX(IoWriteFifo8):
> -push%esi
> -cld
> -movw8(%esp), %dx
> -mov 12(%esp), %ecx
> -mov 16(%esp), %esi
> -rep outsb
> -pop %esi
> -ret
> -
> -#--
> -#  VOID
> -#  EFIAPI
> -#  IoWriteFifo16 (
> -#IN UINTN  Port,
> -#IN UINTN  Count,
> -#IN VOID   *Buffer
> -#);
> -#--
> -ASM_GLOBAL ASM_PFX(IoWriteFifo16)
> -ASM_PFX(IoWriteFifo16):
> -push%esi
> -cld
> -movw8(%esp), %dx
> -mov 12(%esp), %ecx
> -mov 16(%esp), %esi
> -rep outsw
> -pop %esi
> -ret
> -
> -#--
> -#  VOID
> -#  EFIAPI
> -#  IoWriteFifo32 (
> -#IN UINTN  Port,
> -#IN UINTN  Count,
> -#IN VOID   *Buffer
> -#);
> -#--
> -ASM_GLOBAL ASM_PFX(IoWriteFifo32)
> -ASM_PFX(IoWriteFifo32):
> - 

[edk2] [PATCH] OvmfPkg: Enable Network2 Commands for IPv6

[Gary Lin]

Enable the network2 commands when NETWORK_IP6_ENABLE is TRUE, so we
would have Ping6 and Ifconfig6.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Gary Ching-Pang Lin 
---
 OvmfPkg/OvmfPkgIa32.dsc| 3 +++
 OvmfPkg/OvmfPkgIa32X64.dsc | 3 +++
 OvmfPkg/OvmfPkgX64.dsc | 3 +++
 3 files changed, 9 insertions(+)

diff --git a/OvmfPkg/OvmfPkgIa32.dsc b/OvmfPkg/OvmfPkgIa32.dsc
index 2b92850..9b603f0 100644
--- a/OvmfPkg/OvmfPkgIa32.dsc
+++ b/OvmfPkg/OvmfPkgIa32.dsc
@@ -686,6 +686,9 @@ [Components]
   
NULL|ShellPkg/Library/UefiShellDebug1CommandsLib/UefiShellDebug1CommandsLib.inf
   
NULL|ShellPkg/Library/UefiShellInstall1CommandsLib/UefiShellInstall1CommandsLib.inf
   
NULL|ShellPkg/Library/UefiShellNetwork1CommandsLib/UefiShellNetwork1CommandsLib.inf
+!if $(NETWORK_IP6_ENABLE) == TRUE
+  
NULL|ShellPkg/Library/UefiShellNetwork2CommandsLib/UefiShellNetwork2CommandsLib.inf
+!endif
   NULL|ShellPkg/Library/UefiShellTftpCommandLib/UefiShellTftpCommandLib.inf
   
HandleParsingLib|ShellPkg/Library/UefiHandleParsingLib/UefiHandleParsingLib.inf
   ShellLib|ShellPkg/Library/UefiShellLib/UefiShellLib.inf
diff --git a/OvmfPkg/OvmfPkgIa32X64.dsc b/OvmfPkg/OvmfPkgIa32X64.dsc
index 8d62718..1d68eb9 100644
--- a/OvmfPkg/OvmfPkgIa32X64.dsc
+++ b/OvmfPkg/OvmfPkgIa32X64.dsc
@@ -693,6 +693,9 @@ [Components.X64]
   
NULL|ShellPkg/Library/UefiShellDebug1CommandsLib/UefiShellDebug1CommandsLib.inf
   
NULL|ShellPkg/Library/UefiShellInstall1CommandsLib/UefiShellInstall1CommandsLib.inf
   
NULL|ShellPkg/Library/UefiShellNetwork1CommandsLib/UefiShellNetwork1CommandsLib.inf
+!if $(NETWORK_IP6_ENABLE) == TRUE
+  
NULL|ShellPkg/Library/UefiShellNetwork2CommandsLib/UefiShellNetwork2CommandsLib.inf
+!endif
   NULL|ShellPkg/Library/UefiShellTftpCommandLib/UefiShellTftpCommandLib.inf
   
HandleParsingLib|ShellPkg/Library/UefiHandleParsingLib/UefiHandleParsingLib.inf
   ShellLib|ShellPkg/Library/UefiShellLib/UefiShellLib.inf
diff --git a/OvmfPkg/OvmfPkgX64.dsc b/OvmfPkg/OvmfPkgX64.dsc
index e3f97f1..b971ee8 100644
--- a/OvmfPkg/OvmfPkgX64.dsc
+++ b/OvmfPkg/OvmfPkgX64.dsc
@@ -691,6 +691,9 @@ [Components]
   
NULL|ShellPkg/Library/UefiShellDebug1CommandsLib/UefiShellDebug1CommandsLib.inf
   
NULL|ShellPkg/Library/UefiShellInstall1CommandsLib/UefiShellInstall1CommandsLib.inf
   
NULL|ShellPkg/Library/UefiShellNetwork1CommandsLib/UefiShellNetwork1CommandsLib.inf
+!if $(NETWORK_IP6_ENABLE) == TRUE
+  
NULL|ShellPkg/Library/UefiShellNetwork2CommandsLib/UefiShellNetwork2CommandsLib.inf
+!endif
   NULL|ShellPkg/Library/UefiShellTftpCommandLib/UefiShellTftpCommandLib.inf
   
HandleParsingLib|ShellPkg/Library/UefiHandleParsingLib/UefiHandleParsingLib.inf
   ShellLib|ShellPkg/Library/UefiShellLib/UefiShellLib.inf
-- 
2.7.2

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Re: [edk2] [PATCH 0/5] OvmfPkg: enable PCIe on Q35

[Jordan Justen]

Series Reviewed-by: Jordan Justen 

On 2016-03-04 06:46:29, Laszlo Ersek wrote:
> The first two patches should fix
> , based on Marcel's
> analysis in that item. (Thanks a lot for that again!) These patches are
> (and should be) independent of -D USE_OLD_PCI_HOST; that is, they are
> active regardless of the fallback that we're temporarily retaining.
> 
> Michał, can you please test if the series solves your issue?
> 
> Then, based on the first two patches, the other three expose ECAM to the
> firmware modules proper (DXE and later). These do depend on
> USE_OLD_PCI_HOST==FALSE (which is the default now, and the only
> supported build in the mid term).
> 
> I tested & regression tested the series in a bunch of scenarios; the
> most interesting is probably the usual physical GPU assignment. On Q35,
> the core PciHostBridgeDxe now permits access to the full extended config
> space, and it works all right with the PCIe GTX750.
> 
> Gabriel, can you please check if your Q35 OSX guest(s) continue working
> with this?
> 
> Public branch: .
> 
> Cc: Gabriel Somlo 
> Cc: Jordan Justen 
> Cc: Marcel Apfelbaum 
> Cc: Michał Zegan 
> Cc: Ruiyu Ni 
> 
> Thanks!
> Laszlo
> 
> Laszlo Ersek (5):
>   OvmfPkg: IndustryStandard/Q35MchIch9.h: add PCIEXBAR macros
>   OvmfPkg: PlatformPei: enable PCIEXBAR (aka MMCONFIG / ECAM) on Q35
>   OvmfPkg: add DxePciLibI440FxQ35
>   OvmfPkg: match PCI config access to machine type (if not
> USE_OLD_PCI_HOST)
>   OvmfPkg: PciHostBridgeLib: permit access to the full extended config
> space
> 
>  OvmfPkg/Include/IndustryStandard/Q35MchIch9.h
>  |   8 +
>  OvmfPkg/Library/DxePciLibI440FxQ35/DxePciLibI440FxQ35.inf
>  |  47 ++
>  {MdePkg/Library/BasePciLibCf8 => 
> OvmfPkg/Library/DxePciLibI440FxQ35}/PciLib.c | 161 +++-
>  OvmfPkg/Library/PciHostBridgeLib/PciHostBridgeLib.c  
>  |   4 +-
>  OvmfPkg/Library/PciHostBridgeLib/PciHostBridgeLib.inf
>  |   1 +
>  OvmfPkg/OvmfPkgIa32.dsc  
>  |  29 
>  OvmfPkg/OvmfPkgIa32X64.dsc   
>  |  29 
>  OvmfPkg/OvmfPkgX64.dsc   
>  |  29 
>  OvmfPkg/PlatformPei/Platform.c   
>  |  81 ++
>  OvmfPkg/PlatformPei/PlatformPei.inf  
>  |   3 +
>  10 files changed, 356 insertions(+), 36 deletions(-)
>  create mode 100644 OvmfPkg/Library/DxePciLibI440FxQ35/DxePciLibI440FxQ35.inf
>  copy {MdePkg/Library/BasePciLibCf8 => 
> OvmfPkg/Library/DxePciLibI440FxQ35}/PciLib.c (85%)
> 
> -- 
> 1.8.3.1
> 
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