[edk2] [Patch] CryptoPkg/OpensslLib: Upgrade OpenSSL version to 1.0.2g

[Qin Long]

OpenSSL 1.0.2g was released with several severity fixes at
01-Mar-2016(https://www.openssl.org/news/secadv/20160301.txt).
Upgrade the supported OpenSSL version in CryptoPkg/OpensslLib to
catch the latest release 1.0.2g.
(NOTE: RT4175 from David Woodhouse was included in 1.0.2g. The
   new-generated patch will remove this part. And the line
   endings were still kept as before in this version for
   consistency)

CC: David Woodhouse 
CC: Ting Ye 
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Qin Long 
---
 CryptoPkg/CryptoPkg.dec|  2 +-
 ...ssl-1.0.2f.patch => EDKII_openssl-1.0.2g.patch} | 95 --
 CryptoPkg/Library/OpensslLib/Install.cmd   |  2 +-
 CryptoPkg/Library/OpensslLib/Install.sh|  2 +-
 CryptoPkg/Library/OpensslLib/OpensslLib.inf|  2 +-
 CryptoPkg/Library/OpensslLib/Patch-HOWTO.txt   | 26 +++---
 CryptoPkg/Library/OpensslLib/opensslconf.h |  6 ++
 7 files changed, 56 insertions(+), 79 deletions(-)
 rename CryptoPkg/Library/OpensslLib/{EDKII_openssl-1.0.2f.patch => 
EDKII_openssl-1.0.2g.patch} (94%)

diff --git a/CryptoPkg/CryptoPkg.dec b/CryptoPkg/CryptoPkg.dec
index 82d24f5..e1cdb8e 100644
--- a/CryptoPkg/CryptoPkg.dec
+++ b/CryptoPkg/CryptoPkg.dec
@@ -24,7 +24,7 @@
 
 [Includes]
   Include
-  Library/OpensslLib/openssl-1.0.2f/include
+  Library/OpensslLib/openssl-1.0.2g/include
 
 [LibraryClasses]
   ##  @libraryclass  Provides basic library functions for cryptographic 
primitives.
diff --git a/CryptoPkg/Library/OpensslLib/EDKII_openssl-1.0.2f.patch 
b/CryptoPkg/Library/OpensslLib/EDKII_openssl-1.0.2g.patch
similarity index 94%
rename from CryptoPkg/Library/OpensslLib/EDKII_openssl-1.0.2f.patch
rename to CryptoPkg/Library/OpensslLib/EDKII_openssl-1.0.2g.patch
index b799bf2..25dbebc 100644
--- a/CryptoPkg/Library/OpensslLib/EDKII_openssl-1.0.2f.patch
+++ b/CryptoPkg/Library/OpensslLib/EDKII_openssl-1.0.2g.patch
@@ -1,8 +1,8 @@
 diff --git a/Configure b/Configure
-index 4a715dc..b4a4781 100755
+index c98107a..c122709 100755
 --- a/Configure
 +++ b/Configure
-@@ -605,6 +605,9 @@ my %table=(
+@@ -609,6 +609,9 @@ my %table=(
  # with itself, Applink is never engaged and can as well be omitted.
  "mingw64", "gcc:-mno-cygwin -DL_ENDIAN -O3 -Wall -DWIN32_LEAN_AND_MEAN 
-DUNICODE -D_UNICODE::-D_MT:MINGW64:-lws2_32 -lgdi32 -lcrypt32:SIXTY_FOUR_BIT 
RC4_CHUNK_LL DES_INT 
EXPORT_VAR_AS_FN:${x86_64_asm}:mingw64:win32:cygwin-shared:-D_WINDLL:-mno-cygwin:.dll.a",
  
@@ -12,7 +12,7 @@ index 4a715dc..b4a4781 100755
  # UWIN 
  "UWIN", "cc:-DTERMIOS -DL_ENDIAN -O -Wall:::UWIN::BN_LLONG ${x86_gcc_des} 
${x86_gcc_opts}:${no_asm}:win32",
  
-@@ -1082,7 +1085,7 @@ if (defined($disabled{"tls1"}))
+@@ -1088,7 +1091,7 @@ if (defined($disabled{"tls1"}))
}
  
  if (defined($disabled{"ec"}) || defined($disabled{"dsa"})
@@ -22,7 +22,7 @@ index 4a715dc..b4a4781 100755
$disabled{"gost"} = "forced";
}
 diff --git a/apps/apps.c b/apps/apps.c
-index 2e77805..e21e759 100644
+index b1dd970..8278c28 100644
 --- a/apps/apps.c
 +++ b/apps/apps.c
 @@ -2374,6 +2374,8 @@ int args_verify(char ***pargs, int *pargc,
@@ -462,7 +462,7 @@ index c042cf2..a25b636 100644
  }
  
 diff --git a/crypto/cryptlib.c b/crypto/cryptlib.c
-index c9f674b..39ead7f 100644
+index 1925428..da4b34d 100644
 --- a/crypto/cryptlib.c
 +++ b/crypto/cryptlib.c
 @@ -263,7 +263,7 @@ int CRYPTO_get_new_dynlockid(void)
@@ -525,7 +525,7 @@ index c9f674b..39ead7f 100644
  }
 +#endif
  
- int CRYPTO_memcmp(const void *in_a, const void *in_b, size_t len)
+ int CRYPTO_memcmp(const volatile void *in_a, const volatile void *in_b, 
size_t len)
  {
 diff --git a/crypto/cryptlib.h b/crypto/cryptlib.h
 index fba180a..3e3ea5e 100644
@@ -542,7 +542,7 @@ index fba180a..3e3ea5e 100644
  
  #ifdef  __cplusplus
 diff --git a/crypto/crypto.h b/crypto/crypto.h
-index c450d7a..063d78e 100644
+index 6c644ce..bea4ca1 100644
 --- a/crypto/crypto.h
 +++ b/crypto/crypto.h
 @@ -235,15 +235,15 @@ typedef struct openssl_item_st {
@@ -656,7 +656,7 @@ index 46fa5ac..cc366ec 100644
  dh_kdf.o: ../../include/openssl/crypto.h ../../include/openssl/dh.h
  dh_kdf.o: ../../include/openssl/e_os2.h ../../include/openssl/ec.h
 diff --git a/crypto/dh/dh.h b/crypto/dh/dh.h
-index 5498a9d..4a5c665 100644
+index a5bd901..6488879 100644
 --- a/crypto/dh/dh.h
 +++ b/crypto/dh/dh.h
 @@ -240,11 +240,13 @@ DH *DH_get_1024_160(void);
@@ -1021,7 +1021,7 @@ index 5747c73..fe465cc 100644
   * These functions write a private key in PKCS#8 format: it is a "drop in"
   * replacement for PEM_write_bio_PrivateKey() and friends. As usual if 'enc'
 diff --git a/crypto/pkcs7/pk7_smime.c b/crypto/pkcs7/pk7_smime.c
-index c4d3724..0bc3d43 100644
+index dc9b484..0bc3d43 100644
 --- a/crypto/pkcs7/pk7_smime.c
 +++ b/crypto/pkcs7/pk7_smime.c
 @@ -64,6 +64,9 @@
@@ -1043,37 +1043,7 @@ index c4d3724..0bc3d43 100644
  int i, j = 0, k, ret = 0;
  BIO *p7bio = NULL;
  BIO *tmpin = NUL

Re: [edk2] [Patch] CryptoPkg: Fix the potential system hang issue

[David Woodhouse]

On Fri, 2016-03-11 at 12:35 +0800, Jiaxin Wu wrote:
> This patch is used to fix the potential system hang
> caused by the NULL 'time' parameter usage.

Looks good. Thanks.

> Cc: David Woodhouse 
> Cc: Long Qin 
> Cc: Ye Ting 
> Contributed-under: TianoCore Contribution Agreement 1.0
> Signed-off-by: Jiaxin Wu 

Reviewed-by: David Woodhouse 

-- 
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david.woodho...@intel.com  Intel Corporation



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Re: [edk2] [Patch 2/6] CryptoPkg: Add OpensslTlsLib module to enable 'openssl\ssl'

[David Woodhouse]

On Wed, 2016-02-24 at 16:15 +0800, Jiaxin Wu wrote:
> --- a/CryptoPkg/CryptoPkg.dsc
> +++ b/CryptoPkg/CryptoPkg.dsc
> @@ -48,10 +48,11 @@
>    
> UefiDriverEntryPoint|MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf
>    
> UefiApplicationEntryPoint|MdePkg/Library/UefiApplicationEntryPoint/UefiApplicationEntryPoint.inf
>  
>    IntrinsicLib|CryptoPkg/Library/IntrinsicLib/IntrinsicLib.inf
>    OpensslLib|CryptoPkg/Library/OpensslLib/OpensslLib.inf
> +  OpensslTlsLib|CryptoPkg/Library/OpensslLib/OpensslTlsLib.inf

One more thing... does this *need* to be a separate library?

It looks like the libraries are built into an archive and then linked
statically. So only those objects which are *referenced* are actually
pulled into the build. Which means that if we just *add* the ssl/
directory to the OpensslLib build, it will only be pulled in if
something *uses* it. Doesn't it?

-- 
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david.woodho...@intel.com  Intel Corporation




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Re: [edk2] [Patch] CryptoPkg/OpensslLib: Upgrade OpenSSL version to 1.0.2g

[David Woodhouse]

On Fri, 2016-03-11 at 00:20 -0800, Qin Long wrote:
> OpenSSL 1.0.2g was released with several severity fixes at
> 01-Mar-2016(https://www.openssl.org/news/secadv/20160301.txt).
> Upgrade the supported OpenSSL version in CryptoPkg/OpensslLib to
> catch the latest release 1.0.2g.
> (NOTE: RT4175 from David Woodhouse was included in 1.0.2g. The
>    new-generated patch will remove this part. And the line
>    endings were still kept as before in this version for
>    consistency)
> 
> CC: David Woodhouse 
> CC: Ting Ye 
> Contributed-under: TianoCore Contribution Agreement 1.0
> Signed-off-by: Qin Long 

Secure boot seems to work in OVMF using Laszlo's instructions (thanks
again). As does the Cryptest applications.

Reviewed-by: David Woodhouse 

-- 
-- 
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david.woodho...@intel.com  Intel Corporation



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Re: [edk2] [Patch 2/6] CryptoPkg: Add OpensslTlsLib module to enable 'openssl\ssl'

[Long, Qin]

> -Original Message-
> From: David Woodhouse [mailto:dw...@infradead.org]
> Sent: Friday, March 11, 2016 1:00 AM
> To: Wu, Jiaxin ; edk2-de...@ml01.01.org
> Cc: Ye, Ting ; Fu, Siyuan ; Long, Qin 
> 
> Subject: Re: [edk2] [Patch 2/6] CryptoPkg: Add OpensslTlsLib module to enable 
> 'openssl\ssl'
> 
> On Wed, 2016-02-24 at 16:15 +0800, Jiaxin Wu wrote:
> > --- a/CryptoPkg/CryptoPkg.dsc
> > +++ b/CryptoPkg/CryptoPkg.dsc
> > @@ -48,10 +48,11 @@
> >    
> > UefiDriverEntryPoint|MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf
> >    
> > UefiApplicationEntryPoint|MdePkg/Library/UefiApplicationEntryPoint/UefiApplicationEntryPoint.inf
> >
> >    IntrinsicLib|CryptoPkg/Library/IntrinsicLib/IntrinsicLib.inf
> >    OpensslLib|CryptoPkg/Library/OpensslLib/OpensslLib.inf
> > +  OpensslTlsLib|CryptoPkg/Library/OpensslLib/OpensslTlsLib.inf
> 
> One more thing... does this *need* to be a separate library?
> 
> It looks like the libraries are built into an archive and then linked
> statically. So only those objects which are *referenced* are actually
> pulled into the build. Which means that if we just *add* the ssl/
> directory to the OpensslLib build, it will only be pulled in if
> something *uses* it. Doesn't it?
> 

Yes, it's feasible to archive two libraries into one, and only referenced 
symbols will be included. 
The current design (separated libraries) is try to keep the original openssl 
layout (libcrypto and libssl). Different library serve as different scopes. Of 
cause, the name of OpensslLib.inf looks confusing, which should be one crypto 
library only. 

I agree the proposal looks also valuable. We should ever discuss this 
internally. Let me try and get some size data for evaluations (I think the 
total symbols / functions in image still highly depend on the capabilities of 
the compiler / linker). 

> --
> David WoodhouseOpen Source Technology Centre
> david.woodho...@intel.com  Intel Corporation
> 

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Re: [edk2] [Patch 2/6] CryptoPkg: Add OpensslTlsLib module to enable 'openssl\ssl'

[David Woodhouse]

On Fri, 2016-03-11 at 09:39 +, Long, Qin wrote:
> 
> > It looks like the libraries are built into an archive and then
> linked
> > statically. So only those objects which are *referenced* are
> actually
> > pulled into the build. Which means that if we just *add* the ssl/
> > directory to the OpensslLib build, it will only be pulled in if
> > something *uses* it. Doesn't it?
> > 
> 
> Yes, it's feasible to archive two libraries into one, and only
> referenced symbols will be included. 
> The current design (separated libraries) is try to keep the original
> openssl layout (libcrypto and libssl). Different library serve as
> different scopes. Of cause, the name of OpensslLib.inf looks
> confusing, which should be one crypto library only. 
> 
> I agree the proposal looks also valuable. We should ever discuss this
> internally. Let me try and get some size data for evaluations (I
> think the total symbols / functions in image still highly depend on
> the capabilities of the compiler / linker).

Yeah. With GCC we seem to have function granularity — if a function
isn't actually called, it gets completely dropped out of the image.

With MSVC it seems to be object file granularity. So if *one* function
in a given .obj file is called, that whole .obj file is included.

That's why we had additional problems with the MSVC build and needed
extra cleanups in the OpenSSL code (and I could reproduce them on Linux
by adding -fno-function-sections to the CFLAGS).

But I think that in both cases, we should have confidence that if you
don't *use* anything from the objects in the ssl/ directory, you won't
get anything else pulled in.

I'll try just fixing the process_files.sh script to include the ssl/*.c
files in the build. If I'm right, the resulting image will be
identical.

I'm slightly concerned by all the other duplication in the
OpensslTlsLib.inf file — the CFLAGS and other things. Merging them into
one, if it's technically feasible, does seem cleaner.

-- 
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david.woodho...@intel.com  Intel Corporation



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[edk2] [Patch] BaseTools: Add two macros into AutoGenObject macro dict

[Yonghong Zhu]

Add DEST_DIR_OUTPUT and DEST_DIR_DEBUG into AutoGenObject macro dict.
Because some module (eg: BaseUefiCpuLib) may use this macro in the make
file.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Yonghong Zhu 
---
 BaseTools/Source/Python/AutoGen/AutoGen.py | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/BaseTools/Source/Python/AutoGen/AutoGen.py 
b/BaseTools/Source/Python/AutoGen/AutoGen.py
index 05ce72b..7106a7c 100644
--- a/BaseTools/Source/Python/AutoGen/AutoGen.py
+++ b/BaseTools/Source/Python/AutoGen/AutoGen.py
@@ -2376,10 +2376,12 @@ class ModuleAutoGen(AutoGen):
 self._Macro["BIN_DIR"   ] = 
os.path.join(self.PlatformInfo.BuildDir, self.Arch)
 self._Macro["LIB_DIR"   ] = 
os.path.join(self.PlatformInfo.BuildDir, self.Arch)
 self._Macro["MODULE_BUILD_DIR"  ] = self.BuildDir
 self._Macro["OUTPUT_DIR"] = self.OutputDir
 self._Macro["DEBUG_DIR" ] = self.DebugDir
+self._Macro["DEST_DIR_OUTPUT"   ] = self.OutputDir
+self._Macro["DEST_DIR_DEBUG"] = self.DebugDir
 return self._Macro
 
 ## Return the module build data object
 def _GetModule(self):
 if self._Module == None:
-- 
2.6.1.windows.1

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Re: [edk2] [PATCH] ArmVirtPkg/VirtFdtDxe: set /chosen/linux, pci-probe-only to 1 in DTB

[Laszlo Ersek]

On 03/11/16 03:53, Ard Biesheuvel wrote:
> Unlike Linux on x86, which typically honors the PCI configuration performed
> by the firmware, Linux on ARM assumes that the PCI subsystem needs to be
> configured from scratch. This is not entirely unreasonable given the
> historical background of embedded systems using very basic bootloaders,
> but is no longer tenable with Linux on arm64 moving to UEFI and ACPI in the
> server space. For this reason, PCI support in the arm64 kernel running under
> ACPI is likely to move to the x86 model of honoring the PCI configuration
> done by the firmware.
> 
> So let's align with that in our DT based configuration as well, and set the
> /chosen/linux,pci-probe-only property to 1 in the Device Tree before we
> hand it to the OS.
> 
> In case we are exposing an emulated VGA PCI device to the guest, which may
> subsequently get exposed via the Graphics Output protocol and driven as an
> efifb by the OS, this ensures the PCI resource allocations for the framebuffer
> are not overridden, since that would cause the framebuffer to stop working.
> 
> Contributed-under: TianoCore Contribution Agreement 1.0
> Signed-off-by: Ard Biesheuvel 
> ---
>  ArmVirtPkg/VirtFdtDxe/VirtFdtDxe.c | 23 +++-
>  1 file changed, 22 insertions(+), 1 deletion(-)

The commit message is very clear, thanks for that.

> diff --git a/ArmVirtPkg/VirtFdtDxe/VirtFdtDxe.c 
> b/ArmVirtPkg/VirtFdtDxe/VirtFdtDxe.c
> index 74f80d1d2b78..36484a0bbb7e 100644
> --- a/ArmVirtPkg/VirtFdtDxe/VirtFdtDxe.c
> +++ b/ArmVirtPkg/VirtFdtDxe/VirtFdtDxe.c
> @@ -286,6 +286,7 @@ InitializeVirtFdtDxe (
>VOID   *DeviceTreeBase;
>INT32  Node, Prev;
>INT32  RtcNode;
> +  INT32  ChosenNode;
>EFI_STATUS Status;
>CONST CHAR8*Type;
>INT32  Len;
> @@ -356,8 +357,28 @@ InitializeVirtFdtDxe (
>ASSERT (Len == 2 * sizeof (UINT64));
>Status = ProcessPciHost (DeviceTreeBase, Node, RegProp);
>ASSERT_EFI_ERROR (Status);
> -  break;
>  
> +  //
> +  // Set the /chosen/linux,pci-probe-only property to 1, so that the PCI
> +  // setup we will perform in the firmware is honored by the Linux OS,
> +  // rather than torn down and done from scratch. This is generally a 
> more
> +  // sensible approach, and aligns with what ACPI based OSes do in 
> general.
> +  //
> +  // In case we are exposing an emulated VGA PCI device to the guest, 
> which
> +  // may subsequently get exposed via the Graphics Output protocol and
> +  // driven as an efifb by Linux, we need this setting to prevent the
> +  // framebuffer from becoming unresponsive.
> +  //
> +  ChosenNode = fdt_path_offset (DeviceTreeBase, "/chosen");
> +  if (ChosenNode < 0) {
> +ChosenNode = fdt_add_subnode (DeviceTreeBase, 0, "/chosen");
> +  }
> +  if (ChosenNode < 0) {
> +DEBUG ((EFI_D_WARN, "Failed to set /chosen/linux,pci-probe-only 
> property"));
> +break;
> +  }
> +  fdt_setprop_u32 (DeviceTreeBase, ChosenNode, "linux,pci-probe-only", 
> 1);
> +  break;
>  case PropertyTypeFwCfg:
>ASSERT (Len == 2 * sizeof (UINT64));

Can you please move this logic out of the loop? I reviewed the
documentation for fdt_add_subnode() and fdt_setprop_u32(), and they can
both insert new data in the device tree, changing the offsets of some
existing nodes.

Theoretically, this could mean that the offset of the current node
changes, and then the Prev = Node; fdt_next_node (... Prev ... )
sequence might not work. Without the libfdt header giving more specific
guarantees, I think we should keep all modifications of the device tree
out of the loop body -- the iteration should be read only.

There is already an example for this, the modification of the RTC node
near the end of the function. In order to constrain the logic to the
case when a PCI host node is present, you could introduce a boolean flag
(to be set under the case label), or even compare
PcdPciExpressBaseAddress against zero (it is set by ProcessPciHost()).

... Actually, since the loop caches the RtcNode offset as well, that's
another thing that could break if we inserted nodes or properties during
the iteration. So this manipulation has to happen after disabling the
RTC -- looking up /chosen from scratch will work fine even then.

Thanks
Laszlo
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Re: [edk2] [PATCH] ArmVirtPkg/VirtFdtDxe: set /chosen/linux, pci-probe-only to 1 in DTB

[Ard Biesheuvel]

On 11 March 2016 at 18:47, Laszlo Ersek  wrote:
> On 03/11/16 03:53, Ard Biesheuvel wrote:
>> Unlike Linux on x86, which typically honors the PCI configuration performed
>> by the firmware, Linux on ARM assumes that the PCI subsystem needs to be
>> configured from scratch. This is not entirely unreasonable given the
>> historical background of embedded systems using very basic bootloaders,
>> but is no longer tenable with Linux on arm64 moving to UEFI and ACPI in the
>> server space. For this reason, PCI support in the arm64 kernel running under
>> ACPI is likely to move to the x86 model of honoring the PCI configuration
>> done by the firmware.
>>
>> So let's align with that in our DT based configuration as well, and set the
>> /chosen/linux,pci-probe-only property to 1 in the Device Tree before we
>> hand it to the OS.
>>
>> In case we are exposing an emulated VGA PCI device to the guest, which may
>> subsequently get exposed via the Graphics Output protocol and driven as an
>> efifb by the OS, this ensures the PCI resource allocations for the 
>> framebuffer
>> are not overridden, since that would cause the framebuffer to stop working.
>>
>> Contributed-under: TianoCore Contribution Agreement 1.0
>> Signed-off-by: Ard Biesheuvel 
>> ---
>>  ArmVirtPkg/VirtFdtDxe/VirtFdtDxe.c | 23 +++-
>>  1 file changed, 22 insertions(+), 1 deletion(-)
>
> The commit message is very clear, thanks for that.
>
>> diff --git a/ArmVirtPkg/VirtFdtDxe/VirtFdtDxe.c 
>> b/ArmVirtPkg/VirtFdtDxe/VirtFdtDxe.c
>> index 74f80d1d2b78..36484a0bbb7e 100644
>> --- a/ArmVirtPkg/VirtFdtDxe/VirtFdtDxe.c
>> +++ b/ArmVirtPkg/VirtFdtDxe/VirtFdtDxe.c
>> @@ -286,6 +286,7 @@ InitializeVirtFdtDxe (
>>VOID   *DeviceTreeBase;
>>INT32  Node, Prev;
>>INT32  RtcNode;
>> +  INT32  ChosenNode;
>>EFI_STATUS Status;
>>CONST CHAR8*Type;
>>INT32  Len;
>> @@ -356,8 +357,28 @@ InitializeVirtFdtDxe (
>>ASSERT (Len == 2 * sizeof (UINT64));
>>Status = ProcessPciHost (DeviceTreeBase, Node, RegProp);
>>ASSERT_EFI_ERROR (Status);
>> -  break;
>>
>> +  //
>> +  // Set the /chosen/linux,pci-probe-only property to 1, so that the PCI
>> +  // setup we will perform in the firmware is honored by the Linux OS,
>> +  // rather than torn down and done from scratch. This is generally a 
>> more
>> +  // sensible approach, and aligns with what ACPI based OSes do in 
>> general.
>> +  //
>> +  // In case we are exposing an emulated VGA PCI device to the guest, 
>> which
>> +  // may subsequently get exposed via the Graphics Output protocol and
>> +  // driven as an efifb by Linux, we need this setting to prevent the
>> +  // framebuffer from becoming unresponsive.
>> +  //
>> +  ChosenNode = fdt_path_offset (DeviceTreeBase, "/chosen");
>> +  if (ChosenNode < 0) {
>> +ChosenNode = fdt_add_subnode (DeviceTreeBase, 0, "/chosen");
>> +  }
>> +  if (ChosenNode < 0) {
>> +DEBUG ((EFI_D_WARN, "Failed to set /chosen/linux,pci-probe-only 
>> property"));
>> +break;
>> +  }
>> +  fdt_setprop_u32 (DeviceTreeBase, ChosenNode, "linux,pci-probe-only", 
>> 1);
>> +  break;
>>  case PropertyTypeFwCfg:
>>ASSERT (Len == 2 * sizeof (UINT64));
>
> Can you please move this logic out of the loop? I reviewed the
> documentation for fdt_add_subnode() and fdt_setprop_u32(), and they can
> both insert new data in the device tree, changing the offsets of some
> existing nodes.
>
> Theoretically, this could mean that the offset of the current node
> changes, and then the Prev = Node; fdt_next_node (... Prev ... )
> sequence might not work. Without the libfdt header giving more specific
> guarantees, I think we should keep all modifications of the device tree
> out of the loop body -- the iteration should be read only.
>
> There is already an example for this, the modification of the RTC node
> near the end of the function. In order to constrain the logic to the
> case when a PCI host node is present, you could introduce a boolean flag
> (to be set under the case label), or even compare
> PcdPciExpressBaseAddress against zero (it is set by ProcessPciHost()).
>
> ... Actually, since the loop caches the RtcNode offset as well, that's
> another thing that could break if we inserted nodes or properties during
> the iteration. So this manipulation has to happen after disabling the
> RTC -- looking up /chosen from scratch will work fine even then.
>

Ah yes, how sloppy of me. I will just add a boolean, and move this
code to the end of the function.

Thanks,
Ard.
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[edk2] [PATCH v2] ArmVirtPkg/VirtFdtDxe: set /chosen/linux, pci-probe-only to 1 in DTB

[Ard Biesheuvel]

Unlike Linux on x86, which typically honors the PCI configuration performed
by the firmware, Linux on ARM assumes that the PCI subsystem needs to be
configured from scratch. This is not entirely unreasonable given the
historical background of embedded systems using very basic bootloaders,
but is no longer tenable with Linux on arm64 moving to UEFI and ACPI in the
server space. For this reason, PCI support in the arm64 kernel running under
ACPI is likely to move to the x86 model of honoring the PCI configuration
done by the firmware.

So let's align with that in our DT based configuration as well, and set the
/chosen/linux,pci-probe-only property to 1 in the Device Tree before we
hand it to the OS.

In case we are exposing an emulated VGA PCI device to the guest, which may
subsequently get exposed via the Graphics Output protocol and driven as an
efifb by the OS, this ensures the PCI resource allocations for the framebuffer
are not overridden, since that would cause the framebuffer to stop working.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel 
---
 ArmVirtPkg/VirtFdtDxe/VirtFdtDxe.c | 27 +++-
 1 file changed, 26 insertions(+), 1 deletion(-)

diff --git a/ArmVirtPkg/VirtFdtDxe/VirtFdtDxe.c 
b/ArmVirtPkg/VirtFdtDxe/VirtFdtDxe.c
index 74f80d1d2b78..4e4989751455 100644
--- a/ArmVirtPkg/VirtFdtDxe/VirtFdtDxe.c
+++ b/ArmVirtPkg/VirtFdtDxe/VirtFdtDxe.c
@@ -304,6 +304,7 @@ InitializeVirtFdtDxe (
   UINT64 FwCfgDataSize;
   UINT64 FwCfgDmaAddress;
   UINT64 FwCfgDmaSize;
+  BOOLEANHavePci;
 
   Hob = GetFirstGuidHob(&gFdtHobGuid);
   if (Hob == NULL || GET_GUID_HOB_DATA_SIZE (Hob) != sizeof (UINT64)) {
@@ -322,6 +323,7 @@ InitializeVirtFdtDxe (
   DEBUG ((EFI_D_INFO, "%a: DTB @ 0x%p\n", __FUNCTION__, DeviceTreeBase));
 
   RtcNode = -1;
+  HavePci = FALSE;
   //
   // Now enumerate the nodes and install peripherals that we are interested in,
   // i.e., GIC, RTC and virtio MMIO nodes
@@ -356,8 +358,8 @@ InitializeVirtFdtDxe (
   ASSERT (Len == 2 * sizeof (UINT64));
   Status = ProcessPciHost (DeviceTreeBase, Node, RegProp);
   ASSERT_EFI_ERROR (Status);
+  HavePci = TRUE;
   break;
-
 case PropertyTypeFwCfg:
   ASSERT (Len == 2 * sizeof (UINT64));
 
@@ -579,5 +581,28 @@ InitializeVirtFdtDxe (
 "disabled") != 0) {
 DEBUG ((EFI_D_WARN, "Failed to set PL031 status to 'disabled'\n"));
   }
+
+  if (HavePci) {
+//
+// Set the /chosen/linux,pci-probe-only property to 1, so that the PCI
+// setup we will perform in the firmware is honored by the Linux OS,
+// rather than torn down and done from scratch. This is generally a more
+// sensible approach, and aligns with what ACPI based OSes do in general.
+//
+// In case we are exposing an emulated VGA PCI device to the guest, which
+// may subsequently get exposed via the Graphics Output protocol and
+// driven as an efifb by Linux, we need this setting to prevent the
+// framebuffer from becoming unresponsive.
+//
+Node = fdt_path_offset (DeviceTreeBase, "/chosen");
+if (Node < 0) {
+  Node = fdt_add_subnode (DeviceTreeBase, 0, "/chosen");
+}
+if (Node < 0 ||
+fdt_setprop_u32 (DeviceTreeBase, Node, "linux,pci-probe-only", 1) < 0) 
{
+  DEBUG ((EFI_D_WARN, "Failed to set /chosen/linux,pci-probe-only 
property"));
+}
+  }
+
   return EFI_SUCCESS;
 }
-- 
1.9.1

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Re: [edk2] [PATCH v2] ArmVirtPkg/VirtFdtDxe: set /chosen/linux, pci-probe-only to 1 in DTB

[Laszlo Ersek]

On 03/11/16 13:19, Ard Biesheuvel wrote:
> Unlike Linux on x86, which typically honors the PCI configuration performed
> by the firmware, Linux on ARM assumes that the PCI subsystem needs to be
> configured from scratch. This is not entirely unreasonable given the
> historical background of embedded systems using very basic bootloaders,
> but is no longer tenable with Linux on arm64 moving to UEFI and ACPI in the
> server space. For this reason, PCI support in the arm64 kernel running under
> ACPI is likely to move to the x86 model of honoring the PCI configuration
> done by the firmware.
> 
> So let's align with that in our DT based configuration as well, and set the
> /chosen/linux,pci-probe-only property to 1 in the Device Tree before we
> hand it to the OS.
> 
> In case we are exposing an emulated VGA PCI device to the guest, which may
> subsequently get exposed via the Graphics Output protocol and driven as an
> efifb by the OS, this ensures the PCI resource allocations for the framebuffer
> are not overridden, since that would cause the framebuffer to stop working.
> 
> Contributed-under: TianoCore Contribution Agreement 1.0
> Signed-off-by: Ard Biesheuvel 
> ---
>  ArmVirtPkg/VirtFdtDxe/VirtFdtDxe.c | 27 +++-
>  1 file changed, 26 insertions(+), 1 deletion(-)
> 
> diff --git a/ArmVirtPkg/VirtFdtDxe/VirtFdtDxe.c 
> b/ArmVirtPkg/VirtFdtDxe/VirtFdtDxe.c
> index 74f80d1d2b78..4e4989751455 100644
> --- a/ArmVirtPkg/VirtFdtDxe/VirtFdtDxe.c
> +++ b/ArmVirtPkg/VirtFdtDxe/VirtFdtDxe.c
> @@ -304,6 +304,7 @@ InitializeVirtFdtDxe (
>UINT64 FwCfgDataSize;
>UINT64 FwCfgDmaAddress;
>UINT64 FwCfgDmaSize;
> +  BOOLEANHavePci;
>  
>Hob = GetFirstGuidHob(&gFdtHobGuid);
>if (Hob == NULL || GET_GUID_HOB_DATA_SIZE (Hob) != sizeof (UINT64)) {
> @@ -322,6 +323,7 @@ InitializeVirtFdtDxe (
>DEBUG ((EFI_D_INFO, "%a: DTB @ 0x%p\n", __FUNCTION__, DeviceTreeBase));
>  
>RtcNode = -1;
> +  HavePci = FALSE;
>//
>// Now enumerate the nodes and install peripherals that we are interested 
> in,
>// i.e., GIC, RTC and virtio MMIO nodes
> @@ -356,8 +358,8 @@ InitializeVirtFdtDxe (
>ASSERT (Len == 2 * sizeof (UINT64));
>Status = ProcessPciHost (DeviceTreeBase, Node, RegProp);
>ASSERT_EFI_ERROR (Status);
> +  HavePci = TRUE;
>break;
> -

Any particular reason to remove this empty line? I think it should be kept.

>  case PropertyTypeFwCfg:
>ASSERT (Len == 2 * sizeof (UINT64));
>  
> @@ -579,5 +581,28 @@ InitializeVirtFdtDxe (
>  "disabled") != 0) {
>  DEBUG ((EFI_D_WARN, "Failed to set PL031 status to 'disabled'\n"));
>}
> +
> +  if (HavePci) {
> +//
> +// Set the /chosen/linux,pci-probe-only property to 1, so that the PCI
> +// setup we will perform in the firmware is honored by the Linux OS,
> +// rather than torn down and done from scratch. This is generally a more
> +// sensible approach, and aligns with what ACPI based OSes do in general.
> +//
> +// In case we are exposing an emulated VGA PCI device to the guest, which
> +// may subsequently get exposed via the Graphics Output protocol and
> +// driven as an efifb by Linux, we need this setting to prevent the
> +// framebuffer from becoming unresponsive.
> +//
> +Node = fdt_path_offset (DeviceTreeBase, "/chosen");
> +if (Node < 0) {
> +  Node = fdt_add_subnode (DeviceTreeBase, 0, "/chosen");
> +}
> +if (Node < 0 ||
> +fdt_setprop_u32 (DeviceTreeBase, Node, "linux,pci-probe-only", 1) < 
> 0) {
> +  DEBUG ((EFI_D_WARN, "Failed to set /chosen/linux,pci-probe-only 
> property"));

Another nit (sorry I did notice this in v1, but ultimately forgot to
mention it): please add a "\n" at the end of the warning.

Please fix these up before you commit the patch.

Reviewed-by: Laszlo Ersek 

Thanks!
Laszlo

> +}
> +  }
> +
>return EFI_SUCCESS;
>  }
> 

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Re: [edk2] [PATCH v2] ArmVirtPkg/VirtFdtDxe: set /chosen/linux, pci-probe-only to 1 in DTB

[Ard Biesheuvel]

On 11 March 2016 at 19:25, Laszlo Ersek  wrote:
> On 03/11/16 13:19, Ard Biesheuvel wrote:
>> Unlike Linux on x86, which typically honors the PCI configuration performed
>> by the firmware, Linux on ARM assumes that the PCI subsystem needs to be
>> configured from scratch. This is not entirely unreasonable given the
>> historical background of embedded systems using very basic bootloaders,
>> but is no longer tenable with Linux on arm64 moving to UEFI and ACPI in the
>> server space. For this reason, PCI support in the arm64 kernel running under
>> ACPI is likely to move to the x86 model of honoring the PCI configuration
>> done by the firmware.
>>
>> So let's align with that in our DT based configuration as well, and set the
>> /chosen/linux,pci-probe-only property to 1 in the Device Tree before we
>> hand it to the OS.
>>
>> In case we are exposing an emulated VGA PCI device to the guest, which may
>> subsequently get exposed via the Graphics Output protocol and driven as an
>> efifb by the OS, this ensures the PCI resource allocations for the 
>> framebuffer
>> are not overridden, since that would cause the framebuffer to stop working.
>>
>> Contributed-under: TianoCore Contribution Agreement 1.0
>> Signed-off-by: Ard Biesheuvel 
>> ---
>>  ArmVirtPkg/VirtFdtDxe/VirtFdtDxe.c | 27 +++-
>>  1 file changed, 26 insertions(+), 1 deletion(-)
>>
>> diff --git a/ArmVirtPkg/VirtFdtDxe/VirtFdtDxe.c 
>> b/ArmVirtPkg/VirtFdtDxe/VirtFdtDxe.c
>> index 74f80d1d2b78..4e4989751455 100644
>> --- a/ArmVirtPkg/VirtFdtDxe/VirtFdtDxe.c
>> +++ b/ArmVirtPkg/VirtFdtDxe/VirtFdtDxe.c
>> @@ -304,6 +304,7 @@ InitializeVirtFdtDxe (
>>UINT64 FwCfgDataSize;
>>UINT64 FwCfgDmaAddress;
>>UINT64 FwCfgDmaSize;
>> +  BOOLEANHavePci;
>>
>>Hob = GetFirstGuidHob(&gFdtHobGuid);
>>if (Hob == NULL || GET_GUID_HOB_DATA_SIZE (Hob) != sizeof (UINT64)) {
>> @@ -322,6 +323,7 @@ InitializeVirtFdtDxe (
>>DEBUG ((EFI_D_INFO, "%a: DTB @ 0x%p\n", __FUNCTION__, DeviceTreeBase));
>>
>>RtcNode = -1;
>> +  HavePci = FALSE;
>>//
>>// Now enumerate the nodes and install peripherals that we are interested 
>> in,
>>// i.e., GIC, RTC and virtio MMIO nodes
>> @@ -356,8 +358,8 @@ InitializeVirtFdtDxe (
>>ASSERT (Len == 2 * sizeof (UINT64));
>>Status = ProcessPciHost (DeviceTreeBase, Node, RegProp);
>>ASSERT_EFI_ERROR (Status);
>> +  HavePci = TRUE;
>>break;
>> -
>
> Any particular reason to remove this empty line? I think it should be kept.
>

Post-conference exhaustion syndrome, mostly, and the fact that the red
'-' does not stand out in my grey-on-black terminal


>>  case PropertyTypeFwCfg:
>>ASSERT (Len == 2 * sizeof (UINT64));
>>
>> @@ -579,5 +581,28 @@ InitializeVirtFdtDxe (
>>  "disabled") != 0) {
>>  DEBUG ((EFI_D_WARN, "Failed to set PL031 status to 'disabled'\n"));
>>}
>> +
>> +  if (HavePci) {
>> +//
>> +// Set the /chosen/linux,pci-probe-only property to 1, so that the PCI
>> +// setup we will perform in the firmware is honored by the Linux OS,
>> +// rather than torn down and done from scratch. This is generally a more
>> +// sensible approach, and aligns with what ACPI based OSes do in 
>> general.
>> +//
>> +// In case we are exposing an emulated VGA PCI device to the guest, 
>> which
>> +// may subsequently get exposed via the Graphics Output protocol and
>> +// driven as an efifb by Linux, we need this setting to prevent the
>> +// framebuffer from becoming unresponsive.
>> +//
>> +Node = fdt_path_offset (DeviceTreeBase, "/chosen");
>> +if (Node < 0) {
>> +  Node = fdt_add_subnode (DeviceTreeBase, 0, "/chosen");
>> +}
>> +if (Node < 0 ||
>> +fdt_setprop_u32 (DeviceTreeBase, Node, "linux,pci-probe-only", 1) < 
>> 0) {
>> +  DEBUG ((EFI_D_WARN, "Failed to set /chosen/linux,pci-probe-only 
>> property"));
>
> Another nit (sorry I did notice this in v1, but ultimately forgot to
> mention it): please add a "\n" at the end of the warning.
>
> Please fix these up before you commit the patch.
>
> Reviewed-by: Laszlo Ersek 
>

Thanks. Committed as 8b816c624dd4
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Re: [edk2] [PATCH v3] NetworkPkg: Add URI configuration form to HTTP boot driver.

[Laszlo Ersek]

On 03/11/16 05:26, Gary Lin wrote:
> On Thu, Mar 10, 2016 at 12:31:18PM +0100, Laszlo Ersek wrote:
>> On 03/10/16 11:02, Gary Lin wrote:
>>> On Thu, Mar 10, 2016 at 10:20:12AM +0100, Laszlo Ersek wrote:
 On 03/10/16 08:49, Gary Lin wrote:
>>
> I found that it's related to iPXE. If I disable iPXE with
>
> "-netdev user,id=hostnet0 -device virtio-net-pci,romfile=,netdev=hostnet0"
>
> then everything works as expected. I'll try to dig deeper to find more
> information.

 How fresh is your ipxe? And did you build it with CONFIG=qemu?

>>> It comes from the qemu 2.5.0 tarball and I just installed it from
>>> openSUSE Virtualization repo.
>>> https://build.opensuse.org/package/show/Virtualization/qemu
>>
>> QEMU 2.5 bundles iPXE binaries built with CONFIG=qemu, but that
>> configuration doesn't enable IPv6 for the moment.
>>
>> Apparently, combining iPXE (CONFIG=qemu) with NETWORK_IP6_ENABLE (set in
>> OVMF) causes problems. I don't understand how this causes side effects,
>> because CONFIG=qemu instructs iPXE to provide SNP drivers only. SNP is
>> independent of IP version.
>>
>> With this combination, IPv6 PXE should work (not be absent), and IPv6
>> HTTP Boot should work too (not blow up).
>>
>> Can you perhaps remove grub2 from the equation? What if you play with
>> disconnect / reconnect / connect in the UEFI shell?
>>
> hmmm I found another way to crash the system with a different assert.
> 
> Just disconnect/reconnect the handle providing HttpServiceBinding, and
> OVMF crashed with/without iPXE:
> 
> ASSERT /home/gary/git/edk2/NetworkPkg/HttpBootDxe/HttpBootDxe.c(796): CR has 
> Bad Signature
> 
> Here is the function that issues the assert.
> 
> EFIAPI HttpBootIp6DxeDriverBindingStart ()
>   ...
>   if (!EFI_ERROR (Status)) {
> Private = HTTP_BOOT_PRIVATE_DATA_FROM_ID(Id); < CRASH
>   } else {
>   ...
> 
> This also only happens after fa848a4048943251fc057fe8d6c5a82e01d2ffb6.

Here's a stack dump:

#0  0x7e86cd8c in CpuDeadLoop () at 
MdePkg/Library/BaseLib/CpuDeadLoop.c:37
#1  0x7e86756c in DebugAssert (FileName=0x7e86d7c8 
"NetworkPkg/HttpBootDxe/HttpBootDxe.c", LineNumber=796, Description=0x7e86d823 
"CR has Bad Signature")
at OvmfPkg/Library/PlatformDebugLibIoPort/DebugLib.c:153
#2  0x7e85a8bf in HttpBootIp6DxeDriverBindingStart (This=0x7e871e60, 
ControllerHandle=0x7f040d98, RemainingDevicePath=0x0) at 
NetworkPkg/HttpBootDxe/HttpBootDxe.c:796
#3  0x7ff6afc0 in CoreConnectSingleController 
(ControllerHandle=0x7f040d98, ContextDriverImageHandles=0x0, 
RemainingDevicePath=0x0) at MdeModulePkg/Core/Dxe/Hand/DriverSupport.c:646
#4  0x7ff6a2cf in CoreConnectController (ControllerHandle=0x7f040d98, 
DriverImageHandle=0x0, RemainingDevicePath=0x0, Recursive=1 '\001') at 
MdeModulePkg/Core/Dxe/Hand/DriverSupport.c:137
#5  0x7ff6d887 in CoreDisconnectControllersUsingProtocolInterface 
(UserHandle=0x7f040d98, Prot=0x7eecfb98) at 
MdeModulePkg/Core/Dxe/Hand/Handle.c:687
#6  0x7ff6d955 in CoreUninstallProtocolInterface 
(UserHandle=0x7f040d98, Protocol=0x7e885f60 
, Interface=0x7eecfce0) at 
MdeModulePkg/Core/Dxe/Hand/Handle.c:754
#7  0x7e87536b in HttpDxeStop (This=0x7e8860e0, 
ControllerHandle=0x7eed3cd8, NumberOfChildren=0, ChildHandleBuffer=0x0, 
IpVersion=6 '\006') at NetworkPkg/HttpDxe/HttpDriver.c:576
#8  0x7e875509 in HttpDxeIp6DriverBindingStop (This=0x7e8860e0, 
ControllerHandle=0x7eed3cd8, NumberOfChildren=0, ChildHandleBuffer=0x0) at 
NetworkPkg/HttpDxe/HttpDriver.c:891
#9  0x7ff6b987 in CoreDisconnectController 
(ControllerHandle=0x7eed3cd8, DriverImageHandle=0x7f17ebd8, ChildHandle=0x0) at 
MdeModulePkg/Core/Dxe/Hand/DriverSupport.c:938
#10 0x7ff6d6fc in CoreDisconnectControllersUsingProtocolInterface 
(UserHandle=0x7eed3cd8, Prot=0x7eed3c58) at 
MdeModulePkg/Core/Dxe/Hand/Handle.c:651
#11 0x7ff6d955 in CoreUninstallProtocolInterface 
(UserHandle=0x7eed3cd8, Protocol=0x7e948f10 , 
Interface=0x7eed3a38) at MdeModulePkg/Core/Dxe/Hand/Handle.c:754
#12 0x7ff6dafd in CoreUninstallMultipleProtocolInterfaces 
(Handle=0x7eed3cd8) at MdeModulePkg/Core/Dxe/Hand/Handle.c:854
#13 0x7e935f6c in SockDestroy (Sock=0x7eed3918) at 
NetworkPkg/TcpDxe/SockImpl.c:849
#14 0x7e92af15 in SockDestroyChild (Sock=0x7eed3918) at 
NetworkPkg/TcpDxe/SockInterface.c:195
#15 0x7e92aaf6 in TcpServiceBindingDestroyChild (This=0x7e78dd00, 
ChildHandle=0x7eed3cd8) at NetworkPkg/TcpDxe/TcpDriver.c:1002
#16 0x7e92a018 in TcpDestroyChildEntryInHandleBuffer (Entry=0x7eed3940, 
Context=0x7ff5dc20) at NetworkPkg/TcpDxe/TcpDriver.c:401
#17 0x7e93fd63 in NetDestroyLinkList (List=0x7e78dd10, 
CallBack=0x7e929f2d , Context=0x7ff5dc20, 
ListLength=0x0) at MdeModulePkg/Library/DxeNetLib/DxeNetLib.c:1117
#18 0x7e92a1ee in TcpDestroyService (Controller=0x7ee18d18, 
ImageHandle=0x7f1852d8, NumberOfChildren=2, ChildHandleBuffer=0x7ee52d98, 
Ip

[edk2] performance problem with the UEFI shell's DEVICES command

[Laszlo Ersek]

Hi,

not sure if I'm doing wrong something, but when I run the DEVICES
command, it pegs the CPU, and prints about 1 line per second near the
end of the list. Near the beginning of the list, a line can take several
seconds. I vaguely remember that this used to be much faster.

Thanks
Laszlo
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Re: [edk2] [PATCH v3] NetworkPkg: Add URI configuration form to HTTP boot driver.

[Laszlo Ersek]

On 03/11/16 05:26, Gary Lin wrote:
> On Thu, Mar 10, 2016 at 12:31:18PM +0100, Laszlo Ersek wrote:
>> On 03/10/16 11:02, Gary Lin wrote:
>>> On Thu, Mar 10, 2016 at 10:20:12AM +0100, Laszlo Ersek wrote:
 On 03/10/16 08:49, Gary Lin wrote:
>>
> I found that it's related to iPXE. If I disable iPXE with
>
> "-netdev user,id=hostnet0 -device virtio-net-pci,romfile=,netdev=hostnet0"
>
> then everything works as expected. I'll try to dig deeper to find more
> information.

 How fresh is your ipxe? And did you build it with CONFIG=qemu?

>>> It comes from the qemu 2.5.0 tarball and I just installed it from
>>> openSUSE Virtualization repo.
>>> https://build.opensuse.org/package/show/Virtualization/qemu
>>
>> QEMU 2.5 bundles iPXE binaries built with CONFIG=qemu, but that
>> configuration doesn't enable IPv6 for the moment.
>>
>> Apparently, combining iPXE (CONFIG=qemu) with NETWORK_IP6_ENABLE (set in
>> OVMF) causes problems. I don't understand how this causes side effects,
>> because CONFIG=qemu instructs iPXE to provide SNP drivers only. SNP is
>> independent of IP version.
>>
>> With this combination, IPv6 PXE should work (not be absent), and IPv6
>> HTTP Boot should work too (not blow up).
>>
>> Can you perhaps remove grub2 from the equation? What if you play with
>> disconnect / reconnect / connect in the UEFI shell?
>>
> hmmm I found another way to crash the system with a different assert.
> 
> Just disconnect/reconnect the handle providing HttpServiceBinding, and
> OVMF crashed with/without iPXE:
> 
> ASSERT /home/gary/git/edk2/NetworkPkg/HttpBootDxe/HttpBootDxe.c(796): CR has 
> Bad Signature
> 
> Here is the function that issues the assert.
> 
> EFIAPI HttpBootIp6DxeDriverBindingStart ()
>   ...
>   if (!EFI_ERROR (Status)) {
> Private = HTTP_BOOT_PRIVATE_DATA_FROM_ID(Id); < CRASH
>   } else {
>   ...
> 
> This also only happens after fa848a4048943251fc057fe8d6c5a82e01d2ffb6.

I found the bug. There are two key UEFI facts that are necessary for
understanding it.

(1) The first fact is that for any given handle, at most one instance of
a given protocol interface (= GUID) can be installed on it. In other
words, if you pick a handle, and pick a GUID, the handle either has the
protocol interface installed, or not. The handle cannot have two or more
instances of the same protocol.

(2) The second fact is how the DisconnectController() boot service
works, in case the DriverImageHandle parameter is specified as non-NULL,
and the ChildHandle parameter is NULL. (This case means "disconnect the
given driver from the given controller".) Let me quote the spec:

A driver is disconnected from a controller by calling the Stop()
service of the EFI_DRIVER_BINDING_PROTOCOL. The
EFI_DRIVER_BINDING_PROTOCOL is on the driver image handle, and the
handle of the controller is passed into the Stop() service.

Now put the two facts together. You have a driver. For the driver, you
have one ImageHandle. On that handle, you can install one instance of
the driver binding protocol (due to fact (1)). So, when someone wants to
disconnect a given controller from your driver, and calls
gBS->DisconnectController() accordingly, exactly *one* Stop() function
in your driver will be called. After that, the DisconnectController()
boot service will return, and a complete successful disconnection
between your driver and the controller will be assumed by the system.

The HttpBootDxe driver violates this.

If you look at its entry point function (called
HttpBootDxeDriverEntryPoint()), you see that it installs *two* instances
of the driver binding protocol -- but only the first (the IPv4 one) goes
on the driver's genuine ImageHandle. The second instance (the IPv6 one)
goes on to a NULL handle.

The EfiLibInstallDriverBindingComponentName2() utility function seems to
support this. A new handle is created by the system, and the
"gHttpBootIp6DxeDriverBinding" protocol instance is installed on that
separate, new handle.

Now let us consider the HttpBootConfigFormInit() and
HttpBootConfigFormUnload() functions that were introduced by the commit
you found. The HttpBootConfigFormInit() function adds a permanent
reference to the parent handle's HTTP SB protocol, using the attribute
EFI_OPEN_PROTOCOL_BY_CHILD_CONTROLLER. The HttpBootConfigFormUnload()
function removes this reference.

The IPv4 and IPv6 variants of the driver binding start & stop functions
implement a kind of reference counting between each other. Namely,
regardless of which one of the IPv4 or IPv6 binding start functions is
called first, *that* first one will call HttpBootConfigFormInit(), and
the second one will not call it. The resources set up by the
HttpBootConfigFormInit() function (including the child reference to HTTP
SB) are shared between IPv4 and IPv6.

Similarly, when the stop functions are called, their ordering is
irrelevant; it is always the second one that is supposed to call
HttpBootConfigFormUnload().

Now,

Re: [edk2] [Patch 2/6] CryptoPkg: Add OpensslTlsLib module to enable 'openssl\ssl'

[James Bottomley]

On Fri, 2016-03-11 at 09:00 +, David Woodhouse wrote:
> On Wed, 2016-02-24 at 16:15 +0800, Jiaxin Wu wrote:
> > --- a/CryptoPkg/CryptoPkg.dsc
> > +++ b/CryptoPkg/CryptoPkg.dsc
> > @@ -48,10 +48,11 @@
> >   
> > UefiDriverEntryPoint|MdePkg/Library/UefiDriverEntryPoint/UefiDriver
> > EntryPoint.inf
> >   
> > UefiApplicationEntryPoint|MdePkg/Library/UefiApplicationEntryPoint/
> > UefiApplicationEntryPoint.inf
> >  
> >IntrinsicLib|CryptoPkg/Library/IntrinsicLib/IntrinsicLib.inf
> >OpensslLib|CryptoPkg/Library/OpensslLib/OpensslLib.inf
> > +  OpensslTlsLib|CryptoPkg/Library/OpensslLib/OpensslTlsLib.inf
> 
> One more thing... does this *need* to be a separate library?
> 
> It looks like the libraries are built into an archive and then linked
> statically. So only those objects which are *referenced* are actually
> pulled into the build. Which means that if we just *add* the ssl/
> directory to the OpensslLib build, it will only be pulled in if
> something *uses* it. Doesn't it?

I package it here:

https://build.opensuse.org/package/show/home:jejb1:UEFI/OVMF

in edk2-devel

I don't *need* to, but it's really useful having a single linkable sour
ce for an openssl EFI library rather than having to build it ourselves
(as shim currently does)

James


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Re: [edk2] [Patch 2/6] CryptoPkg: Add OpensslTlsLib module to enable 'openssl\ssl'

[David Woodhouse]

On Fri, 2016-03-11 at 07:54 -0800, James Bottomley wrote:
> 
> I package it here:
> 
> https://build.opensuse.org/package/show/home:jejb1:UEFI/OVMF
> 
> in edk2-devel

With the ssl/ directory enabled?

-- 
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[edk2] More OpenSSL fun...

[David Woodhouse]

At git//, https://git.infradead.org/users/dwmw2/edk2.git and in
following emails you can find the following:

As before, the ones which update to OpenSSL HEAD, and after that, are
for comment only.

David Woodhouse (7):
      CryptoPkg/OpensslLib: Convert saved opensslconf.h to DOS line endings
  CryptoPkg/OpensslLib: Fix handling of &strcmp function pointers
  CryptoPkg/OpensslLib: Fix GCC unused-value warnings with HOST_c2l() 
(RT#4347)
  CryptoPkg/OpensslLib: Enable warnings in GCC builds
  CryptoPkg: Support building with OpenSSL HEAD (1.1.0-devel)
  CryptoPkg: Abuse internal headers to make OpenSSL HEAD build work
  CryptoPkg/OpensslLib: Enable building of ssl/ subdirectory of OpenSSL

Jiaxin Wu (1):
  CryptoPkg: Fix time(NULL) crash

Qin Long (1):
  CryptoPkg/OpensslLib: Upgrade OpenSSL version to 1.0.2g


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Re: [edk2] [Patch 2/6] CryptoPkg: Add OpensslTlsLib module to enable 'openssl\ssl'

[James Bottomley]

On Fri, 2016-03-11 at 16:32 +, David Woodhouse wrote:
> On Fri, 2016-03-11 at 07:54 -0800, James Bottomley wrote:
> > 
> > I package it here:
> > 
> > https://build.opensuse.org/package/show/home:jejb1:UEFI/OVMF
> > 
> > in edk2-devel
> 
> With the ssl/ directory enabled?

Yes, if you crack the package, this is the contents:

/usr/include/edk2
/usr/include/edk2/Base.h
/usr/include/edk2/Guid
/usr/include/edk2/Guid/GlobalVariable.h
/usr/include/edk2/Guid/ImageAuthentication.h
/usr/include/edk2/Library
/usr/include/edk2/Library/BaseCryptLib.h
/usr/include/edk2/ProcessorBind.h
/usr/include/edk2/Protocol
/usr/include/edk2/Protocol/Hash.h
/usr/include/edk2/Protocol/Pkcs7Verify.h
/usr/include/edk2/Uefi
/usr/include/edk2/Uefi/UefiBaseType.h
/usr/lib64/edk2
/usr/lib64/edk2/OpensslLib.lib

It's the OpensslLib.lib that allows you to link all openssl functions
in EFI.  It's cheating quite a bit because the headers aren't present,
so you use the Linux headers from openssl-devel when you compile.

James


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[edk2] [PATCH 1/9] CryptoPkg/OpensslLib: Convert saved opensslconf.h to DOS line endings

[David Woodhouse]

Until we fix the git repository to store line endings properly and then
just check them out in the appropriate form for the platform, let's make
process_files.sh convert the opensslconf.h to DOS line endings when it
creates it.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: David Woodhouse 
Reviewed-by: Qin Long 
---
v2: Add missing '-n' arg.

 CryptoPkg/Library/OpensslLib/process_files.sh | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/CryptoPkg/Library/OpensslLib/process_files.sh 
b/CryptoPkg/Library/OpensslLib/process_files.sh
index bb33c8a..885adf3 100755
--- a/CryptoPkg/Library/OpensslLib/process_files.sh
+++ b/CryptoPkg/Library/OpensslLib/process_files.sh
@@ -93,5 +93,6 @@ function filelist ()
 filelist < "${OPENSSL_PATH}/MINFO" |  sed -n -f - -i OpensslLib.inf
 
 # We can tell Windows users to put this back manually if they can't run
-# Configure.
-cp "${OPENSSL_PATH}/crypto/opensslconf.h" .
+# Configure. For now, until the git repository is fixed to store things
+# sanely, also convert to DOS line-endings
+unix2dos -n "${OPENSSL_PATH}/crypto/opensslconf.h" opensslconf.h
-- 
2.5.0

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[edk2] [PATCH 2/9] CryptoPkg/OpensslLib: Upgrade OpenSSL version to 1.0.2g

[David Woodhouse]

From: Qin Long 

OpenSSL 1.0.2g was released with several severity fixes at
01-Mar-2016(https://www.openssl.org/news/secadv/20160301.txt).
Upgrade the supported OpenSSL version in CryptoPkg/OpensslLib to
catch the latest release 1.0.2g.
(NOTE: RT4175 from David Woodhouse was included in 1.0.2g. The
   new-generated patch will remove this part. And the line
   endings were still kept as before in this version for
   consistency)

CC: Ting Ye 
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Qin Long 
Reviewed-by: David Woodhouse 
---
 CryptoPkg/CryptoPkg.dec|  2 +-
 ...ssl-1.0.2f.patch => EDKII_openssl-1.0.2g.patch} | 95 --
 CryptoPkg/Library/OpensslLib/Install.cmd   |  2 +-
 CryptoPkg/Library/OpensslLib/Install.sh|  2 +-
 CryptoPkg/Library/OpensslLib/OpensslLib.inf|  2 +-
 CryptoPkg/Library/OpensslLib/Patch-HOWTO.txt   | 26 +++---
 CryptoPkg/Library/OpensslLib/opensslconf.h |  6 ++
 7 files changed, 56 insertions(+), 79 deletions(-)
 rename CryptoPkg/Library/OpensslLib/{EDKII_openssl-1.0.2f.patch => 
EDKII_openssl-1.0.2g.patch} (94%)

diff --git a/CryptoPkg/CryptoPkg.dec b/CryptoPkg/CryptoPkg.dec
index 82d24f5..e1cdb8e 100644
--- a/CryptoPkg/CryptoPkg.dec
+++ b/CryptoPkg/CryptoPkg.dec
@@ -24,7 +24,7 @@
 
 [Includes]
   Include
-  Library/OpensslLib/openssl-1.0.2f/include
+  Library/OpensslLib/openssl-1.0.2g/include
 
 [LibraryClasses]
   ##  @libraryclass  Provides basic library functions for cryptographic 
primitives.
diff --git a/CryptoPkg/Library/OpensslLib/EDKII_openssl-1.0.2f.patch 
b/CryptoPkg/Library/OpensslLib/EDKII_openssl-1.0.2g.patch
similarity index 94%
rename from CryptoPkg/Library/OpensslLib/EDKII_openssl-1.0.2f.patch
rename to CryptoPkg/Library/OpensslLib/EDKII_openssl-1.0.2g.patch
index b799bf2..25dbebc 100644
--- a/CryptoPkg/Library/OpensslLib/EDKII_openssl-1.0.2f.patch
+++ b/CryptoPkg/Library/OpensslLib/EDKII_openssl-1.0.2g.patch
@@ -1,8 +1,8 @@
 diff --git a/Configure b/Configure
-index 4a715dc..b4a4781 100755
+index c98107a..c122709 100755
 --- a/Configure
 +++ b/Configure
-@@ -605,6 +605,9 @@ my %table=(
+@@ -609,6 +609,9 @@ my %table=(
  # with itself, Applink is never engaged and can as well be omitted.
  "mingw64", "gcc:-mno-cygwin -DL_ENDIAN -O3 -Wall -DWIN32_LEAN_AND_MEAN 
-DUNICODE -D_UNICODE::-D_MT:MINGW64:-lws2_32 -lgdi32 -lcrypt32:SIXTY_FOUR_BIT 
RC4_CHUNK_LL DES_INT 
EXPORT_VAR_AS_FN:${x86_64_asm}:mingw64:win32:cygwin-shared:-D_WINDLL:-mno-cygwin:.dll.a",
  
@@ -12,7 +12,7 @@ index 4a715dc..b4a4781 100755
  # UWIN 
  "UWIN", "cc:-DTERMIOS -DL_ENDIAN -O -Wall:::UWIN::BN_LLONG ${x86_gcc_des} 
${x86_gcc_opts}:${no_asm}:win32",
  
-@@ -1082,7 +1085,7 @@ if (defined($disabled{"tls1"}))
+@@ -1088,7 +1091,7 @@ if (defined($disabled{"tls1"}))
    }
  
  if (defined($disabled{"ec"}) || defined($disabled{"dsa"})
@@ -22,7 +22,7 @@ index 4a715dc..b4a4781 100755
    $disabled{"gost"} = "forced";
    }
 diff --git a/apps/apps.c b/apps/apps.c
-index 2e77805..e21e759 100644
+index b1dd970..8278c28 100644
 --- a/apps/apps.c
 +++ b/apps/apps.c
 @@ -2374,6 +2374,8 @@ int args_verify(char ***pargs, int *pargc,
@@ -462,7 +462,7 @@ index c042cf2..a25b636 100644
  }
  
 diff --git a/crypto/cryptlib.c b/crypto/cryptlib.c
-index c9f674b..39ead7f 100644
+index 1925428..da4b34d 100644
 --- a/crypto/cryptlib.c
 +++ b/crypto/cryptlib.c
 @@ -263,7 +263,7 @@ int CRYPTO_get_new_dynlockid(void)
@@ -525,7 +525,7 @@ index c9f674b..39ead7f 100644
  }
 +#endif
  
- int CRYPTO_memcmp(const void *in_a, const void *in_b, size_t len)
+ int CRYPTO_memcmp(const volatile void *in_a, const volatile void *in_b, 
size_t len)
  {
 diff --git a/crypto/cryptlib.h b/crypto/cryptlib.h
 index fba180a..3e3ea5e 100644
@@ -542,7 +542,7 @@ index fba180a..3e3ea5e 100644
  
  #ifdef  __cplusplus
 diff --git a/crypto/crypto.h b/crypto/crypto.h
-index c450d7a..063d78e 100644
+index 6c644ce..bea4ca1 100644
 --- a/crypto/crypto.h
 +++ b/crypto/crypto.h
 @@ -235,15 +235,15 @@ typedef struct openssl_item_st {
@@ -656,7 +656,7 @@ index 46fa5ac..cc366ec 100644
  dh_kdf.o: ../../include/openssl/crypto.h ../../include/openssl/dh.h
  dh_kdf.o: ../../include/openssl/e_os2.h ../../include/openssl/ec.h
 diff --git a/crypto/dh/dh.h b/crypto/dh/dh.h
-index 5498a9d..4a5c665 100644
+index a5bd901..6488879 100644
 --- a/crypto/dh/dh.h
 +++ b/crypto/dh/dh.h
 @@ -240,11 +240,13 @@ DH *DH_get_1024_160(void);
@@ -1021,7 +1021,7 @@ index 5747c73..fe465cc 100644
   * These functions write a private key in PKCS#8 format: it is a "drop in"
   * replacement for PEM_write_bio_PrivateKey() and friends. As usual if 'enc'
 diff --git a/crypto/pkcs7/pk7_smime.c b/crypto/pkcs7/pk7_smime.c
-index c4d3724..0bc3d43 100644
+index dc9b484..0bc3d43 100644
 --- a/crypto/pkcs7/pk7_smime.c
 +++ b/crypto/pkcs7/pk7_smime.c
 @@ -64,6 +64,9 @@
@@ -1043,37 +1043,7 @@ index c4d3724..0bc3d43 100644
  int i, j = 0, k, ret = 0;
  BIO *p7bio = NU

[edk2] [PATCH 3/9] CryptoPkg/OpensslLib: Fix handling of &strcmp function pointers

[David Woodhouse]

In a couple of places, OpenSSL code uses the address of the strcmp()
function, and assigns it to another comparator function pointer.

Unfortunately, this falls foul of the inconsistent function ABI that we
use in EDKII. We '#define strcmp AsciiStrCmp' but AsciiStrCmp is an
EFIAPI function with the Microsoft ABI. And we're assigning its address
to a non-EFIAPI function, which may well have a different ABI.

The compiler *should* have complained about this error, thus:

…/crypto/objects/o_names.c: In function ‘OBJ_NAME_new_index’:
…/crypto/objects/o_names.c:94:30: error: assignment from incompatible pointer 
type [-Werror=incompatible-pointer-types]
 name_funcs->cmp_func = OPENSSL_strcmp;
  ^

Unfortunately, all warnings are disabled when building OpenSSL code.

There's another one in crypto/lhash/lhash.c::lh_new() which has an
explicit cast so even with compiler warnings we wouldn't have seen it.

Fix this by providing an actual strcmp() function in the default ABI.
We already *had* a prototype for it in OpenSslSupport.h, which was then
superseded by the #define strcmp AsciiStrCmp.

Now, OpenSSL code *can* use &strcmp without problems.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: David Woodhouse 
---
 CryptoPkg/Include/OpenSslSupport.h| 1 -
 CryptoPkg/Library/IntrinsicLib/MemoryIntrinsics.c | 6 ++
 2 files changed, 6 insertions(+), 1 deletion(-)

diff --git a/CryptoPkg/Include/OpenSslSupport.h 
b/CryptoPkg/Include/OpenSslSupport.h
index 239ae8b..8bb4277 100644
--- a/CryptoPkg/Include/OpenSslSupport.h
+++ b/CryptoPkg/Include/OpenSslSupport.h
@@ -261,7 +261,6 @@ extern FILE  *stdout;
 #define memchr(buf,ch,count)  
ScanMem8(buf,(UINTN)(count),(UINT8)ch)
 #define memcmp(buf1,buf2,count)   
(int)(CompareMem(buf1,buf2,(UINTN)(count)))
 #define memmove(dest,source,count)CopyMem(dest,source,(UINTN)(count))
-#define strcmpAsciiStrCmp
 #define strncmp(string1,string2,count)
(int)(AsciiStrnCmp(string1,string2,(UINTN)(count)))
 #define strcpy(strDest,strSource) 
AsciiStrCpyS(strDest,MAX_STRING_SIZE,strSource)
 #define strncpy(strDest,strSource,count)  
AsciiStrnCpyS(strDest,MAX_STRING_SIZE,strSource,(UINTN)count)
diff --git a/CryptoPkg/Library/IntrinsicLib/MemoryIntrinsics.c 
b/CryptoPkg/Library/IntrinsicLib/MemoryIntrinsics.c
index 9d6867e..f559da0 100644
--- a/CryptoPkg/Library/IntrinsicLib/MemoryIntrinsics.c
+++ b/CryptoPkg/Library/IntrinsicLib/MemoryIntrinsics.c
@@ -15,6 +15,7 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER 
EXPRESS OR IMPLIED.
 
 #include 
 #include 
+#include 
 
 /* OpenSSL will use floating point support, and C compiler produces the 
_fltused
symbol by default. Simply define this symbol here to satisfy the linker. */
@@ -44,3 +45,8 @@ void * memset (void *dest, char ch, unsigned int count)
   
   return dest;
 }
+
+int strcmp (const char *s1, const char *s2)
+{
+  return AsciiStrCmp(s1, s2);
+}
-- 
2.5.0

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[edk2] [PATCH 4/9] CryptoPkg/OpensslLib: Fix GCC unused-value warnings with HOST_c2l() (RT#4347)

[David Woodhouse]

If we actually allow GCC to produce warnings, we'll see a lot of these:
…/crypto/md5/md5_dgst.c:109:56: error: right-hand operand of comma expression 
has no effect [-Werror=unused-value]

These were fixed in OpenSSL 1.1; backport the fix to our 1.0.2 tree too.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: David Woodhouse 
---
 .../Library/OpensslLib/EDKII_openssl-1.0.2g.patch  | 168 +
 1 file changed, 168 insertions(+)

diff --git a/CryptoPkg/Library/OpensslLib/EDKII_openssl-1.0.2g.patch 
b/CryptoPkg/Library/OpensslLib/EDKII_openssl-1.0.2g.patch
index 25dbebc..58565b6 100644
--- a/CryptoPkg/Library/OpensslLib/EDKII_openssl-1.0.2g.patch
+++ b/CryptoPkg/Library/OpensslLib/EDKII_openssl-1.0.2g.patch
@@ -915,6 +915,79 @@ index 5be9e33..63c8866 100644
  
  int EVP_BytesToKey(const EVP_CIPHER *type, const EVP_MD *md,
 const unsigned char *salt, const unsigned char *data,
+diff --git a/crypto/md5/md5_dgst.c b/crypto/md5/md5_dgst.c
+index 2b51946..4ec1719 100644
+--- a/crypto/md5/md5_dgst.c
 b/crypto/md5/md5_dgst.c
+@@ -106,52 +106,52 @@ void md5_block_data_order(MD5_CTX *c, const void *data_, 
size_t num)
+ D = c->D;
+ 
+ for (; num--;) {
+-HOST_c2l(data, l);
++(void)HOST_c2l(data, l);
+ X(0) = l;
+-HOST_c2l(data, l);
++(void)HOST_c2l(data, l);
+ X(1) = l;
+ /* Round 0 */
+ R0(A, B, C, D, X(0), 7, 0xd76aa478L);
+-HOST_c2l(data, l);
++(void)HOST_c2l(data, l);
+ X(2) = l;
+ R0(D, A, B, C, X(1), 12, 0xe8c7b756L);
+-HOST_c2l(data, l);
++(void)HOST_c2l(data, l);
+ X(3) = l;
+ R0(C, D, A, B, X(2), 17, 0x242070dbL);
+-HOST_c2l(data, l);
++(void)HOST_c2l(data, l);
+ X(4) = l;
+ R0(B, C, D, A, X(3), 22, 0xc1bdceeeL);
+-HOST_c2l(data, l);
++(void)HOST_c2l(data, l);
+ X(5) = l;
+ R0(A, B, C, D, X(4), 7, 0xf57c0fafL);
+-HOST_c2l(data, l);
++(void)HOST_c2l(data, l);
+ X(6) = l;
+ R0(D, A, B, C, X(5), 12, 0x4787c62aL);
+-HOST_c2l(data, l);
++(void)HOST_c2l(data, l);
+ X(7) = l;
+ R0(C, D, A, B, X(6), 17, 0xa8304613L);
+-HOST_c2l(data, l);
++(void)HOST_c2l(data, l);
+ X(8) = l;
+ R0(B, C, D, A, X(7), 22, 0xfd469501L);
+-HOST_c2l(data, l);
++(void)HOST_c2l(data, l);
+ X(9) = l;
+ R0(A, B, C, D, X(8), 7, 0x698098d8L);
+-HOST_c2l(data, l);
++(void)HOST_c2l(data, l);
+ X(10) = l;
+ R0(D, A, B, C, X(9), 12, 0x8b44f7afL);
+-HOST_c2l(data, l);
++(void)HOST_c2l(data, l);
+ X(11) = l;
+ R0(C, D, A, B, X(10), 17, 0x5bb1L);
+-HOST_c2l(data, l);
++(void)HOST_c2l(data, l);
+ X(12) = l;
+ R0(B, C, D, A, X(11), 22, 0x895cd7beL);
+-HOST_c2l(data, l);
++(void)HOST_c2l(data, l);
+ X(13) = l;
+ R0(A, B, C, D, X(12), 7, 0x6b901122L);
+-HOST_c2l(data, l);
++(void)HOST_c2l(data, l);
+ X(14) = l;
+ R0(D, A, B, C, X(13), 12, 0xfd987193L);
+-HOST_c2l(data, l);
++(void)HOST_c2l(data, l);
+ X(15) = l;
+ R0(C, D, A, B, X(14), 17, 0xa679438eL);
+ R0(B, C, D, A, X(15), 22, 0x49b40821L);
 diff --git a/crypto/opensslconf.h.in b/crypto/opensslconf.h.in
 index 7a1c85d..7162c0f 100644
 --- a/crypto/opensslconf.h.in
@@ -1221,6 +1294,101 @@ index 4e06218..ddead3d 100644
  
  const EVP_PKEY_ASN1_METHOD rsa_asn1_meths[] = {
  {
+diff --git a/crypto/sha/sha256.c b/crypto/sha/sha256.c
+index 72a1159..64702cd 100644
+--- a/crypto/sha/sha256.c
 b/crypto/sha/sha256.c
+@@ -184,7 +184,7 @@ static void sha256_block_data_order(SHA256_CTX *ctx, const 
void *in,
+ h = ctx->h[7];
+ 
+ for (i = 0; i < 16; i++) {
+-HOST_c2l(data, l);
++(void)HOST_c2l(data, l);
+ T1 = X[i] = l;
+ T1 += h + Sigma1(e) + Ch(e, f, g) + K256[i];
+ T2 = Sigma0(a) + Maj(a, b, c);
+@@ -308,52 +308,52 @@ static void sha256_block_data_order(SHA256_CTX *ctx, 
const void *in,
+ } else {
+ SHA_LONG l;
+ 
+-HOST_c2l(data, l);
++(void)HOST_c2l(data, l);
+ T1 = X[0] = l;
+ ROUND_00_15(0, a, b, c, d, e, f, g, h);
+-HOST_c2l(data, l);
++(void)HOST_c2l(data, l);
+ T1 = X[1] = l;
+ ROUND_00_15(1, h, a, b, c, d, e, f, g);
+-HOST_c2l(data, l);
++(void)HOST_c2l(data, l);
+ T1 = X[2] = l;
+ ROUND_00_15(2, g, h, a, b, c, d, e, f);
+-HOST_c2l(data, l);
++(void)HOST_c2l(data, l);
+ T1 = X[3] = l;
+ ROUND_00_15(3, f, g, h, a, b, c, d, e);
+-HOST_c2l(data, l);
++(void)HOST_c2l(data, l);
+ T1 = X[4] = l;
+

[edk2] [PATCH 5/9] CryptoPkg/OpensslLib: Enable warnings in GCC builds

[David Woodhouse]

[This space intentionally left blank, in case I accidentally venture
 an opinion about the fact that we *ever* added '-w' to the build
 flags of a security-sensitive piece of code.]

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: David Woodhouse 
---
 CryptoPkg/Library/OpensslLib/OpensslLib.inf | 10 +-
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/CryptoPkg/Library/OpensslLib/OpensslLib.inf 
b/CryptoPkg/Library/OpensslLib/OpensslLib.inf
index 8757100..9e5897f 100644
--- a/CryptoPkg/Library/OpensslLib/OpensslLib.inf
+++ b/CryptoPkg/Library/OpensslLib/OpensslLib.inf
@@ -508,11 +508,11 @@
   INTEL:*_*_X64_CC_FLAGS= -U_WIN32 -U_WIN64 -U_MSC_VER -U__ICC 
$(OPENSSL_FLAGS) /w
   INTEL:*_*_IPF_CC_FLAGS= -U_WIN32 -U_WIN64 -U_MSC_VER -U__ICC 
$(OPENSSL_FLAGS) /w
 
-  GCC:*_*_IA32_CC_FLAGS = -U_WIN32 -U_WIN64 $(OPENSSL_FLAGS) -w
-  GCC:*_*_X64_CC_FLAGS  = -U_WIN32 -U_WIN64 $(OPENSSL_FLAGS) -w 
-UNO_BUILTIN_VA_FUNCS
-  GCC:*_*_IPF_CC_FLAGS  = -U_WIN32 -U_WIN64 $(OPENSSL_FLAGS) -w
-  GCC:*_*_ARM_CC_FLAGS  = $(OPENSSL_FLAGS) -w
-  GCC:*_*_AARCH64_CC_FLAGS  = $(OPENSSL_FLAGS) -w
+  GCC:*_*_IA32_CC_FLAGS = -U_WIN32 -U_WIN64 $(OPENSSL_FLAGS)
+  GCC:*_*_X64_CC_FLAGS  = -U_WIN32 -U_WIN64 $(OPENSSL_FLAGS) 
-UNO_BUILTIN_VA_FUNCS
+  GCC:*_*_IPF_CC_FLAGS  = -U_WIN32 -U_WIN64 $(OPENSSL_FLAGS)
+  GCC:*_*_ARM_CC_FLAGS  = $(OPENSSL_FLAGS)
+  GCC:*_*_AARCH64_CC_FLAGS  = $(OPENSSL_FLAGS)
 
   # suppress the following warnings in openssl so we don't break the build 
with warnings-as-errors:
   # 1295: Deprecated declaration  - give arg types
-- 
2.5.0

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[edk2] [PATCH 6/9] CryptoPkg: Fix time(NULL) crash

[David Woodhouse]

From: Jiaxin Wu 

The POSIX time() function can be called with a NULL pointer, but our
implementation in BaseCryptLib didn't cope with that. Fix it, since
we want to start building the ssl/ directory of OpenSSL too, and it
does precisely this.

Cc: Long Qin 
Cc: Ye Ting 
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jiaxin Wu 
Reviewed-by: David Woodhouse 
---
I took the liberty of changing the commit comment a little.

 .../Library/BaseCryptLib/SysCall/TimerWrapper.c| 29 +-
 1 file changed, 17 insertions(+), 12 deletions(-)

diff --git a/CryptoPkg/Library/BaseCryptLib/SysCall/TimerWrapper.c 
b/CryptoPkg/Library/BaseCryptLib/SysCall/TimerWrapper.c
index 6422d61..93e487d 100644
--- a/CryptoPkg/Library/BaseCryptLib/SysCall/TimerWrapper.c
+++ b/CryptoPkg/Library/BaseCryptLib/SysCall/TimerWrapper.c
@@ -2,7 +2,7 @@
   C Run-Time Libraries (CRT) Time Management Routines Wrapper Implementation
   for OpenSSL-based Cryptographic Library (used in DXE & RUNTIME).
 
-Copyright (c) 2010 - 2011, Intel Corporation. All rights reserved.
+Copyright (c) 2010 - 2016, Intel Corporation. All rights reserved.
 This program and the accompanying materials
 are licensed and made available under the terms and conditions of the BSD 
License
 which accompanies this distribution.  The full text of the license may be 
found at
@@ -73,6 +73,7 @@ UINTN CumulativeDays[2][14] = {
 time_t time (time_t *timer)
 {
   EFI_TIME  Time;
+  time_tCalTime;
   UINTN Year;
 
   //
@@ -84,22 +85,26 @@ time_t time (time_t *timer)
   // Years Handling
   // UTime should now be set to 00:00:00 on Jan 1 of the current year.
   //
-  for (Year = 1970, *timer = 0; Year != Time.Year; Year++) {
-*timer = *timer + (time_t)(CumulativeDays[IsLeap(Year)][13] * SECSPERDAY);
+  for (Year = 1970, CalTime = 0; Year != Time.Year; Year++) {
+CalTime = CalTime + (time_t)(CumulativeDays[IsLeap(Year)][13] * 
SECSPERDAY);
   }
 
   //
   // Add in number of seconds for current Month, Day, Hour, Minute, Seconds, 
and TimeZone adjustment
   //
-  *timer = *timer + 
-   (time_t)((Time.TimeZone != EFI_UNSPECIFIED_TIMEZONE) ? 
(Time.TimeZone * 60) : 0) +
-   (time_t)(CumulativeDays[IsLeap(Time.Year)][Time.Month] * 
SECSPERDAY) + 
-   (time_t)(((Time.Day > 0) ? Time.Day - 1 : 0) * SECSPERDAY) + 
-   (time_t)(Time.Hour * SECSPERHOUR) + 
-   (time_t)(Time.Minute * 60) + 
-   (time_t)Time.Second;
-
-  return *timer;
+  CalTime = CalTime + 
+(time_t)((Time.TimeZone != EFI_UNSPECIFIED_TIMEZONE) ? 
(Time.TimeZone * 60) : 0) +
+(time_t)(CumulativeDays[IsLeap(Time.Year)][Time.Month] * 
SECSPERDAY) + 
+(time_t)(((Time.Day > 0) ? Time.Day - 1 : 0) * SECSPERDAY) + 
+(time_t)(Time.Hour * SECSPERHOUR) + 
+(time_t)(Time.Minute * 60) + 
+(time_t)Time.Second;
+
+  if (timer != NULL) {
+*timer = CalTime;
+  }
+
+  return CalTime;
 }
 
 //
-- 
2.5.0

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[edk2] [PATCH 8/9] CryptoPkg: Abuse internal headers to make OpenSSL HEAD build work

[David Woodhouse]

More stuff got hidden. Some of this is tolerable. Other bits are
horrid, but given that we expose *requires* that we know the size
of the data structure, it's hard to see how we can avoid it.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: David Woodhouse 
---
Really need to sort this one out properly...

 CryptoPkg/Library/BaseCryptLib/Hmac/CryptHmacMd5.c  | 7 ---
 CryptoPkg/Library/BaseCryptLib/Hmac/CryptHmacSha1.c | 6 --
 CryptoPkg/Library/BaseCryptLib/Pk/CryptPkcs7Sign.c  | 1 +
 CryptoPkg/Library/BaseCryptLib/Pk/CryptTs.c | 2 ++
 CryptoPkg/Library/BaseCryptLib/Pk/CryptX509.c   | 1 +
 5 files changed, 12 insertions(+), 5 deletions(-)

diff --git a/CryptoPkg/Library/BaseCryptLib/Hmac/CryptHmacMd5.c 
b/CryptoPkg/Library/BaseCryptLib/Hmac/CryptHmacMd5.c
index 693cd32..93c2bcb 100644
--- a/CryptoPkg/Library/BaseCryptLib/Hmac/CryptHmacMd5.c
+++ b/CryptoPkg/Library/BaseCryptLib/Hmac/CryptHmacMd5.c
@@ -14,7 +14,7 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER 
EXPRESS OR IMPLIED.
 
 #include "InternalCryptLib.h"
 #include 
-
+#include <../hmac/hmac_lcl.h>
 /**
   Retrieves the size, in bytes, of the context buffer required for HMAC-MD5 
operations.
 
@@ -65,7 +65,8 @@ HmacMd5Init (
   //
   // OpenSSL HMAC-MD5 Context Initialization
   //
-  HMAC_CTX_init (HmacMd5Context);
+  memset(HmacMd5Context, 0, sizeof(HMAC_CTX));
+  HMAC_CTX_reset (HmacMd5Context);
   HMAC_Init_ex (HmacMd5Context, Key, (UINT32) KeySize, EVP_md5(), NULL);
 
   return TRUE;
@@ -191,7 +192,7 @@ HmacMd5Final (
   // OpenSSL HMAC-MD5 digest finalization
   //
   HMAC_Final (HmacMd5Context, HmacValue, &Length);
-  HMAC_CTX_cleanup (HmacMd5Context);
+  HMAC_CTX_reset (HmacMd5Context);
 
   return TRUE;
 }
diff --git a/CryptoPkg/Library/BaseCryptLib/Hmac/CryptHmacSha1.c 
b/CryptoPkg/Library/BaseCryptLib/Hmac/CryptHmacSha1.c
index 881d26c..5710f26 100644
--- a/CryptoPkg/Library/BaseCryptLib/Hmac/CryptHmacSha1.c
+++ b/CryptoPkg/Library/BaseCryptLib/Hmac/CryptHmacSha1.c
@@ -14,6 +14,7 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER 
EXPRESS OR IMPLIED.
 
 #include "InternalCryptLib.h"
 #include 
+#include <../hmac/hmac_lcl.h>
 
 /**
   Retrieves the size, in bytes, of the context buffer required for HMAC-SHA1 
operations.
@@ -65,7 +66,8 @@ HmacSha1Init (
   //
   // OpenSSL HMAC-SHA1 Context Initialization
   //
-  HMAC_CTX_init (HmacSha1Context);
+  memset(HmacSha1Context, 0, sizeof(HMAC_CTX));
+  HMAC_CTX_reset (HmacSha1Context);
   HMAC_Init_ex (HmacSha1Context, Key, (UINT32) KeySize, EVP_sha1(), NULL);
 
   return TRUE;
@@ -191,7 +193,7 @@ HmacSha1Final (
   // OpenSSL HMAC-SHA1 digest finalization
   //
   HMAC_Final (HmacSha1Context, HmacValue, &Length);
-  HMAC_CTX_cleanup (HmacSha1Context);
+  HMAC_CTX_reset (HmacSha1Context);
 
   return TRUE;
 }
diff --git a/CryptoPkg/Library/BaseCryptLib/Pk/CryptPkcs7Sign.c 
b/CryptoPkg/Library/BaseCryptLib/Pk/CryptPkcs7Sign.c
index 704eb4e..8e0d896 100644
--- a/CryptoPkg/Library/BaseCryptLib/Pk/CryptPkcs7Sign.c
+++ b/CryptoPkg/Library/BaseCryptLib/Pk/CryptPkcs7Sign.c
@@ -17,6 +17,7 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER 
EXPRESS OR IMPLIED.
 #include 
 #include 
 #include 
+#include 
 
 
 /**
diff --git a/CryptoPkg/Library/BaseCryptLib/Pk/CryptTs.c 
b/CryptoPkg/Library/BaseCryptLib/Pk/CryptTs.c
index d495812..c6799ae 100644
--- a/CryptoPkg/Library/BaseCryptLib/Pk/CryptTs.c
+++ b/CryptoPkg/Library/BaseCryptLib/Pk/CryptTs.c
@@ -23,6 +23,7 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER 
EXPRESS OR IMPLIED.
 #include 
 #include 
 #include 
+#include <../evp/evp_locl.h>
 
 //
 // OID ASN.1 Value for SPC_RFC3161_OBJID ("1.3.6.1.4.1.311.3.3.1")
@@ -285,6 +286,7 @@ CheckTSTInfo (
   if (HashedMsg == NULL) {
 goto _Exit;
   }
+  memset(&MdCtx, 0, sizeof(MdCtx));
   EVP_DigestInit (&MdCtx, Md);
   EVP_DigestUpdate (&MdCtx, TimestampedData, DataSize);
   EVP_DigestFinal (&MdCtx, HashedMsg, NULL);
diff --git a/CryptoPkg/Library/BaseCryptLib/Pk/CryptX509.c 
b/CryptoPkg/Library/BaseCryptLib/Pk/CryptX509.c
index 7dc4596..d392bed 100644
--- a/CryptoPkg/Library/BaseCryptLib/Pk/CryptX509.c
+++ b/CryptoPkg/Library/BaseCryptLib/Pk/CryptX509.c
@@ -15,6 +15,7 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER 
EXPRESS OR IMPLIED.
 #include "InternalCryptLib.h"
 #include 
 #include 
+#include 
 
 /**
   Construct a X509 object from DER-encoded certificate data.
-- 
2.5.0

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[edk2] [PATCH 9/9] CryptoPkg/OpensslLib: Enable building of ssl/ subdirectory of OpenSSL

[David Woodhouse]

Since it's just a library archive, let's just build the ssl/ parts
unconditionally. If they're referenced, they'll get pulled in. If not
then they won't.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: David Woodhouse 
---
An alternative approach, which might be simpler. qv.

 CryptoPkg/Library/OpensslLib/OpensslLib.inf   | 39 +++
 CryptoPkg/Library/OpensslLib/process_files.sh | 12 -
 2 files changed, 44 insertions(+), 7 deletions(-)

diff --git a/CryptoPkg/Library/OpensslLib/OpensslLib.inf 
b/CryptoPkg/Library/OpensslLib/OpensslLib.inf
index d48c8f1..50f256d 100644
--- a/CryptoPkg/Library/OpensslLib/OpensslLib.inf
+++ b/CryptoPkg/Library/OpensslLib/OpensslLib.inf
@@ -477,6 +477,45 @@
   $(OPENSSL_PATH)/crypto/kdf/tls1_prf.c
   $(OPENSSL_PATH)/crypto/kdf/kdf_err.c
   $(OPENSSL_PATH)/crypto/kdf/hkdf.c
+  $(OPENSSL_PATH)/ssl/pqueue.c
+  $(OPENSSL_PATH)/ssl/statem/statem_srvr.c
+  $(OPENSSL_PATH)/ssl/statem/statem_clnt.c
+  $(OPENSSL_PATH)/ssl/s3_lib.c
+  $(OPENSSL_PATH)/ssl/s3_enc.c
+  $(OPENSSL_PATH)/ssl/record/rec_layer_s3.c
+  $(OPENSSL_PATH)/ssl/statem/statem_lib.c
+  $(OPENSSL_PATH)/ssl/s3_cbc.c
+  $(OPENSSL_PATH)/ssl/s3_msg.c
+  $(OPENSSL_PATH)/ssl/methods.c
+  $(OPENSSL_PATH)/ssl/t1_lib.c
+  $(OPENSSL_PATH)/ssl/t1_enc.c
+  $(OPENSSL_PATH)/ssl/t1_ext.c
+  $(OPENSSL_PATH)/ssl/d1_lib.c
+  $(OPENSSL_PATH)/ssl/record/rec_layer_d1.c
+  $(OPENSSL_PATH)/ssl/d1_msg.c
+  $(OPENSSL_PATH)/ssl/statem/statem_dtls.c
+  $(OPENSSL_PATH)/ssl/d1_srtp.c
+  $(OPENSSL_PATH)/ssl/ssl_lib.c
+  $(OPENSSL_PATH)/ssl/ssl_cert.c
+  $(OPENSSL_PATH)/ssl/ssl_sess.c
+  $(OPENSSL_PATH)/ssl/ssl_ciph.c
+  $(OPENSSL_PATH)/ssl/ssl_stat.c
+  $(OPENSSL_PATH)/ssl/ssl_rsa.c
+  $(OPENSSL_PATH)/ssl/ssl_asn1.c
+  $(OPENSSL_PATH)/ssl/ssl_txt.c
+  $(OPENSSL_PATH)/ssl/ssl_init.c
+  $(OPENSSL_PATH)/ssl/ssl_conf.c
+  $(OPENSSL_PATH)/ssl/ssl_mcnf.c
+  $(OPENSSL_PATH)/ssl/bio_ssl.c
+  $(OPENSSL_PATH)/ssl/ssl_err.c
+  $(OPENSSL_PATH)/ssl/t1_reneg.c
+  $(OPENSSL_PATH)/ssl/tls_srp.c
+  $(OPENSSL_PATH)/ssl/t1_trce.c
+  $(OPENSSL_PATH)/ssl/ssl_utst.c
+  $(OPENSSL_PATH)/ssl/record/ssl3_buffer.c
+  $(OPENSSL_PATH)/ssl/record/ssl3_record.c
+  $(OPENSSL_PATH)/ssl/record/dtls1_bitmap.c
+  $(OPENSSL_PATH)/ssl/statem/statem.c
 
 # Autogenerated files list ends here
 
diff --git a/CryptoPkg/Library/OpensslLib/process_files.sh 
b/CryptoPkg/Library/OpensslLib/process_files.sh
index 8ab0deb..90fa6a1 100755
--- a/CryptoPkg/Library/OpensslLib/process_files.sh
+++ b/CryptoPkg/Library/OpensslLib/process_files.sh
@@ -70,13 +70,11 @@ function filelist ()
    ;;
    LIBSRC=*)
    LIBSRC=$(echo "$LINE" | sed s/^LIBSRC=//)
-   if [ "$RELATIVE_DIRECTORY" != "ssl" ]; then
-   for FILE in $LIBSRC; do
-   if [ "$FILE" != "b_print.c" ]; then
-   echo -e '  
$(OPENSSL_PATH)/'$RELATIVE_DIRECTORY/$FILE\\r\\
-   fi
-   done
-   fi
+   for FILE in $LIBSRC; do
+   if [ "$FILE" != "b_print.c" ]; then
+   echo -e '  
$(OPENSSL_PATH)/'$RELATIVE_DIRECTORY/$FILE\\r\\
+   fi
+   done
    ;;
    esac
 done
-- 
2.5.0

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Re: [edk2] [PATCH 4/9] CryptoPkg/OpensslLib: Fix GCC unused-value warnings with HOST_c2l() (RT#4347)

[David Woodhouse]

On Fri, 2016-03-11 at 17:30 +, David Woodhouse wrote:
> If we actually allow GCC to produce warnings, we'll see a lot of these:
> …/crypto/md5/md5_dgst.c:109:56: error: right-hand operand of comma expression 
> has no effect [-Werror=unused-value]
> 
> These were fixed in OpenSSL 1.1; backport the fix to our 1.0.2 tree too.

I also pushed this to my OpenSSL-1.0.2g-EDK2 branch from which the
EDKII_openssl patches are now autogenerated:

https://github.com/dwmw2/openssl/commits/OpenSSL-1.0.2g-EDK2

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Re: [edk2] [Patch 2/6] CryptoPkg: Add OpensslTlsLib module to enable 'openssl\ssl'

[David Woodhouse]

On Fri, 2016-03-11 at 09:25 -0800, James Bottomley wrote:
> 
> > With the ssl/ directory enabled?
> 
> Yes, if you crack the package, this is the contents:
> 
> /usr/include/edk2
> /usr/include/edk2/Base.h
> /usr/include/edk2/Guid
> /usr/include/edk2/Guid/GlobalVariable.h
> /usr/include/edk2/Guid/ImageAuthentication.h
> /usr/include/edk2/Library
> /usr/include/edk2/Library/BaseCryptLib.h
> /usr/include/edk2/ProcessorBind.h
> /usr/include/edk2/Protocol
> /usr/include/edk2/Protocol/Hash.h
> /usr/include/edk2/Protocol/Pkcs7Verify.h
> /usr/include/edk2/Uefi
> /usr/include/edk2/Uefi/UefiBaseType.h
> /usr/lib64/edk2
> /usr/lib64/edk2/OpensslLib.lib
> 
> It's the OpensslLib.lib that allows you to link all openssl functions
> in EFI.  It's cheating quite a bit because the headers aren't present,
> so you use the Linux headers from openssl-devel when you compile.

That's dangerous and likely to break; various structures change.

But still, the OpensslLib in EDK2 only builds libcrypto; the contents
of the crypto/ directory of OpenSSL.

The discussion here is about building libssl, from ssl/.

Jiaxin proposed building it as a separate library. I asked why not just
build it into the *same* OpensslLib.

Did you *really* enable the building of openssl-1.0.2x/ssl/*.c in the
above builds? Or are you talking about something different?

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Re: [edk2] [Patch 2/6] CryptoPkg: Add OpensslTlsLib module to enable 'openssl\ssl'

[James Bottomley]

On Fri, 2016-03-11 at 17:38 +, David Woodhouse wrote:
> On Fri, 2016-03-11 at 09:25 -0800, James Bottomley wrote:
> > 
> > > With the ssl/ directory enabled?
> > 
> > Yes, if you crack the package, this is the contents:
> > 
> > /usr/include/edk2
> > /usr/include/edk2/Base.h
> > /usr/include/edk2/Guid
> > /usr/include/edk2/Guid/GlobalVariable.h
> > /usr/include/edk2/Guid/ImageAuthentication.h
> > /usr/include/edk2/Library
> > /usr/include/edk2/Library/BaseCryptLib.h
> > /usr/include/edk2/ProcessorBind.h
> > /usr/include/edk2/Protocol
> > /usr/include/edk2/Protocol/Hash.h
> > /usr/include/edk2/Protocol/Pkcs7Verify.h
> > /usr/include/edk2/Uefi
> > /usr/include/edk2/Uefi/UefiBaseType.h
> > /usr/lib64/edk2
> > /usr/lib64/edk2/OpensslLib.lib
> > 
> > It's the OpensslLib.lib that allows you to link all openssl
> > functions
> > in EFI.  It's cheating quite a bit because the headers aren't
> > present,
> > so you use the Linux headers from openssl-devel when you compile.
> 
> That's dangerous and likely to break; various structures change.
> 
> But still, the OpensslLib in EDK2 only builds libcrypto; the contents
> of the crypto/ directory of OpenSSL.
> 
> The discussion here is about building libssl, from ssl/.
> 
> Jiaxin proposed building it as a separate library. I asked why not 
> just build it into the *same* OpensslLib.

Oh, right, sorry misunderstood.  It does look like my build is
currently without this component, since we mostly only care about the
pkcs7 and x509 functions.

> Did you *really* enable the building of openssl-1.0.2x/ssl/*.c in the
> above builds? Or are you talking about something different?

No, and since I'm not using it, separating it is fine with me.

James


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Re: [edk2] [Patch 2/6] CryptoPkg: Add OpensslTlsLib module to enable 'openssl\ssl'

[David Woodhouse]

On Fri, 2016-03-11 at 09:45 -0800, James Bottomley wrote:
> 
> > Did you *really* enable the building of openssl-1.0.2x/ssl/*.c in the
> > above builds? Or are you talking about something different?
> 
> No, and since I'm not using it, separating it is fine with me.

And here's where I came in... is there any need for it to be separate?

If the objects corresponding to ssl/*.c are present in the library
archive, doesn't that just mean that they'll get pulled in if they're
*referenced*, and not if they're not? So why separate it out into
OpensslTlsLib at all?

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Re: [edk2] More OpenSSL fun...

[Long, Qin]

Looks great. It's really helpful. 
We can follow this for step-by-step integration & fixes. :-)


Best Regards & Thanks,
LONG, Qin

> -Original Message-
> From: David Woodhouse [mailto:dw...@infradead.org]
> Sent: Friday, March 11, 2016 9:24 AM
> To: edk2-de...@ml01.01.org
> Cc: Long, Qin ; Wu, Jiaxin ; Ye, 
> Ting 
> Subject: More OpenSSL fun...
> 
> At git//, https://git.infradead.org/users/dwmw2/edk2.git and in
> following emails you can find the following:
> 
> As before, the ones which update to OpenSSL HEAD, and after that, are
> for comment only.
> 
> David Woodhouse (7):
>       CryptoPkg/OpensslLib: Convert saved opensslconf.h to DOS line endings
>   CryptoPkg/OpensslLib: Fix handling of &strcmp function pointers
>   CryptoPkg/OpensslLib: Fix GCC unused-value warnings with HOST_c2l() 
> (RT#4347)
>   CryptoPkg/OpensslLib: Enable warnings in GCC builds
>   CryptoPkg: Support building with OpenSSL HEAD (1.1.0-devel)
>   CryptoPkg: Abuse internal headers to make OpenSSL HEAD build work
>   CryptoPkg/OpensslLib: Enable building of ssl/ subdirectory of OpenSSL
> 
> Jiaxin Wu (1):
>   CryptoPkg: Fix time(NULL) crash
> 
> Qin Long (1):
>   CryptoPkg/OpensslLib: Upgrade OpenSSL version to 1.0.2g
> 
> 
> --
> David WoodhouseOpen Source Technology Centre
> david.woodho...@intel.com  Intel Corporation

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[edk2] Linux Version of EDK2

[Jim Slaughter]

 Working with 2015.Under Linux, Red Hat, I do the following and get this 
error?One document says with Linux you just need to do "make"?What is the 
correct initialization?Jim S.
v-jaslau@fe01:~/edk2/2015> . edksetup.sh BaseTools
BaseTools not found in your tree, and EDK_TOOLS_PATH is not set.
Please check that WORKSPACE is not set incorrectly in your
shell, or point EDK_TOOLS_PATH at the directory that contains
the EDK2 BuildEnv script.
v-jaslau@fe01:~/edk2/2015> 
Here is my directory structure:
v-jaslau@fe01:~/edk2/2015> ll
total 92922
drwxr-xr-x. 11 v-jaslau hardware  545 Sep 21 21:51 BaseTools
-rwxr-x---.  1 v-jaslau hardware 45721600 Sep 22 23:12 BaseToolsLinux.tar
drwxr-x---.  4 v-jaslau hardware   79 Mar  4 14:42 BaseTools(Windows)
-rwxr-x---.  1 v-jaslau hardware 18779335 Sep 22 00:20 BaseTools(Windows).zip
drwxr-xr-x.  2 v-jaslau hardware   56 Sep 21 22:19 Conf
drwxr-x---.  2 v-jaslau hardware  768 Mar  4 14:40 Documents
-rwxr-xr-x.  1 v-jaslau hardware 3104 Sep 21 21:43 edksetup.sh
drwxr-x---.  2 v-jaslau hardware  560 Mar  4 14:40 Notes
-rwxr-x---.  1 v-jaslau hardware 14336667 Sep 29 15:36 UDK2015.MyWorkSpace.zip
-rwxr-x---.  1 v-jaslau hardware    16113 Sep 29 15:42 
UDK2015-ReleaseNotes-MyWorkSpace.txt
v-jaslau@fe01:~/edk2/2015> 

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[edk2] Still Cannot Find Files

[Jim Slaughter]

 I loaded Windows version 2015 and finally got the edksetup.sh to run.
I started this endeavor needing to build a library(s) with the Ffs functions 
for use on an assignment.They are defined in the edk2-master under embeddedpkg 
I believe.I cannot find them in 2015 under Source, 
..\edk2\BaseTools\Source\...There is a folder called GenFfs but I do not see 
the file FfsFindNextVolume() or the others I need..Where are these files? Have 
they been renamed and/or relocated?
Edk2-master had the missing directory so I could not run edksetup. It was 
suggester I move to 2015.Thanks.
Jim S.


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Re: [edk2] Linux Version of EDK2

[Jordan Justen]

For setting up a Linux build environment, I'd recommend starting with:

https://github.com/tianocore/tianocore.github.io/wiki/Using-EDK-II-with-Native-GCC

This will get you setup to build from EDK II's main branch. Do you
need to use UDK2015?

-Jordan

On 2016-03-11 11:05:57, Jim Slaughter wrote:
>  Working with 2015.Under Linux, Red Hat, I do the following and get this 
> error?One document says with Linux you just need to do "make"?What is the 
> correct initialization?Jim S.
> v-jaslau@fe01:~/edk2/2015> . edksetup.sh BaseTools
> BaseTools not found in your tree, and EDK_TOOLS_PATH is not set.
> Please check that WORKSPACE is not set incorrectly in your
> shell, or point EDK_TOOLS_PATH at the directory that contains
> the EDK2 BuildEnv script.
> v-jaslau@fe01:~/edk2/2015> 
> Here is my directory structure:
> v-jaslau@fe01:~/edk2/2015> ll
> total 92922
> drwxr-xr-x. 11 v-jaslau hardware  545 Sep 21 21:51 BaseTools
> -rwxr-x---.  1 v-jaslau hardware 45721600 Sep 22 23:12 BaseToolsLinux.tar
> drwxr-x---.  4 v-jaslau hardware   79 Mar  4 14:42 BaseTools(Windows)
> -rwxr-x---.  1 v-jaslau hardware 18779335 Sep 22 00:20 BaseTools(Windows).zip
> drwxr-xr-x.  2 v-jaslau hardware   56 Sep 21 22:19 Conf
> drwxr-x---.  2 v-jaslau hardware  768 Mar  4 14:40 Documents
> -rwxr-xr-x.  1 v-jaslau hardware 3104 Sep 21 21:43 edksetup.sh
> drwxr-x---.  2 v-jaslau hardware  560 Mar  4 14:40 Notes
> -rwxr-x---.  1 v-jaslau hardware 14336667 Sep 29 15:36 UDK2015.MyWorkSpace.zip
> -rwxr-x---.  1 v-jaslau hardware    16113 Sep 29 15:42 
> UDK2015-ReleaseNotes-MyWorkSpace.txt
> v-jaslau@fe01:~/edk2/2015> 
> 
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Re: [edk2] Linux Version of EDK2

[Jim Slaughter]

No I was told to move to 2015 from edk2-masterJim S.
 

On Friday, March 11, 2016 11:21 AM, Jordan Justen 
 wrote:
 

 For setting up a Linux build environment, I'd recommend starting with:

https://github.com/tianocore/tianocore.github.io/wiki/Using-EDK-II-with-Native-GCC

This will get you setup to build from EDK II's main branch. Do you
need to use UDK2015?

-Jordan

On 2016-03-11 11:05:57, Jim Slaughter wrote:
>  Working with 2015.Under Linux, Red Hat, I do the following and get this 
>error?One document says with Linux you just need to do "make"?What is the 
>correct initialization?Jim S.
> v-jaslau@fe01:~/edk2/2015> . edksetup.sh BaseTools
> BaseTools not found in your tree, and EDK_TOOLS_PATH is not set.
> Please check that WORKSPACE is not set incorrectly in your
> shell, or point EDK_TOOLS_PATH at the directory that contains
> the EDK2 BuildEnv script.
> v-jaslau@fe01:~/edk2/2015> 
> Here is my directory structure:
> v-jaslau@fe01:~/edk2/2015> ll
> total 92922
> drwxr-xr-x. 11 v-jaslau hardware  545 Sep 21 21:51 BaseTools
> -rwxr-x---.  1 v-jaslau hardware 45721600 Sep 22 23:12 BaseToolsLinux.tar
> drwxr-x---.  4 v-jaslau hardware   79 Mar  4 14:42 BaseTools(Windows)
> -rwxr-x---.  1 v-jaslau hardware 18779335 Sep 22 00:20 BaseTools(Windows).zip
> drwxr-xr-x.  2 v-jaslau hardware   56 Sep 21 22:19 Conf
> drwxr-x---.  2 v-jaslau hardware  768 Mar  4 14:40 Documents
> -rwxr-xr-x.  1 v-jaslau hardware 3104 Sep 21 21:43 edksetup.sh
> drwxr-x---.  2 v-jaslau hardware  560 Mar  4 14:40 Notes
> -rwxr-x---.  1 v-jaslau hardware 14336667 Sep 29 15:36 UDK2015.MyWorkSpace.zip
> -rwxr-x---.  1 v-jaslau hardware    16113 Sep 29 15:42 
> UDK2015-ReleaseNotes-MyWorkSpace.txt
> v-jaslau@fe01:~/edk2/2015> 
> 
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[edk2] [Patch v2 02/21] UefiCpuPkg/Include: Add Core 2 MSR include file

[Michael Kinney]

Add Core 2 MSRs from:
Intel(R) 64 and IA-32 Architectures Software Developer's
Manual, Volume 3, December 2015, Chapter 35
Model-Specific-Registers (MSR), Section 35-2.

Cc: Jeff Fan 
Cc: Jiewen Yao 
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Michael Kinney 
---
 UefiCpuPkg/Include/Register/Msr/Core2Msr.h | 1325 
 1 file changed, 1325 insertions(+)
 create mode 100644 UefiCpuPkg/Include/Register/Msr/Core2Msr.h

diff --git a/UefiCpuPkg/Include/Register/Msr/Core2Msr.h 
b/UefiCpuPkg/Include/Register/Msr/Core2Msr.h
new file mode 100644
index 000..5fbde51
--- /dev/null
+++ b/UefiCpuPkg/Include/Register/Msr/Core2Msr.h
@@ -0,0 +1,1325 @@
+/** @file
+   MSR Definitions for the Intel(R) Core(TM) 2 Processor Family.
+
+  Provides defines for Machine Specific Registers(MSR) indexes. Data structures
+  are provided for MSRs that contain one or more bit fields.  If the MSR value
+  returned is a single 32-bit or 64-bit value, then a data structure is not
+  provided for that MSR.
+
+  Copyright (c) 2016, Intel Corporation. All rights reserved.
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD 
License
+  which accompanies this distribution.  The full text of the license may be 
found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+  @par Specification Reference:
+  Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,
+  December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-2.
+
+**/
+
+#ifndef __CORE2_MSR_H__
+#define __CORE2_MSR_H__
+
+#include 
+
+/**
+  Shared. Model Specific Platform ID (R).
+
+  @param  ECX  MSR_CORE2_PLATFORM_ID (0x0017)
+  @param  EAX  Lower 32-bits of MSR value.
+   Described by the type MSR_CORE2_PLATFORM_ID_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+   Described by the type MSR_CORE2_PLATFORM_ID_REGISTER.
+
+  Example usage
+  @code
+  MSR_CORE2_PLATFORM_ID_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_CORE2_PLATFORM_ID);
+  @endcode
+**/
+#define MSR_CORE2_PLATFORM_ID0x0017
+
+/**
+  MSR information returned for MSR index #MSR_CORE2_PLATFORM_ID
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+UINT32  Reserved1:8;
+///
+/// [Bits 12:8] Maximum Qualified Ratio (R)  The maximum allowed bus ratio.
+///
+UINT32  MaximumQualifiedRatio:5;
+UINT32  Reserved2:19;
+UINT32  Reserved3:18;
+///
+/// [Bits 52:50] See Table 35-2.
+///
+UINT32  PlatformId:3;
+UINT32  Reserved4:11;
+  } Bits;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_CORE2_PLATFORM_ID_REGISTER;
+
+
+/**
+  Shared. Processor Hard Power-On Configuration (R/W) Enables and disables
+  processor features; (R) indicates current processor configuration.
+
+  @param  ECX  MSR_CORE2_EBL_CR_POWERON (0x002A)
+  @param  EAX  Lower 32-bits of MSR value.
+   Described by the type MSR_CORE2_EBL_CR_POWERON_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+   Described by the type MSR_CORE2_EBL_CR_POWERON_REGISTER.
+
+  Example usage
+  @code
+  MSR_CORE2_EBL_CR_POWERON_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_CORE2_EBL_CR_POWERON);
+  AsmWriteMsr64 (MSR_CORE2_EBL_CR_POWERON, Msr.Uint64);
+  @endcode
+**/
+#define MSR_CORE2_EBL_CR_POWERON 0x002A
+
+/**
+  MSR information returned for MSR index #MSR_CORE2_EBL_CR_POWERON
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+UINT32  Reserved1:1;
+///
+/// [Bit 1] Data Error Checking Enable (R/W) 1 = Enabled; 0 = Disabled
+/// Note: Not all processor implements R/W.
+///
+UINT32  DataErrorCheckingEnable:1;
+///
+/// [Bit 2] Response Error Checking Enable (R/W) 1 = Enabled; 0 = Disabled
+/// Note: Not all processor implements R/W.
+///
+UINT32  ResponseErrorCheckingEnable:1;
+///
+/// [Bit 3] MCERR# Drive Enable (R/W)  1 = Enabled; 0 = Disabled Note: Not
+/// all processor implements R/W.
+///
+UINT32  MCERR_DriveEnable:1;
+///
+/// [Bit 4] Address Parity Enable (R/W) 1 = Enabled; 0 = Disabled Note:
+/// Not all processor implements R/W.
+///
+UINT32  AddressParityEnable:1;
+UINT32  Reserved2:1;
+UINT32  Reserved3:1;
+///
+/// [Bit 7] BINIT# Driver Enable (R/W) 1 = Enabled; 0 = Disabled Note: Not
+/// all processor implements R/W.
+///
+UINT32  BINIT_DriverEnable:1;
+///
+/// [Bit 8] Output Tri-state Enabled (R/O) 1 = Enabled; 0 = Disabled.
+///
+UINT32  OutputTriStateEnable:1;
+///
+/// [Bit 9] Execute BIST (R/O) 1 = Enabled; 0 = Disabled.
+///
+UINT32  ExecuteBIST:1;
+///

[edk2] [Patch v2 06/21] UefiCpuPkg/Include: Add Xeon 5600 MSR include file

[Michael Kinney]

Add Xeon 5600 MSRs from:
Intel(R) 64 and IA-32 Architectures Software Developer's
Manual, Volume 3, December 2015, Chapter 35
Model-Specific-Registers (MSR), Section 35-6.

Cc: Jeff Fan 
Cc: Jiewen Yao 
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Michael Kinney 
---
 UefiCpuPkg/Include/Register/Msr/Xeon5600Msr.h | 182 ++
 1 file changed, 182 insertions(+)
 create mode 100644 UefiCpuPkg/Include/Register/Msr/Xeon5600Msr.h

diff --git a/UefiCpuPkg/Include/Register/Msr/Xeon5600Msr.h 
b/UefiCpuPkg/Include/Register/Msr/Xeon5600Msr.h
new file mode 100644
index 000..a4c6ba0
--- /dev/null
+++ b/UefiCpuPkg/Include/Register/Msr/Xeon5600Msr.h
@@ -0,0 +1,182 @@
+/** @file
+  MSR Definitions for Intel(R) Xeon(R) Processor Series 5600.
+
+  Provides defines for Machine Specific Registers(MSR) indexes. Data structures
+  are provided for MSRs that contain one or more bit fields.  If the MSR value
+  returned is a single 32-bit or 64-bit value, then a data structure is not
+  provided for that MSR.
+
+  Copyright (c) 2016, Intel Corporation. All rights reserved.
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD 
License
+  which accompanies this distribution.  The full text of the license may be 
found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+  @par Specification Reference:
+  Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,
+  December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-6.
+
+**/
+
+#ifndef __XEON_5600_MSR_H__
+#define __XEON_5600_MSR_H__
+
+#include 
+
+/**
+  Core. AES Configuration (RW-L) Privileged post-BIOS agent must provide a #GP
+  handler to handle unsuccessful read of this MSR.
+
+  @param  ECX  MSR_XEON_5600_FEATURE_CONFIG (0x013C)
+  @param  EAX  Lower 32-bits of MSR value.
+   Described by the type MSR_XEON_5600_FEATURE_CONFIG_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+   Described by the type MSR_XEON_5600_FEATURE_CONFIG_REGISTER.
+
+  Example usage
+  @code
+  MSR_XEON_5600_FEATURE_CONFIG_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_XEON_5600_FEATURE_CONFIG);
+  AsmWriteMsr64 (MSR_XEON_5600_FEATURE_CONFIG, Msr.Uint64);
+  @endcode
+**/
+#define MSR_XEON_5600_FEATURE_CONFIG 0x013C
+
+/**
+  MSR information returned for MSR index #MSR_XEON_5600_FEATURE_CONFIG
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+///
+/// [Bits 1:0] AES Configuration (RW-L)  Upon a successful read of this
+/// MSR, the configuration of AES instruction set availability is as
+/// follows: 11b: AES instructions are not available until next RESET.
+/// otherwise, AES instructions are available. Note, AES instruction set
+/// is not available if read is unsuccessful. If the configuration is not
+/// 01b, AES instruction can be mis-configured if a privileged agent
+/// unintentionally writes 11b.
+///
+UINT32  AESConfiguration:2;
+UINT32  Reserved1:30;
+UINT32  Reserved2:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_XEON_5600_FEATURE_CONFIG_REGISTER;
+
+
+/**
+  Thread. Offcore Response Event Select Register (R/W).
+
+  @param  ECX  MSR_XEON_5600_OFFCORE_RSP_1 (0x01A7)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  Example usage
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_XEON_5600_OFFCORE_RSP_1);
+  AsmWriteMsr64 (MSR_XEON_5600_OFFCORE_RSP_1, Msr);
+  @endcode
+**/
+#define MSR_XEON_5600_OFFCORE_RSP_1  0x01A7
+
+
+/**
+  Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0,
+  RW if MSR_PLATFORM_INFO.[28] = 1.
+
+  @param  ECX  MSR_XEON_5600_TURBO_RATIO_LIMIT (0x01AD)
+  @param  EAX  Lower 32-bits of MSR value.
+   Described by the type MSR_XEON_5600_TURBO_RATIO_LIMIT_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+   Described by the type MSR_XEON_5600_TURBO_RATIO_LIMIT_REGISTER.
+
+  Example usage
+  @code
+  MSR_XEON_5600_TURBO_RATIO_LIMIT_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_XEON_5600_TURBO_RATIO_LIMIT);
+  @endcode
+**/
+#define MSR_XEON_5600_TURBO_RATIO_LIMIT  0x01AD
+
+/**
+  MSR information returned for MSR index 
#MSR_XEON_5600_TURBO_RATIO_LIMIT_REGISTER
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+///
+/// [Bits 7:0] Package. Maximum Ratio Limit for 1C Maximum turbo ratio
+/// limit of 1 core active.
+///
+UINT32  Maximum1C:8;
+///
+/// [Bits 15:8] Package. Maximum Ratio Limit for 2C Maximum turbo ratio
+

[edk2] [Patch v2 03/21] UefiCpuPkg/Include: Add Atom MSR include file

[Michael Kinney]

Add Atom MSRs from:
Intel(R) 64 and IA-32 Architectures Software Developer's
Manual, Volume 3, December 2015, Chapter 35
Model-Specific-Registers (MSR), Section 35-3.

Cc: Jeff Fan 
Cc: Jiewen Yao 
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Michael Kinney 
---
 UefiCpuPkg/Include/Register/Msr/AtomMsr.h | 878 ++
 1 file changed, 878 insertions(+)
 create mode 100644 UefiCpuPkg/Include/Register/Msr/AtomMsr.h

diff --git a/UefiCpuPkg/Include/Register/Msr/AtomMsr.h 
b/UefiCpuPkg/Include/Register/Msr/AtomMsr.h
new file mode 100644
index 000..01e0d9a
--- /dev/null
+++ b/UefiCpuPkg/Include/Register/Msr/AtomMsr.h
@@ -0,0 +1,878 @@
+/** @file
+  MSR Definitions for the Intel(R) Atom(TM) Processor Family.
+
+  Provides defines for Machine Specific Registers(MSR) indexes. Data structures
+  are provided for MSRs that contain one or more bit fields.  If the MSR value
+  returned is a single 32-bit or 64-bit value, then a data structure is not
+  provided for that MSR.
+
+  Copyright (c) 2016, Intel Corporation. All rights reserved.
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD 
License
+  which accompanies this distribution.  The full text of the license may be 
found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+  @par Specification Reference:
+  Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,
+  December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-3.
+
+**/
+
+#ifndef __ATOM_MSR_H__
+#define __ATOM_MSR_H__
+
+#include 
+
+/**
+  Shared. Model Specific Platform ID (R).
+
+  @param  ECX  MSR_ATOM_PLATFORM_ID (0x0017)
+  @param  EAX  Lower 32-bits of MSR value.
+   Described by the type MSR_ATOM_PLATFORM_ID_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+   Described by the type MSR_ATOM_PLATFORM_ID_REGISTER.
+
+  Example usage
+  @code
+  MSR_ATOM_PLATFORM_ID_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_ATOM_PLATFORM_ID);
+  @endcode
+**/
+#define MSR_ATOM_PLATFORM_ID 0x0017
+
+/**
+  MSR information returned for MSR index #MSR_ATOM_PLATFORM_ID
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+UINT32  Reserved1:8;
+///
+/// [Bits 12:8] Maximum Qualified Ratio (R)  The maximum allowed bus ratio.
+///
+UINT32  MaximumQualifiedRatio:5;
+UINT32  Reserved2:19;
+UINT32  Reserved3:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_ATOM_PLATFORM_ID_REGISTER;
+
+
+/**
+  Shared. Processor Hard Power-On Configuration (R/W) Enables and disables
+  processor features; (R) indicates current processor configuration.
+
+  @param  ECX  MSR_ATOM_EBL_CR_POWERON (0x002A)
+  @param  EAX  Lower 32-bits of MSR value.
+   Described by the type MSR_ATOM_EBL_CR_POWERON_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+   Described by the type MSR_ATOM_EBL_CR_POWERON_REGISTER.
+
+  Example usage
+  @code
+  MSR_ATOM_EBL_CR_POWERON_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_ATOM_EBL_CR_POWERON);
+  AsmWriteMsr64 (MSR_ATOM_EBL_CR_POWERON, Msr.Uint64);
+  @endcode
+**/
+#define MSR_ATOM_EBL_CR_POWERON  0x002A
+
+/**
+  MSR information returned for MSR index #MSR_ATOM_EBL_CR_POWERON
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+UINT32  Reserved1:1;
+///
+/// [Bit 1] Data Error Checking Enable (R/W) 1 = Enabled; 0 = Disabled
+/// Always 0.
+///
+UINT32  DataErrorCheckingEnable:1;
+///
+/// [Bit 2] Response Error Checking Enable (R/W) 1 = Enabled; 0 = Disabled
+/// Always 0.
+///
+UINT32  ResponseErrorCheckingEnable:1;
+///
+/// [Bit 3] AERR# Drive Enable (R/W)  1 = Enabled; 0 = Disabled Always 0.
+///
+UINT32  AERR_DriveEnable:1;
+///
+/// [Bit 4] BERR# Enable for initiator bus requests (R/W) 1 = Enabled; 0 =
+/// Disabled Always 0.
+///
+UINT32  BERR_Enable:1;
+UINT32  Reserved2:1;
+UINT32  Reserved3:1;
+///
+/// [Bit 7] BINIT# Driver Enable (R/W) 1 = Enabled; 0 = Disabled Always 0.
+///
+UINT32  BINIT_DriverEnable:1;
+UINT32  Reserved4:1;
+///
+/// [Bit 9] Execute BIST (R/O) 1 = Enabled; 0 = Disabled.
+///
+UINT32  ExecuteBIST:1;
+///
+/// [Bit 10] AERR# Observation Enabled (R/O) 1 = Enabled; 0 = Disabled
+/// Always 0.
+///
+UINT32  AERR_ObservationEnabled:1;
+UINT32  Reserved5:1;
+///
+/// [Bit 12] BINIT# Observation Enabled (R/O) 1 = Enabled; 0 = Disabled
+/// Always 0.
+///
+UINT32  BINIT_ObservationEnabled:1;
+ 

[edk2] [Patch v2 08/21] UefiCpuPkg/Include: Add Sandy Bridge MSR include file

[Michael Kinney]

Add Sandy Bridge MSRs from:
Intel(R) 64 and IA-32 Architectures Software Developer's
Manual, Volume 3, December 2015, Chapter 35
Model-Specific-Registers (MSR), Section 35-8.

Cc: Jeff Fan 
Cc: Jiewen Yao 
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Michael Kinney 
---
 UefiCpuPkg/Include/Register/Msr/SandyBridgeMsr.h | 4703 ++
 1 file changed, 4703 insertions(+)
 create mode 100644 UefiCpuPkg/Include/Register/Msr/SandyBridgeMsr.h

diff --git a/UefiCpuPkg/Include/Register/Msr/SandyBridgeMsr.h 
b/UefiCpuPkg/Include/Register/Msr/SandyBridgeMsr.h
new file mode 100644
index 000..c41e45b
--- /dev/null
+++ b/UefiCpuPkg/Include/Register/Msr/SandyBridgeMsr.h
@@ -0,0 +1,4703 @@
+/** @file
+  MSR Definitions for Intel processors based on the Sandy Bridge 
microarchitecture.
+
+  Provides defines for Machine Specific Registers(MSR) indexes. Data structures
+  are provided for MSRs that contain one or more bit fields.  If the MSR value
+  returned is a single 32-bit or 64-bit value, then a data structure is not
+  provided for that MSR.
+
+  Copyright (c) 2016, Intel Corporation. All rights reserved.
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD 
License
+  which accompanies this distribution.  The full text of the license may be 
found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+  @par Specification Reference:
+  Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,
+  December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-8.
+
+**/
+
+#ifndef __SANDY_BRIDGE_MSR_H__
+#define __SANDY_BRIDGE_MSR_H__
+
+#include 
+
+/**
+  Thread. SMI Counter (R/O).
+
+  @param  ECX  MSR_SANDY_BRIDGE_SMI_COUNT (0x0034)
+  @param  EAX  Lower 32-bits of MSR value.
+   Described by the type MSR_SANDY_BRIDGE_SMI_COUNT_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+   Described by the type MSR_SANDY_BRIDGE_SMI_COUNT_REGISTER.
+
+  Example usage
+  @code
+  MSR_SANDY_BRIDGE_SMI_COUNT_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_SMI_COUNT);
+  @endcode
+**/
+#define MSR_SANDY_BRIDGE_SMI_COUNT   0x0034
+
+/**
+  MSR information returned for MSR index #MSR_SANDY_BRIDGE_SMI_COUNT
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+///
+/// [Bits 31:0] SMI Count (R/O) Count SMIs.
+///
+UINT32  SMICount:32;
+UINT32  Reserved:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_SANDY_BRIDGE_SMI_COUNT_REGISTER;
+
+
+/**
+  Package. See http://biosbits.org.
+
+  @param  ECX  MSR_SANDY_BRIDGE_PLATFORM_INFO (0x00CE)
+  @param  EAX  Lower 32-bits of MSR value.
+   Described by the type MSR_SANDY_BRIDGE_PLATFORM_INFO_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+   Described by the type MSR_SANDY_BRIDGE_PLATFORM_INFO_REGISTER.
+
+  Example usage
+  @code
+  MSR_SANDY_BRIDGE_PLATFORM_INFO_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_PLATFORM_INFO);
+  AsmWriteMsr64 (MSR_SANDY_BRIDGE_PLATFORM_INFO, Msr.Uint64);
+  @endcode
+**/
+#define MSR_SANDY_BRIDGE_PLATFORM_INFO   0x00CE
+
+/**
+  MSR information returned for MSR index #MSR_SANDY_BRIDGE_PLATFORM_INFO
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+UINT32  Reserved1:8;
+///
+/// [Bits 15:8] Package. Maximum Non-Turbo Ratio (R/O)  The is the ratio
+/// of the frequency that invariant TSC runs at. Frequency = ratio * 100
+/// MHz.
+///
+UINT32  MaximumNonTurboRatio:8;
+UINT32  Reserved2:12;
+///
+/// [Bit 28] Package. Programmable Ratio Limit for Turbo Mode (R/O)  When
+/// set to 1, indicates that Programmable Ratio Limits for Turbo mode is
+/// enabled, and when set to 0, indicates Programmable Ratio Limits for
+/// Turbo mode is disabled.
+///
+UINT32  RatioLimit:1;
+///
+/// [Bit 29] Package. Programmable TDP Limit for Turbo Mode (R/O)  When
+/// set to 1, indicates that TDP Limits for Turbo mode are programmable,
+/// and when set to 0, indicates TDP Limit for Turbo mode is not
+/// programmable.
+///
+UINT32  TDPLimit:1;
+UINT32  Reserved3:2;
+UINT32  Reserved4:8;
+///
+/// [Bits 47:40] Package. Maximum Efficiency Ratio (R/O)  The is the
+/// minimum ratio (maximum efficiency) that the processor can operates, in
+/// units of 100MHz.
+///
+UINT32  MaximumEfficiencyRatio:8;
+UINT32  Reserved5:16;
+  } Bits;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_SANDY_BRIDGE_PLATFORM_INFO_REGISTER;
+
+
+/*

[edk2] [Patch v2 07/21] UefiCpuPkg/Include: Add Xeon E7 MSR include file

[Michael Kinney]

Add Xeon E7 MSRs from:
Intel(R) 64 and IA-32 Architectures Software Developer's
Manual, Volume 3, December 2015, Chapter 35
Model-Specific-Registers (MSR), Section 35-7.

Cc: Jeff Fan 
Cc: Jiewen Yao 
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Michael Kinney 
---
 UefiCpuPkg/Include/Register/Msr/XeonE7Msr.h | 254 
 1 file changed, 254 insertions(+)
 create mode 100644 UefiCpuPkg/Include/Register/Msr/XeonE7Msr.h

diff --git a/UefiCpuPkg/Include/Register/Msr/XeonE7Msr.h 
b/UefiCpuPkg/Include/Register/Msr/XeonE7Msr.h
new file mode 100644
index 000..b95f963
--- /dev/null
+++ b/UefiCpuPkg/Include/Register/Msr/XeonE7Msr.h
@@ -0,0 +1,254 @@
+/** @file
+  MSR Definitions for Intel(R) Xeon(R) Processor E7 Family.
+
+  Provides defines for Machine Specific Registers(MSR) indexes. Data structures
+  are provided for MSRs that contain one or more bit fields.  If the MSR value
+  returned is a single 32-bit or 64-bit value, then a data structure is not
+  provided for that MSR.
+
+  Copyright (c) 2016, Intel Corporation. All rights reserved.
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD 
License
+  which accompanies this distribution.  The full text of the license may be 
found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+  @par Specification Reference:
+  Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,
+  December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-7.
+
+**/
+
+#ifndef __XEON_E7_MSR_H__
+#define __XEON_E7_MSR_H__
+
+#include 
+
+/**
+  Package. Reserved Attempt to read/write will cause #UD.
+
+  @param  ECX  MSR_XEON_E7_TURBO_RATIO_LIMIT (0x01AD)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  Example usage
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_XEON_E7_TURBO_RATIO_LIMIT);
+  AsmWriteMsr64 (MSR_XEON_E7_TURBO_RATIO_LIMIT, Msr);
+  @endcode
+**/
+#define MSR_XEON_E7_TURBO_RATIO_LIMIT0x01AD
+
+
+/**
+  Package. Uncore C-box 8 perfmon local box control MSR.
+
+  @param  ECX  MSR_XEON_E7_C8_PMON_BOX_CTRL (0x0F40)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  Example usage
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_XEON_E7_C8_PMON_BOX_CTRL);
+  AsmWriteMsr64 (MSR_XEON_E7_C8_PMON_BOX_CTRL, Msr);
+  @endcode
+**/
+#define MSR_XEON_E7_C8_PMON_BOX_CTRL 0x0F40
+
+
+/**
+  Package. Uncore C-box 8 perfmon local box status MSR.
+
+  @param  ECX  MSR_XEON_E7_C8_PMON_BOX_STATUS (0x0F41)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  Example usage
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_XEON_E7_C8_PMON_BOX_STATUS);
+  AsmWriteMsr64 (MSR_XEON_E7_C8_PMON_BOX_STATUS, Msr);
+  @endcode
+**/
+#define MSR_XEON_E7_C8_PMON_BOX_STATUS   0x0F41
+
+
+/**
+  Package. Uncore C-box 8 perfmon local box overflow control MSR.
+
+  @param  ECX  MSR_XEON_E7_C8_PMON_BOX_OVF_CTRL (0x0F42)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  Example usage
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_XEON_E7_C8_PMON_BOX_OVF_CTRL);
+  AsmWriteMsr64 (MSR_XEON_E7_C8_PMON_BOX_OVF_CTRL, Msr);
+  @endcode
+**/
+#define MSR_XEON_E7_C8_PMON_BOX_OVF_CTRL 0x0F42
+
+
+/**
+  Package. Uncore C-box 8 perfmon event select MSR.
+
+  @param  ECX  MSR_XEON_E7_C8_PMON_EVNT_SELn
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  Example usage
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_XEON_E7_C8_PMON_EVNT_SEL0);
+  AsmWriteMsr64 (MSR_XEON_E7_C8_PMON_EVNT_SEL0, Msr);
+  @endcode
+  @{
+**/
+#define MSR_XEON_E7_C8_PMON_EVNT_SEL00x0F50
+#define MSR_XEON_E7_C8_PMON_EVNT_SEL10x0F52
+#define MSR_XEON_E7_C8_PMON_EVNT_SEL20x0F54
+#define MSR_XEON_E7_C8_PMON_EVNT_SEL30x0F56
+#define MSR_XEON_E7_C8_PMON_EVNT_SEL40x0F58
+#define MSR_XEON_E7_C8_PMON_EVNT_SEL50x0F5A
+/// @}
+
+
+/**
+  Package. Uncore C-box 8 perfmon counter MSR.
+
+  @param  ECX  MSR_XEON_E7_C8_PMON_CTRn
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  Example usage
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_XEON_E7_C8_PMON_CTR0);
+  AsmWriteMsr64 (MSR_XEON_E7_C8_PMON_CTR0, Msr);
+  @endcode
+  @{
+**/
+#define MSR_XEON_E7_C8_PMON_CTR0 0x0F51
+#define MSR_XEON_E7_C8_PMON_CTR1 0x0F53
+#define MSR_XEON_E7_C8_PMON_CTR2 0x0F55
+#define MSR_XEON_E7_C8_PMON_CTR3 0x0F57
+#define MSR_XEON_E7_C8_PMON_CTR4   

[edk2] [Patch v2 04/21] UefiCpuPkg/Include: Add Silvermont MSR include file

[Michael Kinney]

Add Silvermont MSRs from:
Intel(R) 64 and IA-32 Architectures Software Developer's
Manual, Volume 3, December 2015, Chapter 35
Model-Specific-Registers (MSR), Section 35-4.

Cc: Jeff Fan 
Cc: Jiewen Yao 
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Michael Kinney 
---
 UefiCpuPkg/Include/Register/Msr/SilvermontMsr.h | 1468 +++
 1 file changed, 1468 insertions(+)
 create mode 100644 UefiCpuPkg/Include/Register/Msr/SilvermontMsr.h

diff --git a/UefiCpuPkg/Include/Register/Msr/SilvermontMsr.h 
b/UefiCpuPkg/Include/Register/Msr/SilvermontMsr.h
new file mode 100644
index 000..4272375
--- /dev/null
+++ b/UefiCpuPkg/Include/Register/Msr/SilvermontMsr.h
@@ -0,0 +1,1468 @@
+/** @file
+  MSR Definitions for Intel processors based on the Silvermont 
microarchitecture.
+
+  Provides defines for Machine Specific Registers(MSR) indexes. Data structures
+  are provided for MSRs that contain one or more bit fields.  If the MSR value
+  returned is a single 32-bit or 64-bit value, then a data structure is not
+  provided for that MSR.
+
+  Copyright (c) 2016, Intel Corporation. All rights reserved.
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD 
License
+  which accompanies this distribution.  The full text of the license may be 
found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+  @par Specification Reference:
+  Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,
+  December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-4.
+
+**/
+
+#ifndef __SILVERMONT_MSR_H__
+#define __SILVERMONT_MSR_H__
+
+#include 
+
+/**
+  Shared. Model Specific Platform ID (R).
+
+  @param  ECX  MSR_SILVERMONT_PLATFORM_ID (0x0017)
+  @param  EAX  Lower 32-bits of MSR value.
+   Described by the type MSR_SILVERMONT_PLATFORM_ID_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+   Described by the type MSR_SILVERMONT_PLATFORM_ID_REGISTER.
+
+  Example usage
+  @code
+  MSR_SILVERMONT_PLATFORM_ID_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_PLATFORM_ID);
+  @endcode
+**/
+#define MSR_SILVERMONT_PLATFORM_ID   0x0017
+
+/**
+  MSR information returned for MSR index #MSR_SILVERMONT_PLATFORM_ID
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+UINT32  Reserved1:8;
+///
+/// [Bits 12:8] Maximum Qualified Ratio (R)  The maximum allowed bus ratio.
+///
+UINT32  MaximumQualifiedRatio:5;
+UINT32  Reserved2:19;
+UINT32  Reserved3:18;
+///
+/// [Bits 52:50] See Table 35-2.
+///
+UINT32  PlatformId:3;
+UINT32  Reserved4:11;
+  } Bits;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_SILVERMONT_PLATFORM_ID_REGISTER;
+
+
+/**
+  Shared. Processor Hard Power-On Configuration (R/W) Enables and disables
+  processor features; (R) indicates current processor configuration.
+
+  @param  ECX  MSR_SILVERMONT_EBL_CR_POWERON (0x002A)
+  @param  EAX  Lower 32-bits of MSR value.
+   Described by the type MSR_SILVERMONT_EBL_CR_POWERON_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+   Described by the type MSR_SILVERMONT_EBL_CR_POWERON_REGISTER.
+
+  Example usage
+  @code
+  MSR_SILVERMONT_EBL_CR_POWERON_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_EBL_CR_POWERON);
+  AsmWriteMsr64 (MSR_SILVERMONT_EBL_CR_POWERON, Msr.Uint64);
+  @endcode
+**/
+#define MSR_SILVERMONT_EBL_CR_POWERON0x002A
+
+/**
+  MSR information returned for MSR index #MSR_SILVERMONT_EBL_CR_POWERON
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+UINT32  Reserved1:1;
+///
+/// [Bit 1] Data Error Checking Enable (R/W) 1 = Enabled; 0 = Disabled
+/// Always 0.
+///
+UINT32  DataErrorCheckingEnable:1;
+///
+/// [Bit 2] Response Error Checking Enable (R/W) 1 = Enabled; 0 = Disabled
+/// Always 0.
+///
+UINT32  ResponseErrorCheckingEnable:1;
+///
+/// [Bit 3] AERR# Drive Enable (R/W)  1 = Enabled; 0 = Disabled Always 0.
+///
+UINT32  AERR_DriveEnable:1;
+///
+/// [Bit 4] BERR# Enable for initiator bus requests (R/W) 1 = Enabled; 0 =
+/// Disabled Always 0.
+///
+UINT32  BERR_Enable:1;
+UINT32  Reserved2:1;
+UINT32  Reserved3:1;
+///
+/// [Bit 7] BINIT# Driver Enable (R/W) 1 = Enabled; 0 = Disabled Always 0.
+///
+UINT32  BINIT_DriverEnable:1;
+UINT32  Reserved4:1;
+///
+/// [Bit 9] Execute BIST (R/O) 1 = Enabled; 0 = Disabled.
+///
+UINT32  ExecuteBIST:1;
+///
+/// [Bit 10] AERR# Observation Enabled (R/O) 1 = Enabled; 0 = Disabled
+/// Always 0.
+///
+UINT32  AERR_ObservationEnabled:

[edk2] [Patch v2 00/21] UefiCpuPkg/Include: Add MSR include files

[Michael Kinney]

Add include files for Architectural MSRs and family specific 
MSRs described in section 35.1 to 35.20 of the 
Intel(R) 64 and IA-32 Architectures Software Developer's
Manual, Volume 3, December 2015, Chapter 35
Model-Specific-Registers (MSR).

New in V2 based on review feedback from Jeff Fan
=
* Fix spelling errors in comments
* Remove KERNEL_GSBASE from all family specific .h files.  
  These are identical to KERNEL_GS_BASE in ArchitecturalMsr.h
* Remove IA32_TSC_AUX from XeonPhi.h.  
  It is identical to IA32_TSC_AUX in ArchitecturalMsr.h
* Move 5 MSR_BROADWELL_C17_PMON_BOX_STATUS and MSR_BROADWELL_C17_PMON_CRTn 
  MSRs from BroadwellMsr.h to HaswellEMsr.h
* PentiumMMsr.h: Change field from Reserved to BTS in 
  MSR_PENTIUM_M_IA32_MISC_ENABLE
* SandyBridgeMsr.h: Remove MSR_SANDY_BRIDGE_X2APIC
* Xeon5600Msr.h: Move bitfieds from MSR_XEON_5600_OFFCORE_RSP_1 to 
  MSR_XEON_5600_TURBO_RATIO_LIMIT
* XeonDMsr.h: Change Reserved to BTS in MSR_XEON_D_IA32_L3_QOS_MASK_REGISTER

These files can also be pulled and reviewd from:

https://github.com/mdkinney/edk2/tree/Msr_V2

These includes files are not being used by any modules or 
libraries yet, so adding these .h files should not have any
impact on any build.  

I have tested that these include files do not cause any
build failures when used in UefiCPuPkg/Application/Cpuid.

These include files are being added so the defines and 
REGISTER structures can be used clean up IA32/X64 CPU 
modules and libraries that access MSRs.

Cc: Jeff Fan 
Cc: Jiewen Yao 
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Michael Kinney 

Michael Kinney (21):
  UefiCpuPkg/Include: Add Architectural MSR include file
  UefiCpuPkg/Include: Add Core 2 MSR include file
  UefiCpuPkg/Include: Add Atom MSR include file
  UefiCpuPkg/Include: Add Silvermont MSR include file
  UefiCpuPkg/Include: Add Nehalem MSR include file
  UefiCpuPkg/Include: Add Xeon 5600 MSR include file
  UefiCpuPkg/Include: Add Xeon E7 MSR include file
  UefiCpuPkg/Include: Add Sandy Bridge MSR include file
  UefiCpuPkg/Include: Add Ivy Bridge MSR include file
  UefiCpuPkg/Include: Add Haswell MSR include file
  UefiCpuPkg/Include: Add Haswell-E MSR include file
  UefiCpuPkg/Include: Add Broadwell MSR include file
  UefiCpuPkg/Include: Add Xeon Processor D MSR include file
  UefiCpuPkg/Include: Add Skylake MSR include file
  UefiCpuPkg/Include: Add Xeon Phi MSR include file
  UefiCpuPkg/Include: Add Pentium 4 MSR include file
  UefiCpuPkg/Include: Add Core Solo/Duo MSR include file
  UefiCpuPkg/Include: Add Pentium M MSR include file
  UefiCpuPkg/Include: Add P6 MSR include file
  UefiCpuPkg/Include: Add Pentium MSR include file
  UefiCpuPkg/Include: Add top level MSR include file

 UefiCpuPkg/Include/Register/ArchitecturalMsr.h   | 5801 +
 UefiCpuPkg/Include/Register/Msr.h|   48 +
 UefiCpuPkg/Include/Register/Msr/AtomMsr.h|  878 +++
 UefiCpuPkg/Include/Register/Msr/BroadwellMsr.h   |  265 +
 UefiCpuPkg/Include/Register/Msr/Core2Msr.h   | 1325 
 UefiCpuPkg/Include/Register/Msr/CoreMsr.h| 1074 
 UefiCpuPkg/Include/Register/Msr/HaswellEMsr.h| 5995 ++
 UefiCpuPkg/Include/Register/Msr/HaswellMsr.h | 2575 
 UefiCpuPkg/Include/Register/Msr/IvyBridgeMsr.h   | 2830 +
 UefiCpuPkg/Include/Register/Msr/NehalemMsr.h | 7196 ++
 UefiCpuPkg/Include/Register/Msr/P6Msr.h  | 1608 +
 UefiCpuPkg/Include/Register/Msr/Pentium4Msr.h| 2550 
 UefiCpuPkg/Include/Register/Msr/PentiumMMsr.h|  643 ++
 UefiCpuPkg/Include/Register/Msr/PentiumMsr.h |  121 +
 UefiCpuPkg/Include/Register/Msr/SandyBridgeMsr.h | 4703 ++
 UefiCpuPkg/Include/Register/Msr/SilvermontMsr.h  | 1468 +
 UefiCpuPkg/Include/Register/Msr/SkylakeMsr.h | 1008 +++
 UefiCpuPkg/Include/Register/Msr/Xeon5600Msr.h|  182 +
 UefiCpuPkg/Include/Register/Msr/XeonDMsr.h   | 1430 +
 UefiCpuPkg/Include/Register/Msr/XeonE7Msr.h  |  254 +
 UefiCpuPkg/Include/Register/Msr/XeonPhiMsr.h | 1426 +
 21 files changed, 43380 insertions(+)
 create mode 100644 UefiCpuPkg/Include/Register/ArchitecturalMsr.h
 create mode 100644 UefiCpuPkg/Include/Register/Msr.h
 create mode 100644 UefiCpuPkg/Include/Register/Msr/AtomMsr.h
 create mode 100644 UefiCpuPkg/Include/Register/Msr/BroadwellMsr.h
 create mode 100644 UefiCpuPkg/Include/Register/Msr/Core2Msr.h
 create mode 100644 UefiCpuPkg/Include/Register/Msr/CoreMsr.h
 create mode 100644 UefiCpuPkg/Include/Register/Msr/HaswellEMsr.h
 create mode 100644 UefiCpuPkg/Include/Register/Msr/HaswellMsr.h
 create mode 100644 UefiCpuPkg/Include/Register/Msr/IvyBridgeMsr.h
 create mode 100644 UefiCpuPkg/Include/Register/Msr/NehalemMsr.h
 create mode 100644 UefiCpuPkg/Include/Register/Msr/P6Msr.h
 create mode 100644 UefiCpuPkg/Include/Register/Msr/Pentium4Msr.h
 create mode 100644 UefiCpuPkg/Include/Register/Ms

[edk2] [Patch v2 20/21] UefiCpuPkg/Include: Add Pentium MSR include file

[Michael Kinney]

Add Pentium MSRs from:
Intel(R) 64 and IA-32 Architectures Software Developer's
Manual, Volume 3, December 2015, Chapter 35
Model-Specific-Registers (MSR), Section 35-20.

Cc: Jeff Fan 
Cc: Jiewen Yao 
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Michael Kinney 
---
 UefiCpuPkg/Include/Register/Msr/PentiumMsr.h | 121 +++
 1 file changed, 121 insertions(+)
 create mode 100644 UefiCpuPkg/Include/Register/Msr/PentiumMsr.h

diff --git a/UefiCpuPkg/Include/Register/Msr/PentiumMsr.h 
b/UefiCpuPkg/Include/Register/Msr/PentiumMsr.h
new file mode 100644
index 000..a8916b4
--- /dev/null
+++ b/UefiCpuPkg/Include/Register/Msr/PentiumMsr.h
@@ -0,0 +1,121 @@
+/** @file
+  MSR Definitions for Pentium Processors.
+
+  Provides defines for Machine Specific Registers(MSR) indexes. Data structures
+  are provided for MSRs that contain one or more bit fields.  If the MSR value
+  returned is a single 32-bit or 64-bit value, then a data structure is not
+  provided for that MSR.
+
+  Copyright (c) 2016, Intel Corporation. All rights reserved.
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD 
License
+  which accompanies this distribution.  The full text of the license may be 
found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+  @par Specification Reference:
+  Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,
+  December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-20.
+
+**/
+
+#ifndef __PENTIUM_MSR_H__
+#define __PENTIUM_MSR_H__
+
+#include 
+
+/**
+  See Section 15.10.2, "Pentium Processor Machine-Check Exception Handling.".
+
+  @param  ECX  MSR_PENTIUM_P5_MC_ADDR (0x)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  Example usage
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_PENTIUM_P5_MC_ADDR);
+  AsmWriteMsr64 (MSR_PENTIUM_P5_MC_ADDR, Msr);
+  @endcode
+**/
+#define MSR_PENTIUM_P5_MC_ADDR   0x
+
+
+/**
+  See Section 15.10.2, "Pentium Processor Machine-Check Exception Handling.".
+
+  @param  ECX  MSR_PENTIUM_P5_MC_TYPE (0x0001)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  Example usage
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_PENTIUM_P5_MC_TYPE);
+  AsmWriteMsr64 (MSR_PENTIUM_P5_MC_TYPE, Msr);
+  @endcode
+**/
+#define MSR_PENTIUM_P5_MC_TYPE   0x0001
+
+
+/**
+  See Section 17.14, "Time-Stamp Counter.".
+
+  @param  ECX  MSR_PENTIUM_TSC (0x0010)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  Example usage
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_PENTIUM_TSC);
+  AsmWriteMsr64 (MSR_PENTIUM_TSC, Msr);
+  @endcode
+**/
+#define MSR_PENTIUM_TSC  0x0010
+
+
+/**
+  See Section 18.20.1, "Control and Event Select Register (CESR).".
+
+  @param  ECX  MSR_PENTIUM_CESR (0x0011)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  Example usage
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_PENTIUM_CESR);
+  AsmWriteMsr64 (MSR_PENTIUM_CESR, Msr);
+  @endcode
+**/
+#define MSR_PENTIUM_CESR 0x0011
+
+
+/**
+  Section 18.20.3, "Events Counted.".
+
+  @param  ECX  MSR_PENTIUM_CTRn
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  Example usage
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_PENTIUM_CTR0);
+  AsmWriteMsr64 (MSR_PENTIUM_CTR0, Msr);
+  @endcode
+  @{
+**/
+#define MSR_PENTIUM_CTR0 0x0012
+#define MSR_PENTIUM_CTR1 0x0013
+/// @}
+
+#endif
-- 
2.6.3.windows.1

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[edk2] [Patch v2 21/21] UefiCpuPkg/Include: Add top level MSR include file

[Michael Kinney]

Add top level MSR include file that includes the Architecural MSR
include file and all family specific MSR files from the Msr
subdirectory

Intel(R) 64 and IA-32 Architectures Software Developer's
Manual, Volume 3, December 2015, Chapter 35
Model-Specific-Registers (MSR).

Cc: Jeff Fan 
Cc: Jiewen Yao 
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Michael Kinney 
---
 UefiCpuPkg/Include/Register/Msr.h | 48 +++
 1 file changed, 48 insertions(+)
 create mode 100644 UefiCpuPkg/Include/Register/Msr.h

diff --git a/UefiCpuPkg/Include/Register/Msr.h 
b/UefiCpuPkg/Include/Register/Msr.h
new file mode 100644
index 000..ffa6d44
--- /dev/null
+++ b/UefiCpuPkg/Include/Register/Msr.h
@@ -0,0 +1,48 @@
+/** @file
+  MSR Definitions.
+
+  Provides defines for Machine Specific Registers(MSR) indexes. Data structures
+  are provided for MSRs that contain one or more bit fields.  If the MSR value
+  returned is a single 32-bit or 64-bit value, then a data structure is not
+  provided for that MSR.
+
+  Copyright (c) 2016, Intel Corporation. All rights reserved.
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD 
License
+  which accompanies this distribution.  The full text of the license may be 
found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+  @par Specification Reference:
+  Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,
+  December 2015, Chapter 35 Model-Specific-Registers (MSR), Chapter 35.
+
+**/
+
+#ifndef __MSR_H__
+#define __MSR_H__
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#endif
-- 
2.6.3.windows.1

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[edk2] [Patch v2 15/21] UefiCpuPkg/Include: Add Xeon Phi MSR include file

[Michael Kinney]

Add Xeon Phi MSRs from:
Intel(R) 64 and IA-32 Architectures Software Developer's
Manual, Volume 3, December 2015, Chapter 35
Model-Specific-Registers (MSR), Section 35-15.

Cc: Jeff Fan 
Cc: Jiewen Yao 
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Michael Kinney 
---
 UefiCpuPkg/Include/Register/Msr/XeonPhiMsr.h | 1426 ++
 1 file changed, 1426 insertions(+)
 create mode 100644 UefiCpuPkg/Include/Register/Msr/XeonPhiMsr.h

diff --git a/UefiCpuPkg/Include/Register/Msr/XeonPhiMsr.h 
b/UefiCpuPkg/Include/Register/Msr/XeonPhiMsr.h
new file mode 100644
index 000..6695b69
--- /dev/null
+++ b/UefiCpuPkg/Include/Register/Msr/XeonPhiMsr.h
@@ -0,0 +1,1426 @@
+/** @file
+  MSR Definitions for Intel(R) Xeon(R) Phi(TM) processor Family.
+
+  Provides defines for Machine Specific Registers(MSR) indexes. Data structures
+  are provided for MSRs that contain one or more bit fields.  If the MSR value
+  returned is a single 32-bit or 64-bit value, then a data structure is not
+  provided for that MSR.
+
+  Copyright (c) 2016, Intel Corporation. All rights reserved.
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD 
License
+  which accompanies this distribution.  The full text of the license may be 
found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+  @par Specification Reference:
+  Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,
+  December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-15.
+
+**/
+
+#ifndef __XEON_PHI_MSR_H__
+#define __XEON_PHI_MSR_H__
+
+#include 
+
+/**
+  Thread. SMI Counter (R/O).
+
+  @param  ECX  MSR_XEON_PHI_SMI_COUNT (0x0034)
+  @param  EAX  Lower 32-bits of MSR value.
+   Described by the type MSR_XEON_PHI_SMI_COUNT_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+   Described by the type MSR_XEON_PHI_SMI_COUNT_REGISTER.
+
+  Example usage
+  @code
+  MSR_XEON_PHI_SMI_COUNT_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_SMI_COUNT);
+  @endcode
+**/
+#define MSR_XEON_PHI_SMI_COUNT   0x0034
+
+/**
+  MSR information returned for MSR index #MSR_XEON_PHI_SMI_COUNT
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+///
+/// [Bits 31:0] SMI Count (R/O).
+///
+UINT32  SMICount:32;
+UINT32  Reserved:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_XEON_PHI_SMI_COUNT_REGISTER;
+
+
+/**
+  Package. See http://biosbits.org.
+
+  @param  ECX  MSR_XEON_PHI_PLATFORM_INFO (0x00CE)
+  @param  EAX  Lower 32-bits of MSR value.
+   Described by the type MSR_XEON_PHI_PLATFORM_INFO_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+   Described by the type MSR_XEON_PHI_PLATFORM_INFO_REGISTER.
+
+  Example usage
+  @code
+  MSR_XEON_PHI_PLATFORM_INFO_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_PLATFORM_INFO);
+  AsmWriteMsr64 (MSR_XEON_PHI_PLATFORM_INFO, Msr.Uint64);
+  @endcode
+**/
+#define MSR_XEON_PHI_PLATFORM_INFO   0x00CE
+
+/**
+  MSR information returned for MSR index #MSR_XEON_PHI_PLATFORM_INFO
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+UINT32  Reserved1:8;
+///
+/// [Bits 15:8] Package. Maximum Non-Turbo Ratio (R/O)  The is the ratio
+/// of the frequency that invariant TSC runs at. Frequency = ratio * 100
+/// MHz.
+///
+UINT32  MaximumNonTurboRatio:8;
+UINT32  Reserved2:12;
+///
+/// [Bit 28] Package. Programmable Ratio Limit for Turbo Mode (R/O)  When
+/// set to 1, indicates that Programmable Ratio Limits for Turbo mode is
+/// enabled, and when set to 0, indicates Programmable Ratio Limits for
+/// Turbo mode is disabled.
+///
+UINT32  RatioLimit:1;
+///
+/// [Bit 29] Package. Programmable TDP Limit for Turbo Mode (R/O)  When
+/// set to 1, indicates that TDP Limits for Turbo mode are programmable,
+/// and when set to 0, indicates TDP Limit for Turbo mode is not
+/// programmable.
+///
+UINT32  TDPLimit:1;
+UINT32  Reserved3:2;
+UINT32  Reserved4:8;
+///
+/// [Bits 47:40] Package. Maximum Efficiency Ratio (R/O)  The is the
+/// minimum ratio (maximum efficiency) that the processor can operates, in
+/// units of 100MHz.
+///
+UINT32  MaximumEfficiencyRatio:8;
+UINT32  Reserved5:16;
+  } Bits;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_XEON_PHI_PLATFORM_INFO_REGISTER;
+
+
+/**
+  Module. C-State Configuration Control (R/W).
+
+  @param  ECX  MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL (0x00E2)

[edk2] [Patch v2 19/21] UefiCpuPkg/Include: Add P6 MSR include file

[Michael Kinney]

Add P6 MSRs from:
Intel(R) 64 and IA-32 Architectures Software Developer's
Manual, Volume 3, December 2015, Chapter 35
Model-Specific-Registers (MSR), Section 35-19.

Cc: Jeff Fan 
Cc: Jiewen Yao 
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Michael Kinney 
---
 UefiCpuPkg/Include/Register/Msr/P6Msr.h | 1608 +++
 1 file changed, 1608 insertions(+)
 create mode 100644 UefiCpuPkg/Include/Register/Msr/P6Msr.h

diff --git a/UefiCpuPkg/Include/Register/Msr/P6Msr.h 
b/UefiCpuPkg/Include/Register/Msr/P6Msr.h
new file mode 100644
index 000..7ee0b28
--- /dev/null
+++ b/UefiCpuPkg/Include/Register/Msr/P6Msr.h
@@ -0,0 +1,1608 @@
+/** @file
+  MSR Definitions for P6 Family Processors.
+
+  Provides defines for Machine Specific Registers(MSR) indexes. Data structures
+  are provided for MSRs that contain one or more bit fields.  If the MSR value
+  returned is a single 32-bit or 64-bit value, then a data structure is not
+  provided for that MSR.
+
+  Copyright (c) 2016, Intel Corporation. All rights reserved.
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD 
License
+  which accompanies this distribution.  The full text of the license may be 
found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+  @par Specification Reference:
+  Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,
+  December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-19.
+
+**/
+
+#ifndef __P6_MSR_H__
+#define __P6_MSR_H__
+
+#include 
+
+/**
+  See Section 35.20, "MSRs in Pentium Processors.".
+
+  @param  ECX  MSR_P6_P5_MC_ADDR (0x)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  Example usage
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_P6_P5_MC_ADDR);
+  AsmWriteMsr64 (MSR_P6_P5_MC_ADDR, Msr);
+  @endcode
+**/
+#define MSR_P6_P5_MC_ADDR0x
+
+
+/**
+  See Section 35.20, "MSRs in Pentium Processors.".
+
+  @param  ECX  MSR_P6_P5_MC_TYPE (0x0001)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  Example usage
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_P6_P5_MC_TYPE);
+  AsmWriteMsr64 (MSR_P6_P5_MC_TYPE, Msr);
+  @endcode
+**/
+#define MSR_P6_P5_MC_TYPE0x0001
+
+
+/**
+  See Section 17.14, "Time-Stamp Counter.".
+
+  @param  ECX  MSR_P6_TSC (0x0010)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  Example usage
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_P6_TSC);
+  AsmWriteMsr64 (MSR_P6_TSC, Msr);
+  @endcode
+**/
+#define MSR_P6_TSC   0x0010
+
+
+/**
+  Platform ID (R)  The operating system can use this MSR to determine "slot"
+  information for the processor and the proper microcode update to load.
+
+  @param  ECX  MSR_P6_IA32_PLATFORM_ID (0x0017)
+  @param  EAX  Lower 32-bits of MSR value.
+   Described by the type MSR_P6_IA32_PLATFORM_ID_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+   Described by the type MSR_P6_IA32_PLATFORM_ID_REGISTER.
+
+  Example usage
+  @code
+  MSR_P6_IA32_PLATFORM_ID_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_P6_IA32_PLATFORM_ID);
+  @endcode
+**/
+#define MSR_P6_IA32_PLATFORM_ID  0x0017
+
+/**
+  MSR information returned for MSR index #MSR_P6_IA32_PLATFORM_ID
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+UINT32  Reserved1:32;
+UINT32  Reserved2:18;
+///
+/// [Bits 52:50] Platform Id (R) Contains information concerning the
+/// intended platform for the processor.
+///
+///  52 51 50
+///   0  0  0  Processor Flag 0.
+///   0  0  1  Processor Flag 1
+///   0  1  0  Processor Flag 2
+///   0  1  1  Processor Flag 3
+///   1  0  0  Processor Flag 4
+///   1  0  1  Processor Flag 5
+///   1  1  0  Processor Flag 6
+///   1  1  1  Processor Flag 7
+///
+UINT32  PlatformId:3;
+///
+/// [Bits 56:53] L2 Cache Latency Read.
+///
+UINT32  L2CacheLatencyRead:4;
+UINT32  Reserved3:3;
+///
+/// [Bit 60] Clock Frequency Ratio Read.
+///
+UINT32  ClockFrequencyRatioRead:1;
+UINT32  Reserved4:3;
+  } Bits;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_P6_IA32_PLATFORM_ID_REGISTER;
+
+
+/**
+  Section 10.4.4, "Local APIC Status and Location.".
+
+  @param  ECX  MSR_P6_APIC_BASE (0x001B)
+  @param  EAX  Lower 32-bits of MSR value.
+   Described by the type MSR_P6_APIC_BASE_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+   Described by the type MSR_P6_APIC_BASE_REGISTER

[edk2] [Patch v2 18/21] UefiCpuPkg/Include: Add Pentium M MSR include file

[Michael Kinney]

Add Pentium M MSRs from:
Intel(R) 64 and IA-32 Architectures Software Developer's
Manual, Volume 3, December 2015, Chapter 35
Model-Specific-Registers (MSR), Section 35-18.

Cc: Jeff Fan 
Cc: Jiewen Yao 
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Michael Kinney 
---
 UefiCpuPkg/Include/Register/Msr/PentiumMMsr.h | 643 ++
 1 file changed, 643 insertions(+)
 create mode 100644 UefiCpuPkg/Include/Register/Msr/PentiumMMsr.h

diff --git a/UefiCpuPkg/Include/Register/Msr/PentiumMMsr.h 
b/UefiCpuPkg/Include/Register/Msr/PentiumMMsr.h
new file mode 100644
index 000..324fc9b
--- /dev/null
+++ b/UefiCpuPkg/Include/Register/Msr/PentiumMMsr.h
@@ -0,0 +1,643 @@
+/** @file
+  MSR Definitions for Pentium M Processors.
+
+  Provides defines for Machine Specific Registers(MSR) indexes. Data structures
+  are provided for MSRs that contain one or more bit fields.  If the MSR value
+  returned is a single 32-bit or 64-bit value, then a data structure is not
+  provided for that MSR.
+
+  Copyright (c) 2016, Intel Corporation. All rights reserved.
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD 
License
+  which accompanies this distribution.  The full text of the license may be 
found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+  @par Specification Reference:
+  Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,
+  December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-18.
+
+**/
+
+#ifndef __PENTIUM_M_MSR_H__
+#define __PENTIUM_M_MSR_H__
+
+#include 
+
+/**
+  See Section 35.20, "MSRs in Pentium Processors.".
+
+  @param  ECX  MSR_PENTIUM_M_P5_MC_ADDR (0x)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  Example usage
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_PENTIUM_M_P5_MC_ADDR);
+  AsmWriteMsr64 (MSR_PENTIUM_M_P5_MC_ADDR, Msr);
+  @endcode
+**/
+#define MSR_PENTIUM_M_P5_MC_ADDR 0x
+
+
+/**
+  See Section 35.20, "MSRs in Pentium Processors.".
+
+  @param  ECX  MSR_PENTIUM_M_P5_MC_TYPE (0x0001)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  Example usage
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_PENTIUM_M_P5_MC_TYPE);
+  AsmWriteMsr64 (MSR_PENTIUM_M_P5_MC_TYPE, Msr);
+  @endcode
+**/
+#define MSR_PENTIUM_M_P5_MC_TYPE 0x0001
+
+
+/**
+  Processor Hard Power-On Configuration (R/W) Enables and disables processor
+  features. (R) Indicates current processor configuration.
+
+  @param  ECX  MSR_PENTIUM_M_EBL_CR_POWERON (0x002A)
+  @param  EAX  Lower 32-bits of MSR value.
+   Described by the type MSR_PENTIUM_M_EBL_CR_POWERON_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+   Described by the type MSR_PENTIUM_M_EBL_CR_POWERON_REGISTER.
+
+  Example usage
+  @code
+  MSR_PENTIUM_M_EBL_CR_POWERON_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_PENTIUM_M_EBL_CR_POWERON);
+  AsmWriteMsr64 (MSR_PENTIUM_M_EBL_CR_POWERON, Msr.Uint64);
+  @endcode
+**/
+#define MSR_PENTIUM_M_EBL_CR_POWERON 0x002A
+
+/**
+  MSR information returned for MSR index #MSR_PENTIUM_M_EBL_CR_POWERON
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+UINT32  Reserved1:1;
+///
+/// [Bit 1] Data Error Checking Enable (R) 0 = Disabled Always 0 on the
+/// Pentium M processor.
+///
+UINT32  DataErrorCheckingEnable:1;
+///
+/// [Bit 2] Response Error Checking Enable (R) 0 = Disabled Always 0 on
+/// the Pentium M processor.
+///
+UINT32  ResponseErrorCheckingEnable:1;
+///
+/// [Bit 3] MCERR# Drive Enable (R)  0 = Disabled Always 0 on the Pentium
+/// M processor.
+///
+UINT32  MCERR_DriveEnable:1;
+///
+/// [Bit 4] Address Parity Enable (R) 0 = Disabled Always 0 on the Pentium
+/// M processor.
+///
+UINT32  AddressParityEnable:1;
+UINT32  Reserved2:2;
+///
+/// [Bit 7] BINIT# Driver Enable (R) 1 = Enabled; 0 = Disabled Always 0 on
+/// the Pentium M processor.
+///
+UINT32  BINIT_DriverEnable:1;
+///
+/// [Bit 8] Output Tri-state Enabled (R/O) 1 = Enabled; 0 = Disabled.
+///
+UINT32  OutputTriStateEnable:1;
+///
+/// [Bit 9] Execute BIST (R/O) 1 = Enabled; 0 = Disabled.
+///
+UINT32  ExecuteBIST:1;
+///
+/// [Bit 10] MCERR# Observation Enabled (R/O) 1 = Enabled; 0 = Disabled
+/// Always 0 on the Pentium M processor.
+///
+UINT32  MCERR_ObservationEnabled:1;
+UINT32  Reserved3:1;
+///
+/// [Bit 12] BINIT# Observation Enabled (R/O) 1 = Enabled; 0 = Disabled
+/// Always 0 on the Pentium M processor.
+///
+UINT3

[edk2] [Patch v2 17/21] UefiCpuPkg/Include: Add Core Solo/Duo MSR include file

[Michael Kinney]

Add Core Solo/Duo MSRs from:
Intel(R) 64 and IA-32 Architectures Software Developer's
Manual, Volume 3, December 2015, Chapter 35
Model-Specific-Registers (MSR), Section 35-17.

Cc: Jeff Fan 
Cc: Jiewen Yao 
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Michael Kinney 
---
 UefiCpuPkg/Include/Register/Msr/CoreMsr.h | 1074 +
 1 file changed, 1074 insertions(+)
 create mode 100644 UefiCpuPkg/Include/Register/Msr/CoreMsr.h

diff --git a/UefiCpuPkg/Include/Register/Msr/CoreMsr.h 
b/UefiCpuPkg/Include/Register/Msr/CoreMsr.h
new file mode 100644
index 000..11956fb
--- /dev/null
+++ b/UefiCpuPkg/Include/Register/Msr/CoreMsr.h
@@ -0,0 +1,1074 @@
+/** @file
+  MSR Definitions for Intel Core Solo and Intel Core Duo Processors.
+
+  Provides defines for Machine Specific Registers(MSR) indexes. Data structures
+  are provided for MSRs that contain one or more bit fields.  If the MSR value
+  returned is a single 32-bit or 64-bit value, then a data structure is not
+  provided for that MSR.
+
+  Copyright (c) 2016, Intel Corporation. All rights reserved.
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD 
License
+  which accompanies this distribution.  The full text of the license may be 
found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+  @par Specification Reference:
+  Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,
+  December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-17.
+
+**/
+
+#ifndef __CORE_MSR_H__
+#define __CORE_MSR_H__
+
+#include 
+
+/**
+  Unique. See Section 35.20, "MSRs in Pentium Processors," and see Table 35-2.
+
+  @param  ECX  MSR_CORE_P5_MC_ADDR (0x)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  Example usage
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_CORE_P5_MC_ADDR);
+  AsmWriteMsr64 (MSR_CORE_P5_MC_ADDR, Msr);
+  @endcode
+**/
+#define MSR_CORE_P5_MC_ADDR  0x
+
+
+/**
+  Unique. See Section 35.20, "MSRs in Pentium Processors," and see Table 35-2.
+
+  @param  ECX  MSR_CORE_P5_MC_TYPE (0x0001)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  Example usage
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_CORE_P5_MC_TYPE);
+  AsmWriteMsr64 (MSR_CORE_P5_MC_TYPE, Msr);
+  @endcode
+**/
+#define MSR_CORE_P5_MC_TYPE  0x0001
+
+
+/**
+  Shared. Processor Hard Power-On Configuration (R/W) Enables and disables
+  processor features; (R) indicates current processor configuration.
+
+  @param  ECX  MSR_CORE_EBL_CR_POWERON (0x002A)
+  @param  EAX  Lower 32-bits of MSR value.
+   Described by the type MSR_CORE_EBL_CR_POWERON_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+   Described by the type MSR_CORE_EBL_CR_POWERON_REGISTER.
+
+  Example usage
+  @code
+  MSR_CORE_EBL_CR_POWERON_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_CORE_EBL_CR_POWERON);
+  AsmWriteMsr64 (MSR_CORE_EBL_CR_POWERON, Msr.Uint64);
+  @endcode
+**/
+#define MSR_CORE_EBL_CR_POWERON  0x002A
+
+/**
+  MSR information returned for MSR index #MSR_CORE_EBL_CR_POWERON
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+UINT32  Reserved1:1;
+///
+/// [Bit 1] Data Error Checking Enable (R/W) 1 = Enabled; 0 = Disabled
+/// Note: Not all processor implements R/W.
+///
+UINT32  DataErrorCheckingEnable:1;
+///
+/// [Bit 2] Response Error Checking Enable (R/W) 1 = Enabled; 0 = Disabled
+/// Note: Not all processor implements R/W.
+///
+UINT32  ResponseErrorCheckingEnable:1;
+///
+/// [Bit 3] MCERR# Drive Enable (R/W)  1 = Enabled; 0 = Disabled Note: Not
+/// all processor implements R/W.
+///
+UINT32  MCERR_DriveEnable:1;
+///
+/// [Bit 4] Address Parity Enable (R/W) 1 = Enabled; 0 = Disabled Note:
+/// Not all processor implements R/W.
+///
+UINT32  AddressParityEnable:1;
+UINT32  Reserved2:2;
+///
+/// [Bit 7] BINIT# Driver Enable (R/W) 1 = Enabled; 0 = Disabled Note: Not
+/// all processor implements R/W.
+///
+UINT32  BINIT_DriverEnable:1;
+///
+/// [Bit 8] Output Tri-state Enabled (R/O) 1 = Enabled; 0 = Disabled.
+///
+UINT32  OutputTriStateEnable:1;
+///
+/// [Bit 9] Execute BIST (R/O) 1 = Enabled; 0 = Disabled.
+///
+UINT32  ExecuteBIST:1;
+///
+/// [Bit 10] MCERR# Observation Enabled (R/O) 1 = Enabled; 0 = Disabled.
+///
+UINT32  MCERR_ObservationEnabled:1;
+UINT32  Reserved3:1;
+///
+/// [Bit 12] BINIT# Observation Enabled (R/O) 1 = Enabled; 0 = Disabled.
+///
+UINT32  BINIT_Ob

[edk2] [Patch v2 12/21] UefiCpuPkg/Include: Add Broadwell MSR include file

[Michael Kinney]

Add Broadwell MSRs from:
Intel(R) 64 and IA-32 Architectures Software Developer's
Manual, Volume 3, December 2015, Chapter 35
Model-Specific-Registers (MSR), Section 35-12.

Cc: Jeff Fan 
Cc: Jiewen Yao 
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Michael Kinney 
---
 UefiCpuPkg/Include/Register/Msr/BroadwellMsr.h | 265 +
 1 file changed, 265 insertions(+)
 create mode 100644 UefiCpuPkg/Include/Register/Msr/BroadwellMsr.h

diff --git a/UefiCpuPkg/Include/Register/Msr/BroadwellMsr.h 
b/UefiCpuPkg/Include/Register/Msr/BroadwellMsr.h
new file mode 100644
index 000..69c404e
--- /dev/null
+++ b/UefiCpuPkg/Include/Register/Msr/BroadwellMsr.h
@@ -0,0 +1,265 @@
+/** @file
+  MSR Definitions for Intel processors based on the Broadwell 
microarchitecture.
+
+  Provides defines for Machine Specific Registers(MSR) indexes. Data structures
+  are provided for MSRs that contain one or more bit fields.  If the MSR value
+  returned is a single 32-bit or 64-bit value, then a data structure is not
+  provided for that MSR.
+
+  Copyright (c) 2016, Intel Corporation. All rights reserved.
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD 
License
+  which accompanies this distribution.  The full text of the license may be 
found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+  @par Specification Reference:
+  Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,
+  December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-12.
+
+**/
+
+#ifndef __BROADWELL_MSR_H__
+#define __BROADWELL_MSR_H__
+
+#include 
+
+/**
+  Thread. See Table 35-2. See Section 18.4.2, "Global Counter Control
+  Facilities.".
+
+  @param  ECX  MSR_BROADWELL_IA32_PERF_GLOBAL_STAUS (0x038E)
+  @param  EAX  Lower 32-bits of MSR value.
+   Described by the type 
MSR_BROADWELL_IA32_PERF_GLOBAL_STAUS_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+   Described by the type 
MSR_BROADWELL_IA32_PERF_GLOBAL_STAUS_REGISTER.
+
+  Example usage
+  @code
+  MSR_BROADWELL_IA32_PERF_GLOBAL_STAUS_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_BROADWELL_IA32_PERF_GLOBAL_STAUS);
+  AsmWriteMsr64 (MSR_BROADWELL_IA32_PERF_GLOBAL_STAUS, Msr.Uint64);
+  @endcode
+**/
+#define MSR_BROADWELL_IA32_PERF_GLOBAL_STAUS 0x038E
+
+/**
+  MSR information returned for MSR index #MSR_BROADWELL_IA32_PERF_GLOBAL_STAUS
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+///
+/// [Bit 0] Ovf_PMC0.
+///
+UINT32  Ovf_PMC0:1;
+///
+/// [Bit 1] Ovf_PMC1.
+///
+UINT32  Ovf_PMC1:1;
+///
+/// [Bit 2] Ovf_PMC2.
+///
+UINT32  Ovf_PMC2:1;
+///
+/// [Bit 3] Ovf_PMC3.
+///
+UINT32  Ovf_PMC3:1;
+UINT32  Reserved1:28;
+///
+/// [Bit 32] Ovf_FixedCtr0.
+///
+UINT32  Ovf_FixedCtr0:1;
+///
+/// [Bit 33] Ovf_FixedCtr1.
+///
+UINT32  Ovf_FixedCtr1:1;
+///
+/// [Bit 34] Ovf_FixedCtr2.
+///
+UINT32  Ovf_FixedCtr2:1;
+UINT32  Reserved2:20;
+///
+/// [Bit 55] Trace_ToPA_PMI. See Section 36.2.4.2, "Table of Physical
+/// Addresses (ToPA).".
+///
+UINT32  Trace_ToPA_PMI:1;
+UINT32  Reserved3:5;
+///
+/// [Bit 61] Ovf_Uncore.
+///
+UINT32  Ovf_Uncore:1;
+///
+/// [Bit 62] Ovf_BufDSSAVE.
+///
+UINT32  OvfBuf:1;
+///
+/// [Bit 63] CondChgd.
+///
+UINT32  CondChgd:1;
+  } Bits;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_BROADWELL_IA32_PERF_GLOBAL_STAUS_REGISTER;
+
+
+/**
+  Core. C-State Configuration Control (R/W) Note: C-state values are processor
+  specific C-state code names, unrelated to MWAIT extension C-state parameters
+  or ACPI C-states. `See http://biosbits.org. `__.
+
+  @param  ECX  MSR_BROADWELL_PKG_CST_CONFIG_CONTROL (0x00E2)
+  @param  EAX  Lower 32-bits of MSR value.
+   Described by the type 
MSR_BROADWELL_PKG_CST_CONFIG_CONTROL_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+   Described by the type 
MSR_BROADWELL_PKG_CST_CONFIG_CONTROL_REGISTER.
+
+  Example usage
+  @code
+  MSR_BROADWELL_PKG_CST_CONFIG_CONTROL_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_BROADWELL_PKG_CST_CONFIG_CONTROL);
+  AsmWriteMsr64 (MSR_BROADWELL_PKG_CST_CONFIG_CONTROL, Msr.Uint64);
+  @endcode
+**/
+#define MSR_BROADWELL_PKG_CST_CONFIG_CONTROL 0x00E2
+
+/**
+  MSR information returned for MSR index #MSR_BROADWELL_PKG_CST_CONFIG_CONTROL
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+///
+/// [Bits 3:0] Package C-State Limit (R/W) Specifies the lowest
+/// processor-specific C-state code name (cons

[edk2] [Patch v2 09/21] UefiCpuPkg/Include: Add Ivy Bridge MSR include file

[Michael Kinney]

Add Ivy Bridge MSRs from:
Intel(R) 64 and IA-32 Architectures Software Developer's
Manual, Volume 3, December 2015, Chapter 35
Model-Specific-Registers (MSR), Section 35-9.

Cc: Jeff Fan 
Cc: Jiewen Yao 
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Michael Kinney 
---
 UefiCpuPkg/Include/Register/Msr/IvyBridgeMsr.h | 2830 
 1 file changed, 2830 insertions(+)
 create mode 100644 UefiCpuPkg/Include/Register/Msr/IvyBridgeMsr.h

diff --git a/UefiCpuPkg/Include/Register/Msr/IvyBridgeMsr.h 
b/UefiCpuPkg/Include/Register/Msr/IvyBridgeMsr.h
new file mode 100644
index 000..0b08c0a
--- /dev/null
+++ b/UefiCpuPkg/Include/Register/Msr/IvyBridgeMsr.h
@@ -0,0 +1,2830 @@
+/** @file
+  MSR Definitions for Intel processors based on the Ivy Bridge 
microarchitecture.
+
+  Provides defines for Machine Specific Registers(MSR) indexes. Data structures
+  are provided for MSRs that contain one or more bit fields.  If the MSR value
+  returned is a single 32-bit or 64-bit value, then a data structure is not
+  provided for that MSR.
+
+  Copyright (c) 2016, Intel Corporation. All rights reserved.
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD 
License
+  which accompanies this distribution.  The full text of the license may be 
found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+  @par Specification Reference:
+  Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,
+  December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-9.
+
+**/
+
+#ifndef __IVY_BRIDGE_MSR_H__
+#define __IVY_BRIDGE_MSR_H__
+
+#include 
+
+/**
+  Package. See http://biosbits.org.
+
+  @param  ECX  MSR_IVY_BRIDGE_PLATFORM_INFO (0x00CE)
+  @param  EAX  Lower 32-bits of MSR value.
+   Described by the type MSR_IVY_BRIDGE_PLATFORM_INFO_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+   Described by the type MSR_IVY_BRIDGE_PLATFORM_INFO_REGISTER.
+
+  Example usage
+  @code
+  MSR_IVY_BRIDGE_PLATFORM_INFO_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_PLATFORM_INFO);
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_PLATFORM_INFO, Msr.Uint64);
+  @endcode
+**/
+#define MSR_IVY_BRIDGE_PLATFORM_INFO 0x00CE
+
+/**
+  MSR information returned for MSR index #MSR_IVY_BRIDGE_PLATFORM_INFO
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+UINT32  Reserved1:8;
+///
+/// [Bits 15:8] Package. Maximum Non-Turbo Ratio (R/O)  The is the ratio
+/// of the frequency that invariant TSC runs at. Frequency = ratio * 100
+/// MHz.
+///
+UINT32  MaximumNonTurboRatio:8;
+UINT32  Reserved2:12;
+///
+/// [Bit 28] Package. Programmable Ratio Limit for Turbo Mode (R/O)  When
+/// set to 1, indicates that Programmable Ratio Limits for Turbo mode is
+/// enabled, and when set to 0, indicates Programmable Ratio Limits for
+/// Turbo mode is disabled.
+///
+UINT32  RatioLimit:1;
+///
+/// [Bit 29] Package. Programmable TDP Limit for Turbo Mode (R/O)  When
+/// set to 1, indicates that TDP Limits for Turbo mode are programmable,
+/// and when set to 0, indicates TDP Limit for Turbo mode is not
+/// programmable.
+///
+UINT32  TDPLimit:1;
+UINT32  Reserved3:2;
+///
+/// [Bit 32] Package. Low Power Mode Support (LPM) (R/O)  When set to 1,
+/// indicates that LPM is supported, and when set to 0, indicates LPM is
+/// not supported.
+///
+UINT32  LowPowerModeSupport:1;
+///
+/// [Bits 34:33] Package. Number of ConfigTDP Levels (R/O) 00: Only Base
+/// TDP level available. 01: One additional TDP level available. 02: Two
+/// additional TDP level available. 11: Reserved.
+///
+UINT32  ConfigTDPLevels:2;
+UINT32  Reserved4:5;
+///
+/// [Bits 47:40] Package. Maximum Efficiency Ratio (R/O)  The is the
+/// minimum ratio (maximum efficiency) that the processor can operates, in
+/// units of 100MHz.
+///
+UINT32  MaximumEfficiencyRatio:8;
+///
+/// [Bits 55:48] Package. Minimum Operating Ratio (R/O) Contains the
+/// minimum supported operating ratio in units of 100 MHz.
+///
+UINT32  MinimumOperatingRatio:8;
+UINT32  Reserved5:8;
+  } Bits;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_IVY_BRIDGE_PLATFORM_INFO_REGISTER;
+
+
+/**
+  Core. C-State Configuration Control (R/W)  Note: C-state values are
+  processor specific C-state code names, unrelated to MWAIT extension C-state
+  parameters or ACPI C-States. See http://biosbits.org.
+
+  @param  ECX  MSR_IVY_BRIDGE_PKG_CST_CONFIG_CONTROL (0x00E2)
+  @param  EAX  Lower 32-bits of MSR value.
+   Described by the type 

[edk2] [Patch v2 14/21] UefiCpuPkg/Include: Add Skylake MSR include file

[Michael Kinney]

Add Skylake MSRs from:
Intel(R) 64 and IA-32 Architectures Software Developer's
Manual, Volume 3, December 2015, Chapter 35
Model-Specific-Registers (MSR), Section 35-14.

Cc: Jeff Fan 
Cc: Jiewen Yao 
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Michael Kinney 
---
 UefiCpuPkg/Include/Register/Msr/SkylakeMsr.h | 1008 ++
 1 file changed, 1008 insertions(+)
 create mode 100644 UefiCpuPkg/Include/Register/Msr/SkylakeMsr.h

diff --git a/UefiCpuPkg/Include/Register/Msr/SkylakeMsr.h 
b/UefiCpuPkg/Include/Register/Msr/SkylakeMsr.h
new file mode 100644
index 000..34868f9
--- /dev/null
+++ b/UefiCpuPkg/Include/Register/Msr/SkylakeMsr.h
@@ -0,0 +1,1008 @@
+/** @file
+  MSR Definitions for Intel processors based on the Skylake microarchitecture.
+
+  Provides defines for Machine Specific Registers(MSR) indexes. Data structures
+  are provided for MSRs that contain one or more bit fields.  If the MSR value
+  returned is a single 32-bit or 64-bit value, then a data structure is not
+  provided for that MSR.
+
+  Copyright (c) 2016, Intel Corporation. All rights reserved.
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD 
License
+  which accompanies this distribution.  The full text of the license may be 
found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+  @par Specification Reference:
+  Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,
+  December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-14.
+
+**/
+
+#ifndef __SKYLAKE_MSR_H__
+#define __SKYLAKE_MSR_H__
+
+#include 
+
+/**
+  Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0,
+  RW if MSR_PLATFORM_INFO.[28] = 1.
+
+  @param  ECX  MSR_SKYLAKE_TURBO_RATIO_LIMIT (0x01AD)
+  @param  EAX  Lower 32-bits of MSR value.
+   Described by the type MSR_SKYLAKE_TURBO_RATIO_LIMIT_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+   Described by the type MSR_SKYLAKE_TURBO_RATIO_LIMIT_REGISTER.
+
+  Example usage
+  @code
+  MSR_SKYLAKE_TURBO_RATIO_LIMIT_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_TURBO_RATIO_LIMIT);
+  @endcode
+**/
+#define MSR_SKYLAKE_TURBO_RATIO_LIMIT0x01AD
+
+/**
+  MSR information returned for MSR index #MSR_SKYLAKE_TURBO_RATIO_LIMIT
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+///
+/// [Bits 7:0] Package. Maximum Ratio Limit for 1C Maximum turbo ratio
+/// limit of 1 core active.
+///
+UINT32  Maximum1C:8;
+///
+/// [Bits 15:8] Package. Maximum Ratio Limit for 2C Maximum turbo ratio
+/// limit of 2 core active.
+///
+UINT32  Maximum2C:8;
+///
+/// [Bits 23:16] Package. Maximum Ratio Limit for 3C Maximum turbo ratio
+/// limit of 3 core active.
+///
+UINT32  Maximum3C:8;
+///
+/// [Bits 31:24] Package. Maximum Ratio Limit for 4C Maximum turbo ratio
+/// limit of 4 core active.
+///
+UINT32  Maximum4C:8;
+UINT32  Reserved:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_SKYLAKE_TURBO_RATIO_LIMIT_REGISTER;
+
+
+/**
+  Thread. Last Branch Record Stack TOS (R/W)  Contains an index (bits 0-4)
+  that points to the MSR containing the most recent branch record.
+
+  @param  ECX  MSR_SKYLAKE_LASTBRANCH_TOS (0x01C9)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  Example usage
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_SKYLAKE_LASTBRANCH_TOS);
+  AsmWriteMsr64 (MSR_SKYLAKE_LASTBRANCH_TOS, Msr);
+  @endcode
+**/
+#define MSR_SKYLAKE_LASTBRANCH_TOS   0x01C9
+
+
+/**
+  Package. Lower 64 Bit OwnerEpoch Component of SGX Key (RO). Low 64 bits of
+  an 128-bit external entropy value for key derivation of an enclave.
+
+  @param  ECX  MSR_SKYLAKE_SGXOWNER0 (0x0300)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  Example usage
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_SKYLAKE_SGXOWNER0);
+  @endcode
+**/
+#define MSR_SKYLAKE_SGXOWNER00x0300
+
+
+/**
+  Package. Upper 64 Bit OwnerEpoch Component of SGX Key (RO). Upper 64 bits of
+  an 128-bit external entropy value for key derivation of an enclave.
+
+  @param  ECX  MSR_SKYLAKE_SGXOWNER1 (0x0301)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  Example usage
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_SKYLAKE_SGXOWNER1);
+  @endcode
+**/
+#define MSR_SKYLAKE_SGXOWNER10x0301
+
+
+/**
+  See Table 35-2. See Section 18.2.2.3, "Full-Width

[edk2] [Patch v2 10/21] UefiCpuPkg/Include: Add Haswell MSR include file

[Michael Kinney]

Add Haswell MSRs from:
Intel(R) 64 and IA-32 Architectures Software Developer's
Manual, Volume 3, December 2015, Chapter 35
Model-Specific-Registers (MSR), Section 35-10.

Cc: Jeff Fan 
Cc: Jiewen Yao 
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Michael Kinney 
---
 UefiCpuPkg/Include/Register/Msr/HaswellMsr.h | 2575 ++
 1 file changed, 2575 insertions(+)
 create mode 100644 UefiCpuPkg/Include/Register/Msr/HaswellMsr.h

diff --git a/UefiCpuPkg/Include/Register/Msr/HaswellMsr.h 
b/UefiCpuPkg/Include/Register/Msr/HaswellMsr.h
new file mode 100644
index 000..78915ec
--- /dev/null
+++ b/UefiCpuPkg/Include/Register/Msr/HaswellMsr.h
@@ -0,0 +1,2575 @@
+/** @file
+  MSR Definitions for Intel processors based on the Haswell microarchitecture.
+
+  Provides defines for Machine Specific Registers(MSR) indexes. Data structures
+  are provided for MSRs that contain one or more bit fields.  If the MSR value
+  returned is a single 32-bit or 64-bit value, then a data structure is not
+  provided for that MSR.
+
+  Copyright (c) 2016, Intel Corporation. All rights reserved.
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD 
License
+  which accompanies this distribution.  The full text of the license may be 
found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+  @par Specification Reference:
+  Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,
+  December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-10.
+
+**/
+
+#ifndef __HASWELL_MSR_H__
+#define __HASWELL_MSR_H__
+
+#include 
+
+/**
+  Package.
+
+  @param  ECX  MSR_HASWELL_PLATFORM_INFO (0x00CE)
+  @param  EAX  Lower 32-bits of MSR value.
+   Described by the type MSR_HASWELL_PLATFORM_INFO_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+   Described by the type MSR_HASWELL_PLATFORM_INFO_REGISTER.
+
+  Example usage
+  @code
+  MSR_HASWELL_PLATFORM_INFO_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_PLATFORM_INFO);
+  AsmWriteMsr64 (MSR_HASWELL_PLATFORM_INFO, Msr.Uint64);
+  @endcode
+**/
+#define MSR_HASWELL_PLATFORM_INFO0x00CE
+
+/**
+  MSR information returned for MSR index #MSR_HASWELL_PLATFORM_INFO
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+UINT32  Reserved1:8;
+///
+/// [Bits 15:8] Package. Maximum Non-Turbo Ratio (R/O)  The is the ratio
+/// of the frequency that invariant TSC runs at. Frequency = ratio * 100
+/// MHz.
+///
+UINT32  MaximumNonTurboRatio:8;
+UINT32  Reserved2:12;
+///
+/// [Bit 28] Package. Programmable Ratio Limit for Turbo Mode (R/O)  When
+/// set to 1, indicates that Programmable Ratio Limits for Turbo mode is
+/// enabled, and when set to 0, indicates Programmable Ratio Limits for
+/// Turbo mode is disabled.
+///
+UINT32  RatioLimit:1;
+///
+/// [Bit 29] Package. Programmable TDP Limit for Turbo Mode (R/O)  When
+/// set to 1, indicates that TDP Limits for Turbo mode are programmable,
+/// and when set to 0, indicates TDP Limit for Turbo mode is not
+/// programmable.
+///
+UINT32  TDPLimit:1;
+UINT32  Reserved3:2;
+///
+/// [Bit 32] Package. Low Power Mode Support (LPM) (R/O)  When set to 1,
+/// indicates that LPM is supported, and when set to 0, indicates LPM is
+/// not supported.
+///
+UINT32  LowPowerModeSupport:1;
+///
+/// [Bits 34:33] Package. Number of ConfigTDP Levels (R/O) 00: Only Base
+/// TDP level available. 01: One additional TDP level available. 02: Two
+/// additional TDP level available. 11: Reserved.
+///
+UINT32  ConfigTDPLevels:2;
+UINT32  Reserved4:5;
+///
+/// [Bits 47:40] Package. Maximum Efficiency Ratio (R/O)  The is the
+/// minimum ratio (maximum efficiency) that the processor can operates, in
+/// units of 100MHz.
+///
+UINT32  MaximumEfficiencyRatio:8;
+///
+/// [Bits 55:48] Package. Minimum Operating Ratio (R/O) Contains the
+/// minimum supported operating ratio in units of 100 MHz.
+///
+UINT32  MinimumOperatingRatio:8;
+UINT32  Reserved5:8;
+  } Bits;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_HASWELL_PLATFORM_INFO_REGISTER;
+
+
+/**
+  THREAD. Performance Event Select for Counter n (R/W) Supports all fields
+  described inTable 35-2 and the fields below.
+
+  @param  ECX  MSR_HASWELL_IA32_PERFEVTSELn
+  @param  EAX  Lower 32-bits of MSR value.
+   Described by the type MSR_HASWELL_IA32_PERFEVTSEL_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+   Described by the type MSR_HASWELL_IA32_PERFEVTSEL_REGISTER.
+
+  Example usa

[edk2] [Patch v2 16/21] UefiCpuPkg/Include: Add Pentium 4 MSR include file

[Michael Kinney]

Add Pentium 4 MSRs from:
Intel(R) 64 and IA-32 Architectures Software Developer's
Manual, Volume 3, December 2015, Chapter 35
Model-Specific-Registers (MSR), Section 35-16.

Cc: Jeff Fan 
Cc: Jiewen Yao 
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Michael Kinney 
---
 UefiCpuPkg/Include/Register/Msr/Pentium4Msr.h | 2550 +
 1 file changed, 2550 insertions(+)
 create mode 100644 UefiCpuPkg/Include/Register/Msr/Pentium4Msr.h

diff --git a/UefiCpuPkg/Include/Register/Msr/Pentium4Msr.h 
b/UefiCpuPkg/Include/Register/Msr/Pentium4Msr.h
new file mode 100644
index 000..caeb5bb
--- /dev/null
+++ b/UefiCpuPkg/Include/Register/Msr/Pentium4Msr.h
@@ -0,0 +1,2550 @@
+/** @file
+  MSR Definitions for Pentium(R) 4 Processors.
+
+  Provides defines for Machine Specific Registers(MSR) indexes. Data structures
+  are provided for MSRs that contain one or more bit fields.  If the MSR value
+  returned is a single 32-bit or 64-bit value, then a data structure is not
+  provided for that MSR.
+
+  Copyright (c) 2016, Intel Corporation. All rights reserved.
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD 
License
+  which accompanies this distribution.  The full text of the license may be 
found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+  @par Specification Reference:
+  Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,
+  December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-16.
+
+**/
+
+#ifndef __PENTIUM_4_MSR_H__
+#define __PENTIUM_4_MSR_H__
+
+#include 
+
+/**
+  3, 4, 6. Shared. See Section 8.10.5, "Monitor/Mwait Address Range
+  Determination.".
+
+  @param  ECX  MSR_PENTIUM_4_IA32_MONITOR_FILTER_LINE_SIZE (0x0006)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  Example usage
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_PENTIUM_4_IA32_MONITOR_FILTER_LINE_SIZE);
+  AsmWriteMsr64 (MSR_PENTIUM_4_IA32_MONITOR_FILTER_LINE_SIZE, Msr);
+  @endcode
+**/
+#define MSR_PENTIUM_4_IA32_MONITOR_FILTER_LINE_SIZE 0x0006
+
+
+/**
+  0, 1, 2, 3, 4, 6. Shared. Processor Hard Power-On Configuration (R/W)
+  Enables and disables processor features; (R) indicates current processor
+  configuration.
+
+  @param  ECX  MSR_PENTIUM_4_EBC_HARD_POWERON (0x002A)
+  @param  EAX  Lower 32-bits of MSR value.
+   Described by the type MSR_PENTIUM_4_EBC_HARD_POWERON_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+   Described by the type MSR_PENTIUM_4_EBC_HARD_POWERON_REGISTER.
+
+  Example usage
+  @code
+  MSR_PENTIUM_4_EBC_HARD_POWERON_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_PENTIUM_4_EBC_HARD_POWERON);
+  AsmWriteMsr64 (MSR_PENTIUM_4_EBC_HARD_POWERON, Msr.Uint64);
+  @endcode
+**/
+#define MSR_PENTIUM_4_EBC_HARD_POWERON   0x002A
+
+/**
+  MSR information returned for MSR index #MSR_PENTIUM_4_EBC_HARD_POWERON
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+///
+/// [Bit 0] Output Tri-state Enabled (R) Indicates whether tri-state
+/// output is enabled (1) or disabled (0) as set by the strapping of SMI#.
+/// The value in this bit is written on the deassertion of RESET#; the bit
+/// is set to 1 when the address bus signal is asserted.
+///
+UINT32  OutputTriStateEnabled:1;
+///
+/// [Bit 1] Execute BIST (R)  Indicates whether the execution of the BIST
+/// is enabled (1) or disabled (0) as set by the strapping of INIT#. The
+/// value in this bit is written on the deassertion of RESET#; the bit is
+/// set to 1 when the address bus signal is asserted.
+///
+UINT32  ExecuteBIST:1;
+///
+/// [Bit 2] In Order Queue Depth (R) Indicates whether the in order queue
+/// depth for the system bus is 1 (1) or up to 12 (0) as set by the
+/// strapping of A7#. The value in this bit is written on the deassertion
+/// of RESET#; the bit is set to 1 when the address bus signal is asserted.
+///
+UINT32  InOrderQueueDepth:1;
+///
+/// [Bit 3] MCERR# Observation Disabled (R) Indicates whether MCERR#
+/// observation is enabled (0) or disabled (1) as determined by the
+/// strapping of A9#. The value in this bit is written on the deassertion
+/// of RESET#; the bit is set to 1 when the address bus signal is asserted.
+///
+UINT32  MCERR_ObservationDisabled:1;
+///
+/// [Bit 4] BINIT# Observation Enabled (R) Indicates whether BINIT#
+/// observation is enabled (0) or disabled (1) as determined by the
+/// strapping of A10#. The value in this bit is written on the deassertion
+/// of RESET#; the bit is set to 1 when the address bus signal is asserted.
+///
+

[edk2] [Patch v2 13/21] UefiCpuPkg/Include: Add Xeon Processor D MSR include file

[Michael Kinney]

Add Xeon Processor D MSRs from:
Intel(R) 64 and IA-32 Architectures Software Developer's
Manual, Volume 3, December 2015, Chapter 35
Model-Specific-Registers (MSR), Section 35-13.

Cc: Jeff Fan 
Cc: Jiewen Yao 
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Michael Kinney 
---
 UefiCpuPkg/Include/Register/Msr/XeonDMsr.h | 1430 
 1 file changed, 1430 insertions(+)
 create mode 100644 UefiCpuPkg/Include/Register/Msr/XeonDMsr.h

diff --git a/UefiCpuPkg/Include/Register/Msr/XeonDMsr.h 
b/UefiCpuPkg/Include/Register/Msr/XeonDMsr.h
new file mode 100644
index 000..43a35f2
--- /dev/null
+++ b/UefiCpuPkg/Include/Register/Msr/XeonDMsr.h
@@ -0,0 +1,1430 @@
+/** @file
+  MSR Definitions for Intel(R) Xeon(R) Processor D product Family.
+
+  Provides defines for Machine Specific Registers(MSR) indexes. Data structures
+  are provided for MSRs that contain one or more bit fields.  If the MSR value
+  returned is a single 32-bit or 64-bit value, then a data structure is not
+  provided for that MSR.
+
+  Copyright (c) 2016, Intel Corporation. All rights reserved.
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD 
License
+  which accompanies this distribution.  The full text of the license may be 
found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+  @par Specification Reference:
+  Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,
+  December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-13.
+
+**/
+
+#ifndef __XEON_D_MSR_H__
+#define __XEON_D_MSR_H__
+
+#include 
+
+/**
+  Package. Protected Processor Inventory Number Enable Control (R/W).
+
+  @param  ECX  MSR_XEON_D_PPIN_CTL (0x004E)
+  @param  EAX  Lower 32-bits of MSR value.
+   Described by the type MSR_XEON_D_PPIN_CTL_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+   Described by the type MSR_XEON_D_PPIN_CTL_REGISTER.
+
+  Example usage
+  @code
+  MSR_XEON_D_PPIN_CTL_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_PPIN_CTL);
+  AsmWriteMsr64 (MSR_XEON_D_PPIN_CTL, Msr.Uint64);
+  @endcode
+**/
+#define MSR_XEON_D_PPIN_CTL  0x004E
+
+/**
+  MSR information returned for MSR index #MSR_XEON_D_PPIN_CTL
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+///
+/// [Bit 0] LockOut (R/WO) See Table 35-21.
+///
+UINT32  LockOut:1;
+///
+/// [Bit 1] Enable_PPIN (R/W) See Table 35-21.
+///
+UINT32  Enable_PPIN:1;
+UINT32  Reserved1:30;
+UINT32  Reserved2:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_XEON_D_PPIN_CTL_REGISTER;
+
+
+/**
+  Package. Protected Processor Inventory Number (R/O). Protected Processor
+  Inventory Number (R/O) See Table 35-21.
+
+  @param  ECX  MSR_XEON_D_PPIN (0x004F)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  Example usage
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_XEON_D_PPIN);
+  @endcode
+**/
+#define MSR_XEON_D_PPIN  0x004F
+
+
+/**
+  Package. See http://biosbits.org.
+
+  @param  ECX  MSR_XEON_D_PLATFORM_INFO (0x00CE)
+  @param  EAX  Lower 32-bits of MSR value.
+   Described by the type MSR_XEON_D_PLATFORM_INFO_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+   Described by the type MSR_XEON_D_PLATFORM_INFO_REGISTER.
+
+  Example usage
+  @code
+  MSR_XEON_D_PLATFORM_INFO_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_PLATFORM_INFO);
+  AsmWriteMsr64 (MSR_XEON_D_PLATFORM_INFO, Msr.Uint64);
+  @endcode
+**/
+#define MSR_XEON_D_PLATFORM_INFO 0x00CE
+
+/**
+  MSR information returned for MSR index #MSR_XEON_D_PLATFORM_INFO
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+UINT32  Reserved1:8;
+///
+/// [Bits 15:8] Package. Maximum Non-Turbo Ratio (R/O) See Table 35-21.
+///
+UINT32  MaximumNonTurboRatio:8;
+UINT32  Reserved2:7;
+///
+/// [Bit 23] Package. PPIN_CAP (R/O) See Table 35-21.
+///
+UINT32  PPIN_CAP:1;
+UINT32  Reserved3:4;
+///
+/// [Bit 28] Package. Programmable Ratio Limit for Turbo Mode (R/O) See
+/// Table 35-21.
+///
+UINT32  RatioLimit:1;
+///
+/// [Bit 29] Package. Programmable TDP Limit for Turbo Mode (R/O) See
+/// Table 35-21.
+///
+UINT32  TDPLimit:1;
+///
+/// [Bit 30] Package. Programmable TJ OFFSET (R/O) See Table 35-21.
+///
+UINT32  TJOFFSET:1;
+UINT32  Reserved4:1;
+UINT32  Reserved5:8;
+///
+/// [Bits 47:40] Package. Maximum Efficiency Rat

Re: [edk2] [Patch 2/6] CryptoPkg: Add OpensslTlsLib module to enable 'openssl\ssl'

[James Bottomley]

On Fri, 2016-03-11 at 17:53 +, David Woodhouse wrote:
> On Fri, 2016-03-11 at 09:45 -0800, James Bottomley wrote:
> > 
> > > Did you *really* enable the building of openssl-1.0.2x/ssl/*.c in
> > > the
> > > above builds? Or are you talking about something different?
> > 
> > No, and since I'm not using it, separating it is fine with me.
> 
> And here's where I came in... is there any need for it to be
> separate?
> 
> If the objects corresponding to ssl/*.c are present in the library
> archive, doesn't that just mean that they'll get pulled in if they're
> *referenced*, and not if they're not? So why separate it out into
> OpensslTlsLib at all?

OK, I promise to wait until un jetlagged before answering next time. 
 However, my answer is no, combined is fine ... it's a libaray.

James



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[edk2] EDK2 Staging Repository 2nd Draft

[Mangefeste, Tony]

After collecting numerous feedback, here's a clean 2nd proposal for review.  
* Message format clean
* Approval process updates for stanging -> EDK2 trunk
* The intention of the staging branch is _not_ to work on features that grow to 
unreasonable sizes.  It is to manage features in an isolated environment that 
requires collaboration and testing by the community.  The stewards will ensure 
that any features that are developed, tested within the staging area are 
managed closely, and prevent unmanageable merges.
* Other minor fixes, changes...

Let's drive for closure on this by Tuesday, March 15, 2016.  If anyone else 
speaks up and needs more time, please speak up, right away.



=
edk2-staging Proposal V2
=

Problem statement
=
Need place on tianocore.org where new features that are not ready for product 
integration can be checked in for evaluation by the EDK II community prior to 
adding to the edk2 trunk.  This serves several purposes:

* Encourage source code to be shared earlier in the development process
* Allow source code to be shared that does not yet meet all edk2 required 
quality criteria
* Allow source code to be shared so the EDK II community can help finish and 
validate new features
* Provide a location to hold new features until they are deemed ready for 
product integration
* Provide a location to hold new features until there is a natural point in 
edk2 release cycle to fully validate the new feature.
* Not intended to be used for bug fixes.
* Not intended to be used for small, simple, or low risk features.

Proposal

1) Create a new repo called edk2-staging
a) edk2-staging is a fork of edk
b) edk2-staging/master tracks edk2/master

2) All edk2-staging discussions use the existing edk2-devel mailing list for 
design/patch/test.
Use the following style for discussion of a specific feature branch in 
edk2-staging repo.

[staging/branch]: Subject

3) All commits to edk2-staging must follow same edk2 rules (e.g. Tiano 
Contributor's Agreement)

4) Process to add a new feature to edk2-staging
a) Request to create a new edk2-staging feature branch sent to 
edk2-devel
Request should include feature summary, owners, timeline, and quality 
criteria to add to edk2.
If Request is a platform or package specific feature, pre-approval for 
edk2 trunk promotion may be requested here.
b) Branch request and branch name must be approved by stewards
c) Branch maintainer creates edk2-staging feature branch
d) Branch maintainer creates Readme.MD in root of feature branch with 
summary, owners, timeline, links to related materials.
e) Branch maintainer is responsible for making sure feature is 
frequently synced to edk2/master

 NOTE: Feature branch may initially use a stable edk2 tag.  As feature 
stabilizes, syncs to edk2/master can begin.

5) Process to update sources in feature branch
a) Patch email send to edk2-devel
b) Commit message subject format

[staging/branch PATCH]: Package/Module: Subject

c) Use same edk2-devel review process 
d) If pass review, then maintainer commits change to edk2-staging 
feature branch

NOTE: win32 binaries are not automatically generated if a feature 
branch includes BaseTools source changes.

6) Process to promote an edk2-staging branch to edk2 trunk
a) Request sent to edk2-devel that describes the feature, design, 
testing, etc.
b) Stewards evaluate request and determine if the feature meets edk2 
criteria.
c) If approved, use edk2 patch review/commit process on edk2-devel 
mailing list
d) Remove feature branch from edk2-staging (maybe archived elsewhere?). 

7) Process to remove an edk2-staging branch
a) Stewards periodically review of feature branches in edk2-staging 
(once a quarter?)
b) If no activity for extended period of time and feature is no longer 
deemed a candidate for edk2 then stewards send email to edk2-devel to request 
deletion of feature branch.  
c) If no objections from EDK II community, then feature branch is 
deleted (maybe archived elsewhere?).

8) Process to evaluate a feature in edk2-staging
a) Clone edk2
b) Create local branch with optional platform packages
c) Build platform in local branch and verify it is stable
d) Clone edk2-staging/[branch name]
e) Create local branch with optional platform packages
f) Build platform in local branch and evaluate new feature



BRs,
Tony
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Re: [edk2] EDK2 Staging Repository 2nd Draft

[Jordan Justen]

On 2016-03-11 16:25:39, Mangefeste, Tony wrote:
> 
> 6) Process to promote an edk2-staging branch to edk2 trunk
> a) Request sent to edk2-devel that describes the feature, design, 
> testing, etc.
> b) Stewards evaluate request and determine if the feature meets edk2 
> criteria.
> c) If approved, use edk2 patch review/commit process on edk2-devel 
> mailing list
> d) Remove feature branch from edk2-staging (maybe archived 
> elsewhere?). 
> 
> 7) Process to remove an edk2-staging branch
> a) Stewards periodically review of feature branches in edk2-staging 
> (once a quarter?)
> b) If no activity for extended period of time and feature is no 
> longer deemed a candidate for edk2 then stewards send email to edk2-devel to 
> request deletion of feature branch.  
> c) If no objections from EDK II community, then feature branch is 
> deleted (maybe archived elsewhere?).

I recommend we move all committed and abandoned staging branches to:

https://github.com/tianocore/edk2-archive

Archiving the committed patchsets might not be useful though.

-Jordan
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Re: [edk2] EDK2 Staging Repository 2nd Draft

[Mangefeste, Tony]

That's a good idea.

-- Original message--
From: Justen, Jordan L
Date: Fri, Mar 11, 2016 5:34 PM
To: Mangefeste, Tony;edk2-devel@lists.01.org;
Cc:
Subject:Re: [edk2] EDK2 Staging Repository 2nd Draft

On 2016-03-11 16:25:39, Mangefeste, Tony wrote:
>
> 6) Process to promote an edk2-staging branch to edk2 trunk
> a) Request sent to edk2-devel that describes the feature, design, 
> testing, etc.
> b) Stewards evaluate request and determine if the feature meets edk2 
> criteria.
> c) If approved, use edk2 patch review/commit process on edk2-devel 
> mailing list
> d) Remove feature branch from edk2-staging (maybe archived 
> elsewhere?).
>
> 7) Process to remove an edk2-staging branch
> a) Stewards periodically review of feature branches in edk2-staging 
> (once a quarter?)
> b) If no activity for extended period of time and feature is no 
> longer deemed a candidate for edk2 then stewards send email to edk2-devel to 
> request deletion of feature branch.
> c) If no objections from EDK II community, then feature branch is 
> deleted (maybe archived elsewhere?).

I recommend we move all committed and abandoned staging branches to:

https://github.com/tianocore/edk2-archive

Archiving the committed patchsets might not be useful though.

-Jordan
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Re: [edk2] [Patch v2 00/21] UefiCpuPkg/Include: Add MSR include files

[Fan, Jeff]

Reviewed-by: Jeff Fan  for this serial of patches.

-Original Message-
From: Kinney, Michael D 
Sent: Saturday, March 12, 2016 8:09 AM
To: edk2-devel@lists.01.org
Cc: Fan, Jeff; Yao, Jiewen
Subject: [Patch v2 00/21] UefiCpuPkg/Include: Add MSR include files

Add include files for Architectural MSRs and family specific MSRs described in 
section 35.1 to 35.20 of the
Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3, 
December 2015, Chapter 35 Model-Specific-Registers (MSR).

New in V2 based on review feedback from Jeff Fan 
=
* Fix spelling errors in comments
* Remove KERNEL_GSBASE from all family specific .h files.  
  These are identical to KERNEL_GS_BASE in ArchitecturalMsr.h
* Remove IA32_TSC_AUX from XeonPhi.h.  
  It is identical to IA32_TSC_AUX in ArchitecturalMsr.h
* Move 5 MSR_BROADWELL_C17_PMON_BOX_STATUS and MSR_BROADWELL_C17_PMON_CRTn
  MSRs from BroadwellMsr.h to HaswellEMsr.h
* PentiumMMsr.h: Change field from Reserved to BTS in
  MSR_PENTIUM_M_IA32_MISC_ENABLE
* SandyBridgeMsr.h: Remove MSR_SANDY_BRIDGE_X2APIC
* Xeon5600Msr.h: Move bitfieds from MSR_XEON_5600_OFFCORE_RSP_1 to
  MSR_XEON_5600_TURBO_RATIO_LIMIT
* XeonDMsr.h: Change Reserved to BTS in MSR_XEON_D_IA32_L3_QOS_MASK_REGISTER

These files can also be pulled and reviewd from:

https://github.com/mdkinney/edk2/tree/Msr_V2

These includes files are not being used by any modules or libraries yet, so 
adding these .h files should not have any impact on any build.  

I have tested that these include files do not cause any build failures when 
used in UefiCPuPkg/Application/Cpuid.

These include files are being added so the defines and REGISTER structures can 
be used clean up IA32/X64 CPU modules and libraries that access MSRs.

Cc: Jeff Fan 
Cc: Jiewen Yao 
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Michael Kinney 

Michael Kinney (21):
  UefiCpuPkg/Include: Add Architectural MSR include file
  UefiCpuPkg/Include: Add Core 2 MSR include file
  UefiCpuPkg/Include: Add Atom MSR include file
  UefiCpuPkg/Include: Add Silvermont MSR include file
  UefiCpuPkg/Include: Add Nehalem MSR include file
  UefiCpuPkg/Include: Add Xeon 5600 MSR include file
  UefiCpuPkg/Include: Add Xeon E7 MSR include file
  UefiCpuPkg/Include: Add Sandy Bridge MSR include file
  UefiCpuPkg/Include: Add Ivy Bridge MSR include file
  UefiCpuPkg/Include: Add Haswell MSR include file
  UefiCpuPkg/Include: Add Haswell-E MSR include file
  UefiCpuPkg/Include: Add Broadwell MSR include file
  UefiCpuPkg/Include: Add Xeon Processor D MSR include file
  UefiCpuPkg/Include: Add Skylake MSR include file
  UefiCpuPkg/Include: Add Xeon Phi MSR include file
  UefiCpuPkg/Include: Add Pentium 4 MSR include file
  UefiCpuPkg/Include: Add Core Solo/Duo MSR include file
  UefiCpuPkg/Include: Add Pentium M MSR include file
  UefiCpuPkg/Include: Add P6 MSR include file
  UefiCpuPkg/Include: Add Pentium MSR include file
  UefiCpuPkg/Include: Add top level MSR include file

 UefiCpuPkg/Include/Register/ArchitecturalMsr.h   | 5801 +
 UefiCpuPkg/Include/Register/Msr.h|   48 +
 UefiCpuPkg/Include/Register/Msr/AtomMsr.h|  878 +++
 UefiCpuPkg/Include/Register/Msr/BroadwellMsr.h   |  265 +
 UefiCpuPkg/Include/Register/Msr/Core2Msr.h   | 1325 
 UefiCpuPkg/Include/Register/Msr/CoreMsr.h| 1074 
 UefiCpuPkg/Include/Register/Msr/HaswellEMsr.h| 5995 ++
 UefiCpuPkg/Include/Register/Msr/HaswellMsr.h | 2575 
 UefiCpuPkg/Include/Register/Msr/IvyBridgeMsr.h   | 2830 +
 UefiCpuPkg/Include/Register/Msr/NehalemMsr.h | 7196 ++
 UefiCpuPkg/Include/Register/Msr/P6Msr.h  | 1608 +
 UefiCpuPkg/Include/Register/Msr/Pentium4Msr.h| 2550 
 UefiCpuPkg/Include/Register/Msr/PentiumMMsr.h|  643 ++
 UefiCpuPkg/Include/Register/Msr/PentiumMsr.h |  121 +
 UefiCpuPkg/Include/Register/Msr/SandyBridgeMsr.h | 4703 ++  
UefiCpuPkg/Include/Register/Msr/SilvermontMsr.h  | 1468 +
 UefiCpuPkg/Include/Register/Msr/SkylakeMsr.h | 1008 +++
 UefiCpuPkg/Include/Register/Msr/Xeon5600Msr.h|  182 +
 UefiCpuPkg/Include/Register/Msr/XeonDMsr.h   | 1430 +
 UefiCpuPkg/Include/Register/Msr/XeonE7Msr.h  |  254 +
 UefiCpuPkg/Include/Register/Msr/XeonPhiMsr.h | 1426 +
 21 files changed, 43380 insertions(+)
 create mode 100644 UefiCpuPkg/Include/Register/ArchitecturalMsr.h
 create mode 100644 UefiCpuPkg/Include/Register/Msr.h  create mode 100644 
UefiCpuPkg/Include/Register/Msr/AtomMsr.h
 create mode 100644 UefiCpuPkg/Include/Register/Msr/BroadwellMsr.h
 create mode 100644 UefiCpuPkg/Include/Register/Msr/Core2Msr.h
 create mode 100644 UefiCpuPkg/Include/Register/Msr/CoreMsr.h
 create mode 100644 UefiCpuPkg/Include/Register/Msr/HaswellEMsr.h
 create mode 100644 UefiCpuPkg/Include/Register/Msr/HaswellMsr.h
 create mode 100644 UefiCpuPkg/Include/Re