Re: [edk2] [PATCH 1/1] EmbeddedPkg: Implement NorFlashLib

[Pankaj Bansal]

Hi Marcin,

The SPI flash Jedec id is not standardized across flashes.
The JEDEDC group only assigns first byte (Manufacturer ID) to different vendors.
Rest of the bytes are up to the Manufacturer to decide.
Therefore this info should be left to the SPI flash driver to parse.
It should not be stored in tabular form rather calculated based on JEDEDC data 
read.

Thanks & Regards,
Pankaj Bansal

-Original Message-
From: edk2-devel [mailto:edk2-devel-boun...@lists.01.org] On Behalf Of Marcin 
Wojtas
Sent: Tuesday, October 31, 2017 1:46 PM
To: Leif Lindholm 
Cc: Tian, Feng ; Hua Jing ; Ard 
Biesheuvel ; edk2-devel-01 
; Gao, Liming ; 
nad...@marvell.com; Kostya Porotchkin ; Neta Zur 
Hershkovits ; Kinney, Michael D 
Subject: Re: [edk2] [PATCH 1/1] EmbeddedPkg: Implement NorFlashLib

Hi Leif,

2017-10-31 8:58 GMT+01:00 Leif Lindholm :
> On Mon, Oct 30, 2017 at 09:30:25PM +0100, Marcin Wojtas wrote:
>> The SPI NOR flash drivers which base on ArmPlatformPkg's NorFlashDxe 
>> usually make use of static declarations of the flash instances with 
>> their type and parameters. As a result it implies hardcoding the 
>> exact way flash handling, not to mention the code does not look very 
>> nice. Much better solution would be obtaining the flash ID and hence 
>> its description in runtime.
>>
>> Because JEDEC compliant SPI NOR devices allow to obtain their ID with 
>> READ_ID command (0x9f), implement a NorFlashLib that gives access to 
>> the NOR flash data, such as name, page size, sector
>> (block) size and others, of more than 50 different models.
>> The new library user should pass an output array issuing READ_ID 
>> command to the GetNorFlashInfo () routine - if the match is found, an 
>> allocated (optionally for RT) pool with the flash description will be 
>> returned.
>>
>> Contributed-under: TianoCore Contribution Agreement 1.1
>> Signed-off-by: Marcin Wojtas 
>> ---
>>  EmbeddedPkg/EmbeddedPkg.dec |   1 +
>>  EmbeddedPkg/Include/Library/NorFlashInfoLib.h   |  84 
>>  EmbeddedPkg/Library/NorFlashInfoLib/NorFlashInfoLib.c   | 225 
>> 
>>  EmbeddedPkg/Library/NorFlashInfoLib/NorFlashInfoLib.inf |  34 +++
>>  4 files changed, 344 insertions(+)
>>
>> diff --git a/EmbeddedPkg/EmbeddedPkg.dec 
>> b/EmbeddedPkg/EmbeddedPkg.dec index 52482af..aa551ab 100644
>> --- a/EmbeddedPkg/EmbeddedPkg.dec
>> +++ b/EmbeddedPkg/EmbeddedPkg.dec
>> @@ -45,6 +45,7 @@
>>EblNetworkLib|Include/Library/EblNetworkLib.h
>>GdbSerialLib|Include/Library/GdbSerialLib.h
>>DebugAgentTimerLib|Include/Library/DebugAgentTimerLib.h
>> +  NorFlashInfoLib|Include/Library/NorFlashInfoLib.h
>>
>>DtPlatformDtbLoaderLib|Include/Library/DtPlatformDtbLoaderLib.h
>>
>> diff --git a/EmbeddedPkg/Include/Library/NorFlashInfoLib.h 
>> b/EmbeddedPkg/Include/Library/NorFlashInfoLib.h
>> new file mode 100644
>> index 000..ae0e45f
>> --- /dev/null
>> +++ b/EmbeddedPkg/Include/Library/NorFlashInfoLib.h
>> @@ -0,0 +1,84 @@
>> +/** @file
>> +*
>> +*  Copyright (c) 2017 Marvell International Ltd.
>> +*
>> +*  This program and the accompanying materials
>> +*  are licensed and made available under the terms and conditions of 
>> +the BSD License
>> +*  which accompanies this distribution.  The full text of the 
>> +license may be found at
>> +*  
>> +https://emea01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fop
>> +ensource.org%2Flicenses%2Fbsd-license.php&data=02%7C01%7Cpankaj.bans
>> +al%40nxp.com%7C753424b872b346c9c76f08d52037acfc%7C686ea1d3bc2b4c6fa9
>> +2cd99c5c301635%7C0%7C0%7C636450345874702676&sdata=cxqjBkGwxPBYUu%2Fh
>> +Rwn8xdMheRjl%2BXBokEA74oIyaTw%3D&reserved=0
>> +*
>> +*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" 
>> +BASIS,
>> +*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR 
>> IMPLIED.
>> +*
>> +**/
>> +
>> +#ifndef __NOR_FLASH_ID_LIB_H__
>> +#define __NOR_FLASH_ID_LIB_H__
>> +
>> +#include 
>> +
>> +#define NOR_FLASH_MAX_ID_LEN6
>> +
>> +typedef struct {
>> +  /* Device name */
>> +  UINT16 *Name;
>> +
>> +  /*
>> +   * JEDEC ID
>> +   */
>> +  UINT8  Id[NOR_FLASH_MAX_ID_LEN];
>> +  UINT8  IdLen;
>> +
>> +  UINT16 PageSize;
>> +
>> +  /*
>> +   * Below parameters can be referred as BlockSize
>> +   * and BlockCount, when treating the NorFlash as
>> +   * block device.
>> +   */
>> +  UINT32 SectorSize;
>> +  UINT32 SectorCount;
>> +
>> +  UINT16 Flags;
>> +#define NF_ERASE_4K  1 << 0  /* Use 4096B erase blocks and CMD_ERASE_4K 
>> */
>> +#define NF_WRITE_FSR 1 << 1  /* Use flag status register for write */
>> +#define NF_4B_ADDR   1 << 2  /* Use 4B addressing */
>
> I think these should keep a NOR_FLASH_ prefix, like the rest of the file.
>
>> +} NOR_FLASH_INFO;
>> +
>> +/**
>> +  Return a pool allocated copy of the NOR flash .
>> +
>> +  @param[in]   Id Pointer to an array with JEDEC ID 
>> obtained
>> +  from the NOR flash with READ_ID 
>>

Re: [edk2] [PATCH edk2-platforms v3 27/27] Silicon/SynQuacer: add description of EXIU to the device tree

[Leif Lindholm]

On Tue, Oct 31, 2017 at 10:52:18AM +, Ard Biesheuvel wrote:
> Add a DT node for the external interrupt unit (EXIU), which handles
> interrupts from GPIO lines. We need OS support for this for things
> like PHY interrupts and a 'wake' button.
> 
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Ard Biesheuvel 

Reviewed-by: Leif Lindholm 

> ---
>  Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi | 9 +
>  1 file changed, 9 insertions(+)
> 
> diff --git a/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi 
> b/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi
> index 0746b7853ebf..a19f88d10511 100644
> --- a/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi
> +++ b/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi
> @@ -523,4 +523,13 @@
>  clocks = <&clk_apb>;
>  base = <0>;
>  };
> +
> +exiu: exiu@510c {
> +compatible = "socionext,sc2a11-exiu";
> +reg = <0x0 0x510c 0x0 0x20>;
> +interrupt-controller;
> +interrupt-parent = <&gic>;
> +#interrupt-cells = <3>;
> +spi-base = <112>;
> +};
>  };
> -- 
> 2.11.0
> 
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Re: [edk2] [PATCH edk2-platforms v3 26/27] Silicon/SynQuacer: add description of GPIO block to device tree

[Leif Lindholm]

On Tue, Oct 31, 2017 at 10:52:17AM +, Ard Biesheuvel wrote:
> Add a description of the SoCs GPIO controller as well as a description
> of DIP switch block #3, which is wired to GPIOs 0 - 7, both on the
> evaluation board as well as the Developer Box.
> 
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Ard Biesheuvel 

Reviewed-by: Leif Lindholm 
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Re: [edk2] [PATCH edk2-platforms v3 24/27] Platform/Socionext: add support for Socionext Developer Box rev 0.1

[Leif Lindholm]

On Tue, Oct 31, 2017 at 10:52:15AM +, Ard Biesheuvel wrote:
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Ard Biesheuvel 

For itself:
Reviewed-by: Leif Lindholm 

However, this patch has an ordering dependency on the arm-tf binary
being added to edk2-non-osi.

/
Leif
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Re: [edk2] [PATCH edk2-platforms v3 22/27] Silicon/SynQuacer/AcpiTables: hide PCI domain #0

[Leif Lindholm]

On Tue, Oct 31, 2017 at 10:52:13AM +, Ard Biesheuvel wrote:
> The ACPI hack to support the broken Synopsys IP only works for endpoints,
> not for non-trivial topologies involving switches. Given that the Linaro
> developer board has a switch soldered on, there is really no way to do
> anything useful with it when booting via ACPI. On top of that, the ITS
> can only be enabled for a single RC.
> 
> So let's hide PCIe domain #0 entirely from the OS. We may be able to
> expose the USB and SATA ports at some point using another ungodly hack,
> but for now, this allows us to boot the board with unmodified installers
> and install onto NVME.
> 
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Ard Biesheuvel 

Reviewed-by: Leif Lindholm 
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Re: [edk2] [PATCH edk2-platforms v3 21/27] Platform/SynQuacerEvalBoard: add signed capsule update support

[Leif Lindholm]

On Tue, Oct 31, 2017 at 10:52:12AM +, Ard Biesheuvel wrote:
> Add all the boilerplate to make the SPI NOR image updateable using
> signed capsules and the FMP protocol.
> 
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Ard Biesheuvel 

Reviewed-by: Leif Lindholm 
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Re: [edk2] [PATCH edk2-platforms v3 17/27] Silicon/SynQuacer: implement PlatformFlashAccessLib

[Leif Lindholm]

On Tue, Oct 31, 2017 at 10:52:08AM +, Ard Biesheuvel wrote:
> In order to support capsule update, implement PlatformFlashAccessLib that
> exposes write access to the UEFI NOR partition.
> 
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Ard Biesheuvel 

You folded in the changes I asked for, so
Reviewed-by: Leif Lindholm 
was already implicit.

/
Leif
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Re: [edk2] [PATCH edk2-platforms v3 10/27] Platform/SynQuacerEvalBoard: add PCI support

[Leif Lindholm]

On Tue, Oct 31, 2017 at 10:52:01AM +, Ard Biesheuvel wrote:
> Wire up the various drivers and libraries for the SynQuacerEvalBoard
> platform. Also enable the usual PCI suspects: XHCI, SATA and NVME,
> and the various bus, partition and file system drivers that we need
> to make use of PCIe devices.
> 
> Given how PCI support enables USB support too, and taking the lack of
> a RNG on this SoC into account, let's enable the ChaosKey driver as
> well.
> 
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Ard Biesheuvel 

Reviewed-by: Leif Lindholm 

> ---
>  Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.dsc | 52 
> 
>  Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.fdf | 41 
> +++
>  2 files changed, 93 insertions(+)
> 
> diff --git a/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.dsc 
> b/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.dsc
> index 3dc8aa7461d6..519a078e15dc 100644
> --- a/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.dsc
> +++ b/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.dsc
> @@ -100,6 +100,7 @@ [LibraryClasses.common]
>DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf
>SortLib|MdeModulePkg/Library/UefiSortLib/UefiSortLib.inf
>UefiUsbLib|MdePkg/Library/UefiUsbLib/UefiUsbLib.inf
> +  UefiScsiLib|MdePkg/Library/UefiScsiLib/UefiScsiLib.inf
>  
># BDS Libraries
>
> UefiBootManagerLib|MdeModulePkg/Library/UefiBootManagerLib/UefiBootManagerLib.inf
> @@ -151,6 +152,12 @@ [LibraryClasses.common.DXE_DRIVER]
>
> SecurityManagementLib|MdeModulePkg/Library/DxeSecurityManagementLib/DxeSecurityManagementLib.inf
>PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.inf
>  
> +  #
> +  # PCI
> +  #
> +  
> PciSegmentLib|Silicon/Socionext/SynQuacer/Library/SynQuacerPciSegmentLib/SynQuacerPciSegmentLib.inf
> +  
> PciHostBridgeLib|Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLib.inf
> +
>  [LibraryClasses.common.UEFI_APPLICATION]
>PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.inf
>HiiLib|MdeModulePkg/Library/UefiHiiLib/UefiHiiLib.inf
> @@ -193,6 +200,7 @@ [PcdsFixedAtBuild.common]
>gSynQuacerTokenSpaceGuid.PcdDramInfoBase|0x2E00FFC0
>  
>gEmbeddedTokenSpaceGuid.PcdPrePiCpuMemorySize|40
> +  gEmbeddedTokenSpaceGuid.PcdPrePiCpuIoSize|24
>  
># 12x 2-core processor clusters
>gArmPlatformTokenSpaceGuid.PcdCoreCount|2
> @@ -430,3 +438,47 @@ [Components.common]
>NULL|MdeModulePkg/Library/BootManagerUiLib/BootManagerUiLib.inf
>
> NULL|MdeModulePkg/Library/BootMaintenanceManagerUiLib/BootMaintenanceManagerUiLib.inf
>}
> +
> +  #
> +  # PCI
> +  #
> +  
> Silicon/Socionext/SynQuacer/Drivers/SynQuacerPciCpuIo2Dxe/SynQuacerPciCpuIo2Dxe.inf
> +  MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf {
> +
> +gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x8010004F
> +  }
> +  MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
> +  MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf
> +  MdeModulePkg/Universal/EbcDxe/EbcDxe.inf
> +
> +  #
> +  # AHCI Support
> +  #
> +  MdeModulePkg/Bus/Pci/SataControllerDxe/SataControllerDxe.inf
> +  MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf
> +  MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf
> +  MdeModulePkg/Bus/Scsi/ScsiBusDxe/ScsiBusDxe.inf
> +  MdeModulePkg/Bus/Scsi/ScsiDiskDxe/ScsiDiskDxe.inf
> +
> +  #
> +  # USB
> +  #
> +  MdeModulePkg/Bus/Pci/UhciDxe/UhciDxe.inf
> +  MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf
> +  MdeModulePkg/Bus/Pci/XhciDxe/XhciDxe.inf
> +  MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf
> +  MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf
> +  MdeModulePkg/Bus/Usb/UsbKbDxe/UsbKbDxe.inf
> +
> +  #
> +  # FAT filesystem + GPT/MBR partitioning
> +  #
> +  MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf
> +  MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf
> +  MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf
> +  FatPkg/EnhancedFatDxe/Fat.inf
> +
> +  #
> +  # RNG
> +  #
> +  Silicon/Openmoko/ChaosKeyDxe/ChaosKeyDxe.inf
> diff --git a/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.fdf 
> b/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.fdf
> index f74e22c31aa5..838963eff612 100644
> --- a/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.fdf
> +++ b/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.fdf
> @@ -132,6 +132,47 @@ [FV.FvMain]
>INF MdeModulePkg/Universal/BdsDxe/BdsDxe.inf
>INF MdeModulePkg/Application/UiApp/UiApp.inf
>  
> +  #
> +  # PCI
> +  #
> +  INF 
> Silicon/Socionext/SynQuacer/Drivers/SynQuacerPciCpuIo2Dxe/SynQuacerPciCpuIo2Dxe.inf
> +  INF MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf
> +  INF MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
> +  INF MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf
> +  INF MdeModulePkg/Univer

Re: [edk2] [PATCH edk2-platforms v3 08/27] Silicon/SynQuacer: implement PciHostBridgeLib support

[Leif Lindholm]

n Tue, Oct 31, 2017 at 10:51:59AM +, Ard Biesheuvel wrote:
> Implement the glue library that exposes the PCIe root complexes to
> the generic PCI host bridge driver. Since that driver is the first
> one to access the PCI config space, put the low level init code for
> the RCs into this library's constructor.
> 
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Ard Biesheuvel 

Reviewed-by: Leif Lindholm 
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Re: [edk2] [PATCH edk2-platforms v3 06/27] Platform: add support for Socionext SynQuacer eval board

[Leif Lindholm]

On Tue, Oct 31, 2017 at 10:51:57AM +, Ard Biesheuvel wrote:
> This is a barebones port based on the .DSC/.FDF and ArmPlatformLib
> code provided by Socionext. It can boot into the UiApp menu screen
> or the UEFI Shell, but lacks support for any peripherals.
> 
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Ard Biesheuvel 

Reviewed-by: Leif Lindholm 
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Re: [edk2] [PATCH edk2-platforms v3 05/27] Silicon/SynQuacer: add MemoryInitPeiLib implementation

[Leif Lindholm]

On Tue, Oct 31, 2017 at 10:51:56AM +, Ard Biesheuvel wrote:
> Implement MemoryInitPeiLib based on the newly added DramInfo
> PPI, which retrieves the DRAM information from lower level
> firmware.
> 
> Note that the firmware volumes in SPI NOR are mapped with
> different attributes: the FV containing the PEI modules that
> may execute in place is mapped as uncached memory, given that
> it requires executable permissions. The FV containing the
> compressed DXE modules is mapped with device attributes for
> performance (!), and copied into DRAM by the platform PEIM
> once permanent memory is installed.
> 
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Ard Biesheuvel 

Reviewed-by: Leif Lindholm 

> ---
>  
> Silicon/Socionext/SynQuacer/Library/SynQuacerMemoryInitPeiLib/SynQuacerMemoryInitPeiLib.c
>| 186 
>  
> Silicon/Socionext/SynQuacer/Library/SynQuacerMemoryInitPeiLib/SynQuacerMemoryInitPeiLib.inf
>  |  67 +++
>  2 files changed, 253 insertions(+)
> 
> diff --git 
> a/Silicon/Socionext/SynQuacer/Library/SynQuacerMemoryInitPeiLib/SynQuacerMemoryInitPeiLib.c
>  
> b/Silicon/Socionext/SynQuacer/Library/SynQuacerMemoryInitPeiLib/SynQuacerMemoryInitPeiLib.c
> new file mode 100644
> index ..e9a266f0997a
> --- /dev/null
> +++ 
> b/Silicon/Socionext/SynQuacer/Library/SynQuacerMemoryInitPeiLib/SynQuacerMemoryInitPeiLib.c
> @@ -0,0 +1,186 @@
> +/** @file
> +*
> +*  Copyright (c) 2011-2015, ARM Limited. All rights reserved.
> +*  Copyright (c) 2017, Linaro, Ltd. All rights reserved.
> +*
> +*  This program and the accompanying materials
> +*  are licensed and made available under the terms and conditions of the BSD 
> License
> +*  which accompanies this distribution.  The full text of the license may be 
> found at
> +*  http://opensource.org/licenses/bsd-license.php
> +*
> +*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR 
> IMPLIED.
> +*
> +**/
> +
> +#include 
> +
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +
> +#include 
> +#include 
> +
> +#include 
> +
> +#define ARM_MEMORY_REGION(Base, Size) \
> +  { (Base), (Base), (Size), ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK }
> +
> +#define ARM_UNCACHED_REGION(Base, Size) \
> +  { (Base), (Base), (Size), ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED }
> +
> +#define ARM_DEVICE_REGION(Base, Size) \
> +  { (Base), (Base), (Size), ARM_MEMORY_REGION_ATTRIBUTE_DEVICE }
> +
> +VOID
> +BuildMemoryTypeInformationHob (
> +  VOID
> +  );
> +
> +STATIC CONST EFI_RESOURCE_ATTRIBUTE_TYPE mDramResourceAttributes =
> +  EFI_RESOURCE_ATTRIBUTE_PRESENT |
> +  EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
> +  EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |
> +  EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |
> +  EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE |
> +  EFI_RESOURCE_ATTRIBUTE_TESTED;
> +
> +STATIC CONST ARM_MEMORY_REGION_DESCRIPTOR mVirtualMemoryTable[] = {
> +  // Memory mapped SPI NOR flash
> +  // Mapped with device attributes for performance (!)
> +  ARM_DEVICE_REGION (FixedPcdGet64 (PcdFdBaseAddress),
> + FixedPcdGet32 (PcdFdSize)),
> +
> +  // Memory mapped SPI NOR flash - XIP region
> +  // Sub-region of the preceding one - supersede with normal-nc attributes
> +  ARM_UNCACHED_REGION (FixedPcdGet64 (PcdFvBaseAddress),
> +   FixedPcdGet32 (PcdFvSize)),
> +
> +  // SynQuacer OnChip peripherals
> +  ARM_DEVICE_REGION (SYNQUACER_PERIPHERALS_BASE,
> + SYNQUACER_PERIPHERALS_SZ),
> +
> +  // SynQuacer OnChip non-secure SRAM
> +  ARM_UNCACHED_REGION (SYNQUACER_NON_SECURE_SRAM_BASE,
> +   SYNQUACER_NON_SECURE_SRAM_SZ),
> +
> +  // SynQuacer GIC-500
> +  ARM_DEVICE_REGION (SYNQUACER_GIC500_DIST_BASE, SYNQUACER_GIC500_DIST_SIZE),
> +  ARM_DEVICE_REGION (SYNQUACER_GIC500_RDIST_BASE, 
> SYNQUACER_GIC500_RDIST_SIZE),
> +
> +  // SynQuacer eMMC(SDH30)
> +  ARM_DEVICE_REGION (SYNQUACER_EMMC_BASE, SYNQUACER_EMMC_BASE_SZ),
> +
> +  // SynQuacer EEPROM - could point to NOR flash as well
> +  ARM_DEVICE_REGION (FixedPcdGet32 (PcdNetsecEepromBase),
> + SYNQUACER_EEPROM_BASE_SZ),
> +
> +  // SynQuacer NETSEC
> +  ARM_DEVICE_REGION (SYNQUACER_NETSEC_BASE, SYNQUACER_NETSEC_BASE_SZ),
> +
> +  // PCIe control registers
> +  ARM_DEVICE_REGION (SYNQUACER_PCIE_BASE, SYNQUACER_PCIE_SIZE),
> +
> +  // PCIe config space
> +  ARM_DEVICE_REGION (SYNQUACER_PCI_SEG0_CONFIG_BASE,
> + SYNQUACER_PCI_SEG0_CONFIG_SIZE),
> +  ARM_DEVICE_REGION (SYNQUACER_PCI_SEG1_CONFIG_BASE,
> + SYNQUACER_PCI_SEG1_CONFIG_SIZE),
> +
> +  // PCIe I/O space
> +  ARM_DEVICE_REGION (SYNQUACER_PCI_SEG0_PORTIO_MEMBASE,
> + SYNQUACER_PCI_SEG0_PORTIO_MEMSIZE),
> +  ARM_DEVICE_REGION (SYNQUACER_PCI_SEG1_PORTIO_MEMBASE,
> + SYNQUACER_PCI_SEG1_PORTIO_MEMSIZE

[edk2] [PATCH v2] MdeModulePkg/PciBus: Disable BME of all devices when entering RT

[Ruiyu Ni]

The patch ensures all DMA transactions are blocked after
ExitBootService.
If a platform enables IOMMU before and needs disable IOMMU after
ExitBootService, the IOMMU should be disabled after PCI bus driver
disables BME.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Michael Turner 
Signed-off-by: Ruiyu Ni 
Cc: Michael D Kinney 
Cc: Jiewen Yao 
Cc: Jeff Fan 
---
 MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h   |  2 +
 MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf  |  3 +
 MdeModulePkg/Bus/Pci/PciBusDxe/PciDeviceSupport.c | 86 +++
 3 files changed, 91 insertions(+)

diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h 
b/MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h
index 55eb3a5a80..79b5b71082 100644
--- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h
+++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h
@@ -18,6 +18,8 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER 
EXPRESS OR IMPLIED.
 
 #include 
 
+#include 
+
 #include 
 #include 
 #include 
diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf 
b/MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
index 97608bfcf2..d5b8fab3ca 100644
--- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
+++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
@@ -80,6 +80,9 @@ [LibraryClasses]
   DebugLib
   PeCoffLib
 
+[Guids]
+  gEfiEventExitBootServicesGuid   ## SOMETIMES_CONSUMES ## 
Event
+
 [Protocols]
   gEfiPciHotPlugRequestProtocolGuid   ## SOMETIMES_PRODUCES
   gEfiPciIoProtocolGuid   ## BY_START
diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciDeviceSupport.c 
b/MdeModulePkg/Bus/Pci/PciBusDxe/PciDeviceSupport.c
index 97bb971a59..004f2a3b5b 100644
--- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciDeviceSupport.c
+++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciDeviceSupport.c
@@ -21,6 +21,72 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER 
EXPRESS OR IMPLIED.
 LIST_ENTRY  mPciDevicePool;
 
 /**
+ Disable Bus Master Enable bit in all devices in the list.
+
+ @param Devices  A device list.
+**/
+VOID
+DisableBmeOnTree (
+  IN LIST_ENTRY  *Devices
+  )
+{
+  LIST_ENTRY  *Link;
+  PCI_IO_DEVICE   *PciIoDevice;
+  UINT16   Command;
+
+  for ( Link = GetFirstNode (Devices)
+  ; !IsNull (Devices, Link)
+  ; Link = GetNextNode (Devices, Link)
+  ) {
+PciIoDevice = PCI_IO_DEVICE_FROM_LINK (Link);
+//
+// Turn off all children's Bus Master, if any
+//
+DisableBmeOnTree (&PciIoDevice->ChildList);
+
+//
+// If this is a device that supports BME, disable BME on this device.
+//
+if ((PciIoDevice->Supports & EFI_PCI_IO_ATTRIBUTE_BUS_MASTER) != 0) {
+  PCI_READ_COMMAND_REGISTER(PciIoDevice, &Command);
+  if ((Command & EFI_PCI_COMMAND_BUS_MASTER) != 0) {
+Command &= ~EFI_PCI_COMMAND_BUS_MASTER;
+PCI_SET_COMMAND_REGISTER (PciIoDevice, Command);
+DEBUG ((
+  DEBUG_INFO,"  %02x   %02x  %02x %04x\n",
+  PciIoDevice->BusNumber, PciIoDevice->DeviceNumber, 
PciIoDevice->FunctionNumber,
+  Command
+  ));
+  }
+}
+  }
+}
+
+/**
+  Exit Boot Services Event notification handler.
+
+  Disable Bus Master on any that were enabled during BDS.
+
+  @param[in]  Event Event whose notification function is being invoked.
+  @param[in]  Context   Pointer to the notification function's context.
+
+**/
+VOID
+EFIAPI
+OnExitBootServices (
+  IN  EFI_EVENT Event,
+  IN  VOID  *Context
+  )
+{
+  DEBUG ((
+DEBUG_INFO,
+"PciBus: Disable Bus Master of all devices...\n"
+"  Bus# Device# Function#  NewCommand\n"
+));
+  DisableBmeOnTree(&mPciDevicePool);
+}
+
+/**
   Initialize the PCI devices pool.
 
 **/
@@ -29,7 +95,27 @@ InitializePciDevicePool (
   VOID
   )
 {
+  EFI_EVENT   ExitBootServicesEvent;
+  EFI_STATUS  Status;
+
   InitializeListHead (&mPciDevicePool);
+
+  //
+  // DisableBME on ExitBootServices should be synchonized with any IOMMU 
ExitBootServices routine.
+  // DisableBME should be run before the IOMMU protections are disabled.
+  // One way to do this is to ensure that the IOMMU ExitBootServices callback 
runs at TPL_CALLBACK.
+  //
+  Status = gBS->CreateEventEx (
+  EVT_NOTIFY_SIGNAL,
+  TPL_NOTIFY,
+  OnExitBootServices,
+  NULL,
+  &gEfiEventExitBootServicesGuid,
+  &ExitBootServicesEvent
+  );
+  if (EFI_ERROR (Status)) {
+DEBUG ((DEBUG_ERROR, "PciBus: Unable to hook ExitBootServices event - 
%r\n", Status));
+  }
 }
 
 /**
-- 
2.12.2.windows.2

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Re: [edk2] [PATCH edk2-platforms v3 04/27] Silicon/SynQuacer: implement a platform DXE driver

[Leif Lindholm]

On Tue, Oct 31, 2017 at 10:51:55AM +, Ard Biesheuvel wrote:
> This implements a driver that will take care of platform specific
> initialization, such as declaring non-discoverable devices. For
> the moment, this is limited to declaring the presence of the NETSEC
> controller.
> 
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Ard Biesheuvel 

Reviewed-by: Leif Lindholm 

> ---
>  Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.c   | 106 
> 
>  Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.inf |  52 
> ++
>  Silicon/Socionext/SynQuacer/SynQuacer.dec   |   3 +
>  3 files changed, 161 insertions(+)
> 
> diff --git a/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.c 
> b/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.c
> new file mode 100644
> index ..86e81bc3593c
> --- /dev/null
> +++ b/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.c
> @@ -0,0 +1,106 @@
> +/** @file
> +  SynQuacer DXE platform driver.
> +
> +  Copyright (c) 2017, Linaro, Ltd. All rights reserved.
> +
> +  This program and the accompanying materials are licensed and made available
> +  under the terms and conditions of the BSD License which accompanies this
> +  distribution.  The full text of the license may be found at
> +  http://opensource.org/licenses/bsd-license.php
> +
> +  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR 
> IMPLIED.
> +**/
> +
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +
> +STATIC EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR mNetsecDesc[] = {
> +  {
> +ACPI_ADDRESS_SPACE_DESCRIPTOR,// Desc
> +sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) - 3,   // Len
> +ACPI_ADDRESS_SPACE_TYPE_MEM,  // ResType
> +0,// GenFlag
> +0,// SpecificFlag
> +32,   // AddrSpaceGranularity
> +SYNQUACER_NETSEC_BASE,// AddrRangeMin
> +SYNQUACER_NETSEC_BASE +
> +SYNQUACER_NETSEC_BASE_SZ - 1, // AddrRangeMax
> +0,// 
> AddrTranslationOffset
> +SYNQUACER_NETSEC_BASE_SZ, // AddrLen
> +  }, {
> +ACPI_ADDRESS_SPACE_DESCRIPTOR,// Desc
> +sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) - 3,   // Len
> +ACPI_ADDRESS_SPACE_TYPE_MEM,  // ResType
> +0,// GenFlag
> +0,// SpecificFlag
> +32,   // AddrSpaceGranularity
> +FixedPcdGet32 (PcdNetsecEepromBase),  // AddrRangeMin
> +FixedPcdGet32 (PcdNetsecEepromBase) +
> +SYNQUACER_EEPROM_BASE_SZ - 1, // AddrRangeMax
> +0,// 
> AddrTranslationOffset
> +SYNQUACER_EEPROM_BASE_SZ, // AddrLen
> +  }, {
> +ACPI_ADDRESS_SPACE_DESCRIPTOR,// Desc
> +sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) - 3,   // Len
> +ACPI_ADDRESS_SPACE_TYPE_MEM,  // ResType
> +0,// GenFlag
> +0,// SpecificFlag
> +32,   // AddrSpaceGranularity
> +FixedPcdGet32 (PcdNetsecPhyAddress),  // AddrRangeMin
> +FixedPcdGet32 (PcdNetsecPhyAddress),  // AddrRangeMax
> +0,// 
> AddrTranslationOffset
> +1,// AddrLen
> +  }, {
> +ACPI_END_TAG_DESCRIPTOR   // Desc
> +  }
> +};
> +
> +STATIC
> +EFI_STATUS
> +RegisterNetsec (
> +  VOID
> +  )
> +{
> +  NON_DISCOVERABLE_DEVICE *Device;
> +  EFI_STATUS  Status;
> +  EFI_HANDLE  Handle;
> +
> +  Device = (NON_DISCOVERABLE_DEVICE *)AllocateZeroPool (sizeof (*Device));
> +  if (Device == NULL) {
> +return EFI_OUT_OF_RESOURCES;
> +  }
> +
> +  Device->Type = &gNetsecNonDiscoverableDeviceGuid;
> +  Device->DmaType = NonDiscoverableDeviceDmaTypeNonCoherent;
> +  Device->Resources = mNetsecDesc;
> +
> +  Handle = NULL;
> +  Status = gBS->InstallMultipleProtocolInterfaces (&Handle,
> +  &gEdkiiNonDiscoverableDeviceProtocolGuid, Device,
> +  NULL);
> +  if (EFI_ERROR (Status)) {
> +goto FreeDevice;
> +  }
> +  return EFI_SUCCESS;
> +
> +FreeDevice:
> +  FreePool (Device);
> +
> +  return Status;
> +}
> +
> +EFI_STATUS
> +EFIAPI
> +Pl

Re: [edk2] [PATCH edk2-platforms v3 03/27] Silicon/Socionext: add PlatformPeilib implementation for SynQuacer

[Leif Lindholm]

On Tue, Oct 31, 2017 at 10:51:54AM +, Ard Biesheuvel wrote:
> Create a specialized PlatformPeiLib implementation that invokes the
> platform specific firmware interface (currently, just a data structure
> left in SRAM) to set the ARM standard PcdSystemMemoryBase|Size PCDs,
> and expose the information via a newly added DramInfo PPI.
> 
> It is also in charge of copying the secondary compressed firmware
> volume to DRAM before decompressing it. This works around a performance
> issue regarding mapping the NOR flash with normal uncached attributes.
> 
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Ard Biesheuvel 

Reviewed-by: Leif Lindholm 

> ---
>  Silicon/Socionext/SynQuacer/Include/Platform/DramInfo.h  
>|  30 
>  Silicon/Socionext/SynQuacer/Include/Ppi/DramInfo.h   
>|  64 
>  
> Silicon/Socionext/SynQuacer/Library/SynQuacerPlatformPeiLib/SynQuacerPlatformPeiLib.c
>| 161 
>  
> Silicon/Socionext/SynQuacer/Library/SynQuacerPlatformPeiLib/SynQuacerPlatformPeiLib.inf
>  |  53 +++
>  Silicon/Socionext/SynQuacer/SynQuacer.dec
>|  12 ++
>  5 files changed, 320 insertions(+)
> 
> diff --git a/Silicon/Socionext/SynQuacer/Include/Platform/DramInfo.h 
> b/Silicon/Socionext/SynQuacer/Include/Platform/DramInfo.h
> new file mode 100644
> index ..f7691bdade4a
> --- /dev/null
> +++ b/Silicon/Socionext/SynQuacer/Include/Platform/DramInfo.h
> @@ -0,0 +1,30 @@
> +/** @file
> +  Data structure for passing DRAM information from lower level firmware
> +
> +  Copyright (c) 2017, Linaro Ltd. All rights reserved.
> +
> +  This program and the accompanying materials are licensed and made available
> +  under the terms and conditions of the BSD License which accompanies this
> +  distribution.  The full text of the license may be found at
> +  http://opensource.org/licenses/bsd-license.php.
> +
> +  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, 
> WITHOUT
> +  WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +
> +**/
> +
> +#ifndef _SYNQUACER_PLATFORM_DRAM_INFO_H_
> +#define _SYNQUACER_PLATFORM_DRAM_INFO_H_
> +
> +typedef struct {
> +  UINT64Base;
> +  UINT64Size;
> +} DRAM_INFO_ENTRY;
> +
> +typedef struct {
> +  UINT32NumRegions;
> +  UINT32Reserved;
> +  DRAM_INFO_ENTRY   Entry[3];
> +} DRAM_INFO;
> +
> +#endif
> diff --git a/Silicon/Socionext/SynQuacer/Include/Ppi/DramInfo.h 
> b/Silicon/Socionext/SynQuacer/Include/Ppi/DramInfo.h
> new file mode 100644
> index ..6453e121317d
> --- /dev/null
> +++ b/Silicon/Socionext/SynQuacer/Include/Ppi/DramInfo.h
> @@ -0,0 +1,64 @@
> +/** @file
> +  DRAM info PPI to retrieve DRAM information from lower level firmware
> +
> +  Copyright (c) 2017, Linaro Ltd. All rights reserved.
> +
> +  This program and the accompanying materials are licensed and made available
> +  under the terms and conditions of the BSD License which accompanies this
> +  distribution.  The full text of the license may be found at
> +  http://opensource.org/licenses/bsd-license.php.
> +
> +  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, 
> WITHOUT
> +  WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +
> +**/
> +
> +#ifndef  _SYNQUACER_DRAMINFO_PPI_
> +#define  _SYNQUACER_DRAMINFO_PPI_
> +
> +#define SYNQUACER_DRAMINFO_PPI_GUID \
> +  { 0x3e1d7356, 0xdda4, 0x4b1a, { 0x93, 0x46, 0xbf, 0x89, 0x1c, 0x86, 0x46, 
> 0xcc } }
> +
> +/**
> +  Retrieve the number of discontiguous DRAM regions
> +
> +  @param[out] RegionCount   The number of available DRAM regions
> +
> +  @retval EFI_SUCCESS   The data was successfully returned.
> +  @retval EFI_INVALID_PARAMETER RegionCount == NULL
> +
> +**/
> +typedef
> +EFI_STATUS
> +(EFIAPI * DRAMINFO_GET_REGION_COUNT) (
> +  OUT   UINTN *RegionCount
> +  );
> +
> +/**
> +  Retrieve the base and size of a DRAM region
> +
> +  @param[in]  RegionIndex   The 0-based index of the region to retrieve
> +  @param[out] Base  The base of the requested region
> +  @param[out] Size  The size of the requested region
> +
> +  @retval EFI_SUCCESS   The data was successfully returned.
> +  @retval EFI_INVALID_PARAMETER Base == NULL or Size == NULL
> +  @retval EFI_NOT_FOUND No region exists with index >= RegionIndex
> +
> +**/
> +typedef
> +EFI_STATUS
> +(EFIAPI * DRAMINFO_GET_REGION) (
> +  INUINTN RegionIndex,
> +  OUT   UINT64*Base,
> +  OUT   UINT64*Size
> +  );
> +
> +typedef struct {
> +  DRAMINFO_GET_REGION_COUNT   GetRegionCount;
> +  DRAMINFO_GET_REGION GetRegion;
> +} SYNQUACER_DRAM_INFO_PPI;
> +
> +extern EFI_GUID gSynQuacerDramInfoPpiGuid;
> +
> +#endif
> diff --git 
> a/Silicon/Socionext/SynQuacer/Library/SynQuace

Re: [edk2] [PATCH] MdeModulePkg/PciBus: Disable BME of all devices when entering RT

[Ni, Ruiyu]

Jeff,
Thanks you for your comments!

How are you in Guiyang?

Thanks/Ray

From: Fan Jeff [mailto:vanjeff_...@hotmail.com]
Sent: Wednesday, November 1, 2017 10:43 AM
To: Ni, Ruiyu ; edk2-devel@lists.01.org
Cc: Kinney, Michael D ; Michael Turner 
; Yao, Jiewen 
Subject: 答复: [edk2] [PATCH] MdeModulePkg/PciBus: Disable BME of all devices 
when entering RT

Minimal comment: To use DEBUG_INFO instead of EFI_D_INFO for consistence in 
this patch.
+DEBUG ((
+  EFI_D_INFO,"  %02x   %02x  %02x %04x\n",
+  PciIoDevice->BusNumber, PciIoDevice->DeviceNumber, 
PciIoDevice->FunctionNumber,
+  Command
+  ));
发件人: Ruiyu Ni
发送时间: 2017年10月31日 15:54
收件人: edk2-devel@lists.01.org
抄送: Michael D Kinney; Michael 
Turner; Jiewen 
Yao
主题: [edk2] [PATCH] MdeModulePkg/PciBus: Disable BME of all devices when 
entering RT

The patch assumes IOMMU protections are disabled after PciBus
disables the BMT bit in Command register.
It ensures all DMA transactions are protected by IOMMU.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Michael Turner 
mailto:michael.tur...@microsoft.com>>
Signed-off-by: Ruiyu Ni mailto:ruiyu...@intel.com>>
Cc: Michael D Kinney 
mailto:michael.d.kin...@intel.com>>
Cc: Jiewen Yao mailto:jiewen@intel.com>>
---
 MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h   |  2 +
 MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf  |  3 +
 MdeModulePkg/Bus/Pci/PciBusDxe/PciDeviceSupport.c | 86 +++
 3 files changed, 91 insertions(+)

diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h 
b/MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h
index 55eb3a5a80..79b5b71082 100644
--- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h
+++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h
@@ -18,6 +18,8 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER 
EXPRESS OR IMPLIED.

 #include 

+#include 
+
 #include 
 #include 
 #include 
diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf 
b/MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
index 97608bfcf2..d5b8fab3ca 100644
--- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
+++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
@@ -80,6 +80,9 @@ [LibraryClasses]
   DebugLib
   PeCoffLib

+[Guids]
+  gEfiEventExitBootServicesGuid   ## SOMETIMES_CONSUMES ## 
Event
+
 [Protocols]
   gEfiPciHotPlugRequestProtocolGuid   ## SOMETIMES_PRODUCES
   gEfiPciIoProtocolGuid   ## BY_START
diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciDeviceSupport.c 
b/MdeModulePkg/Bus/Pci/PciBusDxe/PciDeviceSupport.c
index 97bb971a59..b5530a13d1 100644
--- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciDeviceSupport.c
+++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciDeviceSupport.c
@@ -21,6 +21,72 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER 
EXPRESS OR IMPLIED.
 LIST_ENTRY  mPciDevicePool;

 /**
+ Disable Bus Master Enable bit in all devices in the list.
+
+ @param Devices  A device list.
+**/
+VOID
+DisableBmeOnTree (
+  IN LIST_ENTRY  *Devices
+  )
+{
+  LIST_ENTRY  *Link;
+  PCI_IO_DEVICE   *PciIoDevice;
+  UINT16   Command;
+
+  for ( Link = GetFirstNode (Devices)
+  ; !IsNull (Devices, Link)
+  ; Link = GetNextNode (Devices, Link)
+  ) {
+PciIoDevice = PCI_IO_DEVICE_FROM_LINK (Link);
+//
+// Turn off all children's Bus Master, if any
+//
+DisableBmeOnTree (&PciIoDevice->ChildList);
+
+//
+// If this is a device that supports BME, disable BME on this device.
+//
+if ((PciIoDevice->Supports & EFI_PCI_IO_ATTRIBUTE_BUS_MASTER) != 0) {
+  PCI_READ_COMMAND_REGISTER(PciIoDevice, &Command);
+  if ((Command & EFI_PCI_COMMAND_BUS_MASTER) != 0) {
+Command &= ~EFI_PCI_COMMAND_BUS_MASTER;
+PCI_SET_COMMAND_REGISTER (PciIoDevice, Command);
+DEBUG ((
+  EFI_D_INFO,"  %02x   %02x  %02x %04x\n",
+  PciIoDevice->BusNumber, PciIoDevice->DeviceNumber, 
PciIoDevice->FunctionNumber,
+  Command
+  ));
+  }
+}
+  }
+}
+
+/**
+  Exit Boot Services Event notification handler.
+
+  Disable Bus Master on any that were enabled during BDS.
+
+  @param[in]  Event Event whose notification function is being invoked.
+  @param[in]  Context   Pointer to the notification function's context.
+
+**/
+VOID
+EFIAPI
+OnExitBootServices (
+  IN  EFI_EVENT Event,
+  IN  VOID  *Context
+  )
+{
+  DEBUG ((
+DEBUG_INFO,
+"PciBus: Disable Bus Master of all devices...\n"
+"  Bus# Device# Function#  NewCommand\n"
+));
+  DisableBmeOnTree(&mPciDevicePool);
+}
+
+/**
   Initialize the PCI devices pool.

 **/
@@ -29,7 +95,27 @@ InitializePciDevicePool (
   VOID
   )
 {
+  EFI_EVENT   ExitBootServicesEvent;
+  EFI_STATUS  Status;
+
   InitializeListHead (&mPciDevicePool);
+
+  /

Re: [edk2] [PATCH edk2-platforms v3 02/27] Silicon/Socionext: add driver for NETSEC network controller

[Leif Lindholm]

On Tue, Oct 31, 2017 at 10:51:53AM +, Ard Biesheuvel wrote:
> This adds the NetSecDxe driver provided by Socionext, but reworked
> extensively to improve compliance with the SimpleNetworkProtocol API,
> and to avoid uncached allocations for streaming DMA.
> 
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Ard Biesheuvel 
> Tested-by: Leif Lindholm 

Reviewed-by: Leif Lindholm 
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Re: [edk2] [PATCH v2 1/1] EmbeddedPkg: Implement NorFlashInfoLib

[Leif Lindholm]

On Tue, Oct 31, 2017 at 11:39:02AM +0100, Marcin Wojtas wrote:
> The SPI NOR flash drivers which base on ArmPlatformPkg's
> NorFlashDxe usually make use of static declarations of the
> flash instances with their type and parameters. As a result
> it implies hardcoding the exact way of flash handling, not to
> mention the code does not look very nice. Much better solution
> would be obtaining the flash ID and hence its description
> in runtime.
> 
> Because JEDEC compliant SPI NOR devices allow to obtain their ID
> with READ_ID command (0x9f), implement a NorFlashInfoLib that gives
> an access to the NOR flash data, such as name, page size, sector
> (block) size and others, of more than 50 different models.
> The new library user should pass an output array from issuing
> READ_ID command to the NorFlashGetInfo () routine - if the
> match is found, an allocated (optionally for RT) pool with
> the flash description copy will be returned.
> 
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Marcin Wojtas 
> 
> =
> Patch available in the github:
> https://github.com/MarvellEmbeddedProcessors/edk2/commits/norlib-upstream-r20171031
> 
> Changelog:
> v1 -> v2
>   * In flash info flags: s/NF_/NOR_FLASH_/
>   * Rename routines to NorFlashGetInfo and NorFlashPrintInfo
>   * Fix NorFlashGetInfo description.
>   * Improve commit log (fix typos and other minor improvements)
> 
> ---
>  EmbeddedPkg/EmbeddedPkg.dec |   1 +
>  EmbeddedPkg/Include/Library/NorFlashInfoLib.h   |  84 
>  EmbeddedPkg/Library/NorFlashInfoLib/NorFlashInfoLib.c   | 225 
> 
>  EmbeddedPkg/Library/NorFlashInfoLib/NorFlashInfoLib.inf |  34 +++
>  4 files changed, 344 insertions(+)
> 
> diff --git a/EmbeddedPkg/EmbeddedPkg.dec b/EmbeddedPkg/EmbeddedPkg.dec
> index 52482af..aa551ab 100644
> --- a/EmbeddedPkg/EmbeddedPkg.dec
> +++ b/EmbeddedPkg/EmbeddedPkg.dec
> @@ -45,6 +45,7 @@
>EblNetworkLib|Include/Library/EblNetworkLib.h
>GdbSerialLib|Include/Library/GdbSerialLib.h
>DebugAgentTimerLib|Include/Library/DebugAgentTimerLib.h
> +  NorFlashInfoLib|Include/Library/NorFlashInfoLib.h
>  
>DtPlatformDtbLoaderLib|Include/Library/DtPlatformDtbLoaderLib.h
>  
> diff --git a/EmbeddedPkg/Include/Library/NorFlashInfoLib.h 
> b/EmbeddedPkg/Include/Library/NorFlashInfoLib.h
> new file mode 100644
> index 000..e28c169
> --- /dev/null
> +++ b/EmbeddedPkg/Include/Library/NorFlashInfoLib.h
> @@ -0,0 +1,84 @@
> +/** @file
> +*
> +*  Copyright (c) 2017 Marvell International Ltd.
> +*
> +*  This program and the accompanying materials
> +*  are licensed and made available under the terms and conditions of the BSD 
> License
> +*  which accompanies this distribution.  The full text of the license may be 
> found at
> +*  http://opensource.org/licenses/bsd-license.php
> +*
> +*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR 
> IMPLIED.
> +*
> +**/
> +
> +#ifndef __NOR_FLASH_ID_LIB_H__
> +#define __NOR_FLASH_ID_LIB_H__

Please also fold in the vendor name defines somewhere in this file,
(as NOR_FLASH_*).

> +
> +#include 
> +
> +#define NOR_FLASH_MAX_ID_LEN6
> +
> +typedef struct {
> +  /* Device name */
> +  UINT16 *Name;
> +
> +  /*
> +   * JEDEC ID
> +   */
> +  UINT8  Id[NOR_FLASH_MAX_ID_LEN];
> +  UINT8  IdLen;
> +
> +  UINT16 PageSize;
> +
> +  /*
> +   * Below parameters can be referred as BlockSize
> +   * and BlockCount, when treating the NorFlash as
> +   * block device.
> +   */
> +  UINT32 SectorSize;
> +  UINT32 SectorCount;
> +
> +  UINT16 Flags;
> +#define NOR_FLASH_ERASE_4K (1 << 0)  /* Use 4096B erase blocks and 
> CMD_ERASE_4K */
> +#define NOR_FLASH_WRITE_FSR(1 << 1)  /* Use flag status register for 
> write */
> +#define NOR_FLASH_4B_ADDR  (1 << 2)  /* Use 4B addressing */
> +} NOR_FLASH_INFO;
> +
> +/**
> +  Return an allocated copy pool of the NOR flash information structure.
> +
> +  @param[in]   Id Pointer to an array with JEDEC ID 
> obtained
> +  from the NOR flash with READ_ID command
> +  (0x9f)
> +  @param[in out]   FlashInfo  Pointer to NOR flash information 
> structure
> +  @param[in]   AllocateForRuntime A flag specifying a type of a copy pool
> +  allocation (TRUE for runtime, FALSE for
> +  normal)
> +
> +  @retval   EFI_SUCCESS   Operation completed successfully
> +  @retval   EFI_NOT_FOUND No matching entry in NOR ID table found
> +  @retval   EFI_OUT_OF_RESOURCES  No pool memory available
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +NorFlashGetInfo (
> +  IN UINT8*Id,
> +  IN OUT NOR_FLASH_INFO  **FlashInfo,
> +  IN BOOLEAN   AllocateForRuntime
> +  );
> +
> +

Re: [edk2] [platforms: PATCH 6/6] Marvell/Drivers: MvSpiDxe: Keep data in SPI_DEVICE structure

[Leif Lindholm]

On Tue, Oct 31, 2017 at 04:59:35AM +0100, Marcin Wojtas wrote:
> In the MvSpiDxe driver obtaining host register base address,
> controller clock and device maximum frequency directly from PCDs
> was done all over the code. This patch cleans up the parameters'
> handling and enables accessing them from SPI_DEVICE structure fields.
> 
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Marcin Wojtas 

Reviewed-by: Leif Lindholm 

> ---
>  Platform/Marvell/Drivers/Spi/MvSpiDxe.c | 48 
>  Platform/Marvell/Include/Protocol/Spi.h |  2 +
>  2 files changed, 31 insertions(+), 19 deletions(-)
> 
> diff --git a/Platform/Marvell/Drivers/Spi/MvSpiDxe.c 
> b/Platform/Marvell/Drivers/Spi/MvSpiDxe.c
> index a7db5f2..c60a520 100755
> --- a/Platform/Marvell/Drivers/Spi/MvSpiDxe.c
> +++ b/Platform/Marvell/Drivers/Spi/MvSpiDxe.c
> @@ -38,12 +38,13 @@ SPI_MASTER *mSpiMasterInstance;
>  STATIC
>  EFI_STATUS
>  SpiSetBaudRate (
> +  IN SPI_DEVICE *Slave,
>IN UINT32 CpuClock,
>IN UINT32 MaxFreq
>)
>  {
>UINT32 Spr, BestSpr, Sppr, BestSppr, ClockDivider, Match, Reg, MinBaudDiff;
> -  UINTN SpiRegBase = PcdGet32 (PcdSpiRegBase);
> +  UINTN SpiRegBase = Slave->HostRegisterBaseAddress;
>  
>MinBaudDiff = 0x;
>BestSppr = 0;
> @@ -93,26 +94,28 @@ SpiSetBaudRate (
>  STATIC
>  VOID
>  SpiSetCs (
> -  UINT8 CsId
> +  IN SPI_DEVICE *Slave
>)
>  {
> -  UINT32 Reg, SpiRegBase = PcdGet32 (PcdSpiRegBase);
> +  UINT32 Reg;
> +  UINTN  SpiRegBase = Slave->HostRegisterBaseAddress;
>  
>Reg = MmioRead32 (SpiRegBase + SPI_CTRL_REG);
>Reg &= ~SPI_CS_NUM_MASK;
> -  Reg |= (CsId << SPI_CS_NUM_OFFSET);
> +  Reg |= (Slave->Cs << SPI_CS_NUM_OFFSET);
>MmioWrite32 (SpiRegBase + SPI_CTRL_REG, Reg);
>  }
>  
>  STATIC
>  VOID
>  SpiActivateCs (
> -  UINT8 IN CsId
> +  IN SPI_DEVICE *Slave
>)
>  {
> -  UINT32  Reg, SpiRegBase = PcdGet32 (PcdSpiRegBase);
> +  UINT32 Reg;
> +  UINTN  SpiRegBase = Slave->HostRegisterBaseAddress;
>  
> -  SpiSetCs(CsId);
> +  SpiSetCs(Slave);
>Reg = MmioRead32 (SpiRegBase + SPI_CTRL_REG);
>Reg |= SPI_CS_EN_MASK;
>MmioWrite32(SpiRegBase + SPI_CTRL_REG, Reg);
> @@ -121,10 +124,11 @@ SpiActivateCs (
>  STATIC
>  VOID
>  SpiDeactivateCs (
> -  VOID
> +  IN SPI_DEVICE *Slave
>)
>  {
> -  UINT32  Reg, SpiRegBase = PcdGet32 (PcdSpiRegBase);
> +  UINT32 Reg;
> +  UINTN  SpiRegBase = Slave->HostRegisterBaseAddress;
>  
>Reg = MmioRead32 (SpiRegBase + SPI_CTRL_REG);
>Reg &= ~SPI_CS_EN_MASK;
> @@ -139,14 +143,15 @@ SpiSetupTransfer (
>)
>  {
>SPI_MASTER *SpiMaster;
> -  UINT32 Reg, SpiRegBase, CoreClock, SpiMaxFreq;
> +  UINT32 Reg, CoreClock, SpiMaxFreq;
> +  UINTN SpiRegBase;
>  
>SpiMaster = SPI_MASTER_FROM_SPI_MASTER_PROTOCOL (This);
>  
>// Initialize values from PCDs
> -  SpiRegBase  = PcdGet32 (PcdSpiRegBase);
> -  CoreClock   = PcdGet32 (PcdSpiClockFrequency);
> -  SpiMaxFreq  = PcdGet32 (PcdSpiMaxFrequency);
> +  SpiRegBase  = Slave->HostRegisterBaseAddress;
> +  CoreClock   = Slave->CoreClock;
> +  SpiMaxFreq  = Slave->MaxFreq;
>  
>EfiAcquireLock (&SpiMaster->Lock);
>  
> @@ -154,9 +159,9 @@ SpiSetupTransfer (
>Reg |= SPI_BYTE_LENGTH;
>MmioWrite32 (SpiRegBase + SPI_CONF_REG, Reg);
>  
> -  SpiSetCs(Slave->Cs);
> +  SpiSetCs(Slave);
>  
> -  SpiSetBaudRate (CoreClock, SpiMaxFreq);
> +  SpiSetBaudRate (Slave, CoreClock, SpiMaxFreq);
>  
>Reg = MmioRead32 (SpiRegBase + SPI_CONF_REG);
>Reg &= ~(SPI_CPOL_MASK | SPI_CPHA_MASK | SPI_TXLSBF_MASK | 
> SPI_RXLSBF_MASK);
> @@ -194,21 +199,22 @@ MvSpiTransfer (
>  {
>SPI_MASTER *SpiMaster;
>UINT64  Length;
> -  UINT32  Iterator, Reg, SpiRegBase;
> +  UINT32  Iterator, Reg;
>UINT8   *DataOutPtr = (UINT8 *)DataOut;
>UINT8   *DataInPtr  = (UINT8 *)DataIn;
>UINT8   DataToSend  = 0;
> +  UINTN   SpiRegBase;
>  
>SpiMaster = SPI_MASTER_FROM_SPI_MASTER_PROTOCOL (This);
>  
> -  SpiRegBase = PcdGet32 (PcdSpiRegBase);
> +  SpiRegBase = Slave->HostRegisterBaseAddress;
>  
>Length = 8 * DataByteCount;
>  
>EfiAcquireLock (&SpiMaster->Lock);
>  
>if (Flag & SPI_TRANSFER_BEGIN) {
> -SpiActivateCs (Slave->Cs);
> +SpiActivateCs (Slave);
>}
>  
>// Set 8-bit mode
> @@ -245,7 +251,7 @@ MvSpiTransfer (
>}
>  
>if (Flag & SPI_TRANSFER_END) {
> -SpiDeactivateCs ();
> +SpiDeactivateCs (Slave);
>}
>  
>EfiReleaseLock (&SpiMaster->Lock);
> @@ -312,6 +318,10 @@ MvSpiSetupSlave (
>  Slave->Mode = Mode;
>}
>  
> +  Slave->HostRegisterBaseAddress = PcdGet32 (PcdSpiRegBase);
> +  Slave->CoreClock = PcdGet32 (PcdSpiClockFrequency);
> +  Slave->MaxFreq = PcdGet32 (PcdSpiMaxFrequency);
> +
>SpiSetupTransfer (This, Slave);
>  
>return Slave;
> diff --git a/Platform/Marvell/Include/Protocol/Spi.h 
> b/Platform/Marvell/Include/Protocol/Spi.h
> index 0cf7914..b8981f3 100644
> --- a/Platform/Marvell/Include/Protocol/Spi.h
> +++ b/Platform/Marvell/Include/Protocol/Spi.h
> @@ -52,6 +5

Re: [edk2] [platforms: PATCH 5/6] Marvell/Drivers: MvSpiFlash: Fix bank selection for Spansion

[Leif Lindholm]

On Tue, Oct 31, 2017 at 04:59:34AM +0100, Marcin Wojtas wrote:
> Spansion SPI flash devices use different command for bank
> selection. Update it, basing on the first byte of flash ID.
> 
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Marcin Wojtas 
> ---
>  Platform/Marvell/Drivers/Spi/Devices/MvSpiFlash.c | 5 +
>  Platform/Marvell/Drivers/Spi/Devices/MvSpiFlash.h | 4 
>  2 files changed, 9 insertions(+)
> 
> diff --git a/Platform/Marvell/Drivers/Spi/Devices/MvSpiFlash.c 
> b/Platform/Marvell/Drivers/Spi/Devices/MvSpiFlash.c
> index 703994c..a00fc305 100755
> --- a/Platform/Marvell/Drivers/Spi/Devices/MvSpiFlash.c
> +++ b/Platform/Marvell/Drivers/Spi/Devices/MvSpiFlash.c
> @@ -150,6 +150,11 @@ SpiFlashCmdBankaddrWrite (
>  {
>UINT8 Cmd = CMD_BANK_WRITE;
>  
> +  /* Update bank selection command for Spansion */
> +  if (Slave->Info->Id[0] == SPI_FLASH_MFR_SPANSION) {
> +Cmd = CMD_BANKADDR_BRWR;
> +  }
> +
>MvSpiFlashWriteCommon (Slave, &Cmd, 1, &BankSel, 1);
>  }
>  
> diff --git a/Platform/Marvell/Drivers/Spi/Devices/MvSpiFlash.h 
> b/Platform/Marvell/Drivers/Spi/Devices/MvSpiFlash.h
> index 2583484..00af188 100755
> --- a/Platform/Marvell/Drivers/Spi/Devices/MvSpiFlash.h
> +++ b/Platform/Marvell/Drivers/Spi/Devices/MvSpiFlash.h
> @@ -57,6 +57,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
>  #define CMD_READ_ARRAY_FAST 0x0b
>  #define CMD_PAGE_PROGRAM0x02
>  #define CMD_BANK_WRITE  0xc5
> +#define CMD_BANKADDR_BRWR   0x17
>  #define CMD_ERASE_4K0x20
>  #define CMD_ERASE_32K   0x52
>  #define CMD_ERASE_64K   0xd8
> @@ -72,6 +73,9 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
>  
>  #define SPI_FLASH_16MB_BOUN 0x100
>  
> +/* Manufacturer ID's */
> +#define SPI_FLASH_MFR_SPANSION  0x01
> +

Please move this definition to NorFlashInfoLib.
Otherwise this patch looks OK.

/
Leif

>  typedef enum {
>SPI_FLASH_READ_ID,
>SPI_FLASH_READ, // Read from SPI flash with address
> -- 
> 2.7.4
> 
___
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[edk2] 答复: [PATCH 3/3] UefiCpuPkg/CpuExceptionHandlerLib: Add stack switch support

[Fan Jeff]

Jian,

You are right! The exception handler setup in DxeIplPeim does not need stack at 
all. Thanks your clarification.

Jeff

发件人: Wang, Jian J
发送时间: 2017年11月1日 11:12
收件人: Wang, Jian J; Fan 
Jeff; Yao, Jiewen; 
edk2-devel@lists.01.org
抄送: Kinney, Michael D; Dong, 
Eric; Zeng, Star
主题: RE: [PATCH 3/3] UefiCpuPkg/CpuExceptionHandlerLib: Add stack switch support

Jeff,

Sorry for the misunderstanding. I think stack switch cannot work with NULL 
exception handler. But without exception handler, what do we need stack switch 
for?

Thanks,
Jian

> -Original Message-
> From: edk2-devel [mailto:edk2-devel-boun...@lists.01.org] On Behalf Of Wang,
> Jian J
> Sent: Wednesday, November 01, 2017 11:09 AM
> To: Fan Jeff ; Yao, Jiewen ;
> edk2-devel@lists.01.org
> Cc: Kinney, Michael D ; Dong, Eric
> ; Zeng, Star 
> Subject: Re: [edk2] [PATCH 3/3] UefiCpuPkg/CpuExceptionHandlerLib: Add stack
> switch support
>
> Jeff,
>
> Stack guard will still work. But the developer cannot know what’s going on
> without exception dumping message when stack overflow occurs.
>
> Thanks,
> Jian
>
> From: Fan Jeff [mailto:vanjeff_...@hotmail.com]
> Sent: Wednesday, November 01, 2017 10:59 AM
> To: Wang, Jian J ; Yao, Jiewen ;
> edk2-devel@lists.01.org
> Cc: Kinney, Michael D ; Dong, Eric
> ; Zeng, Star 
> Subject: 答复: [PATCH 3/3] UefiCpuPkg/CpuExceptionHandlerLib: Add stack
> switch support
>
> Jian,
>
> No. I suggest to fix #109 in another separate patch.
>
> But to fix #109, we have to makes sure AsmWriteTr() and some definitions are 
> in
> MdePkg.
> But I have no strong opinion to add them into MdePkg in this patch.
>
> I have another question: If NULL CPU exception handler instance is chosen,
> could Stack Switch work if PCD PcdCpuStackGuard is set to TRUE.
>
> Thanks!
> Jeff
>
> 发件人: Wang, Jian J
> 发送时间: 2017年11月1日 10:48
> 收件人: Fan Jeff; Yao,
> Jiewen; edk2-devel@lists.01.org de...@lists.01.org>
> 抄送: Kinney, Michael D; Dong,
> Eric; Zeng, Star
> 主题: RE: [PATCH 3/3] UefiCpuPkg/CpuExceptionHandlerLib: Add stack switch
> support
>
> Hi Jeff,
>
> Thanks for the feedback. Are you suggesting to fix Bugzilla 109 in this patch?
>
> Thanks,
> Jian
>
> From: Fan Jeff [mailto:vanjeff_...@hotmail.com]
> Sent: Wednesday, November 01, 2017 10:33 AM
> To: Yao, Jiewen mailto:jiewen@intel.com>>;
> Wang, Jian J mailto:jian.j.w...@intel.com>>; edk2-
> de...@lists.01.org
> Cc: Kinney, Michael D
> mailto:michael.d.kin...@intel.com>>; Dong, Eric
> mailto:eric.d...@intel.com>>; Zeng, Star
> mailto:star.z...@intel.com>>
> Subject: 答复: [PATCH 3/3] UefiCpuPkg/CpuExceptionHandlerLib: Add stack
> switch support
>
> Per https://bugzilla.tianocore.org/show_bug.cgi?id=109, TR should be setup
> (Such as in DxeIplPeim) even though NULL Cpu Exception Handler instance is
> chosen.
>
> For long term, I agree we need to move AsmWriteTr,
> IA32_TASK_STATE_SEGMENT, IA32_TSS_DESCRIPTOR to MdePkg(Such as
> BaseLib)
> For this patch, I have no strong opinion.
>
>
> 发件人: Yao, Jiewen
> 发送时间: 2017年11月1日 9:56
> 收件人: Wang, Jian J; edk2-
> de...@lists.01.org
> 抄送: Kinney, Michael D; Dong,
> Eric; Zeng, Star
> 主题: Re: [edk2] [PATCH 3/3] UefiCpuPkg/CpuExceptionHandlerLib: Add stack
> switch support
>
> Hi Jian
> Thanks for the patch.
>
> Can we move all IA32 defined data structure or function to MdePkg?
> Such as: AsmWriteTr, IA32_TASK_STATE_SEGMENT, IA32_TSS_DESCRIPTOR
>
> I am also curious why we use different policy for other boot mode.
> Can we use consistent policy?
> > +  if (PcdGetBool (PcdCpuStackGuard)) {
> > +//
> > +// Stack Guard works with the support of page table established and
> > +// memory management. So we have to exclude those boot modes
> > without
> > +// them.
> > +//
> > +switch (GetBootModeHob()) {
> > +case BOOT_ON_FLASH_UPDATE:
> > +case BOOT_IN_RECOVERY_MODE:
> > +case BOOT_ON_S3_RESUME:
> > +  break;
> > +
> > +default:
> > +  ArchSetupExcpetionStack (IdtTable);
> > +  break;
> > +}
> > +  }
>
>
> Thank you
> Yao Jiewen
>
>
> > -Original Message-
> > From: Wang, Jian J
> > Sent: Tuesday, October 31, 2017 10:24 PM
> > To: edk2-devel@lists.01.org
> > Cc: Zeng, Star mailto:star.z...@intel.com>>; Dong,
> Eric mailto:eric.d...@intel.com>>; Yao,
> > Jiewen mailto:jiewen@intel.com>>; Kinney,
> Michael D
> 

Re: [edk2] [platforms: PATCH 4/6] Marvell/Applications: SpiTool: Do not override existing slave device

[Leif Lindholm]

On Tue, Oct 31, 2017 at 04:59:33AM +0100, Marcin Wojtas wrote:
> Current usage of sf command requires running 'sf probe' prior to
> executing any other option. Because it is done in two separate steps,
> it turned out that SpiMasterProtocol->SetupDevice could easily
> overwrite valid Slave pointer when performing second operation.
> 
> Fix the issue by allocating Slave device only once and keep it
> as global variable in the SpiTool application. This patch
> also updates FirmwareUpdate command to follow the modified
> SetupDevice operation.

Really an unrelated question, but would we not expect to use capsule
updates instead now? Do we have other uses for this tool?

> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Marcin Wojtas 
> ---
>  Platform/Marvell/Applications/FirmwareUpdate/FUpdate.c |  4 ++--
>  Platform/Marvell/Applications/SpiTool/SpiFlashCmd.c|  8 
>  Platform/Marvell/Drivers/Spi/MvSpiDxe.c| 17 +
>  Platform/Marvell/Drivers/Spi/MvSpiDxe.h|  1 +
>  Platform/Marvell/Include/Protocol/Spi.h|  1 +
>  5 files changed, 17 insertions(+), 14 deletions(-)
> 
> diff --git a/Platform/Marvell/Applications/FirmwareUpdate/FUpdate.c 
> b/Platform/Marvell/Applications/FirmwareUpdate/FUpdate.c
> index 750e52a..9ccb1c7 100644
> --- a/Platform/Marvell/Applications/FirmwareUpdate/FUpdate.c
> +++ b/Platform/Marvell/Applications/FirmwareUpdate/FUpdate.c
> @@ -240,7 +240,7 @@ ShellCommandRunFUpdate (
>)
>  {
>IN SHELL_FILE_HANDLEFileHandle;
> -  SPI_DEVICE  *Slave;
> +  SPI_DEVICE  *Slave = NULL;
>UINT64  FileSize;
>UINTN   *FileBuffer = NULL;
>CHAR16  *ProblemParam;
> @@ -302,7 +302,7 @@ ShellCommandRunFUpdate (
>}
>  
>// Setup and probe SPI flash
> -  Slave = SpiMasterProtocol->SetupDevice (SpiMasterProtocol, 0, 0);
> +  Slave = SpiMasterProtocol->SetupDevice (SpiMasterProtocol, Slave, 0, 0);
>if (Slave == NULL) {
>  Print(L"%s: Cannot allocate SPI device!\n", CMD_NAME_STRING);
>  goto HeaderError;
> diff --git a/Platform/Marvell/Applications/SpiTool/SpiFlashCmd.c 
> b/Platform/Marvell/Applications/SpiTool/SpiFlashCmd.c
> index 68a6cf7..1084f68 100644
> --- a/Platform/Marvell/Applications/SpiTool/SpiFlashCmd.c
> +++ b/Platform/Marvell/Applications/SpiTool/SpiFlashCmd.c
> @@ -191,7 +191,7 @@ ShellCommandRunSpiFlash (
>)
>  {
>  EFI_STATUS  Status;
> -  SPI_DEVICE*Slave;
> +  STATIC SPI_DEVICE *Slave;

If this is a safe thing to do, please use a global variable called
mSlave instead, to make it clear that it persists across calls.

>LIST_ENTRY*CheckPackage;
>EFI_PHYSICAL_ADDRESS  Address = 0, Offset = 0;
>SHELL_FILE_HANDLE FileHandle = NULL;
> @@ -273,7 +273,7 @@ EFI_STATUS  Status;
>Cs = PcdGet32 (PcdSpiFlashCs);
>  
>// Setup new spi device
> -  Slave = SpiMasterProtocol->SetupDevice (SpiMasterProtocol, Cs, Mode);
> +  Slave = SpiMasterProtocol->SetupDevice (SpiMasterProtocol, Slave, Cs, 
> Mode);
>  if (Slave == NULL) {
>Print(L"sf: Cannot allocate SPI device!\n");
>return SHELL_ABORTED;
> @@ -285,6 +285,8 @@ EFI_STATUS  Status;
>  Status = FlashProbe (Slave);
>  if (EFI_ERROR(Status)) {
>// No supported spi flash detected
> +  SpiMasterProtocol->FreeDevice(Slave);

Space before (.

/
Leif

> +  Slave = NULL;
>return SHELL_ABORTED;
>  } else {
>return Status;
> @@ -426,8 +428,6 @@ EFI_STATUS  Status;
>  break;
>}
>  
> -  SpiMasterProtocol->FreeDevice(Slave);
> -
>if (EFI_ERROR (Status)) {
>  Print (L"sf: Error while performing spi transfer\n");
>  return SHELL_ABORTED;
> diff --git a/Platform/Marvell/Drivers/Spi/MvSpiDxe.c 
> b/Platform/Marvell/Drivers/Spi/MvSpiDxe.c
> index 3b49147..a7db5f2 100755
> --- a/Platform/Marvell/Drivers/Spi/MvSpiDxe.c
> +++ b/Platform/Marvell/Drivers/Spi/MvSpiDxe.c
> @@ -296,21 +296,22 @@ SPI_DEVICE *
>  EFIAPI
>  MvSpiSetupSlave (
>IN MARVELL_SPI_MASTER_PROTOCOL *This,
> +  IN SPI_DEVICE *Slave,
>IN UINTN Cs,
>IN SPI_MODE Mode
>)
>  {
> -  SPI_DEVICE  *Slave;
> +  if (!Slave) {
> +Slave = AllocateZeroPool (sizeof(SPI_DEVICE));
> +if (Slave == NULL) {
> +  DEBUG((DEBUG_ERROR, "Cannot allocate memory\n"));
> +  return NULL;
> +}
>  
> -  Slave = AllocateZeroPool (sizeof(SPI_DEVICE));
> -  if (Slave == NULL) {
> -DEBUG((DEBUG_ERROR, "Cannot allocate memory\n"));
> -return NULL;
> +Slave->Cs   = Cs;
> +Slave->Mode = Mode;
>}
>  
> -  Slave->Cs   = Cs;
> -  Slave->Mode = Mode;
> -
>SpiSetupTransfer (This, Slave);
>  
>return Slave;
> diff --git a/Platform/Marvell/Drivers/Spi/MvSpiDxe.h 
> b/Platform/Marvell/Drivers/Spi/MvSpiDxe.h
> index 1401f62..e7e280a 100644
> --- a/Platform/Marvell/Drivers/Spi/MvSpiDxe.h
> +++ b/Platfor

Re: [edk2] [platforms: PATCH 3/6] Marvell/Drivers: MvSpiFlash: Remove duplicated macros

[Leif Lindholm]

On Tue, Oct 31, 2017 at 04:59:32AM +0100, Marcin Wojtas wrote:
> Flash commands macros are already defined locally, so
> remove them from the protocol header.

Locally?
I have no issue with the patch, but the commit message can be a bit
more descriptive.

/
Leif

> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Marcin Wojtas 
> ---
>  Platform/Marvell/Include/Protocol/SpiFlash.h | 11 ---
>  1 file changed, 11 deletions(-)
> 
> diff --git a/Platform/Marvell/Include/Protocol/SpiFlash.h 
> b/Platform/Marvell/Include/Protocol/SpiFlash.h
> index 4a3053e..4ba29ba 100644
> --- a/Platform/Marvell/Include/Protocol/SpiFlash.h
> +++ b/Platform/Marvell/Include/Protocol/SpiFlash.h
> @@ -36,17 +36,6 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH 
> DAMAGE.
>  
>  #include 
>  
> -#define CMD_READ_ID 0x9f
> -#define READ_STATUS_REG_CMD 0x0b
> -#define CMD_WRITE_ENABLE0x06
> -#define CMD_FLAG_STATUS 0x70
> -#define CMD_WRITE_STATUS_REG0x01
> -#define CMD_READ_ARRAY_FAST 0x0b
> -#define CMD_PAGE_PROGRAM0x02
> -#define CMD_BANK_WRITE  0xc5
> -#define CMD_ERASE_64K   0xd8
> -#define CMD_4B_ADDR_ENABLE  0xb7
> -
>  extern EFI_GUID gMarvellSpiFlashProtocolGuid;
>  
>  typedef struct _MARVELL_SPI_FLASH_PROTOCOL MARVELL_SPI_FLASH_PROTOCOL;
> -- 
> 2.7.4
> 
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Re: [edk2] [platforms: PATCH 2/6] Marvell/Drivers: MvSpiFlash: Enable dynamic SPI Flash detection

[Leif Lindholm]

On Tue, Oct 31, 2017 at 04:59:31AM +0100, Marcin Wojtas wrote:
> Hitherto mechanism of fixing SPI flash model in the PCDs,
> occured to be very inefficient and problematic. Enable
> dynamic detection by reworking MvSpiFlashReadId() command,
> which now uses newly added NorFlashInfoLib, that helps to
> obtain description of the JEDEC compliant devices.
> 
> This patch updates the MvSpiFlashProtocol ReadId() protocol
> callback on both producer's (MvFlashDxe) and consumers' sides
> (FirmwareUpdate and SpiTool applications). Because all
> information about detected SPI NOR flash is now stored in
> the obtained NorFlashInfo structure fields, use them instead
> of the PCDs.
> 
> Enable compilation of the NorFlashInfoLib and update
> PortingGuide documentation accordingly.
> 
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Marcin Wojtas 
> ---
>  Platform/Marvell/Applications/FirmwareUpdate/FUpdate.c   |  5 +-
>  Platform/Marvell/Applications/FirmwareUpdate/FUpdate.inf |  4 +-
>  Platform/Marvell/Applications/SpiTool/SpiFlashCmd.c  |  5 +-
>  Platform/Marvell/Applications/SpiTool/SpiFlashCmd.inf|  2 +-
>  Platform/Marvell/Armada/Armada.dsc.inc   |  1 +
>  Platform/Marvell/Armada/Armada70x0.dsc   |  5 --
>  Platform/Marvell/Drivers/Spi/Devices/MvSpiFlash.c| 68 
> +++-
>  Platform/Marvell/Drivers/Spi/Devices/MvSpiFlash.inf  |  9 +--
>  Platform/Marvell/Drivers/Spi/MvSpiDxe.inf|  2 +
>  Platform/Marvell/Include/Protocol/Spi.h  |  3 +
>  Platform/Marvell/Include/Protocol/SpiFlash.h |  6 +-
>  Platform/Marvell/Marvell.dec |  6 --
>  Silicon/Marvell/Documentation/PortingGuide.txt   | 18 --
>  13 files changed, 51 insertions(+), 83 deletions(-)
> 
> diff --git a/Platform/Marvell/Applications/FirmwareUpdate/FUpdate.c 
> b/Platform/Marvell/Applications/FirmwareUpdate/FUpdate.c
> index d70645d..750e52a 100644
> --- a/Platform/Marvell/Applications/FirmwareUpdate/FUpdate.c
> +++ b/Platform/Marvell/Applications/FirmwareUpdate/FUpdate.c
> @@ -94,12 +94,9 @@ SpiFlashProbe (
>)
>  {
>EFI_STATUS   Status;
> -  UINT8   *FlashId;
> -
> -  FlashId = (UINT8 *)PcdGetPtr (PcdSpiFlashId);
>  
>// Read SPI flash ID
> -  Status = SpiFlashProtocol->ReadId (Slave, NOR_FLASH_ID_DEFAULT_LEN, 
> FlashId);
> +  Status = SpiFlashProtocol->ReadId (Slave, FALSE);
>if (EFI_ERROR (Status)) {
>  return SHELL_ABORTED;
>}
> diff --git a/Platform/Marvell/Applications/FirmwareUpdate/FUpdate.inf 
> b/Platform/Marvell/Applications/FirmwareUpdate/FUpdate.inf
> index 92c..53ea491 100644
> --- a/Platform/Marvell/Applications/FirmwareUpdate/FUpdate.inf
> +++ b/Platform/Marvell/Applications/FirmwareUpdate/FUpdate.inf
> @@ -44,6 +44,7 @@
>FUpdate.uni
>  
>  [Packages]
> +  EmbeddedPkg/EmbeddedPkg.dec
>MdeModulePkg/MdeModulePkg.dec
>MdePkg/MdePkg.dec
>Platform/Marvell/Marvell.dec
> @@ -64,9 +65,6 @@
>UefiLib
>UefiRuntimeServicesTableLib
>  
> -[Pcd]
> - gMarvellTokenSpaceGuid.PcdSpiFlashId
> -
>  [Protocols]
>   gMarvellSpiFlashProtocolGuid
>   gMarvellSpiMasterProtocolGuid
> diff --git a/Platform/Marvell/Applications/SpiTool/SpiFlashCmd.c 
> b/Platform/Marvell/Applications/SpiTool/SpiFlashCmd.c
> index a12f2ec..68a6cf7 100644
> --- a/Platform/Marvell/Applications/SpiTool/SpiFlashCmd.c
> +++ b/Platform/Marvell/Applications/SpiTool/SpiFlashCmd.c
> @@ -166,11 +166,8 @@ FlashProbe (
>)
>  {
>EFI_STATUS Status;
> -  UINT8  *FlashId;
>  
> -  FlashId = (UINT8 *)PcdGetPtr (PcdSpiFlashId);
> -
> -  Status = SpiFlashProtocol->ReadId (Slave, NOR_FLASH_ID_DEFAULT_LEN, 
> FlashId);
> +  Status = SpiFlashProtocol->ReadId (Slave, FALSE);
>if (EFI_ERROR (Status)) {
>  return SHELL_ABORTED;
>}
> diff --git a/Platform/Marvell/Applications/SpiTool/SpiFlashCmd.inf 
> b/Platform/Marvell/Applications/SpiTool/SpiFlashCmd.inf
> index 887b9a5..a52906b 100644
> --- a/Platform/Marvell/Applications/SpiTool/SpiFlashCmd.inf
> +++ b/Platform/Marvell/Applications/SpiTool/SpiFlashCmd.inf
> @@ -44,6 +44,7 @@
>   SpiFlashCmd.uni
>  
>  [Packages]
> + EmbeddedPkg/EmbeddedPkg.dec
>   MdePkg/MdePkg.dec
>   ShellPkg/ShellPkg.dec
>   MdeModulePkg/MdeModulePkg.dec
> @@ -66,7 +67,6 @@
>  
>  [Pcd]
>   gMarvellTokenSpaceGuid.PcdSpiFlashCs
> - gMarvellTokenSpaceGuid.PcdSpiFlashId
>   gMarvellTokenSpaceGuid.PcdSpiFlashMode
>  
>  [Protocols]
> diff --git a/Platform/Marvell/Armada/Armada.dsc.inc 
> b/Platform/Marvell/Armada/Armada.dsc.inc
> index b9fc384..2cd96e6 100644
> --- a/Platform/Marvell/Armada/Armada.dsc.inc
> +++ b/Platform/Marvell/Armada/Armada.dsc.inc
> @@ -33,6 +33,7 @@
>
> ArmPlatformLib|Platform/Marvell/Armada/Library/Armada70x0Lib/Armada70x0Lib.inf
>ComPhyLib|Platform/Marvell/Library/ComPhyLib/ComPhyLib.inf
>MppLib|Platform/Marvell/Library/MppLib/MppLib.inf
> +  NorFlashInfoLib|EmbeddedPkg/Library/NorFlashInfoLib/Nor

Re: [edk2] [platforms: PATCH 1/6] Marvell/Drivers: MvSpiFlash: Improve ReadId

[Leif Lindholm]

On Tue, Oct 31, 2017 at 10:22:50AM +0100, Marcin Wojtas wrote:
> 2017-10-31 10:07 GMT+01:00 Leif Lindholm :
> > On Tue, Oct 31, 2017 at 04:59:30AM +0100, Marcin Wojtas wrote:
> >> Fix the ReadId routine by using master's ReadWrite callback
> >> instead of the raw Transfer - no longer swapping and byte
> >> shifting is needed. Simplify code by using local array
> >> instead of dynamic allocation. Moreover store the FlashId
> >> in an UINT8 array PCD instead of the concatenated UINT32
> >> format - this way less overhead in the driver is needed
> >> for comparing the buffers.
> >>
> >> The new handling allowed for cleaning Fupdate and Sf
> >> shell commands FlashProbe routines.
> >>
> >> Contributed-under: TianoCore Contribution Agreement 1.1
> >> Signed-off-by: Marcin Wojtas 
> >> ---
> >>  Platform/Marvell/Applications/FirmwareUpdate/FUpdate.c | 22 +++
> >>  Platform/Marvell/Applications/SpiTool/SpiFlashCmd.c| 37 
> >> ++
> >>  Platform/Marvell/Armada/Armada70x0.dsc |  2 +-
> >>  Platform/Marvell/Drivers/Spi/Devices/MvSpiFlash.c  | 41 
> >> 
> >>  Platform/Marvell/Drivers/Spi/Devices/MvSpiFlash.h  |  2 +
> >>  Platform/Marvell/Include/Protocol/SpiFlash.h   |  3 ++
> >>  Platform/Marvell/Marvell.dec   |  2 +-
> >>  7 files changed, 48 insertions(+), 61 deletions(-)
> >>
> >> diff --git a/Platform/Marvell/Applications/FirmwareUpdate/FUpdate.c 
> >> b/Platform/Marvell/Applications/FirmwareUpdate/FUpdate.c
> >> index 664411a..d70645d 100644
> >> --- a/Platform/Marvell/Applications/FirmwareUpdate/FUpdate.c
> >> +++ b/Platform/Marvell/Applications/FirmwareUpdate/FUpdate.c
> >> @@ -94,28 +94,16 @@ SpiFlashProbe (
> >>)
> >>  {
> >>EFI_STATUS   Status;
> >> -  UINT32   IdBuffer, Id, RefId;
> >> +  UINT8   *FlashId;
> >>
> >> -  Id = PcdGet32 (PcdSpiFlashId);
> >> -
> >> -  IdBuffer = CMD_READ_ID & 0xff;
> >> +  FlashId = (UINT8 *)PcdGetPtr (PcdSpiFlashId);
> >>
> >>// Read SPI flash ID
> >> -  SpiFlashProtocol->ReadId (Slave, sizeof (UINT32), (UINT8 *)&IdBuffer);
> >> -
> >> -  // Swap and extract 3 bytes of the ID
> >> -  RefId = SwapBytes32 (IdBuffer) >> 8;
> >> -
> >> -  if (RefId == 0) {
> >> -Print (L"%s: No SPI flash detected");
> >> -return EFI_DEVICE_ERROR;
> >> -  } else if (RefId != Id) {
> >> -Print (L"%s: Unsupported SPI flash detected with ID=%2x\n", 
> >> CMD_NAME_STRING, RefId);
> >> -return EFI_DEVICE_ERROR;
> >> +  Status = SpiFlashProtocol->ReadId (Slave, NOR_FLASH_ID_DEFAULT_LEN, 
> >> FlashId);
> >
> > Is the length not possible to calculate somehow?
> > Having a MAX_LEN defined and then using a DEFAULT_LEN or explicitly
> > extracting 3 bytes from somewhere feels suboptimal.
> >
> 
> I know. It is however a change that was somewhat artificially
> extracted, so that to make the next patch more readable
> (NOR_FLASH_ID_DEFAULT_LEN is removed there). I will substitute it with
> PcdGetSize (PcdSpiFlashId).

Right, OK, that sort of thing is useful to mention in the cover
letter.

But there's also MAX_ID_LEN, which is added here only to allocate
buffers that are hard-coded to always contain value of ID_DEFAULT_LEN.
Surely this could just be left out?

/
Leif
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[edk2] 答复: [PATCH 3/3] UefiCpuPkg/CpuExceptionHandlerLib: Add stack switch support

[Fan Jeff]

That’s fine. Thanks

Developers should have such assumption without exception dumping message if 
NULL instance used.

Jeff

发件人: Wang, Jian J
发送时间: 2017年11月1日 11:08
收件人: Fan Jeff; Yao, 
Jiewen; 
edk2-devel@lists.01.org
抄送: Kinney, Michael D; Dong, 
Eric; Zeng, Star
主题: RE: [PATCH 3/3] UefiCpuPkg/CpuExceptionHandlerLib: Add stack switch support

Jeff,

Stack guard will still work. But the developer cannot know what’s going on 
without exception dumping message when stack overflow occurs.

Thanks,
Jian

From: Fan Jeff [mailto:vanjeff_...@hotmail.com]
Sent: Wednesday, November 01, 2017 10:59 AM
To: Wang, Jian J ; Yao, Jiewen ; 
edk2-devel@lists.01.org
Cc: Kinney, Michael D ; Dong, Eric 
; Zeng, Star 
Subject: 答复: [PATCH 3/3] UefiCpuPkg/CpuExceptionHandlerLib: Add stack switch 
support

Jian,

No. I suggest to fix #109 in another separate patch.

But to fix #109, we have to makes sure AsmWriteTr() and some definitions are in 
MdePkg.
But I have no strong opinion to add them into MdePkg in this patch.

I have another question: If NULL CPU exception handler instance is chosen, 
could Stack Switch work if PCD PcdCpuStackGuard is set to TRUE.

Thanks!
Jeff

发件人: Wang, Jian J
发送时间: 2017年11月1日 10:48
收件人: Fan Jeff; Yao, 
Jiewen; 
edk2-devel@lists.01.org
抄送: Kinney, Michael D; Dong, 
Eric; Zeng, Star
主题: RE: [PATCH 3/3] UefiCpuPkg/CpuExceptionHandlerLib: Add stack switch support

Hi Jeff,

Thanks for the feedback. Are you suggesting to fix Bugzilla 109 in this patch?

Thanks,
Jian

From: Fan Jeff [mailto:vanjeff_...@hotmail.com]
Sent: Wednesday, November 01, 2017 10:33 AM
To: Yao, Jiewen mailto:jiewen@intel.com>>; Wang, Jian 
J mailto:jian.j.w...@intel.com>>; 
edk2-devel@lists.01.org
Cc: Kinney, Michael D 
mailto:michael.d.kin...@intel.com>>; Dong, Eric 
mailto:eric.d...@intel.com>>; Zeng, Star 
mailto:star.z...@intel.com>>
Subject: 答复: [PATCH 3/3] UefiCpuPkg/CpuExceptionHandlerLib: Add stack switch 
support

Per https://bugzilla.tianocore.org/show_bug.cgi?id=109, TR should be setup 
(Such as in DxeIplPeim) even though NULL Cpu Exception Handler instance is 
chosen.

For long term, I agree we need to move AsmWriteTr, IA32_TASK_STATE_SEGMENT, 
IA32_TSS_DESCRIPTOR to MdePkg(Such as BaseLib)
For this patch, I have no strong opinion.


发件人: Yao, Jiewen
发送时间: 2017年11月1日 9:56
收件人: Wang, Jian J; 
edk2-devel@lists.01.org
抄送: Kinney, Michael D; Dong, 
Eric; Zeng, Star
主题: Re: [edk2] [PATCH 3/3] UefiCpuPkg/CpuExceptionHandlerLib: Add stack switch 
support

Hi Jian
Thanks for the patch.

Can we move all IA32 defined data structure or function to MdePkg?
Such as: AsmWriteTr, IA32_TASK_STATE_SEGMENT, IA32_TSS_DESCRIPTOR

I am also curious why we use different policy for other boot mode.
Can we use consistent policy?
> +  if (PcdGetBool (PcdCpuStackGuard)) {
> +//
> +// Stack Guard works with the support of page table established and
> +// memory management. So we have to exclude those boot modes
> without
> +// them.
> +//
> +switch (GetBootModeHob()) {
> +case BOOT_ON_FLASH_UPDATE:
> +case BOOT_IN_RECOVERY_MODE:
> +case BOOT_ON_S3_RESUME:
> +  break;
> +
> +default:
> +  ArchSetupExcpetionStack (IdtTable);
> +  break;
> +}
> +  }


Thank you
Yao Jiewen


> -Original Message-
> From: Wang, Jian J
> Sent: Tuesday, October 31, 2017 10:24 PM
> To: edk2-devel@lists.01.org
> Cc: Zeng, Star mailto:star.z...@intel.com>>; Dong, Eric 
> mailto:eric.d...@intel.com>>; Yao,
> Jiewen mailto:jiewen@intel.com>>; Kinney, Michael D
> mailto:michael.d.kin...@intel.com>>
> Subject: [PATCH 3/3] UefiCpuPkg/CpuExceptionHandlerLib: Add stack switch
> support
>
> If Stack Guard is enabled and there's really a stack overflow happened during
> boot, a Page Fault exception will be triggered. Because the stack is out of
> usage, the exception handler, which shares the stack with normal UEFI driver,
> cannot be executed and cannot dump the processor information.
>
> Without those information, it's very difficult for the BIOS developers locate
> the root cause of stack overflow. And without a workable stack, the developer
> cannot event use single step to debug the UEFI driver with JTAG debugger.
>
> In order to make sure the exception handler to execute normally after stack
> overflow. We need separate stacks for exception han

Re: [edk2] [PATCH 3/3] UefiCpuPkg/CpuExceptionHandlerLib: Add stack switch support

[Wang, Jian J]

Jeff,

Sorry for the misunderstanding. I think stack switch cannot work with NULL 
exception handler. But without exception handler, what do we need stack switch 
for?

Thanks,
Jian

> -Original Message-
> From: edk2-devel [mailto:edk2-devel-boun...@lists.01.org] On Behalf Of Wang,
> Jian J
> Sent: Wednesday, November 01, 2017 11:09 AM
> To: Fan Jeff ; Yao, Jiewen ;
> edk2-devel@lists.01.org
> Cc: Kinney, Michael D ; Dong, Eric
> ; Zeng, Star 
> Subject: Re: [edk2] [PATCH 3/3] UefiCpuPkg/CpuExceptionHandlerLib: Add stack
> switch support
> 
> Jeff,
> 
> Stack guard will still work. But the developer cannot know what’s going on
> without exception dumping message when stack overflow occurs.
> 
> Thanks,
> Jian
> 
> From: Fan Jeff [mailto:vanjeff_...@hotmail.com]
> Sent: Wednesday, November 01, 2017 10:59 AM
> To: Wang, Jian J ; Yao, Jiewen ;
> edk2-devel@lists.01.org
> Cc: Kinney, Michael D ; Dong, Eric
> ; Zeng, Star 
> Subject: 答复: [PATCH 3/3] UefiCpuPkg/CpuExceptionHandlerLib: Add stack
> switch support
> 
> Jian,
> 
> No. I suggest to fix #109 in another separate patch.
> 
> But to fix #109, we have to makes sure AsmWriteTr() and some definitions are 
> in
> MdePkg.
> But I have no strong opinion to add them into MdePkg in this patch.
> 
> I have another question: If NULL CPU exception handler instance is chosen,
> could Stack Switch work if PCD PcdCpuStackGuard is set to TRUE.
> 
> Thanks!
> Jeff
> 
> 发件人: Wang, Jian J
> 发送时间: 2017年11月1日 10:48
> 收件人: Fan Jeff; Yao,
> Jiewen; edk2-devel@lists.01.org de...@lists.01.org>
> 抄送: Kinney, Michael D; Dong,
> Eric; Zeng, Star
> 主题: RE: [PATCH 3/3] UefiCpuPkg/CpuExceptionHandlerLib: Add stack switch
> support
> 
> Hi Jeff,
> 
> Thanks for the feedback. Are you suggesting to fix Bugzilla 109 in this patch?
> 
> Thanks,
> Jian
> 
> From: Fan Jeff [mailto:vanjeff_...@hotmail.com]
> Sent: Wednesday, November 01, 2017 10:33 AM
> To: Yao, Jiewen mailto:jiewen@intel.com>>;
> Wang, Jian J mailto:jian.j.w...@intel.com>>; edk2-
> de...@lists.01.org
> Cc: Kinney, Michael D
> mailto:michael.d.kin...@intel.com>>; Dong, Eric
> mailto:eric.d...@intel.com>>; Zeng, Star
> mailto:star.z...@intel.com>>
> Subject: 答复: [PATCH 3/3] UefiCpuPkg/CpuExceptionHandlerLib: Add stack
> switch support
> 
> Per https://bugzilla.tianocore.org/show_bug.cgi?id=109, TR should be setup
> (Such as in DxeIplPeim) even though NULL Cpu Exception Handler instance is
> chosen.
> 
> For long term, I agree we need to move AsmWriteTr,
> IA32_TASK_STATE_SEGMENT, IA32_TSS_DESCRIPTOR to MdePkg(Such as
> BaseLib)
> For this patch, I have no strong opinion.
> 
> 
> 发件人: Yao, Jiewen
> 发送时间: 2017年11月1日 9:56
> 收件人: Wang, Jian J; edk2-
> de...@lists.01.org
> 抄送: Kinney, Michael D; Dong,
> Eric; Zeng, Star
> 主题: Re: [edk2] [PATCH 3/3] UefiCpuPkg/CpuExceptionHandlerLib: Add stack
> switch support
> 
> Hi Jian
> Thanks for the patch.
> 
> Can we move all IA32 defined data structure or function to MdePkg?
> Such as: AsmWriteTr, IA32_TASK_STATE_SEGMENT, IA32_TSS_DESCRIPTOR
> 
> I am also curious why we use different policy for other boot mode.
> Can we use consistent policy?
> > +  if (PcdGetBool (PcdCpuStackGuard)) {
> > +//
> > +// Stack Guard works with the support of page table established and
> > +// memory management. So we have to exclude those boot modes
> > without
> > +// them.
> > +//
> > +switch (GetBootModeHob()) {
> > +case BOOT_ON_FLASH_UPDATE:
> > +case BOOT_IN_RECOVERY_MODE:
> > +case BOOT_ON_S3_RESUME:
> > +  break;
> > +
> > +default:
> > +  ArchSetupExcpetionStack (IdtTable);
> > +  break;
> > +}
> > +  }
> 
> 
> Thank you
> Yao Jiewen
> 
> 
> > -Original Message-
> > From: Wang, Jian J
> > Sent: Tuesday, October 31, 2017 10:24 PM
> > To: edk2-devel@lists.01.org
> > Cc: Zeng, Star mailto:star.z...@intel.com>>; Dong,
> Eric mailto:eric.d...@intel.com>>; Yao,
> > Jiewen mailto:jiewen@intel.com>>; Kinney,
> Michael D
> > mailto:michael.d.kin...@intel.com>>
> > Subject: [PATCH 3/3] UefiCpuPkg/CpuExceptionHandlerLib: Add stack switch
> > support
> >
> > If Stack Guard is enabled and there's really a stack overflow happened 
> > during
> > boot, a Page Fault exception will be triggered. Because the stack is out of
> > usage, the exception handler, which shares the stack with normal UEFI 
> > driver,
> > cannot be executed and cannot dump the processor information.
> >
> > Without those information, it's very difficult for the BIOS developers 
> > locate
> > the root cause of stack overflow. And

Re: [edk2] [PATCH 3/3] UefiCpuPkg/CpuExceptionHandlerLib: Add stack switch support

[Wang, Jian J]

Jeff,

Stack guard will still work. But the developer cannot know what’s going on 
without exception dumping message when stack overflow occurs.

Thanks,
Jian

From: Fan Jeff [mailto:vanjeff_...@hotmail.com]
Sent: Wednesday, November 01, 2017 10:59 AM
To: Wang, Jian J ; Yao, Jiewen ; 
edk2-devel@lists.01.org
Cc: Kinney, Michael D ; Dong, Eric 
; Zeng, Star 
Subject: 答复: [PATCH 3/3] UefiCpuPkg/CpuExceptionHandlerLib: Add stack switch 
support

Jian,

No. I suggest to fix #109 in another separate patch.

But to fix #109, we have to makes sure AsmWriteTr() and some definitions are in 
MdePkg.
But I have no strong opinion to add them into MdePkg in this patch.

I have another question: If NULL CPU exception handler instance is chosen, 
could Stack Switch work if PCD PcdCpuStackGuard is set to TRUE.

Thanks!
Jeff

发件人: Wang, Jian J
发送时间: 2017年11月1日 10:48
收件人: Fan Jeff; Yao, 
Jiewen; 
edk2-devel@lists.01.org
抄送: Kinney, Michael D; Dong, 
Eric; Zeng, Star
主题: RE: [PATCH 3/3] UefiCpuPkg/CpuExceptionHandlerLib: Add stack switch support

Hi Jeff,

Thanks for the feedback. Are you suggesting to fix Bugzilla 109 in this patch?

Thanks,
Jian

From: Fan Jeff [mailto:vanjeff_...@hotmail.com]
Sent: Wednesday, November 01, 2017 10:33 AM
To: Yao, Jiewen mailto:jiewen@intel.com>>; Wang, Jian 
J mailto:jian.j.w...@intel.com>>; 
edk2-devel@lists.01.org
Cc: Kinney, Michael D 
mailto:michael.d.kin...@intel.com>>; Dong, Eric 
mailto:eric.d...@intel.com>>; Zeng, Star 
mailto:star.z...@intel.com>>
Subject: 答复: [PATCH 3/3] UefiCpuPkg/CpuExceptionHandlerLib: Add stack switch 
support

Per https://bugzilla.tianocore.org/show_bug.cgi?id=109, TR should be setup 
(Such as in DxeIplPeim) even though NULL Cpu Exception Handler instance is 
chosen.

For long term, I agree we need to move AsmWriteTr, IA32_TASK_STATE_SEGMENT, 
IA32_TSS_DESCRIPTOR to MdePkg(Such as BaseLib)
For this patch, I have no strong opinion.


发件人: Yao, Jiewen
发送时间: 2017年11月1日 9:56
收件人: Wang, Jian J; 
edk2-devel@lists.01.org
抄送: Kinney, Michael D; Dong, 
Eric; Zeng, Star
主题: Re: [edk2] [PATCH 3/3] UefiCpuPkg/CpuExceptionHandlerLib: Add stack switch 
support

Hi Jian
Thanks for the patch.

Can we move all IA32 defined data structure or function to MdePkg?
Such as: AsmWriteTr, IA32_TASK_STATE_SEGMENT, IA32_TSS_DESCRIPTOR

I am also curious why we use different policy for other boot mode.
Can we use consistent policy?
> +  if (PcdGetBool (PcdCpuStackGuard)) {
> +//
> +// Stack Guard works with the support of page table established and
> +// memory management. So we have to exclude those boot modes
> without
> +// them.
> +//
> +switch (GetBootModeHob()) {
> +case BOOT_ON_FLASH_UPDATE:
> +case BOOT_IN_RECOVERY_MODE:
> +case BOOT_ON_S3_RESUME:
> +  break;
> +
> +default:
> +  ArchSetupExcpetionStack (IdtTable);
> +  break;
> +}
> +  }


Thank you
Yao Jiewen


> -Original Message-
> From: Wang, Jian J
> Sent: Tuesday, October 31, 2017 10:24 PM
> To: edk2-devel@lists.01.org
> Cc: Zeng, Star mailto:star.z...@intel.com>>; Dong, Eric 
> mailto:eric.d...@intel.com>>; Yao,
> Jiewen mailto:jiewen@intel.com>>; Kinney, Michael D
> mailto:michael.d.kin...@intel.com>>
> Subject: [PATCH 3/3] UefiCpuPkg/CpuExceptionHandlerLib: Add stack switch
> support
>
> If Stack Guard is enabled and there's really a stack overflow happened during
> boot, a Page Fault exception will be triggered. Because the stack is out of
> usage, the exception handler, which shares the stack with normal UEFI driver,
> cannot be executed and cannot dump the processor information.
>
> Without those information, it's very difficult for the BIOS developers locate
> the root cause of stack overflow. And without a workable stack, the developer
> cannot event use single step to debug the UEFI driver with JTAG debugger.
>
> In order to make sure the exception handler to execute normally after stack
> overflow. We need separate stacks for exception handlers in case of unusable
> stack.
>
> IA processor allows to switch to a new stack during handling interrupt and
> exception. But X64 and IA32 provides different ways to make it. X64 provides
> interrupt stack table (IST) to allow maximum 7 different exceptions to have
> new stack for its handler. IA32 doesn't have IST mechanism and can only use
> task gate to do it since task switch allows to load a new stack through its
> task-state segment (TSS).
>
> Note: Stack switch needs to allocate memory pages to be new stacks. So this
>   functionality works

[edk2] 答复: [PATCH 3/3] UefiCpuPkg/CpuExceptionHandlerLib: Add stack switch support

[Fan Jeff]

Jian,

No. I suggest to fix #109 in another separate patch.

But to fix #109, we have to makes sure AsmWriteTr() and some definitions are in 
MdePkg.
But I have no strong opinion to add them into MdePkg in this patch.

I have another question: If NULL CPU exception handler instance is chosen, 
could Stack Switch work if PCD PcdCpuStackGuard is set to TRUE.

Thanks!
Jeff

发件人: Wang, Jian J
发送时间: 2017年11月1日 10:48
收件人: Fan Jeff; Yao, 
Jiewen; 
edk2-devel@lists.01.org
抄送: Kinney, Michael D; Dong, 
Eric; Zeng, Star
主题: RE: [PATCH 3/3] UefiCpuPkg/CpuExceptionHandlerLib: Add stack switch support

Hi Jeff,

Thanks for the feedback. Are you suggesting to fix Bugzilla 109 in this patch?

Thanks,
Jian

From: Fan Jeff [mailto:vanjeff_...@hotmail.com]
Sent: Wednesday, November 01, 2017 10:33 AM
To: Yao, Jiewen ; Wang, Jian J ; 
edk2-devel@lists.01.org
Cc: Kinney, Michael D ; Dong, Eric 
; Zeng, Star 
Subject: 答复: [PATCH 3/3] UefiCpuPkg/CpuExceptionHandlerLib: Add stack switch 
support

Per https://bugzilla.tianocore.org/show_bug.cgi?id=109, TR should be setup 
(Such as in DxeIplPeim) even though NULL Cpu Exception Handler instance is 
chosen.

For long term, I agree we need to move AsmWriteTr, IA32_TASK_STATE_SEGMENT, 
IA32_TSS_DESCRIPTOR to MdePkg(Such as BaseLib)
For this patch, I have no strong opinion.


发件人: Yao, Jiewen
发送时间: 2017年11月1日 9:56
收件人: Wang, Jian J; 
edk2-devel@lists.01.org
抄送: Kinney, Michael D; Dong, 
Eric; Zeng, Star
主题: Re: [edk2] [PATCH 3/3] UefiCpuPkg/CpuExceptionHandlerLib: Add stack switch 
support

Hi Jian
Thanks for the patch.

Can we move all IA32 defined data structure or function to MdePkg?
Such as: AsmWriteTr, IA32_TASK_STATE_SEGMENT, IA32_TSS_DESCRIPTOR

I am also curious why we use different policy for other boot mode.
Can we use consistent policy?
> +  if (PcdGetBool (PcdCpuStackGuard)) {
> +//
> +// Stack Guard works with the support of page table established and
> +// memory management. So we have to exclude those boot modes
> without
> +// them.
> +//
> +switch (GetBootModeHob()) {
> +case BOOT_ON_FLASH_UPDATE:
> +case BOOT_IN_RECOVERY_MODE:
> +case BOOT_ON_S3_RESUME:
> +  break;
> +
> +default:
> +  ArchSetupExcpetionStack (IdtTable);
> +  break;
> +}
> +  }


Thank you
Yao Jiewen


> -Original Message-
> From: Wang, Jian J
> Sent: Tuesday, October 31, 2017 10:24 PM
> To: edk2-devel@lists.01.org
> Cc: Zeng, Star mailto:star.z...@intel.com>>; Dong, Eric 
> mailto:eric.d...@intel.com>>; Yao,
> Jiewen mailto:jiewen@intel.com>>; Kinney, Michael D
> mailto:michael.d.kin...@intel.com>>
> Subject: [PATCH 3/3] UefiCpuPkg/CpuExceptionHandlerLib: Add stack switch
> support
>
> If Stack Guard is enabled and there's really a stack overflow happened during
> boot, a Page Fault exception will be triggered. Because the stack is out of
> usage, the exception handler, which shares the stack with normal UEFI driver,
> cannot be executed and cannot dump the processor information.
>
> Without those information, it's very difficult for the BIOS developers locate
> the root cause of stack overflow. And without a workable stack, the developer
> cannot event use single step to debug the UEFI driver with JTAG debugger.
>
> In order to make sure the exception handler to execute normally after stack
> overflow. We need separate stacks for exception handlers in case of unusable
> stack.
>
> IA processor allows to switch to a new stack during handling interrupt and
> exception. But X64 and IA32 provides different ways to make it. X64 provides
> interrupt stack table (IST) to allow maximum 7 different exceptions to have
> new stack for its handler. IA32 doesn't have IST mechanism and can only use
> task gate to do it since task switch allows to load a new stack through its
> task-state segment (TSS).
>
> Note: Stack switch needs to allocate memory pages to be new stacks. So this
>   functionality works only in the boot phases capable of memory
>   allocation (besides the paging, for the sake of Stack Guard). In
>   other words, only DXE phase can supports Stack Guard with stack switch.
>
> Cc: Star Zeng mailto:star.z...@intel.com>>
> Cc: Eric Dong mailto:eric.d...@intel.com>>
> Cc: Jiewen Yao mailto:jiewen@intel.com>>
> Cc: Michael Kinney 
> mailto:michael.d.kin...@intel.com>>
> Suggested-by: Ayellet Wolman 
> mailto:ayellet.wol...@intel.com>>
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Jian J Wang 
> mailto:jian.j.w...@intel.com>>
> ---
>  .../CpuExceptionHandlerLib/CpuException

Re: [edk2] [PATCH 3/3] UefiCpuPkg/CpuExceptionHandlerLib: Add stack switch support

[Wang, Jian J]

Hi Jeff,

Thanks for the feedback. Are you suggesting to fix Bugzilla 109 in this patch?

Thanks,
Jian

From: Fan Jeff [mailto:vanjeff_...@hotmail.com]
Sent: Wednesday, November 01, 2017 10:33 AM
To: Yao, Jiewen ; Wang, Jian J ; 
edk2-devel@lists.01.org
Cc: Kinney, Michael D ; Dong, Eric 
; Zeng, Star 
Subject: 答复: [PATCH 3/3] UefiCpuPkg/CpuExceptionHandlerLib: Add stack switch 
support

Per https://bugzilla.tianocore.org/show_bug.cgi?id=109, TR should be setup 
(Such as in DxeIplPeim) even though NULL Cpu Exception Handler instance is 
chosen.

For long term, I agree we need to move AsmWriteTr, IA32_TASK_STATE_SEGMENT, 
IA32_TSS_DESCRIPTOR to MdePkg(Such as BaseLib)
For this patch, I have no strong opinion.


发件人: Yao, Jiewen
发送时间: 2017年11月1日 9:56
收件人: Wang, Jian J; 
edk2-devel@lists.01.org
抄送: Kinney, Michael D; Dong, 
Eric; Zeng, Star
主题: Re: [edk2] [PATCH 3/3] UefiCpuPkg/CpuExceptionHandlerLib: Add stack switch 
support

Hi Jian
Thanks for the patch.

Can we move all IA32 defined data structure or function to MdePkg?
Such as: AsmWriteTr, IA32_TASK_STATE_SEGMENT, IA32_TSS_DESCRIPTOR

I am also curious why we use different policy for other boot mode.
Can we use consistent policy?
> +  if (PcdGetBool (PcdCpuStackGuard)) {
> +//
> +// Stack Guard works with the support of page table established and
> +// memory management. So we have to exclude those boot modes
> without
> +// them.
> +//
> +switch (GetBootModeHob()) {
> +case BOOT_ON_FLASH_UPDATE:
> +case BOOT_IN_RECOVERY_MODE:
> +case BOOT_ON_S3_RESUME:
> +  break;
> +
> +default:
> +  ArchSetupExcpetionStack (IdtTable);
> +  break;
> +}
> +  }


Thank you
Yao Jiewen


> -Original Message-
> From: Wang, Jian J
> Sent: Tuesday, October 31, 2017 10:24 PM
> To: edk2-devel@lists.01.org
> Cc: Zeng, Star mailto:star.z...@intel.com>>; Dong, Eric 
> mailto:eric.d...@intel.com>>; Yao,
> Jiewen mailto:jiewen@intel.com>>; Kinney, Michael D
> mailto:michael.d.kin...@intel.com>>
> Subject: [PATCH 3/3] UefiCpuPkg/CpuExceptionHandlerLib: Add stack switch
> support
>
> If Stack Guard is enabled and there's really a stack overflow happened during
> boot, a Page Fault exception will be triggered. Because the stack is out of
> usage, the exception handler, which shares the stack with normal UEFI driver,
> cannot be executed and cannot dump the processor information.
>
> Without those information, it's very difficult for the BIOS developers locate
> the root cause of stack overflow. And without a workable stack, the developer
> cannot event use single step to debug the UEFI driver with JTAG debugger.
>
> In order to make sure the exception handler to execute normally after stack
> overflow. We need separate stacks for exception handlers in case of unusable
> stack.
>
> IA processor allows to switch to a new stack during handling interrupt and
> exception. But X64 and IA32 provides different ways to make it. X64 provides
> interrupt stack table (IST) to allow maximum 7 different exceptions to have
> new stack for its handler. IA32 doesn't have IST mechanism and can only use
> task gate to do it since task switch allows to load a new stack through its
> task-state segment (TSS).
>
> Note: Stack switch needs to allocate memory pages to be new stacks. So this
>   functionality works only in the boot phases capable of memory
>   allocation (besides the paging, for the sake of Stack Guard). In
>   other words, only DXE phase can supports Stack Guard with stack switch.
>
> Cc: Star Zeng mailto:star.z...@intel.com>>
> Cc: Eric Dong mailto:eric.d...@intel.com>>
> Cc: Jiewen Yao mailto:jiewen@intel.com>>
> Cc: Michael Kinney 
> mailto:michael.d.kin...@intel.com>>
> Suggested-by: Ayellet Wolman 
> mailto:ayellet.wol...@intel.com>>
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Jian J Wang 
> mailto:jian.j.w...@intel.com>>
> ---
>  .../CpuExceptionHandlerLib/CpuExceptionCommon.h|  22 ++
>  .../DxeCpuExceptionHandlerLib.inf  |   5 +
>  .../Library/CpuExceptionHandlerLib/DxeException.c  |  19 +
>  .../Ia32/ArchExceptionHandler.c| 135 +++
>  .../Ia32/ArchInterruptDefs.h   | 136 +++
>  .../Ia32/ExceptionTssEntryAsm.nasm | 398
> +
>  .../PeiCpuExceptionHandlerLib.inf  |   1 +
>  .../SecPeiCpuExceptionHandlerLib.inf   |   3 +
>  .../SmmCpuExceptionHandlerLib.inf  |   1 +
>  .../X64/ArchExceptionHandler.c | 108 ++
>  .../CpuExceptionHandlerLib/X64/ArchInterruptDefs.h |  40 +++
>  .../X64/ExceptionHandlerAsm.S  |  12 +
>  .../X64/ExceptionHandlerAsm.asm|  12 +
>  ..

Re: [edk2] [PATCH 3/3] UefiCpuPkg/CpuExceptionHandlerLib: Add stack switch support

[Wang, Jian J]

Hi Jeff,

Thanks for the feedback.

From: Fan Jeff [mailto:vanjeff_...@hotmail.com]
Sent: Wednesday, November 01, 2017 10:37 AM
To: Wang, Jian J ; edk2-devel@lists.01.org
Cc: Kinney, Michael D ; Yao, Jiewen 
; Dong, Eric ; Zeng, Star 

Subject: 答复: [edk2] [PATCH 3/3] UefiCpuPkg/CpuExceptionHandlerLib: Add stack 
switch support


1.  Should add EFIAPI for the following function.
+VOID
+AsmWriteTr (
+  UINT16 Selector
+  );


2.  Should not add EFIAPI for the following function.
+VOID
+EFIAPI
+ArchSetupExcpetionStack (
+  IN IA32_IDT_GATE_DESCRIPTOR   *IdtTable
+  )

发件人: Jian J Wang
发送时间: 2017年10月31日 22:26
收件人: edk2-devel@lists.01.org
抄送: Michael Kinney; Jiewen 
Yao; Eric Dong; Star 
Zeng
主题: [edk2] [PATCH 3/3] UefiCpuPkg/CpuExceptionHandlerLib: Add stack switch 
support

If Stack Guard is enabled and there's really a stack overflow happened during
boot, a Page Fault exception will be triggered. Because the stack is out of
usage, the exception handler, which shares the stack with normal UEFI driver,
cannot be executed and cannot dump the processor information.

Without those information, it's very difficult for the BIOS developers locate
the root cause of stack overflow. And without a workable stack, the developer
cannot event use single step to debug the UEFI driver with JTAG debugger.

In order to make sure the exception handler to execute normally after stack
overflow. We need separate stacks for exception handlers in case of unusable
stack.

IA processor allows to switch to a new stack during handling interrupt and
exception. But X64 and IA32 provides different ways to make it. X64 provides
interrupt stack table (IST) to allow maximum 7 different exceptions to have
new stack for its handler. IA32 doesn't have IST mechanism and can only use
task gate to do it since task switch allows to load a new stack through its
task-state segment (TSS).

Note: Stack switch needs to allocate memory pages to be new stacks. So this
  functionality works only in the boot phases capable of memory
  allocation (besides the paging, for the sake of Stack Guard). In
  other words, only DXE phase can supports Stack Guard with stack switch.

Cc: Star Zeng mailto:star.z...@intel.com>>
Cc: Eric Dong mailto:eric.d...@intel.com>>
Cc: Jiewen Yao mailto:jiewen@intel.com>>
Cc: Michael Kinney 
mailto:michael.d.kin...@intel.com>>
Suggested-by: Ayellet Wolman 
mailto:ayellet.wol...@intel.com>>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Jian J Wang mailto:jian.j.w...@intel.com>>
---
 .../CpuExceptionHandlerLib/CpuExceptionCommon.h|  22 ++
 .../DxeCpuExceptionHandlerLib.inf  |   5 +
 .../Library/CpuExceptionHandlerLib/DxeException.c  |  19 +
 .../Ia32/ArchExceptionHandler.c| 135 +++
 .../Ia32/ArchInterruptDefs.h   | 136 +++
 .../Ia32/ExceptionTssEntryAsm.nasm | 398 +
 .../PeiCpuExceptionHandlerLib.inf  |   1 +
 .../SecPeiCpuExceptionHandlerLib.inf   |   3 +
 .../SmmCpuExceptionHandlerLib.inf  |   1 +
 .../X64/ArchExceptionHandler.c | 108 ++
 .../CpuExceptionHandlerLib/X64/ArchInterruptDefs.h |  40 +++
 .../X64/ExceptionHandlerAsm.S  |  12 +
 .../X64/ExceptionHandlerAsm.asm|  12 +
 .../X64/ExceptionHandlerAsm.nasm   |  12 +
 14 files changed, 904 insertions(+)
 create mode 100644 
UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ExceptionTssEntryAsm.nasm

diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.h 
b/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.h
index 740a58828b..fd4a26a458 100644
--- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.h
+++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.h
@@ -25,6 +25,7 @@
 #include 
 #include 
 #include 
+#include 

 #define  CPU_EXCEPTION_NUM  32
 #define  CPU_INTERRUPT_NUM 256
@@ -288,5 +289,26 @@ CommonExceptionHandlerWorker (
   IN EXCEPTION_HANDLER_DATA  *ExceptionHandlerData
   );

+/**
+  Load given selector into TR register
+
+  @param Selector Task segment selector
+**/
+VOID
+AsmWriteTr (
+  UINT16 Selector
+  );
+
+/**
+  Setup separate stack for specific exceptions.
+
+  @param[in] IdtTableIDT table base.
+**/
+VOID
+EFIAPI
+ArchSetupExcpetionStack (
+  IN IA32_IDT_GATE_DESCRIPTOR   *IdtTable
+  );
+
 #endif

diff --git 
a/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandlerLib.inf 
b/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandlerLib.inf
index f4a8d01c80..b099ef4dad 100644
--- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandlerLib.inf
+++ b/UefiCpuPkg/Library/CpuException

[edk2] 答复: [PATCH] MdeModulePkg/PciBus: Disable BME of all devices when entering RT

[Fan Jeff]

Minimal comment: To use DEBUG_INFO instead of EFI_D_INFO for consistence in 
this patch.
+DEBUG ((
+  EFI_D_INFO,"  %02x   %02x  %02x %04x\n",
+  PciIoDevice->BusNumber, PciIoDevice->DeviceNumber, 
PciIoDevice->FunctionNumber,
+  Command
+  ));
发件人: Ruiyu Ni
发送时间: 2017年10月31日 15:54
收件人: edk2-devel@lists.01.org
抄送: Michael D Kinney; Michael 
Turner; Jiewen 
Yao
主题: [edk2] [PATCH] MdeModulePkg/PciBus: Disable BME of all devices when 
entering RT

The patch assumes IOMMU protections are disabled after PciBus
disables the BMT bit in Command register.
It ensures all DMA transactions are protected by IOMMU.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Michael Turner 
Signed-off-by: Ruiyu Ni 
Cc: Michael D Kinney 
Cc: Jiewen Yao 
---
 MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h   |  2 +
 MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf  |  3 +
 MdeModulePkg/Bus/Pci/PciBusDxe/PciDeviceSupport.c | 86 +++
 3 files changed, 91 insertions(+)

diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h 
b/MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h
index 55eb3a5a80..79b5b71082 100644
--- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h
+++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h
@@ -18,6 +18,8 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER 
EXPRESS OR IMPLIED.

 #include 

+#include 
+
 #include 
 #include 
 #include 
diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf 
b/MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
index 97608bfcf2..d5b8fab3ca 100644
--- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
+++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
@@ -80,6 +80,9 @@ [LibraryClasses]
   DebugLib
   PeCoffLib

+[Guids]
+  gEfiEventExitBootServicesGuid   ## SOMETIMES_CONSUMES ## 
Event
+
 [Protocols]
   gEfiPciHotPlugRequestProtocolGuid   ## SOMETIMES_PRODUCES
   gEfiPciIoProtocolGuid   ## BY_START
diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciDeviceSupport.c 
b/MdeModulePkg/Bus/Pci/PciBusDxe/PciDeviceSupport.c
index 97bb971a59..b5530a13d1 100644
--- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciDeviceSupport.c
+++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciDeviceSupport.c
@@ -21,6 +21,72 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER 
EXPRESS OR IMPLIED.
 LIST_ENTRY  mPciDevicePool;

 /**
+ Disable Bus Master Enable bit in all devices in the list.
+
+ @param Devices  A device list.
+**/
+VOID
+DisableBmeOnTree (
+  IN LIST_ENTRY  *Devices
+  )
+{
+  LIST_ENTRY  *Link;
+  PCI_IO_DEVICE   *PciIoDevice;
+  UINT16   Command;
+
+  for ( Link = GetFirstNode (Devices)
+  ; !IsNull (Devices, Link)
+  ; Link = GetNextNode (Devices, Link)
+  ) {
+PciIoDevice = PCI_IO_DEVICE_FROM_LINK (Link);
+//
+// Turn off all children's Bus Master, if any
+//
+DisableBmeOnTree (&PciIoDevice->ChildList);
+
+//
+// If this is a device that supports BME, disable BME on this device.
+//
+if ((PciIoDevice->Supports & EFI_PCI_IO_ATTRIBUTE_BUS_MASTER) != 0) {
+  PCI_READ_COMMAND_REGISTER(PciIoDevice, &Command);
+  if ((Command & EFI_PCI_COMMAND_BUS_MASTER) != 0) {
+Command &= ~EFI_PCI_COMMAND_BUS_MASTER;
+PCI_SET_COMMAND_REGISTER (PciIoDevice, Command);
+DEBUG ((
+  EFI_D_INFO,"  %02x   %02x  %02x %04x\n",
+  PciIoDevice->BusNumber, PciIoDevice->DeviceNumber, 
PciIoDevice->FunctionNumber,
+  Command
+  ));
+  }
+}
+  }
+}
+
+/**
+  Exit Boot Services Event notification handler.
+
+  Disable Bus Master on any that were enabled during BDS.
+
+  @param[in]  Event Event whose notification function is being invoked.
+  @param[in]  Context   Pointer to the notification function's context.
+
+**/
+VOID
+EFIAPI
+OnExitBootServices (
+  IN  EFI_EVENT Event,
+  IN  VOID  *Context
+  )
+{
+  DEBUG ((
+DEBUG_INFO,
+"PciBus: Disable Bus Master of all devices...\n"
+"  Bus# Device# Function#  NewCommand\n"
+));
+  DisableBmeOnTree(&mPciDevicePool);
+}
+
+/**
   Initialize the PCI devices pool.

 **/
@@ -29,7 +95,27 @@ InitializePciDevicePool (
   VOID
   )
 {
+  EFI_EVENT   ExitBootServicesEvent;
+  EFI_STATUS  Status;
+
   InitializeListHead (&mPciDevicePool);
+
+  //
+  // DisableBME on ExitBootServices should be synchonized with any IOMMU 
ExitBootServices routine.
+  // DisableBME should be run before the IOMMU protections are disabled.
+  // One way to do this is to ensure that the IOMMU ExitBootServices callback 
runs at TPL_CALLBACK.
+  //
+  Status = gBS->CreateEventEx (
+  EVT_NOTIFY_SIGNAL,
+  TPL_NOTIFY,
+  OnExitBootServices,
+  NULL,
+  &gEfiEventExitB

[edk2] 答复: [PATCH 3/3] UefiCpuPkg/CpuExceptionHandlerLib: Add stack switch support

[Fan Jeff]

1. Should add EFIAPI for the following function.
+VOID
+AsmWriteTr (
+  UINT16 Selector
+  );


2. Should not add EFIAPI for the following function.
+VOID
+EFIAPI
+ArchSetupExcpetionStack (
+  IN IA32_IDT_GATE_DESCRIPTOR   *IdtTable
+  )

发件人: Jian J Wang
发送时间: 2017年10月31日 22:26
收件人: edk2-devel@lists.01.org
抄送: Michael Kinney; Jiewen 
Yao; Eric Dong; Star 
Zeng
主题: [edk2] [PATCH 3/3] UefiCpuPkg/CpuExceptionHandlerLib: Add stack switch 
support

If Stack Guard is enabled and there's really a stack overflow happened during
boot, a Page Fault exception will be triggered. Because the stack is out of
usage, the exception handler, which shares the stack with normal UEFI driver,
cannot be executed and cannot dump the processor information.

Without those information, it's very difficult for the BIOS developers locate
the root cause of stack overflow. And without a workable stack, the developer
cannot event use single step to debug the UEFI driver with JTAG debugger.

In order to make sure the exception handler to execute normally after stack
overflow. We need separate stacks for exception handlers in case of unusable
stack.

IA processor allows to switch to a new stack during handling interrupt and
exception. But X64 and IA32 provides different ways to make it. X64 provides
interrupt stack table (IST) to allow maximum 7 different exceptions to have
new stack for its handler. IA32 doesn't have IST mechanism and can only use
task gate to do it since task switch allows to load a new stack through its
task-state segment (TSS).

Note: Stack switch needs to allocate memory pages to be new stacks. So this
  functionality works only in the boot phases capable of memory
  allocation (besides the paging, for the sake of Stack Guard). In
  other words, only DXE phase can supports Stack Guard with stack switch.

Cc: Star Zeng 
Cc: Eric Dong 
Cc: Jiewen Yao 
Cc: Michael Kinney 
Suggested-by: Ayellet Wolman 
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Jian J Wang 
---
 .../CpuExceptionHandlerLib/CpuExceptionCommon.h|  22 ++
 .../DxeCpuExceptionHandlerLib.inf  |   5 +
 .../Library/CpuExceptionHandlerLib/DxeException.c  |  19 +
 .../Ia32/ArchExceptionHandler.c| 135 +++
 .../Ia32/ArchInterruptDefs.h   | 136 +++
 .../Ia32/ExceptionTssEntryAsm.nasm | 398 +
 .../PeiCpuExceptionHandlerLib.inf  |   1 +
 .../SecPeiCpuExceptionHandlerLib.inf   |   3 +
 .../SmmCpuExceptionHandlerLib.inf  |   1 +
 .../X64/ArchExceptionHandler.c | 108 ++
 .../CpuExceptionHandlerLib/X64/ArchInterruptDefs.h |  40 +++
 .../X64/ExceptionHandlerAsm.S  |  12 +
 .../X64/ExceptionHandlerAsm.asm|  12 +
 .../X64/ExceptionHandlerAsm.nasm   |  12 +
 14 files changed, 904 insertions(+)
 create mode 100644 
UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ExceptionTssEntryAsm.nasm

diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.h 
b/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.h
index 740a58828b..fd4a26a458 100644
--- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.h
+++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.h
@@ -25,6 +25,7 @@
 #include 
 #include 
 #include 
+#include 

 #define  CPU_EXCEPTION_NUM  32
 #define  CPU_INTERRUPT_NUM 256
@@ -288,5 +289,26 @@ CommonExceptionHandlerWorker (
   IN EXCEPTION_HANDLER_DATA  *ExceptionHandlerData
   );

+/**
+  Load given selector into TR register
+
+  @param Selector Task segment selector
+**/
+VOID
+AsmWriteTr (
+  UINT16 Selector
+  );
+
+/**
+  Setup separate stack for specific exceptions.
+
+  @param[in] IdtTableIDT table base.
+**/
+VOID
+EFIAPI
+ArchSetupExcpetionStack (
+  IN IA32_IDT_GATE_DESCRIPTOR   *IdtTable
+  );
+
 #endif

diff --git 
a/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandlerLib.inf 
b/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandlerLib.inf
index f4a8d01c80..b099ef4dad 100644
--- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandlerLib.inf
+++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandlerLib.inf
@@ -30,6 +30,7 @@
 [Sources.Ia32]
   Ia32/ExceptionHandlerAsm.asm
   Ia32/ExceptionHandlerAsm.nasm
+  Ia32/ExceptionTssEntryAsm.nasm
   Ia32/ExceptionHandlerAsm.S
   Ia32/ArchExceptionHandler.c
   Ia32/ArchInterruptDefs.h
@@ -47,6 +48,9 @@
   PeiDxeSmmCpuException.c
   DxeException.c

+[Pcd]
+  gEfiMdeModulePkgTokenSpaceGuid.PcdCpuStackGuard
+
 [Packages]
   MdePkg/MdePkg.dec
   MdeModulePkg/MdeModulePkg.dec
@@ -61,3 +65,4 @@
   PeCoffGetEntryPointLib
   MemoryAllocationLi

Re: [edk2] [PATCH 3/3] UefiCpuPkg/CpuExceptionHandlerLib: Add stack switch support

[Wang, Jian J]

Hi Jiewen,

Thanks for the feedback. 

> -Original Message-
> From: Yao, Jiewen
> Sent: Wednesday, November 01, 2017 9:57 AM
> To: Wang, Jian J ; edk2-devel@lists.01.org
> Cc: Zeng, Star ; Dong, Eric ;
> Kinney, Michael D 
> Subject: RE: [PATCH 3/3] UefiCpuPkg/CpuExceptionHandlerLib: Add stack switch
> support
> 
> Hi Jian
> Thanks for the patch.
> 
> Can we move all IA32 defined data structure or function to MdePkg?
> Such as: AsmWriteTr, IA32_TASK_STATE_SEGMENT, IA32_TSS_DESCRIPTOR
> 

Sure we can.

> I am also curious why we use different policy for other boot mode.
> Can we use consistent policy?
> > +  if (PcdGetBool (PcdCpuStackGuard)) {
> > +//
> > +// Stack Guard works with the support of page table established and
> > +// memory management. So we have to exclude those boot modes
> > without
> > +// them.
> > +//
> > +switch (GetBootModeHob()) {
> > +case BOOT_ON_FLASH_UPDATE:
> > +case BOOT_IN_RECOVERY_MODE:
> > +case BOOT_ON_S3_RESUME:
> > +  break;
> > +
> > +default:
> > +  ArchSetupExcpetionStack (IdtTable);
> > +  break;
> > +}
> > +  }
> 

As far as I'm aware of, those boot modes cannot provide both paging and
memory management, which are needed by stack guard to work. Let me know
if I'm wrong.

> 
> Thank you
> Yao Jiewen
> 
> 
> > -Original Message-
> > From: Wang, Jian J
> > Sent: Tuesday, October 31, 2017 10:24 PM
> > To: edk2-devel@lists.01.org
> > Cc: Zeng, Star ; Dong, Eric ; Yao,
> > Jiewen ; Kinney, Michael D
> > 
> > Subject: [PATCH 3/3] UefiCpuPkg/CpuExceptionHandlerLib: Add stack switch
> > support
> >
> > If Stack Guard is enabled and there's really a stack overflow happened 
> > during
> > boot, a Page Fault exception will be triggered. Because the stack is out of
> > usage, the exception handler, which shares the stack with normal UEFI 
> > driver,
> > cannot be executed and cannot dump the processor information.
> >
> > Without those information, it's very difficult for the BIOS developers 
> > locate
> > the root cause of stack overflow. And without a workable stack, the 
> > developer
> > cannot event use single step to debug the UEFI driver with JTAG debugger.
> >
> > In order to make sure the exception handler to execute normally after stack
> > overflow. We need separate stacks for exception handlers in case of unusable
> > stack.
> >
> > IA processor allows to switch to a new stack during handling interrupt and
> > exception. But X64 and IA32 provides different ways to make it. X64 provides
> > interrupt stack table (IST) to allow maximum 7 different exceptions to have
> > new stack for its handler. IA32 doesn't have IST mechanism and can only use
> > task gate to do it since task switch allows to load a new stack through its
> > task-state segment (TSS).
> >
> > Note: Stack switch needs to allocate memory pages to be new stacks. So this
> >   functionality works only in the boot phases capable of memory
> >   allocation (besides the paging, for the sake of Stack Guard). In
> >   other words, only DXE phase can supports Stack Guard with stack 
> > switch.
> >
> > Cc: Star Zeng 
> > Cc: Eric Dong 
> > Cc: Jiewen Yao 
> > Cc: Michael Kinney 
> > Suggested-by: Ayellet Wolman 
> > Contributed-under: TianoCore Contribution Agreement 1.1
> > Signed-off-by: Jian J Wang 
> > ---
> >  .../CpuExceptionHandlerLib/CpuExceptionCommon.h|  22 ++
> >  .../DxeCpuExceptionHandlerLib.inf  |   5 +
> >  .../Library/CpuExceptionHandlerLib/DxeException.c  |  19 +
> >  .../Ia32/ArchExceptionHandler.c| 135 +++
> >  .../Ia32/ArchInterruptDefs.h   | 136 +++
> >  .../Ia32/ExceptionTssEntryAsm.nasm | 398
> > +
> >  .../PeiCpuExceptionHandlerLib.inf  |   1 +
> >  .../SecPeiCpuExceptionHandlerLib.inf   |   3 +
> >  .../SmmCpuExceptionHandlerLib.inf  |   1 +
> >  .../X64/ArchExceptionHandler.c | 108 ++
> >  .../CpuExceptionHandlerLib/X64/ArchInterruptDefs.h |  40 +++
> >  .../X64/ExceptionHandlerAsm.S  |  12 +
> >  .../X64/ExceptionHandlerAsm.asm|  12 +
> >  .../X64/ExceptionHandlerAsm.nasm   |  12 +
> >  14 files changed, 904 insertions(+)
> >  create mode 100644
> >
> UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ExceptionTssEntryAsm.nasm
> >
> > diff --git
> > a/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.h
> > b/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.h
> > index 740a58828b..fd4a26a458 100644
> > --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.h
> > +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.h
> > @@ -25,6 +25,7 @@
> >  #include 
> >  #include 
> >  #include 
> > +#include 
> >
> >  #define  CPU_EXCEPTION_NUM  32
> >  #define  CPU_INTERRUPT_NUM 256
> > @@ -288,5 +289,26 @@ CommonExceptionHandler

Re: [edk2] [patch] UefiCpuPkg/MpInitLib:Make function comments align with function

[Dong, Eric]

Dandan,

Thanks to help to fix this issue. 

Reviewed-by: Eric Dong 

Thanks,
Eric
> -Original Message-
> From: edk2-devel [mailto:edk2-devel-boun...@lists.01.org] On Behalf Of
> Dandan Bi
> Sent: Wednesday, November 1, 2017 9:37 AM
> To: edk2-devel@lists.01.org
> Cc: Dong, Eric 
> Subject: [edk2] [patch] UefiCpuPkg/MpInitLib:Make function comments
> align with function
> 
> Cc: Eric Dong 
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Dandan Bi 
> ---
>  UefiCpuPkg/Library/MpInitLib/MpLib.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/UefiCpuPkg/Library/MpInitLib/MpLib.c
> b/UefiCpuPkg/Library/MpInitLib/MpLib.c
> index 18060fd..61b14c9 100644
> --- a/UefiCpuPkg/Library/MpInitLib/MpLib.c
> +++ b/UefiCpuPkg/Library/MpInitLib/MpLib.c
> @@ -534,11 +534,11 @@ InitializeApData (
> 
>  /**
>This function will be called from AP reset code if BSP uses WakeUpAP.
> 
>@param[in] ExchangeInfo Pointer to the MP exchange info buffer
> -  @param[in] NumApsExecuting  Number of current executing AP
> +  @param[in] ApIndex  Number of current executing AP
>  **/
>  VOID
>  EFIAPI
>  ApWakeupFunction (
>IN MP_CPU_EXCHANGE_INFO  *ExchangeInfo,
> --
> 1.9.5.msysgit.1
> 
> ___
> edk2-devel mailing list
> edk2-devel@lists.01.org
> https://lists.01.org/mailman/listinfo/edk2-devel
___
edk2-devel mailing list
edk2-devel@lists.01.org
https://lists.01.org/mailman/listinfo/edk2-devel

[edk2] 答复: [PATCH 3/3] UefiCpuPkg/CpuExceptionHandlerLib: Add stack switch support

[Fan Jeff]

Per https://bugzilla.tianocore.org/show_bug.cgi?id=109, TR should be setup 
(Such as in DxeIplPeim) even though NULL Cpu Exception Handler instance is 
chosen.

For long term, I agree we need to move AsmWriteTr, IA32_TASK_STATE_SEGMENT, 
IA32_TSS_DESCRIPTOR to MdePkg(Such as BaseLib)
For this patch, I have no strong opinion.


发件人: Yao, Jiewen
发送时间: 2017年11月1日 9:56
收件人: Wang, Jian J; 
edk2-devel@lists.01.org
抄送: Kinney, Michael D; Dong, 
Eric; Zeng, Star
主题: Re: [edk2] [PATCH 3/3] UefiCpuPkg/CpuExceptionHandlerLib: Add stack switch 
support

Hi Jian
Thanks for the patch.

Can we move all IA32 defined data structure or function to MdePkg?
Such as: AsmWriteTr, IA32_TASK_STATE_SEGMENT, IA32_TSS_DESCRIPTOR

I am also curious why we use different policy for other boot mode.
Can we use consistent policy?
> +  if (PcdGetBool (PcdCpuStackGuard)) {
> +//
> +// Stack Guard works with the support of page table established and
> +// memory management. So we have to exclude those boot modes
> without
> +// them.
> +//
> +switch (GetBootModeHob()) {
> +case BOOT_ON_FLASH_UPDATE:
> +case BOOT_IN_RECOVERY_MODE:
> +case BOOT_ON_S3_RESUME:
> +  break;
> +
> +default:
> +  ArchSetupExcpetionStack (IdtTable);
> +  break;
> +}
> +  }


Thank you
Yao Jiewen


> -Original Message-
> From: Wang, Jian J
> Sent: Tuesday, October 31, 2017 10:24 PM
> To: edk2-devel@lists.01.org
> Cc: Zeng, Star ; Dong, Eric ; Yao,
> Jiewen ; Kinney, Michael D
> 
> Subject: [PATCH 3/3] UefiCpuPkg/CpuExceptionHandlerLib: Add stack switch
> support
>
> If Stack Guard is enabled and there's really a stack overflow happened during
> boot, a Page Fault exception will be triggered. Because the stack is out of
> usage, the exception handler, which shares the stack with normal UEFI driver,
> cannot be executed and cannot dump the processor information.
>
> Without those information, it's very difficult for the BIOS developers locate
> the root cause of stack overflow. And without a workable stack, the developer
> cannot event use single step to debug the UEFI driver with JTAG debugger.
>
> In order to make sure the exception handler to execute normally after stack
> overflow. We need separate stacks for exception handlers in case of unusable
> stack.
>
> IA processor allows to switch to a new stack during handling interrupt and
> exception. But X64 and IA32 provides different ways to make it. X64 provides
> interrupt stack table (IST) to allow maximum 7 different exceptions to have
> new stack for its handler. IA32 doesn't have IST mechanism and can only use
> task gate to do it since task switch allows to load a new stack through its
> task-state segment (TSS).
>
> Note: Stack switch needs to allocate memory pages to be new stacks. So this
>   functionality works only in the boot phases capable of memory
>   allocation (besides the paging, for the sake of Stack Guard). In
>   other words, only DXE phase can supports Stack Guard with stack switch.
>
> Cc: Star Zeng 
> Cc: Eric Dong 
> Cc: Jiewen Yao 
> Cc: Michael Kinney 
> Suggested-by: Ayellet Wolman 
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Jian J Wang 
> ---
>  .../CpuExceptionHandlerLib/CpuExceptionCommon.h|  22 ++
>  .../DxeCpuExceptionHandlerLib.inf  |   5 +
>  .../Library/CpuExceptionHandlerLib/DxeException.c  |  19 +
>  .../Ia32/ArchExceptionHandler.c| 135 +++
>  .../Ia32/ArchInterruptDefs.h   | 136 +++
>  .../Ia32/ExceptionTssEntryAsm.nasm | 398
> +
>  .../PeiCpuExceptionHandlerLib.inf  |   1 +
>  .../SecPeiCpuExceptionHandlerLib.inf   |   3 +
>  .../SmmCpuExceptionHandlerLib.inf  |   1 +
>  .../X64/ArchExceptionHandler.c | 108 ++
>  .../CpuExceptionHandlerLib/X64/ArchInterruptDefs.h |  40 +++
>  .../X64/ExceptionHandlerAsm.S  |  12 +
>  .../X64/ExceptionHandlerAsm.asm|  12 +
>  .../X64/ExceptionHandlerAsm.nasm   |  12 +
>  14 files changed, 904 insertions(+)
>  create mode 100644
> UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ExceptionTssEntryAsm.nasm
>
> diff --git
> a/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.h
> b/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.h
> index 740a58828b..fd4a26a458 100644
> --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.h
> +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.h
> @@ -25,6 +25,7 @@
>  #include 
>  #include 
>  #include 
> +#include 
>
>  #define  CPU_EXCEPTION_NUM  32
>  #define  CPU_INTERRUPT_NUM 256
> @@ -288,5 +289,26 @@ CommonExceptionHandlerWorker (
>   

Re: [edk2] [PATCH 3/3] UefiCpuPkg/CpuExceptionHandlerLib: Add stack switch support

[Yao, Jiewen]

Hi Jian
Thanks for the patch.

Can we move all IA32 defined data structure or function to MdePkg?
Such as: AsmWriteTr, IA32_TASK_STATE_SEGMENT, IA32_TSS_DESCRIPTOR

I am also curious why we use different policy for other boot mode.
Can we use consistent policy?
> +  if (PcdGetBool (PcdCpuStackGuard)) {
> +//
> +// Stack Guard works with the support of page table established and
> +// memory management. So we have to exclude those boot modes
> without
> +// them.
> +//
> +switch (GetBootModeHob()) {
> +case BOOT_ON_FLASH_UPDATE:
> +case BOOT_IN_RECOVERY_MODE:
> +case BOOT_ON_S3_RESUME:
> +  break;
> +
> +default:
> +  ArchSetupExcpetionStack (IdtTable);
> +  break;
> +}
> +  }


Thank you
Yao Jiewen


> -Original Message-
> From: Wang, Jian J
> Sent: Tuesday, October 31, 2017 10:24 PM
> To: edk2-devel@lists.01.org
> Cc: Zeng, Star ; Dong, Eric ; Yao,
> Jiewen ; Kinney, Michael D
> 
> Subject: [PATCH 3/3] UefiCpuPkg/CpuExceptionHandlerLib: Add stack switch
> support
> 
> If Stack Guard is enabled and there's really a stack overflow happened during
> boot, a Page Fault exception will be triggered. Because the stack is out of
> usage, the exception handler, which shares the stack with normal UEFI driver,
> cannot be executed and cannot dump the processor information.
> 
> Without those information, it's very difficult for the BIOS developers locate
> the root cause of stack overflow. And without a workable stack, the developer
> cannot event use single step to debug the UEFI driver with JTAG debugger.
> 
> In order to make sure the exception handler to execute normally after stack
> overflow. We need separate stacks for exception handlers in case of unusable
> stack.
> 
> IA processor allows to switch to a new stack during handling interrupt and
> exception. But X64 and IA32 provides different ways to make it. X64 provides
> interrupt stack table (IST) to allow maximum 7 different exceptions to have
> new stack for its handler. IA32 doesn't have IST mechanism and can only use
> task gate to do it since task switch allows to load a new stack through its
> task-state segment (TSS).
> 
> Note: Stack switch needs to allocate memory pages to be new stacks. So this
>   functionality works only in the boot phases capable of memory
>   allocation (besides the paging, for the sake of Stack Guard). In
>   other words, only DXE phase can supports Stack Guard with stack switch.
> 
> Cc: Star Zeng 
> Cc: Eric Dong 
> Cc: Jiewen Yao 
> Cc: Michael Kinney 
> Suggested-by: Ayellet Wolman 
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Jian J Wang 
> ---
>  .../CpuExceptionHandlerLib/CpuExceptionCommon.h|  22 ++
>  .../DxeCpuExceptionHandlerLib.inf  |   5 +
>  .../Library/CpuExceptionHandlerLib/DxeException.c  |  19 +
>  .../Ia32/ArchExceptionHandler.c| 135 +++
>  .../Ia32/ArchInterruptDefs.h   | 136 +++
>  .../Ia32/ExceptionTssEntryAsm.nasm | 398
> +
>  .../PeiCpuExceptionHandlerLib.inf  |   1 +
>  .../SecPeiCpuExceptionHandlerLib.inf   |   3 +
>  .../SmmCpuExceptionHandlerLib.inf  |   1 +
>  .../X64/ArchExceptionHandler.c | 108 ++
>  .../CpuExceptionHandlerLib/X64/ArchInterruptDefs.h |  40 +++
>  .../X64/ExceptionHandlerAsm.S  |  12 +
>  .../X64/ExceptionHandlerAsm.asm|  12 +
>  .../X64/ExceptionHandlerAsm.nasm   |  12 +
>  14 files changed, 904 insertions(+)
>  create mode 100644
> UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ExceptionTssEntryAsm.nasm
> 
> diff --git
> a/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.h
> b/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.h
> index 740a58828b..fd4a26a458 100644
> --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.h
> +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.h
> @@ -25,6 +25,7 @@
>  #include 
>  #include 
>  #include 
> +#include 
> 
>  #define  CPU_EXCEPTION_NUM  32
>  #define  CPU_INTERRUPT_NUM 256
> @@ -288,5 +289,26 @@ CommonExceptionHandlerWorker (
>IN EXCEPTION_HANDLER_DATA  *ExceptionHandlerData
>);
> 
> +/**
> +  Load given selector into TR register
> +
> +  @param Selector Task segment selector
> +**/
> +VOID
> +AsmWriteTr (
> +  UINT16 Selector
> +  );
> +
> +/**
> +  Setup separate stack for specific exceptions.
> +
> +  @param[in] IdtTableIDT table base.
> +**/
> +VOID
> +EFIAPI
> +ArchSetupExcpetionStack (
> +  IN IA32_IDT_GATE_DESCRIPTOR   *IdtTable
> +  );
> +
>  #endif
> 
> diff --git
> a/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandlerLib.inf
> b/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandlerLib.inf
> index f4a8d01c80..b099ef4dad 100644
> ---
> a/UefiCpuPkg/Library/CpuExceptionHan

[edk2] [patch] UefiCpuPkg/MpInitLib:Make function comments align with function

[Dandan Bi]

Cc: Eric Dong 
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Dandan Bi 
---
 UefiCpuPkg/Library/MpInitLib/MpLib.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/UefiCpuPkg/Library/MpInitLib/MpLib.c 
b/UefiCpuPkg/Library/MpInitLib/MpLib.c
index 18060fd..61b14c9 100644
--- a/UefiCpuPkg/Library/MpInitLib/MpLib.c
+++ b/UefiCpuPkg/Library/MpInitLib/MpLib.c
@@ -534,11 +534,11 @@ InitializeApData (
 
 /**
   This function will be called from AP reset code if BSP uses WakeUpAP.
 
   @param[in] ExchangeInfo Pointer to the MP exchange info buffer
-  @param[in] NumApsExecuting  Number of current executing AP
+  @param[in] ApIndex  Number of current executing AP
 **/
 VOID
 EFIAPI
 ApWakeupFunction (
   IN MP_CPU_EXCHANGE_INFO  *ExchangeInfo,
-- 
1.9.5.msysgit.1

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Re: [edk2] [PATCH] Add one maintainer to CorebootModulePkg and CorebootPayloadPkg

[Ma, Maurice]

Reviewed-by: Maurice Ma 

-Original Message-
From: edk2-devel [mailto:edk2-devel-boun...@lists.01.org] On Behalf Of You, 
Benjamin
Sent: Monday, October 30, 2017 11:56 PM
To: edk2-devel@lists.01.org
Cc: Agyeman, Prince 
Subject: [edk2] [PATCH] Add one maintainer to CorebootModulePkg and 
CorebootPayloadPkg

Add one maintainer (Benjamin You) to CorebootModulePkg and CorebootPayloadPkg

Cc: Maurice Ma 
Cc: Prince Agyeman 
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Benjamin You 
---
 Maintainers.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Maintainers.txt b/Maintainers.txt index 297a9bfd2b..3930ff07a9 
100644
--- a/Maintainers.txt
+++ b/Maintainers.txt
@@ -91,6 +91,7 @@ CorebootModulePkg, CorebootPayloadPkg
 W: https://github.com/tianocore/tianocore.github.io/wiki/Coreboot_UEFI_payload
 M: Maurice Ma 
 M: Prince Agyeman 
+M: Benjamin You 
 S: Maintained
 
 CryptoPkg
--
2.14.3.windows.1

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[edk2] [PATCH 2/2] PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe: Replace RTC macros

[Leo Duran]

Use FixedPCD's to set platform-specific values for RTC registers.

Specifically, the replaced macros are:
1) RTC_INIT_REGISTER_A
2) RTC_INIT_REGISTER_B
3) RTC_INIT_REGISTER_D

Cc: Ruiyu Ni 
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Leo Duran 
---
 PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcRtc.c|  8 +---
 PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcRtc.h|  9 ++---
 .../PcatRealTimeClockRuntimeDxe.inf   | 11 +--
 3 files changed, 16 insertions(+), 12 deletions(-)

diff --git a/PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcRtc.c 
b/PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcRtc.c
index 857918d..c032e16 100644
--- a/PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcRtc.c
+++ b/PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcRtc.c
@@ -2,6 +2,8 @@
   RTC Architectural Protocol GUID as defined in DxeCis 0.96.
 
 Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.
+Copyright (c) 2017, AMD Inc. All rights reserved.
+
 This program and the accompanying materials
 are licensed and made available under the terms and conditions of the BSD 
License
 which accompanies this distribution.  The full text of the license may be 
found at
@@ -128,7 +130,7 @@ PcRtcInit (
   // Make sure Division Chain is properly configured,
   // or RTC clock won't "tick" -- time won't increment
   //
-  RegisterA.Data = RTC_INIT_REGISTER_A;
+  RegisterA.Data = FixedPcdGet8 (PcdInitialValueRtcRegisterA);
   RtcWrite (RTC_ADDRESS_REGISTER_A, RegisterA.Data);
 
   //
@@ -144,7 +146,7 @@ PcRtcInit (
   //
   // Clear RTC register D
   //
-  RegisterD.Data = RTC_INIT_REGISTER_D;
+  RegisterD.Data = FixedPcdGet8 (PcdInitialValueRtcRegisterD);
   RtcWrite (RTC_ADDRESS_REGISTER_D, RegisterD.Data);
 
   //
@@ -176,7 +178,7 @@ PcRtcInit (
   // Set RTC configuration after get original time
   // The value of bit AIE should be reserved.
   //
-  RegisterB.Data = RTC_INIT_REGISTER_B | (RegisterB.Data & BIT5);
+  RegisterB.Data = FixedPcdGet8 (PcdInitialValueRtcRegisterB) | 
(RegisterB.Data & BIT5);
   RtcWrite (RTC_ADDRESS_REGISTER_B, RegisterB.Data);
 
   //
diff --git a/PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcRtc.h 
b/PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcRtc.h
index ba6092d..8aeb12c 100644
--- a/PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcRtc.h
+++ b/PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcRtc.h
@@ -2,6 +2,8 @@
   Header file for real time clock driver.
 
 Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.
+Copyright (c) 2017, AMD Inc. All rights reserved.
+
 This program and the accompanying materials
 are licensed and made available under the terms and conditions of the BSD 
License
 which accompanies this distribution.  The full text of the license may be 
found at
@@ -75,13 +77,6 @@ extern PC_RTC_MODULE_GLOBALS  mModuleGlobal;
 #define RTC_INIT_DAY1
 #define RTC_INIT_MONTH  1
 
-//
-// Register initial values
-//
-#define RTC_INIT_REGISTER_A 0x26
-#define RTC_INIT_REGISTER_B 0x02
-#define RTC_INIT_REGISTER_D 0x0
-
 #pragma pack(1)
 //
 // Register A
diff --git 
a/PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcatRealTimeClockRuntimeDxe.inf 
b/PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcatRealTimeClockRuntimeDxe.inf
index dd746a2..1b2b063 100644
--- a/PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcatRealTimeClockRuntimeDxe.inf
+++ b/PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcatRealTimeClockRuntimeDxe.inf
@@ -5,6 +5,8 @@
 # It will install a tagging protocol with gEfiRealTimeClockArchProtocolGuid.
 #
 # Copyright (c) 2006 - 2015, Intel Corporation. All rights reserved.
+# Copyright (c) 2017, AMD Inc. All rights reserved.
+#
 # This program and the accompanying materials
 # are licensed and made available under the terms and conditions of the BSD 
License
 # which accompanies this distribution.  The full text of the license may be 
found at
@@ -66,13 +68,18 @@
   ## SOMETIMES_CONSUMES ## SystemTable
   gEfiAcpiTableGuid
 
-[Depex]
-  gEfiVariableArchProtocolGuid AND gEfiVariableWriteArchProtocolGuid
+[FixedPcd]
+  gPcAtChipsetPkgTokenSpaceGuid.PcdInitialValueRtcRegisterA ## CONSUMES
+  gPcAtChipsetPkgTokenSpaceGuid.PcdInitialValueRtcRegisterB ## CONSUMES
+  gPcAtChipsetPkgTokenSpaceGuid.PcdInitialValueRtcRegisterD ## CONSUMES
   
 [Pcd]
   gEfiMdeModulePkgTokenSpaceGuid.PcdRealTimeClockUpdateTimeout  ## CONSUMES
   gPcAtChipsetPkgTokenSpaceGuid.PcdMinimalValidYear ## CONSUMES
   gPcAtChipsetPkgTokenSpaceGuid.PcdMaximalValidYear ## CONSUMES
 
+[Depex]
+  gEfiVariableArchProtocolGuid AND gEfiVariableWriteArchProtocolGuid
+
 [UserExtensions.TianoCore."ExtraFiles"]
   PcRtcExtra.uni
-- 
2.7.4

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[edk2] [PATCH 1/2] PcAtChipsetPkg: Define FixePCD's for RTC register values

[Leo Duran]

Define FixedPCD's to replace macros in RTC driver, to allow
for platform-specific configurations.

Cc: Ruiyu Ni 
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Leo Duran 
---
 PcAtChipsetPkg/PcAtChipsetPkg.dec | 13 +
 1 file changed, 13 insertions(+)

diff --git a/PcAtChipsetPkg/PcAtChipsetPkg.dec 
b/PcAtChipsetPkg/PcAtChipsetPkg.dec
index b0b2b62..f11d204 100644
--- a/PcAtChipsetPkg/PcAtChipsetPkg.dec
+++ b/PcAtChipsetPkg/PcAtChipsetPkg.dec
@@ -5,6 +5,7 @@
 # PcAt defacto standard.
 #
 # Copyright (c) 2009 - 2015, Intel Corporation. All rights reserved.
+# Copyright (c) 2017, AMD Inc. All rights reserved.
 #
 # This program and the accompanying materials
 # are licensed and made available under the terms and conditions of the BSD 
License
@@ -181,5 +182,17 @@
   # @Prompt Reset Control Register value for cold reset
   
gPcAtChipsetPkgTokenSpaceGuid.PcdResetControlValueColdReset|0xFE|UINT8|0x001A
 
+  ## Specifies the initial value for Register_A in RTC.
+  # @Prompt Initial value for Register_A in RTC.
+  
gPcAtChipsetPkgTokenSpaceGuid.PcdInitialValueRtcRegisterA|0x26|UINT8|0x001B
+
+  ## Specifies the initial value for Register_B in RTC.
+  # @Prompt Initial value for Register_B in RTC.
+  
gPcAtChipsetPkgTokenSpaceGuid.PcdInitialValueRtcRegisterB|0x02|UINT8|0x001C
+
+  ## Specifies the initial value for Register_D in RTC.
+  # @Prompt Initial value for Register_D in RTC.
+  
gPcAtChipsetPkgTokenSpaceGuid.PcdInitialValueRtcRegisterD|0x00|UINT8|0x001D
+
 [UserExtensions.TianoCore."ExtraFiles"]
   PcAtChipsetPkgExtra.uni
-- 
2.7.4

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[edk2] [PATCH 0/2] Define PCD's for RTC init values

[Leo Duran]

We have an RTC implementation that requires non-standard
initial values for the A/B/D registers, so this patch-set
replaces the macros defined in PcRtc.h with FixedPCD's
that allow for platform-specific configurations.

The changes all localized to the PcAtChipsetPkg, and should be
completely non-intrusive.

Leo Duran (2):
  PcAtChipsetPkg: Define FixePCD's for RTC register values
  PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe: Replace RTC macros

 PcAtChipsetPkg/PcAtChipsetPkg.dec   | 13 +
 PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcRtc.c  |  8 +---
 PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcRtc.h  |  9 ++---
 .../PcatRealTimeClockRuntimeDxe.inf | 11 +--
 4 files changed, 29 insertions(+), 12 deletions(-)

-- 
2.7.4

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Re: [edk2] [RFC] MdeModulePkg/NonDiscoverablePciDeviceDxe: NonCoherentPciIoAllocateBuffer issue with AArch64

[Heyi Guo]

OK, we'll make the change for D0x too.

Thanks,

Heyi

On 30 October 2017 at 23:17, Ard Biesheuvel 
wrote:

> On 30 October 2017 at 15:13, Heyi Guo  wrote:
> > Hi Ard,
> >
> >
> > On 10/30/2017 04:21 PM, Ard Biesheuvel wrote:
> >>
> >> On 30 October 2017 at 03:52, Heyi Guo  wrote:
> >>>
> >>> Hi folks,
> >>>
> >>> In NonDiscoverablePciDeviceDxe driver, NonCoherentPciIoAllocateBuffer
> may
> >>> allocate EFI_MEMORY_UC buffer depending on input Attributes and GCD
> >>> capabilities. If it does, it actually allocates memory of "device" type
> >>> in
> >>> AArch64, but not "normal uncacheable" memory. For "device" memory type,
> >>> it
> >>> requires restrict access alignment and it may trigger alignment fault
> >>> exception with BaseMemoryLibOptDxe in which read/write alignment is not
> >>> guaranteed.
> >>>
> >>> Is EFI_MOMORY_WC enough for AArch64 platforms? How about other
> platforms,
> >>> like X86?
> >>>
> >> Hello Heyi,
> >>
> >> Do you mean EFI_MEMORY_UC in the last sentence? If not, I don't
> >> understand the question.
> >
> > I actually meant EFI_MOMORY_WC for I supposed EFI_MOMORY_WC should be
> enough
> > for AArch64 non cacheable DMA access.
> >
> >>
> >> Anyway, in reality, this code will only allocate EFI_MEMORY_UC memory
> >> if any memory already exists in the memory map with that capability,
> >> otherwise it will fall back to EFI_MEMORY_WC. On most arm64 platforms,
> >> we no longer add this capability to system memoryEFI_MOMORY_WC by
> default,
> >> so you
> >> should be getting EFI_MEMORY_WC in most cases.
> >
> >
> > Oh, I supposed we always have UC capability for system memory and we
> > actually still do that on D0x platforms. Does it mean we'd better remove
> > this capability to get the issue fixed?
>
> Yes.
>
> > Is there any architectural reason
> > for not setting UC capability on system memory?
> >
>
> Yes, exactly the reasons you mention: memory no longer behaves as
> memory if you map it with EFI_MEMORY_UC attributes, i.e., unaligned
> accesses or DC ZVA instructions can no longer be used.
>
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[edk2] UEFI shell hash tools?

[Jeff Westfahl]

Hello all,

I'm looking for tools that run in the UEFI shell and do typical hash functions 
on files. Basically the UEFI shell equivalent of md5sum, sha1sum, sha256sum, 
etc. It seems like these tools would be pretty useful, and that they should 
already exist, but I haven't found anything. Perhaps my google-foo is weak.

Does anybody know of any such tools?

Thank you,

Jeff Westfahl
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[edk2] [Help] UEFI boot KVM4T vm hang On TianoCore

[Hangaohuai]

Hi, Laszlo Ersek;

I have tested the uefi booting KVM vm with the configuration(xml); but start 
hang.
Enable the memoryhotplug, with usb3.0 config. The config as Config1 below.

Tested branches:
UDK2017 eea98eea4ccbb1d640657770bccb5497fddc6064
Master   76fd5a660d704538a1b14a58d03a4eef9682b01c

Both hang on the snapshot TianoCore in VNC

Try to shoot the problem;
I find the early version can boot success with the same config.
Maybe the patch1 below cause the problem;

Try to ignore the patch does, the master/ UDK2017 both can boot success.
But I don't know why. Hope for your help,thanks.

Patch1
***
commit 4f5eff8193096eb847639f090a7dfae3cff95fde
Author: Laszlo Ersek 
Date:   Fri Mar 4 20:06:26 2016 +0100

OvmfPkg: PciHostBridgeLib: install 64-bit PCI host aperture

diff --git a/OvmfPkg/Library/PciHostBridgeLib/PciHostBridgeLib.c 
b/OvmfPkg/Library/PciHostBridgeLib/PciHostBridgeLib
index 3e02778..1d3d10a 100644
--- a/OvmfPkg/Library/PciHostBridgeLib/PciHostBridgeLib.c
+++ b/OvmfPkg/Library/PciHostBridgeLib/PciHostBridgeLib.c
@@ -132,6 +132,13 @@ InitRootBridge (
   RootBus->MemAbove4G.Base  = 0;
   RootBus->MemAbove4G.Limit = 0;
+  if (PcdGet64 (PcdPciMmio64Size) > 0) {
+RootBus->AllocationAttributes |= EFI_PCI_HOST_BRIDGE_MEM64_DECODE;
+RootBus->MemAbove4G.Base   = PcdGet64 (PcdPciMmio64Base);
+RootBus->MemAbove4G.Limit  = PcdGet64 (PcdPciMmio64Base) +
+ (PcdGet64 (PcdPciMmio64Size) - 1);
+  }
+
   RootBus->Bus.Base  = RootBusNumber;
   RootBus->Bus.Limit = MaxSubBusNumber;
   RootBus->Io.Base   = PcdGet64 (PcdPciIoBase);
diff --git a/OvmfPkg/Library/PciHostBridgeLib/PciHostBridgeLib.inf 
b/OvmfPkg/Library/PciHostBridgeLib/PciHostBridgeL
index bbec746..7a964c7 100644
--- a/OvmfPkg/Library/PciHostBridgeLib/PciHostBridgeLib.inf
+++ b/OvmfPkg/Library/PciHostBridgeLib/PciHostBridgeLib.inf
@@ -51,4 +51,6 @@
   gUefiOvmfPkgTokenSpaceGuid.PcdPciIoSize
   gUefiOvmfPkgTokenSpaceGuid.PcdPciMmio32Base
   gUefiOvmfPkgTokenSpaceGuid.PcdPciMmio32Size
+  gUefiOvmfPkgTokenSpaceGuid.PcdPciMmio64Base
+  gUefiOvmfPkgTokenSpaceGuid.PcdPciMmio64Size
   gUefiOvmfPkgTokenSpaceGuid.PcdOvmfHostBridgePciDevId
***


Config1
***
4294967296
  4294967
  4294967
Xxxx


 
***



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[edk2] [PATCH 0/3] Implement stack guard feature

[Jian J Wang]

Stack guard feature makes use of paging mechanism to monitor if there's a
stack overflow occurred during boot. A new PCD PcdCpuStackGuard is added to
enable/disable this feature.

If this feature is enabled, DxeIpl will setup page tables and set page where
the stack bottom is at to be NON-PRESENT. If stack overflow occurs, Page
Fault exception will be triggered.

In order to make sure exception handler works normally even when the stack
is corrupted, stack switching is implemented for exception library.

Due to the mechanism behind Stack Guard, this feature is only avaiable for
UEFI drivers. That also means it doesn't support NT32 emulated platform.

Validation works include:
  a. OVMF emulated platform: boot to shell (IA32/X64)
  b. Intel real platform: boot to shell (IA32/X64)

Jian J Wang (3):
  MdeModulePkg/metafile: Add PCD PcdCpuStackGuard
  MdeModulePkg/DxeIpl: Enable paging for stack guard
  UefiCpuPkg/CpuExceptionHandlerLib: Add stack switch support

 MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf|   1 +
 MdeModulePkg/Core/DxeIplPeim/Ia32/DxeLoadFunc.c|  35 +-
 MdeModulePkg/Core/DxeIplPeim/X64/DxeLoadFunc.c |   1 +
 MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c   |  51 ++-
 MdeModulePkg/MdeModulePkg.dec  |   7 +
 MdeModulePkg/MdeModulePkg.uni  |   7 +
 .../CpuExceptionHandlerLib/CpuExceptionCommon.h|  22 ++
 .../DxeCpuExceptionHandlerLib.inf  |   5 +
 .../Library/CpuExceptionHandlerLib/DxeException.c  |  19 +
 .../Ia32/ArchExceptionHandler.c| 135 +++
 .../Ia32/ArchInterruptDefs.h   | 136 +++
 .../Ia32/ExceptionTssEntryAsm.nasm | 398 +
 .../PeiCpuExceptionHandlerLib.inf  |   1 +
 .../SecPeiCpuExceptionHandlerLib.inf   |   3 +
 .../SmmCpuExceptionHandlerLib.inf  |   1 +
 .../X64/ArchExceptionHandler.c | 108 ++
 .../CpuExceptionHandlerLib/X64/ArchInterruptDefs.h |  40 +++
 .../X64/ExceptionHandlerAsm.S  |  12 +
 .../X64/ExceptionHandlerAsm.asm|  12 +
 .../X64/ExceptionHandlerAsm.nasm   |  12 +
 20 files changed, 989 insertions(+), 17 deletions(-)
 create mode 100644 
UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ExceptionTssEntryAsm.nasm

-- 
2.14.1.windows.1

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[edk2] [PATCH 3/3] UefiCpuPkg/CpuExceptionHandlerLib: Add stack switch support

[Jian J Wang]

If Stack Guard is enabled and there's really a stack overflow happened during
boot, a Page Fault exception will be triggered. Because the stack is out of
usage, the exception handler, which shares the stack with normal UEFI driver,
cannot be executed and cannot dump the processor information.

Without those information, it's very difficult for the BIOS developers locate
the root cause of stack overflow. And without a workable stack, the developer
cannot event use single step to debug the UEFI driver with JTAG debugger.

In order to make sure the exception handler to execute normally after stack
overflow. We need separate stacks for exception handlers in case of unusable
stack.

IA processor allows to switch to a new stack during handling interrupt and
exception. But X64 and IA32 provides different ways to make it. X64 provides
interrupt stack table (IST) to allow maximum 7 different exceptions to have
new stack for its handler. IA32 doesn't have IST mechanism and can only use
task gate to do it since task switch allows to load a new stack through its
task-state segment (TSS).

Note: Stack switch needs to allocate memory pages to be new stacks. So this
  functionality works only in the boot phases capable of memory
  allocation (besides the paging, for the sake of Stack Guard). In
  other words, only DXE phase can supports Stack Guard with stack switch.

Cc: Star Zeng 
Cc: Eric Dong 
Cc: Jiewen Yao 
Cc: Michael Kinney 
Suggested-by: Ayellet Wolman 
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Jian J Wang 
---
 .../CpuExceptionHandlerLib/CpuExceptionCommon.h|  22 ++
 .../DxeCpuExceptionHandlerLib.inf  |   5 +
 .../Library/CpuExceptionHandlerLib/DxeException.c  |  19 +
 .../Ia32/ArchExceptionHandler.c| 135 +++
 .../Ia32/ArchInterruptDefs.h   | 136 +++
 .../Ia32/ExceptionTssEntryAsm.nasm | 398 +
 .../PeiCpuExceptionHandlerLib.inf  |   1 +
 .../SecPeiCpuExceptionHandlerLib.inf   |   3 +
 .../SmmCpuExceptionHandlerLib.inf  |   1 +
 .../X64/ArchExceptionHandler.c | 108 ++
 .../CpuExceptionHandlerLib/X64/ArchInterruptDefs.h |  40 +++
 .../X64/ExceptionHandlerAsm.S  |  12 +
 .../X64/ExceptionHandlerAsm.asm|  12 +
 .../X64/ExceptionHandlerAsm.nasm   |  12 +
 14 files changed, 904 insertions(+)
 create mode 100644 
UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ExceptionTssEntryAsm.nasm

diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.h 
b/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.h
index 740a58828b..fd4a26a458 100644
--- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.h
+++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.h
@@ -25,6 +25,7 @@
 #include 
 #include 
 #include 
+#include 
 
 #define  CPU_EXCEPTION_NUM  32
 #define  CPU_INTERRUPT_NUM 256
@@ -288,5 +289,26 @@ CommonExceptionHandlerWorker (
   IN EXCEPTION_HANDLER_DATA  *ExceptionHandlerData
   );
 
+/**
+  Load given selector into TR register
+
+  @param Selector Task segment selector
+**/
+VOID
+AsmWriteTr (
+  UINT16 Selector
+  );
+
+/**
+  Setup separate stack for specific exceptions.
+
+  @param[in] IdtTableIDT table base.
+**/
+VOID
+EFIAPI
+ArchSetupExcpetionStack (
+  IN IA32_IDT_GATE_DESCRIPTOR   *IdtTable
+  );
+
 #endif
 
diff --git 
a/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandlerLib.inf 
b/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandlerLib.inf
index f4a8d01c80..b099ef4dad 100644
--- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandlerLib.inf
+++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandlerLib.inf
@@ -30,6 +30,7 @@
 [Sources.Ia32]
   Ia32/ExceptionHandlerAsm.asm
   Ia32/ExceptionHandlerAsm.nasm
+  Ia32/ExceptionTssEntryAsm.nasm
   Ia32/ExceptionHandlerAsm.S
   Ia32/ArchExceptionHandler.c
   Ia32/ArchInterruptDefs.h
@@ -47,6 +48,9 @@
   PeiDxeSmmCpuException.c
   DxeException.c
 
+[Pcd]
+  gEfiMdeModulePkgTokenSpaceGuid.PcdCpuStackGuard
+
 [Packages]
   MdePkg/MdePkg.dec
   MdeModulePkg/MdeModulePkg.dec
@@ -61,3 +65,4 @@
   PeCoffGetEntryPointLib
   MemoryAllocationLib
   DebugLib
+  HobLib
diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeException.c 
b/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeException.c
index 31febec976..e9dcd00e02 100644
--- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeException.c
+++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeException.c
@@ -16,6 +16,7 @@
 #include "CpuExceptionCommon.h"
 #include 
 #include 
+#include 
 
 CONST UINTNmDoFarReturnFlag  = 0;
 
@@ -155,6 +156,24 @@ InitializeCpuInterruptHandlers (
 
   UpdateIdtTable (IdtTable, &TemplateMap, &mExceptionHandlerData);
 
+  if (PcdGetBool (PcdCpuStackGuard)) {
+//
+// Stack Guard works 

[edk2] [PATCH 2/3] MdeModulePkg/DxeIpl: Enable paging for stack guard

[Jian J Wang]

Stack guard feature makes use of paging mechanism to monitor if there's a
stack overflow occurred during boot.

This patch will check setting of PCD PcdCpuStackGuard. If it's TRUE, DxeIpl
will setup page table and set the page at which the stack base locates to be
NOT PRESENT. If stack is used up and memory access cross into the last page
of it, #PF exception will be triggered.

Cc: Star Zeng 
Cc: Eric Dong 
Suggested-by: Ayellet Wolman 
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Jian J Wang 
---
 MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf  |  1 +
 MdeModulePkg/Core/DxeIplPeim/Ia32/DxeLoadFunc.c  | 35 ++--
 MdeModulePkg/Core/DxeIplPeim/X64/DxeLoadFunc.c   |  1 +
 MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c | 51 ++--
 4 files changed, 71 insertions(+), 17 deletions(-)

diff --git a/MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf 
b/MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf
index 9d0e76a293..bc857629f8 100644
--- a/MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf
+++ b/MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf
@@ -116,6 +116,7 @@
   gEfiMdeModulePkgTokenSpaceGuid.PcdUse1GPageTable  ## 
SOMETIMES_CONSUMES
   gEfiMdeModulePkgTokenSpaceGuid.PcdPteMemoryEncryptionAddressOrMask## 
CONSUMES
   gEfiMdeModulePkgTokenSpaceGuid.PcdNullPointerDetectionPropertyMask## 
CONSUMES
+  gEfiMdeModulePkgTokenSpaceGuid.PcdCpuStackGuard   ## 
CONSUMES
 
 [Pcd.IA32,Pcd.X64,Pcd.ARM,Pcd.AARCH64]
   gEfiMdeModulePkgTokenSpaceGuid.PcdSetNxForStack   ## 
SOMETIMES_CONSUMES
diff --git a/MdeModulePkg/Core/DxeIplPeim/Ia32/DxeLoadFunc.c 
b/MdeModulePkg/Core/DxeIplPeim/Ia32/DxeLoadFunc.c
index 96f5718444..92f2247bd4 100644
--- a/MdeModulePkg/Core/DxeIplPeim/Ia32/DxeLoadFunc.c
+++ b/MdeModulePkg/Core/DxeIplPeim/Ia32/DxeLoadFunc.c
@@ -211,6 +211,36 @@ IsExecuteDisableBitAvailable (
   return Available;
 }
 
+/**
+  The function will check if page table should be setup or not.
+
+  @retval TRUE  Page table should be created.
+  @retval FALSE Page table should not be created.
+**/
+BOOLEAN
+ToBuildPageTable (
+  VOID
+  )
+{
+  if (!IsIa32PaeSupport ()) {
+return FALSE;
+  }
+
+  if (IsNullDetectionEnabled ()) {
+return TRUE;
+  }
+
+  if (PcdGetBool (PcdCpuStackGuard)) {
+return TRUE;
+  }
+
+  if (PcdGetBool (PcdSetNxForStack) && IsExecuteDisableBitAvailable ()) {
+return TRUE;
+  }
+
+  return FALSE;
+}
+
 /**
Transfers control to DxeCore.
 
@@ -385,10 +415,7 @@ HandOffToDxeCore (
 TopOfStack = (EFI_PHYSICAL_ADDRESS) (UINTN) ALIGN_POINTER (TopOfStack, 
CPU_STACK_ALIGNMENT);
 
 PageTables = 0;
-BuildPageTablesIa32Pae = (BOOLEAN) (IsIa32PaeSupport () &&
-(IsNullDetectionEnabled () ||
- (PcdGetBool (PcdSetNxForStack) &&
-  IsExecuteDisableBitAvailable (;
+BuildPageTablesIa32Pae = ToBuildPageTable();
 if (BuildPageTablesIa32Pae) {
   PageTables = Create4GPageTablesIa32Pae (BaseOfStack, STACK_SIZE);
   if (IsExecuteDisableBitAvailable ()) {
diff --git a/MdeModulePkg/Core/DxeIplPeim/X64/DxeLoadFunc.c 
b/MdeModulePkg/Core/DxeIplPeim/X64/DxeLoadFunc.c
index f613221b81..b75a4489bf 100644
--- a/MdeModulePkg/Core/DxeIplPeim/X64/DxeLoadFunc.c
+++ b/MdeModulePkg/Core/DxeIplPeim/X64/DxeLoadFunc.c
@@ -95,6 +95,7 @@ HandOffToDxeCore (
 // for the DxeIpl and the DxeCore are both X64.
 //
 ASSERT (PcdGetBool (PcdSetNxForStack) == FALSE);
+ASSERT (PcdGetBool (PcdCpuStackGuard) == FALSE);
   }
   
   //
diff --git a/MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c 
b/MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c
index 29b6205e88..a2466b7766 100644
--- a/MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c
+++ b/MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c
@@ -117,6 +117,39 @@ EnableExecuteDisableBit (
   AsmWriteMsr64 (0xC080, MsrRegisters);
 }
 
+/**
+  The function will check if page table entry should be splitted to smaller
+  granularity.
+
+  @retval TRUE  Page table should be created.
+  @retval FALSE Page table should not be created.
+**/
+BOOLEAN
+ToSplitPageTable (
+  IN EFI_PHYSICAL_ADDRESS   Address,
+  IN UINTN  Size,
+  IN EFI_PHYSICAL_ADDRESS   StackBase,
+  IN UINTN  StackSize
+  )
+{
+  if (IsNullDetectionEnabled () && Address == 0) {
+return TRUE;
+  }
+
+  if (PcdGetBool (PcdCpuStackGuard)) {
+if (StackBase >= Address && StackBase < (Address + Size)) {
+  return TRUE;
+}
+  }
+
+  if (PcdGetBool (PcdSetNxForStack)) {
+if ((Address < StackBase + StackSize) && ((Address + Size) > StackBase)) {
+  return TRUE;
+}
+  }
+
+  return FALSE;
+}
 /**
   Split 2M page to 4K.
 
@@ -160,7 +193,8 @@ Split2MPageTo4K (
 PageTableEntry->Uint64 = (UINT64) PhysicalAddress4K | AddressEncMask;
 PageTableEntry->Bits.ReadWrite = 1;
 
-  

[edk2] [PATCH 1/3] MdeModulePkg/metafile: Add PCD PcdCpuStackGuard

[Jian J Wang]

Cc: Star Zeng 
Cc: Eric Dong 
Suggested-by: Ayellet Wolman 
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Jian J Wang 
---
 MdeModulePkg/MdeModulePkg.dec | 7 +++
 MdeModulePkg/MdeModulePkg.uni | 7 +++
 2 files changed, 14 insertions(+)

diff --git a/MdeModulePkg/MdeModulePkg.dec b/MdeModulePkg/MdeModulePkg.dec
index 20a07be96e..5a9704d22c 100644
--- a/MdeModulePkg/MdeModulePkg.dec
+++ b/MdeModulePkg/MdeModulePkg.dec
@@ -883,6 +883,13 @@
   # @Prompt Enable NULL address detection.
   
gEfiMdeModulePkgTokenSpaceGuid.PcdNullPointerDetectionPropertyMask|0x0|UINT8|0x30001050
 
+  ## Indicates if UEFI Stack Guard will be enabled.
+  #  If enabled, stack overflow in UEFI can be caught, preventing chaotic 
consequences.
+  #   TRUE  - UEFI Stack Guard will be enabled.
+  #   FALSE - UEFI Stack Guard will be disabled.
+  # @Prompt Enable UEFI Stack Guard.
+  gEfiMdeModulePkgTokenSpaceGuid.PcdCpuStackGuard|FALSE|BOOLEAN|0x30001055
+
 [PcdsFixedAtBuild, PcdsPatchableInModule]
   ## Dynamic type PCD can be registered callback function for Pcd setting 
action.
   #  PcdMaxPeiPcdCallBackNumberPerPcdEntry indicates the maximum number of 
callback function
diff --git a/MdeModulePkg/MdeModulePkg.uni b/MdeModulePkg/MdeModulePkg.uni
index f8b31694ba..a28a022377 100644
--- a/MdeModulePkg/MdeModulePkg.uni
+++ b/MdeModulePkg/MdeModulePkg.uni
@@ -1140,3 +1140,10 @@

" exception caused by legacy memory (0-4095) access 
after EndOfDxe,"

" such as Windows 7 boot on Qemu.\n"
 
+#string STR_gEfiMdeModulePkgTokenSpaceGuid_PcdCpuStackGuard_PROMPT  #language 
en-US "Enable UEFI Stack Guard"
+
+#string STR_gEfiMdeModulePkgTokenSpaceGuid_PcdCpuStackGuard_HELP#language 
en-US "Indicates if UEFI Stack Guard will be enabled.\n"
+   
 "  If enabled, stack overflow in UEFI can be caught, preventing chaotic 
consequences.\n"
+   
 "   TRUE  - UEFI Stack Guard will be enabled.\n"
+   
 "   FALSE - UEFI Stack Guard will be disabled."
+
-- 
2.14.1.windows.1

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[edk2] [PATCH edk2-platforms v3 26/27] Silicon/SynQuacer: add description of GPIO block to device tree

[Ard Biesheuvel]

Add a description of the SoCs GPIO controller as well as a description
of DIP switch block #3, which is wired to GPIOs 0 - 7, both on the
evaluation board as well as the Developer Box.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel 
---
 Silicon/Socionext/SynQuacer/DeviceTree/DeveloperBox.dts   | 50 

 Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi | 12 +
 Silicon/Socionext/SynQuacer/DeviceTree/SynQuacerEvalBoard.dts | 50 

 3 files changed, 112 insertions(+)

diff --git a/Silicon/Socionext/SynQuacer/DeviceTree/DeveloperBox.dts 
b/Silicon/Socionext/SynQuacer/DeviceTree/DeveloperBox.dts
index 9e0acd593311..791e690adccd 100644
--- a/Silicon/Socionext/SynQuacer/DeviceTree/DeveloperBox.dts
+++ b/Silicon/Socionext/SynQuacer/DeviceTree/DeveloperBox.dts
@@ -19,3 +19,53 @@
 model = "Socionext Developer Box";
 compatible = "socionext,developer-box", "socionext,synquacer";
 };
+
+&gpio {
+dsw3_1 {
+gpios = <0 GPIO_ACTIVE_HIGH>;
+gpio-hog;
+input;
+};
+
+dsw3_2 {
+gpios = <1 GPIO_ACTIVE_HIGH>;
+gpio-hog;
+input;
+};
+
+dsw3_3 {
+gpios = <2 GPIO_ACTIVE_HIGH>;
+gpio-hog;
+input;
+};
+
+dsw3_4 {
+gpios = <3 GPIO_ACTIVE_HIGH>;
+gpio-hog;
+input;
+};
+
+dsw3_5 {
+gpios = <4 GPIO_ACTIVE_HIGH>;
+gpio-hog;
+input;
+};
+
+dsw3_6 {
+gpios = <5 GPIO_ACTIVE_HIGH>;
+gpio-hog;
+input;
+};
+
+dsw3_7 {
+gpios = <6 GPIO_ACTIVE_HIGH>;
+gpio-hog;
+input;
+};
+
+dsw3_8 {
+gpios = <7 GPIO_ACTIVE_HIGH>;
+gpio-hog;
+input;
+};
+};
diff --git a/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi 
b/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi
index 3aef10294662..0746b7853ebf 100644
--- a/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi
+++ b/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi
@@ -21,6 +21,9 @@
 #define IRQ_TYPE_LEVEL_HIGH 4
 #define IRQ_TYPE_LEVEL_LOW  8
 
+#define GPIO_ACTIVE_HIGH0
+#define GPIO_ACTIVE_LOW 1
+
 / {
 #address-cells = <2>;
 #size-cells = <2>;
@@ -511,4 +514,13 @@
 msi-map = <0x0 &its 0x1 0x7f00>;
 dma-coherent;
 };
+
+gpio: gpio@5100 {
+compatible = "socionext,sc2a11-gpio", "fujitsu,mb86s70-gpio";
+reg = <0x0 0x5100 0x0 0x100>;
+gpio-controller;
+#gpio-cells = <2>;
+clocks = <&clk_apb>;
+base = <0>;
+};
 };
diff --git a/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacerEvalBoard.dts 
b/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacerEvalBoard.dts
index cda72fdf2f99..062c1e5eeeb1 100644
--- a/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacerEvalBoard.dts
+++ b/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacerEvalBoard.dts
@@ -19,3 +19,53 @@
 model = "SynQuacer Evaluation Board";
 compatible = "socionext,synquacer-eval-board", "socionext,synquacer";
 };
+
+&gpio {
+dsw3_1 {
+gpios = <0 GPIO_ACTIVE_HIGH>;
+gpio-hog;
+input;
+};
+
+dsw3_2 {
+gpios = <1 GPIO_ACTIVE_HIGH>;
+gpio-hog;
+input;
+};
+
+dsw3_3 {
+gpios = <2 GPIO_ACTIVE_HIGH>;
+gpio-hog;
+input;
+};
+
+dsw3_4 {
+gpios = <3 GPIO_ACTIVE_HIGH>;
+gpio-hog;
+input;
+};
+
+dsw3_5 {
+gpios = <4 GPIO_ACTIVE_HIGH>;
+gpio-hog;
+input;
+};
+
+dsw3_6 {
+gpios = <5 GPIO_ACTIVE_HIGH>;
+gpio-hog;
+input;
+};
+
+dsw3_7 {
+gpios = <6 GPIO_ACTIVE_HIGH>;
+gpio-hog;
+input;
+};
+
+dsw3_8 {
+gpios = <7 GPIO_ACTIVE_HIGH>;
+gpio-hog;
+input;
+};
+};
-- 
2.11.0

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[edk2] [PATCH edk2-platforms v3 25/27] Platform/DeveloperBox: add ConsolePrefDxe driver

[Ard Biesheuvel]

In order to improve the 'out of the box' experience when booting
this system with a monitor and keyboard attached, include the serial
console preference driver that prevents the installer GUI to only
appear on the serial port in this case.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel 
Reviewed-by: Leif Lindholm 
---
 Platform/Socionext/DeveloperBox/DeveloperBox.dsc | 8 
 Platform/Socionext/DeveloperBox/DeveloperBox.fdf | 5 +
 2 files changed, 13 insertions(+)

diff --git a/Platform/Socionext/DeveloperBox/DeveloperBox.dsc 
b/Platform/Socionext/DeveloperBox/DeveloperBox.dsc
index f239692d614b..98586a44a892 100644
--- a/Platform/Socionext/DeveloperBox/DeveloperBox.dsc
+++ b/Platform/Socionext/DeveloperBox/DeveloperBox.dsc
@@ -597,6 +597,14 @@ [Components.common]
   }
 
   #
+  # Console preference selection
+  #
+  EmbeddedPkg/Drivers/ConsolePrefDxe/ConsolePrefDxe.inf {
+
+  FdtLib|EmbeddedPkg/Library/FdtLib/FdtLib.inf
+  }
+
+  #
   # ACPI support
   #
   MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf {
diff --git a/Platform/Socionext/DeveloperBox/DeveloperBox.fdf 
b/Platform/Socionext/DeveloperBox/DeveloperBox.fdf
index 9acb5974ac4c..6d51b1dabeb7 100644
--- a/Platform/Socionext/DeveloperBox/DeveloperBox.fdf
+++ b/Platform/Socionext/DeveloperBox/DeveloperBox.fdf
@@ -214,6 +214,11 @@ [FV.FvMain]
   INF Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/NetsecDxe.inf
 
   #
+  # Console preference selection
+  #
+  INF EmbeddedPkg/Drivers/ConsolePrefDxe/ConsolePrefDxe.inf
+
+  #
   # ACPI support
   #
   INF MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf
-- 
2.11.0

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[edk2] [PATCH edk2-platforms v3 27/27] Silicon/SynQuacer: add description of EXIU to the device tree

[Ard Biesheuvel]

Add a DT node for the external interrupt unit (EXIU), which handles
interrupts from GPIO lines. We need OS support for this for things
like PHY interrupts and a 'wake' button.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel 
---
 Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi | 9 +
 1 file changed, 9 insertions(+)

diff --git a/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi 
b/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi
index 0746b7853ebf..a19f88d10511 100644
--- a/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi
+++ b/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi
@@ -523,4 +523,13 @@
 clocks = <&clk_apb>;
 base = <0>;
 };
+
+exiu: exiu@510c {
+compatible = "socionext,sc2a11-exiu";
+reg = <0x0 0x510c 0x0 0x20>;
+interrupt-controller;
+interrupt-parent = <&gic>;
+#interrupt-cells = <3>;
+spi-base = <112>;
+};
 };
-- 
2.11.0

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[edk2] [PATCH edk2-platforms v3 22/27] Silicon/SynQuacer/AcpiTables: hide PCI domain #0

[Ard Biesheuvel]

The ACPI hack to support the broken Synopsys IP only works for endpoints,
not for non-trivial topologies involving switches. Given that the Linaro
developer board has a switch soldered on, there is really no way to do
anything useful with it when booting via ACPI. On top of that, the ITS
can only be enabled for a single RC.

So let's hide PCIe domain #0 entirely from the OS. We may be able to
expose the USB and SATA ports at some point using another ungodly hack,
but for now, this allows us to boot the board with unmodified installers
and install onto NVME.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel 
---
 Silicon/Socionext/SynQuacer/AcpiTables/AcpiSsdtRootPci.asl | 264 
++--
 Silicon/Socionext/SynQuacer/AcpiTables/Iort.aslc   |  44 ++--
 Silicon/Socionext/SynQuacer/AcpiTables/Mcfg.aslc   |  14 +-
 3 files changed, 161 insertions(+), 161 deletions(-)

diff --git a/Silicon/Socionext/SynQuacer/AcpiTables/AcpiSsdtRootPci.asl 
b/Silicon/Socionext/SynQuacer/AcpiTables/AcpiSsdtRootPci.asl
index fb845d2c107e..3e231e10f7dd 100644
--- a/Silicon/Socionext/SynQuacer/AcpiTables/AcpiSsdtRootPci.asl
+++ b/Silicon/Socionext/SynQuacer/AcpiTables/AcpiSsdtRootPci.asl
@@ -25,138 +25,138 @@ DefinitionBlock("SsdtPci.aml", "SSDT", 1, "SNI", 
"SYNQUACR", EFI_ACPI_OEM_REVISI
 //
 // PCI Root Complex
 //
-Device(PCI0)
-{
-Name(_HID, EISAID("PNP0A08"))   // PCI Express Root Bridge
-Name(_CID, EISAID("PNP0A03"))   // Compatible PCI Root Bridge
-Name(_SEG, Zero)// PCI Segment Group number
-Name(_BBN, Zero)// PCI Base Bus Number
-Name(_CCA, 1)   // Cache Coherency Attribute
-
-// PCI Routing Table
-Name(_PRT, Package() {
-Package () { 0x, 0, Zero, 222 },   // INTA
-Package () { 0x, 1, Zero, 222 },   // INTB
-Package () { 0x, 2, Zero, 222 },   // INTC
-Package () { 0x, 3, Zero, 222 },   // INTD
-})
-// Root complex resources
-Method (_CRS, 0, Serialized) {
-Name (RBUF, ResourceTemplate () {
-WordBusNumber ( // Bus numbers assigned to this root
-ResourceProducer,
-MinFixed, MaxFixed, PosDecode,
-0,  // AddressGranularity
-SYNQUACER_PCI_SEG0_BUSNUM_MIN,  // AddressMinimum - 
Minimum Bus Number
-SYNQUACER_PCI_SEG0_BUSNUM_MIN,  // AddressMaximum - 
Maximum Bus Number
-0,  // AddressTranslation - 
Set to 0
-1   // RangeLength - Number of 
Busses
-)
-
-DWordMemory ( // 32-bit BAR Windows
-ResourceProducer, PosDecode,
-MinFixed, MaxFixed,
-Cacheable, ReadWrite,
-0x, // Granularity
-SYNQUACER_PCI_SEG0_MMIO32_MIN,  // Min Base Address
-SYNQUACER_PCI_SEG0_MMIO32_MAX,  // Max Base Address
-0x, // Translate
-SYNQUACER_PCI_SEG0_MMIO32_SIZE  // Length
-)
-
-QWordMemory ( // 64-bit BAR Windows
-ResourceProducer, PosDecode,
-MinFixed, MaxFixed,
-Cacheable, ReadWrite,
-0x, // Granularity
-SYNQUACER_PCI_SEG0_MMIO64_MIN,  // Min Base Address
-SYNQUACER_PCI_SEG0_MMIO64_MAX,  // Max Base Address
-0x, // Translate
-SYNQUACER_PCI_SEG0_MMIO64_SIZE  // Length
-)
-
-DWordIo ( // IO window
-ResourceProducer,
-MinFixed,
-MaxFixed,
-PosDecode,
-EntireRange,
-0x, // Granularity
-SYNQUACER_PCI_SEG0_PORTIO_MIN,  // Min Base Address
-SYNQUACER_PCI_SEG0_PORTIO_MAX,  // Max Base Address
-SYNQUACER_PCI_SEG0_PORTIO_MEMBASE,  // Translate
-SYNQUACER_PCI_SEG0_PORTIO_SIZE, // Length
-,
-,
-,
-TypeTranslation
-)
-}) // Name(RBUF)
-
-Return (RBUF)
-} // Method(_CRS)
-
-Device (RES0)
-{
-Name (_HID, "PNP0C02")
-Name (_CRS, ResourceTemplate ()
-{
-Memory32Fixed (ReadWrite,
-   SYNQUACER_PCI_SEG0_CONFIG_BASE,
- 

[edk2] [PATCH edk2-platforms v3 23/27] Silicon/SynQuacerPciHostBridgeLib: add workaround to support 32-bit only cards

[Ard Biesheuvel]

Implement workaround suggested by Socionext to get legacy endpoints
with 32-bit BARs working. This fixes the issue on Developer Box with
the onboard ASM1061 SATA controller.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel 
Reviewed-by: Leif Lindholm 
---
 
Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLibConstructor.c
 | 8 ++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git 
a/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLibConstructor.c
 
b/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLibConstructor.c
index b5bfea8e0e75..1bbef5b6cf98 100644
--- 
a/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLibConstructor.c
+++ 
b/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLibConstructor.c
@@ -32,10 +32,13 @@
 #define IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_IO   0x2
 #define IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_CFG0 0x4
 #define IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_CFG1 0x5
+#define IATU_REGION_CTRL_1_OFF_OUTBOUND_0_THBIT12
 
 #define IATU_REGION_CTRL_2_OFF_OUTBOUND_0   0x908
 #define IATU_REGION_CTRL_2_OFF_OUTBOUND_0_REGION_EN BIT31
 #define IATU_REGION_CTRL_2_OFF_OUTBOUND_0_CFG_SHIFT_MODEBIT28
+#define IATU_REGION_CTRL_2_OFF_OUTBOUND_0_MSG_CODE_32BIT0xF
+#define IATU_REGION_CTRL_2_OFF_OUTBOUND_0_MSG_CODE_64BIT0xFF
 
 #define IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0   0x90C
 #define IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_0 0x910
@@ -297,8 +300,9 @@ PciInitController (
 RootBridge->Mem.Base,
 RootBridge->Mem.Base,
 RootBridge->Mem.Limit - RootBridge->Mem.Base + 1,
-IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_MEM,
-0);
+IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_MEM |
+IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TH,
+IATU_REGION_CTRL_2_OFF_OUTBOUND_0_MSG_CODE_32BIT);
 
   // Region 1: Type 0 config space
   ConfigureWindow (DbiBase, 1,
-- 
2.11.0

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[edk2] [PATCH edk2-platforms v3 24/27] Platform/Socionext: add support for Socionext Developer Box rev 0.1

[Ard Biesheuvel]

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel 
---
 Platform/Socionext/DeveloperBox/DeveloperBox.dsc   
   | 629 
 Platform/Socionext/DeveloperBox/DeveloperBox.fdf   
   | 487 +++
 
Platform/Socionext/DeveloperBox/SystemFirmwareDescriptor/SystemFirmwareDescriptor.aslc
|  80 +++
 
Platform/Socionext/DeveloperBox/SystemFirmwareDescriptor/SystemFirmwareDescriptor.inf
 |  46 ++
 
Platform/Socionext/DeveloperBox/SystemFirmwareDescriptor/SystemFirmwareDescriptorPei.c
|  68 +++
 
Platform/Socionext/DeveloperBox/SystemFirmwareUpdateConfig/SystemFirmwareUpdateConfig.ini
 |  25 +
 Silicon/Socionext/SynQuacer/DeviceTree/DeveloperBox.dts
   |  21 +
 Silicon/Socionext/SynQuacer/DeviceTree/DeveloperBox.inf
   |  33 +
 8 files changed, 1389 insertions(+)

diff --git a/Platform/Socionext/DeveloperBox/DeveloperBox.dsc 
b/Platform/Socionext/DeveloperBox/DeveloperBox.dsc
new file mode 100644
index ..f239692d614b
--- /dev/null
+++ b/Platform/Socionext/DeveloperBox/DeveloperBox.dsc
@@ -0,0 +1,629 @@
+#
+#  Copyright (c) 2013-2014, ARM Limited. All rights reserved.
+#  Copyright (c) 2017, Linaro Limited. All rights reserved.
+#
+#  This program and the accompanying materials
+#  are licensed and made available under the terms and conditions of the BSD 
License
+#  which accompanies this distribution.  The full text of the license may be 
found at
+#  http://opensource.org/licenses/bsd-license.php
+#
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR 
IMPLIED.
+#
+
+
+#
+# Defines Section - statements that will be processed to create a Makefile.
+#
+
+[Defines]
+  PLATFORM_NAME  = DeveloperBox
+  PLATFORM_GUID  = d32612b4-e1c5-431f-823a-fa1aa7b9deb7
+  PLATFORM_VERSION   = 0.1
+  DSC_SPECIFICATION  = 0x0001001B
+  OUTPUT_DIRECTORY   = Build/$(PLATFORM_NAME)
+  SUPPORTED_ARCHITECTURES= AARCH64|ARM
+  BUILD_TARGETS  = DEBUG|RELEASE
+  SKUID_IDENTIFIER   = DEFAULT
+  FLASH_DEFINITION   = 
Platform/Socionext/DeveloperBox/DeveloperBox.fdf
+
+[BuildOptions]
+  RELEASE_*_*_CC_FLAGS  = -DMDEPKG_NDEBUG -U_FORTIFY_SOURCE -D_FORTIFY_SOURCE=0
+
+[BuildOptions.common.EDKII.DXE_CORE,BuildOptions.common.EDKII.DXE_DRIVER,BuildOptions.common.EDKII.UEFI_DRIVER,BuildOptions.common.EDKII.UEFI_APPLICATION]
+  GCC:*_*_*_DLINK_FLAGS = -z common-page-size=0x1000
+
+[BuildOptions.common.EDKII.DXE_RUNTIME_DRIVER]
+  GCC:*_*_ARM_DLINK_FLAGS = -z common-page-size=0x1000
+  GCC:*_*_AARCH64_DLINK_FLAGS = -z common-page-size=0x1
+
+[LibraryClasses.common]
+  
ArmPlatformLib|Silicon/Socionext/SynQuacer/Library/SynQuacerLib/SynQuacerLib.inf
+  ArmHvcLib|ArmPkg/Library/ArmHvcLib/ArmHvcLib.inf
+  ArmSmcLib|ArmPkg/Library/ArmSmcLib/ArmSmcLib.inf
+
+  TimerLib|ArmPkg/Library/ArmArchTimerLib/ArmArchTimerLib.inf
+  FileHandleLib|MdePkg/Library/UefiFileHandleLib/UefiFileHandleLib.inf
+
+!if $(TARGET) == RELEASE
+  DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf
+!else
+  DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf
+!endif
+  
DebugPrintErrorLevelLib|MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.inf
+
+  BaseMemoryLib|MdePkg/Library/BaseMemoryLibOptDxe/BaseMemoryLibOptDxe.inf
+
+  # Networking Requirements
+  NetLib|MdeModulePkg/Library/DxeNetLib/DxeNetLib.inf
+  DpcLib|MdeModulePkg/Library/DxeDpcLib/DxeDpcLib.inf
+  UdpIoLib|MdeModulePkg/Library/DxeUdpIoLib/DxeUdpIoLib.inf
+  IpIoLib|MdeModulePkg/Library/DxeIpIoLib/DxeIpIoLib.inf
+
+  # ARM Architectural Libraries
+  
CacheMaintenanceLib|ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMaintenanceLib.inf
+  
DefaultExceptionHandlerLib|ArmPkg/Library/DefaultExceptionHandlerLib/DefaultExceptionHandlerLib.inf
+  CpuExceptionHandlerLib|ArmPkg/Library/ArmExceptionLib/ArmExceptionLib.inf
+  ArmDisassemblerLib|ArmPkg/Library/ArmDisassemblerLib/ArmDisassemblerLib.inf
+  ArmLib|ArmPkg/Library/ArmLib/ArmBaseLib.inf
+  ArmMmuLib|ArmPkg/Library/ArmMmuLib/ArmMmuBaseLib.inf
+  ArmGicLib|ArmPkg/Drivers/ArmGic/ArmGicLib.inf
+  ArmGicArchLib|ArmPkg/Library/ArmGicArchLib/ArmGicArchLib.inf
+  
ArmPlatformStackLib|ArmPlatformPkg/Library/ArmPlatformStackLib/ArmPlatformStackLib.inf
+  ArmSmcLib|ArmPkg/Library/ArmSmcLib/ArmSmcLib.inf
+  
ArmGenericTimerCounterLib|ArmPkg/Library/ArmGenericTimerPhyCounterLib/ArmGenericTimerPhyCounterLib.inf
+
+  BaseLib|MdePkg/Library/BaseLib/BaseLib.inf
+  
SynchronizationLib|MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.inf
+  
Per

[edk2] [PATCH edk2-platforms v3 21/27] Platform/SynQuacerEvalBoard: add signed capsule update support

[Ard Biesheuvel]

Add all the boilerplate to make the SPI NOR image updateable using
signed capsules and the FMP protocol.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel 
---
 Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.dsc   
 | 20 +
 Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.fdf   
 | 86 
 
Platform/Socionext/SynQuacerEvalBoard/SystemFirmwareDescriptor/SystemFirmwareDescriptor.aslc
| 80 ++
 
Platform/Socionext/SynQuacerEvalBoard/SystemFirmwareDescriptor/SystemFirmwareDescriptor.inf
 | 46 +++
 
Platform/Socionext/SynQuacerEvalBoard/SystemFirmwareDescriptor/SystemFirmwareDescriptorPei.c
| 68 
 
Platform/Socionext/SynQuacerEvalBoard/SystemFirmwareUpdateConfig/SystemFirmwareUpdateConfig.ini
 | 25 ++
 6 files changed, 325 insertions(+)

diff --git a/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.dsc 
b/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.dsc
index 5d2736a6130e..c2d84481dc4c 100644
--- a/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.dsc
+++ b/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.dsc
@@ -120,6 +120,10 @@ [LibraryClasses.common]
   NULL|ArmPkg/Library/CompilerIntrinsicsLib/CompilerIntrinsicsLib.inf
   NULL|MdePkg/Library/BaseStackCheckLib/BaseStackCheckLib.inf
 
+  BaseCryptLib|CryptoPkg/Library/BaseCryptLib/BaseCryptLib.inf
+  OpensslLib|CryptoPkg/Library/OpensslLib/OpensslLibCrypto.inf
+  IntrinsicLib|CryptoPkg/Library/IntrinsicLib/IntrinsicLib.inf
+
 [LibraryClasses.common.SEC]
   PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
   BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf
@@ -154,7 +158,15 @@ [LibraryClasses.common.DXE_CORE]
 [LibraryClasses.common.DXE_DRIVER]
   
SecurityManagementLib|MdeModulePkg/Library/DxeSecurityManagementLib/DxeSecurityManagementLib.inf
   PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.inf
+
+  #
+  # Firmware update
+  #
   CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibFmp/DxeCapsuleLib.inf
+  
EdkiiSystemCapsuleLib|SignedCapsulePkg/Library/EdkiiSystemCapsuleLib/EdkiiSystemCapsuleLib.inf
+  
FmpAuthenticationLib|SecurityPkg/Library/FmpAuthenticationLibPkcs7/FmpAuthenticationLibPkcs7.inf
+  
PlatformFlashAccessLib|Silicon/Socionext/SynQuacer/Library/SynQuacerPlatformFlashAccessLib/SynQuacerPlatformFlashAccessLib.inf
+  IniParsingLib|SignedCapsulePkg/Library/IniParsingLib/IniParsingLib.inf
 
   #
   # PCI
@@ -586,3 +598,11 @@ [Components.common]
 
   
DtPlatformDtbLoaderLib|EmbeddedPkg/Library/DxeDtPlatformDtbLoaderLibDefault/DxeDtPlatformDtbLoaderLibDefault.inf
   }
+
+  #
+  # Firmware update
+  #
+  
Platform/Socionext/SynQuacerEvalBoard/SystemFirmwareDescriptor/SystemFirmwareDescriptor.inf
+  MdeModulePkg/Universal/EsrtDxe/EsrtDxe.inf
+  SignedCapsulePkg/Universal/SystemFirmwareUpdate/SystemFirmwareReportDxe.inf
+  SignedCapsulePkg/Universal/SystemFirmwareUpdate/SystemFirmwareUpdateDxe.inf
diff --git a/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.fdf 
b/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.fdf
index 53f5fef96466..a57581f9ac5a 100644
--- a/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.fdf
+++ b/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.fdf
@@ -218,6 +218,16 @@ [FV.FvMain]
   INF EmbeddedPkg/Drivers/DtPlatformDxe/DtPlatformDxe.inf
   INF RuleOverride = DTB 
Silicon/Socionext/SynQuacer/DeviceTree/SynQuacerEvalBoard.inf
 
+  #
+  # Firmware update
+  #
+  INF MdeModulePkg/Universal/EsrtDxe/EsrtDxe.inf
+  INF 
SignedCapsulePkg/Universal/SystemFirmwareUpdate/SystemFirmwareReportDxe.inf
+  FILE FREEFORM = 
PCD(gEfiSignedCapsulePkgTokenSpaceGuid.PcdEdkiiPkcs7TestPublicKeyFileGuid) {
+ SECTION RAW = BaseTools/Source/Python/Pkcs7Sign/TestRoot.cer
+ SECTION UI = "Pkcs7TestRoot"
+  }
+
 [FV.FVMAIN_PEI]
 FvAlignment= 16
 ERASE_POLARITY = 1
@@ -245,6 +255,7 @@ [FV.FVMAIN_PEI]
   INF MdeModulePkg/Universal/FaultTolerantWritePei/FaultTolerantWritePei.inf
   INF MdeModulePkg/Universal/Variable/Pei/VariablePei.inf
   INF MdeModulePkg/Universal/CapsulePei/CapsulePei.inf
+  INF RuleOverride = FMP_IMAGE_DESC 
Platform/Socionext/SynQuacerEvalBoard/SystemFirmwareDescriptor/SystemFirmwareDescriptor.inf
   INF MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf
 
 [FV.FVMAIN_COMPACT]
@@ -273,6 +284,72 @@ [FV.FVMAIN_COMPACT]
 }
   }
 
+[FV.CapsuleDispatchFv]
+FvAlignment= 16
+ERASE_POLARITY = 1
+MEMORY_MAPPED  = TRUE
+STICKY_WRITE   = TRUE
+LOCK_CAP   = TRUE
+LOCK_STATUS= TRUE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP  = TRUE
+WRITE_STATUS   = TRUE
+WRITE_LOCK_CAP = TRUE
+WRITE_LOCK_STATUS  = TRUE
+READ_DISABLED_CAP  = TRUE
+READ_ENABLED_CAP   = TRUE
+READ_STATUS= TRUE
+READ_LOCK_CAP  = TRUE
+READ_LOCK_STATUS   = TRUE
+
+INF  
SignedCapsulePkg/Universal/SystemFirmwareUpdat

[edk2] [PATCH edk2-platforms v3 20/27] Socionext/SynQuacerEvalBoard: switch to execute in place

[Ard Biesheuvel]

Now that we switched to PrePeiCore, we can execute the firmware image
in place, using a stack and temporary heap in non-secure SRAM. This
allows us to query the secure firmware for the size and placement of
DRAM, and also allows the use of capsules for firmware update.

NOTE: this requires ARM Trusted Firmware to be built with PRELOADED_BL33_BASE
set to the base of UEFI in the NOR flash, 0x820_ in our case.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel 
Reviewed-by: Leif Lindholm 
---
 Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.fdf | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.fdf 
b/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.fdf
index f39f67f053be..53f5fef96466 100644
--- a/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.fdf
+++ b/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.fdf
@@ -26,7 +26,7 @@
 

 
 [FD.BL33_AP_UEFI]
-BaseAddress   = 0xE000|gArmTokenSpaceGuid.PcdFdBaseAddress  # The base 
address of the Firmware in NOR Flash.
+BaseAddress   = 0x0820|gArmTokenSpaceGuid.PcdFdBaseAddress  # The base 
address of the Firmware in NOR Flash.
 Size  = 0x0020|gArmTokenSpaceGuid.PcdFdSize # The size in 
bytes of the FLASH Device
 ErasePolarity = 1
 
-- 
2.11.0

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[edk2] [PATCH edk2-platforms v3 17/27] Silicon/SynQuacer: implement PlatformFlashAccessLib

[Ard Biesheuvel]

In order to support capsule update, implement PlatformFlashAccessLib that
exposes write access to the UEFI NOR partition.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel 
---
 
Silicon/Socionext/SynQuacer/Library/SynQuacerPlatformFlashAccessLib/SynQuacerPlatformFlashAccessLib.c
   | 251 
 
Silicon/Socionext/SynQuacer/Library/SynQuacerPlatformFlashAccessLib/SynQuacerPlatformFlashAccessLib.inf
 |  38 +++
 2 files changed, 289 insertions(+)

diff --git 
a/Silicon/Socionext/SynQuacer/Library/SynQuacerPlatformFlashAccessLib/SynQuacerPlatformFlashAccessLib.c
 
b/Silicon/Socionext/SynQuacer/Library/SynQuacerPlatformFlashAccessLib/SynQuacerPlatformFlashAccessLib.c
new file mode 100644
index ..5a67f8c00995
--- /dev/null
+++ 
b/Silicon/Socionext/SynQuacer/Library/SynQuacerPlatformFlashAccessLib/SynQuacerPlatformFlashAccessLib.c
@@ -0,0 +1,251 @@
+/** @file
+  Platform flash device access library for Socionext SynQuacer
+
+  Copyright (c) 2016, Linaro, Ltd. All rights reserved.
+
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD 
License
+  which accompanies this distribution.  The full text of the license may be 
found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include 
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+
+/**
+  Gets firmware volume block handle by given address.
+
+  This function gets firmware volume block handle whose
+  address range contains the parameter Address.
+
+  @param[in]  AddressAddress which should be contained
+ by returned FVB handle.
+  @param[out] FvbHandle  Pointer to FVB handle for output.
+
+  @retval EFI_SUCCESSFVB handle successfully returned.
+  @retval EFI_NOT_FOUND  Failed to find FVB handle by address.
+
+**/
+STATIC
+EFI_STATUS
+GetFvbByAddress (
+  IN  EFI_PHYSICAL_ADDRESSAddress,
+  OUT EFI_FIRMWARE_VOLUME_BLOCK_PROTOCOL  **OutFvb,
+  OUT EFI_PHYSICAL_ADDRESS*FvbBaseAddress
+  )
+{
+  EFI_STATUS  Status;
+  EFI_HANDLE  *HandleBuffer;
+  UINTN   HandleCount;
+  UINTN   Index;
+  EFI_FIRMWARE_VOLUME_BLOCK_PROTOCOL  *Fvb;
+  EFI_FIRMWARE_VOLUME_HEADER  *FwVolHeader;
+  EFI_FVB_ATTRIBUTES_2Attributes;
+
+  //
+  // Locate all handles with Firmware Volume Block protocol
+  //
+  Status = gBS->LocateHandleBuffer (
+  ByProtocol,
+  &gEfiFirmwareVolumeBlockProtocolGuid,
+  NULL,
+  &HandleCount,
+  &HandleBuffer
+  );
+  if (EFI_ERROR (Status)) {
+return EFI_NOT_FOUND;
+  }
+  //
+  // Traverse all the handles, searching for the one containing parameter 
Address
+  //
+  for (Index = 0; Index < HandleCount; Index += 1) {
+Status = gBS->HandleProtocol (
+HandleBuffer[Index],
+&gEfiFirmwareVolumeBlockProtocolGuid,
+(VOID **) &Fvb
+);
+if (EFI_ERROR (Status)) {
+  Status = EFI_NOT_FOUND;
+  break;
+}
+//
+// Checks if the address range of this handle contains parameter Address
+//
+Status = Fvb->GetPhysicalAddress (Fvb, FvbBaseAddress);
+if (EFI_ERROR (Status)) {
+  continue;
+}
+
+//
+// Check if this FVB is writable: DXE core produces FVB protocols for
+// firmware volumes as well.
+//
+Status = Fvb->GetAttributes (Fvb, &Attributes);
+if (EFI_ERROR (Status) || !(Attributes & EFI_FVB2_WRITE_STATUS)) {
+  DEBUG ((DEBUG_INFO,
+"%a: ignoring read-only FVB protocol implementation\n",
+__FUNCTION__));
+  continue;
+}
+
+FwVolHeader = (EFI_FIRMWARE_VOLUME_HEADER *) ((UINTN) *FvbBaseAddress);
+if ((Address >= *FvbBaseAddress) && (Address <= (*FvbBaseAddress + 
FwVolHeader->FvLength))) {
+  *OutFvb  = Fvb;
+  Status   = EFI_SUCCESS;
+  break;
+}
+
+Status = EFI_NOT_FOUND;
+  }
+
+  FreePool (HandleBuffer);
+  return Status;
+}
+
+/**
+  Perform flash write operation.
+
+  @param[in] FirmwareType  The type of firmware.
+  @param[in] FlashAddress  The address of flash device to be accessed.
+  @param[in] FlashAddressType  The type of flash device address.
+  @param[in] BufferThe pointer to the data buffer.
+  @param[in] LengthThe length of data buffer in bytes.
+
+  @retval EFI_SUCCESS   The operation returns successfully.
+  @retval EFI_WRITE_PROTECTED   The flash device is read only.
+  @retval EFI_UNSUPPORTED   The flash device access is unsupported.
+  @retval EFI_INVALID_PARAMETER The input parameter is

[edk2] [PATCH edk2-platforms v3 19/27] Socionext/SynQuacerEvalBoard: wire up basic capsule support

[Ard Biesheuvel]

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel 
Reviewed-by: Leif Lindholm 
---
 Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.dsc | 7 ++-
 Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.fdf | 2 ++
 2 files changed, 8 insertions(+), 1 deletion(-)

diff --git a/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.dsc 
b/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.dsc
index ea9d0bbcbf7b..5d2736a6130e 100644
--- a/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.dsc
+++ b/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.dsc
@@ -154,6 +154,7 @@ [LibraryClasses.common.DXE_CORE]
 [LibraryClasses.common.DXE_DRIVER]
   
SecurityManagementLib|MdeModulePkg/Library/DxeSecurityManagementLib/DxeSecurityManagementLib.inf
   PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.inf
+  CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibFmp/DxeCapsuleLib.inf
 
   #
   # PCI
@@ -178,7 +179,7 @@ [LibraryClasses.common.UEFI_APPLICATION]
 
 [LibraryClasses.common.DXE_RUNTIME_DRIVER]
   HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf
-  CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf
+  CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibFmp/DxeRuntimeCapsuleLib.inf
   
ResetSystemLib|ArmPkg/Library/ArmSmcPsciResetSystemLib/ArmSmcPsciResetSystemLib.inf
 
 

@@ -194,6 +195,8 @@ [PcdsFeatureFlag]
   gEfiMdeModulePkgTokenSpaceGuid.PcdConOutUgaSupport|FALSE
   gEfiMdePkgTokenSpaceGuid.PcdUgaConsumeSupport|FALSE
 
+  gEfiMdeModulePkgTokenSpaceGuid.PcdSupportUpdateCapsuleReset|TRUE
+
 [PcdsFixedAtBuild.common]
   gArmPlatformTokenSpaceGuid.PcdFirmwareVendor|"Linaro"
 
@@ -384,7 +387,9 @@ [Components.common]
   ArmPlatformPkg/PlatformPei/PlatformPeim.inf
   ArmPlatformPkg/MemoryInitPei/MemoryInitPeim.inf
   ArmPkg/Drivers/CpuPei/CpuPei.inf
+  MdeModulePkg/Universal/FaultTolerantWritePei/FaultTolerantWritePei.inf
   MdeModulePkg/Universal/Variable/Pei/VariablePei.inf
+  MdeModulePkg/Universal/CapsulePei/CapsulePei.inf
   MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf {
 
   
NULL|MdeModulePkg/Library/LzmaCustomDecompressLib/LzmaCustomDecompressLib.inf
diff --git a/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.fdf 
b/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.fdf
index 5ff6bcacf838..f39f67f053be 100644
--- a/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.fdf
+++ b/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.fdf
@@ -242,7 +242,9 @@ [FV.FVMAIN_PEI]
   INF ArmPlatformPkg/PlatformPei/PlatformPeim.inf
   INF ArmPlatformPkg/MemoryInitPei/MemoryInitPeim.inf
   INF ArmPkg/Drivers/CpuPei/CpuPei.inf
+  INF MdeModulePkg/Universal/FaultTolerantWritePei/FaultTolerantWritePei.inf
   INF MdeModulePkg/Universal/Variable/Pei/VariablePei.inf
+  INF MdeModulePkg/Universal/CapsulePei/CapsulePei.inf
   INF MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf
 
 [FV.FVMAIN_COMPACT]
-- 
2.11.0

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[edk2] [PATCH edk2-platforms v3 18/27] SynQuacer/SynQuacerMemoryInitPeiLib: add capsule support

[Ard Biesheuvel]

Add support for dealing with capsules left in memory by the OS before
reboot. This needs to be done early, before the memory is reused, which
is why the initial handling must reside here.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel 
Reviewed-by: Leif Lindholm 
---
 
Silicon/Socionext/SynQuacer/Library/SynQuacerMemoryInitPeiLib/SynQuacerMemoryInitPeiLib.c
   | 52 
 
Silicon/Socionext/SynQuacer/Library/SynQuacerMemoryInitPeiLib/SynQuacerMemoryInitPeiLib.inf
 |  4 +-
 2 files changed, 55 insertions(+), 1 deletion(-)

diff --git 
a/Silicon/Socionext/SynQuacer/Library/SynQuacerMemoryInitPeiLib/SynQuacerMemoryInitPeiLib.c
 
b/Silicon/Socionext/SynQuacer/Library/SynQuacerMemoryInitPeiLib/SynQuacerMemoryInitPeiLib.c
index ed616c3bedee..69dd96bb5877 100644
--- 
a/Silicon/Socionext/SynQuacer/Library/SynQuacerMemoryInitPeiLib/SynQuacerMemoryInitPeiLib.c
+++ 
b/Silicon/Socionext/SynQuacer/Library/SynQuacerMemoryInitPeiLib/SynQuacerMemoryInitPeiLib.c
@@ -22,10 +22,12 @@
 #include 
 #include 
 #include 
+#include 
 
 #include 
 #include 
 
+#include 
 #include 
 
 #define ARM_MEMORY_REGION(Base, Size) \
@@ -177,6 +179,11 @@ MemoryPeim (
 {
   EFI_STATUSStatus;
   ARM_MEMORY_REGION_DESCRIPTOR  *VirtualMemoryTable;
+  EFI_PEI_SERVICES  **PeiServices;
+  PEI_CAPSULE_PPI   *Capsule;
+  VOID  *CapsuleBuffer;
+  UINTN CapsuleBufferLength;
+  BOOLEAN   HaveCapsule;
 
   Status = DeclareDram (&VirtualMemoryTable);
   ASSERT_EFI_ERROR (Status);
@@ -184,12 +191,57 @@ MemoryPeim (
 return Status;
   }
 
+  PeiServices = (EFI_PEI_SERVICES **) GetPeiServicesTablePointer ();
+  ASSERT (PeiServices != NULL);
+
+  Status = PeiServicesLocatePpi (&gPeiCapsulePpiGuid, 0, NULL,
+ (VOID **)&Capsule);
+  ASSERT_EFI_ERROR (Status);
+
+  //
+  // Check for persistent capsules
+  //
+  HaveCapsule = FALSE;
+  Status = Capsule->CheckCapsuleUpdate (PeiServices);
+  if (!EFI_ERROR (Status)) {
+
+//
+// Coalesce the capsule into unused memory. CreateState() below will copy
+// it to a properly allocated buffer.
+//
+CapsuleBuffer = (VOID *)PcdGet64 (PcdSystemMemoryBase);
+CapsuleBufferLength = UefiMemoryBase - PcdGet64 (PcdSystemMemoryBase);
+
+PeiServicesSetBootMode (BOOT_ON_FLASH_UPDATE);
+
+Status = Capsule->Coalesce (PeiServices, &CapsuleBuffer,
+   &CapsuleBufferLength);
+if (!EFI_ERROR (Status)) {
+  DEBUG ((DEBUG_INFO, "%a: Coalesced capsule @ %p (0x%lx)\n",
+__FUNCTION__, CapsuleBuffer, CapsuleBufferLength));
+  HaveCapsule = TRUE;
+} else {
+  DEBUG ((DEBUG_WARN, "%a: failed to coalesce() capsule (Status == %r)\n",
+__FUNCTION__, Status));
+}
+  }
+
   Status = ArmConfigureMmu (VirtualMemoryTable, NULL, NULL);
   ASSERT_EFI_ERROR (Status);
   if (EFI_ERROR (Status)) {
 return Status;
   }
 
+  if (HaveCapsule) {
+Status = Capsule->CreateState (PeiServices, CapsuleBuffer,
+CapsuleBufferLength);
+
+if (EFI_ERROR (Status)) {
+  DEBUG ((DEBUG_WARN, "%a: Capsule->CreateState failed (Status == %r)\n",
+__FUNCTION__, Status));
+}
+  }
+
   if (FeaturePcdGet (PcdPrePiProduceMemoryTypeInformationHob)) {
 // Optional feature that helps prevent EFI memory map fragmentation.
 BuildMemoryTypeInformationHob ();
diff --git 
a/Silicon/Socionext/SynQuacer/Library/SynQuacerMemoryInitPeiLib/SynQuacerMemoryInitPeiLib.inf
 
b/Silicon/Socionext/SynQuacer/Library/SynQuacerMemoryInitPeiLib/SynQuacerMemoryInitPeiLib.inf
index f433d9a57079..c6071557fd41 100644
--- 
a/Silicon/Socionext/SynQuacer/Library/SynQuacerMemoryInitPeiLib/SynQuacerMemoryInitPeiLib.inf
+++ 
b/Silicon/Socionext/SynQuacer/Library/SynQuacerMemoryInitPeiLib/SynQuacerMemoryInitPeiLib.inf
@@ -39,6 +39,7 @@ [LibraryClasses]
   DebugLib
   MemoryAllocationLib
   PeiServicesLib
+  PeiServicesTablePointerLib
 
 [FeaturePcd]
   gEmbeddedTokenSpaceGuid.PcdPrePiProduceMemoryTypeInformationHob
@@ -64,7 +65,8 @@ [Pcd]
   gArmTokenSpaceGuid.PcdSystemMemoryBase
 
 [Ppis]
+  gPeiCapsulePpiGuid## CONSUMES
   gSynQuacerDramInfoPpiGuid ## CONSUMES
 
 [Depex]
-  gSynQuacerDramInfoPpiGuid
+  gPeiCapsulePpiGuid AND gSynQuacerDramInfoPpiGuid
-- 
2.11.0

___
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[edk2] [PATCH edk2-platforms v3 16/27] Platform/SynQuacer: incorporate NOR flash and variable drivers

[Ard Biesheuvel]

Wire up the non-volatile EFI variable store support, by switching from
the emulation driver to the real one, and enabling the prerequisite
FTW and NOR flash drivers.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel 
Reviewed-by: Leif Lindholm 
---
 Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.dsc   
 | 32 ++--
 Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.fdf   
 |  9 --
 
Silicon/Socionext/SynQuacer/Library/SynQuacerMemoryInitPeiLib/SynQuacerMemoryInitPeiLib.c
   | 12 
 
Silicon/Socionext/SynQuacer/Library/SynQuacerMemoryInitPeiLib/SynQuacerMemoryInitPeiLib.inf
 |  3 ++
 4 files changed, 52 insertions(+), 4 deletions(-)

diff --git a/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.dsc 
b/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.dsc
index ac90c718d003..ea9d0bbcbf7b 100644
--- a/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.dsc
+++ b/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.dsc
@@ -337,6 +337,19 @@ [PcdsFixedAtBuild.common]
   #
   gEfiMdeModulePkgTokenSpaceGuid.PcdSetNxForStack|TRUE
 
+  #
+  # Variable store
+  #
+  gFip006DxeTokenSpaceGuid.PcdFip006DxeRegBaseAddress|0x5480
+  gFip006DxeTokenSpaceGuid.PcdFip006DxeMemBaseAddress|0x0800
+
+  gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase|0x0840
+  gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize|0x0001
+  gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase|0x0841
+  gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize|0x0001
+  gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase|0x0842
+  gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize|0x0001
+
 [PcdsPatchableInModule]
   gEfiMdeModulePkgTokenSpaceGuid.PcdVideoHorizontalResolution|0
   gEfiMdeModulePkgTokenSpaceGuid.PcdVideoVerticalResolution|0
@@ -403,7 +416,6 @@ [Components.common]
   MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
   MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf
   ArmPkg/Drivers/TimerDxe/TimerDxe.inf
-  MdeModulePkg/Universal/Variable/EmuRuntimeDxe/EmuVariableRuntimeDxe.inf
   ArmPkg/Drivers/GenericWatchdogDxe/GenericWatchdogDxe.inf
   MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
 
@@ -422,6 +434,22 @@ [Components.common]
   }
 
   #
+  # Variable services
+  #
+  Silicon/Socionext/SynQuacer/Drivers/Fip006Dxe/Fip006Dxe.inf {
+
+  
NorFlashPlatformLib|Silicon/Socionext/SynQuacer/Library/NorFlashSynQuacerLib/NorFlashSynQuacerLib.inf
+  }
+  MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf
+  MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf {
+
+  
AuthVariableLib|MdeModulePkg/Library/AuthVariableLibNull/AuthVariableLibNull.inf
+  NULL|MdeModulePkg/Library/VarCheckUefiLib/VarCheckUefiLib.inf
+  
TpmMeasurementLib|MdeModulePkg/Library/TpmMeasurementLibNull/TpmMeasurementLibNull.inf
+  VarCheckLib|MdeModulePkg/Library/VarCheckLib/VarCheckLib.inf
+  }
+
+  #
   # UEFI application (Shell Embedded Boot Loader)
   #
   ShellPkg/Application/Shell/Shell.inf {
@@ -535,7 +563,7 @@ [Components.common]
   #
   MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf {
 
-  #NULL|EmbeddedPkg/Library/PlatformHasAcpiLib/PlatformHasAcpiLib.inf
+  NULL|EmbeddedPkg/Library/PlatformHasAcpiLib/PlatformHasAcpiLib.inf
 
 
   # support ACPI v5.0 or later
diff --git a/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.fdf 
b/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.fdf
index 961482b12e62..5ff6bcacf838 100644
--- a/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.fdf
+++ b/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.fdf
@@ -1,4 +1,3 @@
-
 #
 #  Copyright (c) 2013-2014, ARM Limited. All rights reserved.
 #  Copyright (c) 2017, Linaro Limited. All rights reserved.
@@ -105,7 +104,6 @@ [FV.FvMain]
   INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
   INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf
   INF ArmPkg/Drivers/TimerDxe/TimerDxe.inf
-  INF MdeModulePkg/Universal/Variable/EmuRuntimeDxe/EmuVariableRuntimeDxe.inf
   INF ArmPkg/Drivers/GenericWatchdogDxe/GenericWatchdogDxe.inf
   INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
 
@@ -120,6 +118,13 @@ [FV.FvMain]
   INF ArmPkg/Drivers/ArmGic/ArmGicDxe.inf
 
   #
+  # Variable services
+  #
+  INF Silicon/Socionext/SynQuacer/Drivers/Fip006Dxe/Fip006Dxe.inf
+  INF MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf
+  INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf
+
+  #
   # UEFI applications
   #
   INF ShellPkg/Application/Shell/Shell.inf
diff --git 
a/Silicon/Socionext/SynQuacer/Library/SynQuacerMemoryInitPeiLib/SynQuacerMemoryInitPeiLib.c
 
b/Silicon/Socionext/SynQuacer/Library/SynQuacerMemoryInitPeiLib/SynQuacerMemoryInitPeiLib.c
index e9a

[edk2] [PATCH edk2-platforms v3 12/27] Silicon/SynQuacer: add ACPI support

[Ard Biesheuvel]

Enable ACPI support for the SynQuacerEvalBoard platform: add descriptions
of the CPUs, the GIC, the serial port, the timers and the PCIe RCs,
including the MSI routing via the GICv3 ITS.

Note that PCIe support is limited to a single bus per RC. Anything beyond
that is unsupported due to a limitation in the hardware that makes it
impossible to expose the PCIe RCs in a fully ECAM compliant manner.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel 
---
 Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.dsc |  15 +
 Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.fdf |  14 +
 Silicon/Socionext/SynQuacer/AcpiTables/AcpiSsdtRootPci.asl   | 294 

 Silicon/Socionext/SynQuacer/AcpiTables/AcpiTables.h  |  58 
 Silicon/Socionext/SynQuacer/AcpiTables/AcpiTables.inf|  62 +
 Silicon/Socionext/SynQuacer/AcpiTables/Dsdt.asl  | 167 +++
 Silicon/Socionext/SynQuacer/AcpiTables/Fadt.aslc |  89 ++
 Silicon/Socionext/SynQuacer/AcpiTables/Gtdt.aslc |  98 +++
 Silicon/Socionext/SynQuacer/AcpiTables/Iort.aslc | 164 +++
 Silicon/Socionext/SynQuacer/AcpiTables/Madt.aslc | 152 ++
 Silicon/Socionext/SynQuacer/AcpiTables/Mcfg.aslc |  63 +
 Silicon/Socionext/SynQuacer/AcpiTables/Spcr.aslc | 127 +
 12 files changed, 1303 insertions(+)

diff --git a/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.dsc 
b/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.dsc
index f8579e5739b5..02db912562bd 100644
--- a/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.dsc
+++ b/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.dsc
@@ -529,3 +529,18 @@ [Components.common]
 
   DmaLib|EmbeddedPkg/Library/NonCoherentDmaLib/NonCoherentDmaLib.inf
   }
+
+  #
+  # ACPI support
+  #
+  MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf {
+
+  #NULL|EmbeddedPkg/Library/PlatformHasAcpiLib/PlatformHasAcpiLib.inf
+
+
+  # support ACPI v5.0 or later
+  gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiExposedTableVersions|0x20
+  }
+  MdeModulePkg/Universal/Acpi/AcpiPlatformDxe/AcpiPlatformDxe.inf
+  Silicon/Socionext/SynQuacer/AcpiTables/AcpiTables.inf
+  
MdeModulePkg/Universal/Acpi/BootGraphicsResourceTableDxe/BootGraphicsResourceTableDxe.inf
diff --git a/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.fdf 
b/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.fdf
index 3e1af577371a..2935f19139b6 100644
--- a/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.fdf
+++ b/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.fdf
@@ -198,6 +198,14 @@ [FV.FvMain]
   INF NetworkPkg/HttpBootDxe/HttpBootDxe.inf
   INF Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/NetsecDxe.inf
 
+  #
+  # ACPI support
+  #
+  INF MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf
+  INF MdeModulePkg/Universal/Acpi/AcpiPlatformDxe/AcpiPlatformDxe.inf
+  INF RuleOverride = ACPITABLE 
Silicon/Socionext/SynQuacer/AcpiTables/AcpiTables.inf
+  INF 
MdeModulePkg/Universal/Acpi/BootGraphicsResourceTableDxe/BootGraphicsResourceTableDxe.inf
+
 [FV.FVMAIN_PEI]
 FvAlignment= 16
 ERASE_POLARITY = 1
@@ -354,3 +362,9 @@ [Rule.Common.UEFI_APPLICATION.BINARY]
 UISTRING="$(MODULE_NAME)" Optional
 VERSION   STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
   }
+
+[Rule.Common.USER_DEFINED.ACPITABLE]
+  FILE FREEFORM = $(NAMED_GUID) {
+RAW ACPI   |.acpi
+RAW ASL|.aml
+  }
diff --git a/Silicon/Socionext/SynQuacer/AcpiTables/AcpiSsdtRootPci.asl 
b/Silicon/Socionext/SynQuacer/AcpiTables/AcpiSsdtRootPci.asl
new file mode 100644
index ..fb845d2c107e
--- /dev/null
+++ b/Silicon/Socionext/SynQuacer/AcpiTables/AcpiSsdtRootPci.asl
@@ -0,0 +1,294 @@
+/** @file
+  Secondary System Description Table (SSDT) for SynQuacer PCIe RCs
+
+  Copyright (c) 2014-2016, ARM Ltd. All rights reserved.
+  Copyright (c) 2017, Linaro Ltd. All rights reserved.
+
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD 
License
+  which accompanies this distribution.  The full text of the license may be 
found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include 
+
+#include "AcpiTables.h"
+
+DefinitionBlock("SsdtPci.aml", "SSDT", 1, "SNI", "SYNQUACR", 
EFI_ACPI_OEM_REVISION)
+{
+  Scope(_SB)
+  {
+//
+// PCI Root Complex
+//
+Device(PCI0)
+{
+Name(_HID, EISAID("PNP0A08"))   // PCI Express Root Bridge
+Name(_CID, EISAID("PNP0A03"))   // Compatible PCI Root Bridge
+Name(_SEG, Zero)// PCI Segment Group number
+Name(_BBN, Zero)// P

[edk2] [PATCH edk2-platforms v3 15/27] Silicon/Socionext: add driver for SPI NOR flash

[Ard Biesheuvel]

From: Pipat Methavanitpong 

This imports the driver sources provided by Socionext for the FIP006
SPI NOR flash device found on SynQuacer SoCs. It has been slightly
tweaked to bring it up to date with the changes made on the EDK2 side
since it was forked.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Pipat Methavanitpong 
Signed-off-by: Ard Biesheuvel 
---
 Silicon/Socionext/SynQuacer/Drivers/Fip006Dxe/Fip006Dxe.dec|   31 +
 Silicon/Socionext/SynQuacer/Drivers/Fip006Dxe/Fip006Dxe.inf|   79 ++
 Silicon/Socionext/SynQuacer/Drivers/Fip006Dxe/Fip006Reg.h  |  244 
 Silicon/Socionext/SynQuacer/Drivers/Fip006Dxe/NorFlashBlockIoDxe.c |  138 ++
 Silicon/Socionext/SynQuacer/Drivers/Fip006Dxe/NorFlashDxe.c| 1376 

 Silicon/Socionext/SynQuacer/Drivers/Fip006Dxe/NorFlashDxe.h|  314 +
 Silicon/Socionext/SynQuacer/Drivers/Fip006Dxe/NorFlashFvbDxe.c |  859 

 7 files changed, 3041 insertions(+)

diff --git a/Silicon/Socionext/SynQuacer/Drivers/Fip006Dxe/Fip006Dxe.dec 
b/Silicon/Socionext/SynQuacer/Drivers/Fip006Dxe/Fip006Dxe.dec
new file mode 100644
index ..aec95bc82387
--- /dev/null
+++ b/Silicon/Socionext/SynQuacer/Drivers/Fip006Dxe/Fip006Dxe.dec
@@ -0,0 +1,31 @@
+## @file
+#  Socionext FIP006 High-Speed SPI Controller with NOR Flash Driver
+#
+#  Copyright (c) 2017, Socionext Inc. All rights reserved.
+#
+#  This program and the accompanying materials
+#  are licensed and made available under the terms and conditions of the BSD 
License
+#  which accompanies this distribution.  The full text of the license may be 
found at
+#  http://opensource.org/licenses/bsd-license.php
+#
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR 
IMPLIED.
+#
+##
+
+[Defines]
+  DEC_SPECIFICATION = 0x0001001A
+  PACKAGE_NAME  = Fip006DxePkg
+  PACKAGE_GUID  = ABC7870B-FE82-4DAD-8179-FEC5F5194FA0
+  PACKAGE_VERSION   = 0.1
+
+[Guids]
+  gFip006DxeTokenSpaceGuid  = {0x4D45399E, 0x98F9, 0x4127, {0x8F, 
0xB9,0xF8, 0xDE, 0x22, 0xA1, 0x09, 0x2C}}
+
+[PcdsFixedAtBuild]
+  gFip006DxeTokenSpaceGuid.PcdFip006DxeRegBaseAddress|0x0|UINT32|0x0001
+  gFip006DxeTokenSpaceGuid.PcdFip006DxeMemBaseAddress|0x0|UINT32|0x0002
+  gFip006DxeTokenSpaceGuid.PcdN25qSlaveId|0x0|UINT8|0x0003
+  gFip006DxeTokenSpaceGuid.PcdN25qBlockSize|256|UINT32|0x0004
+  gFip006DxeTokenSpaceGuid.PcdN25qBlockCount|524288|UINT32|0x0005
+
diff --git a/Silicon/Socionext/SynQuacer/Drivers/Fip006Dxe/Fip006Dxe.inf 
b/Silicon/Socionext/SynQuacer/Drivers/Fip006Dxe/Fip006Dxe.inf
new file mode 100644
index ..52ffdd8c0304
--- /dev/null
+++ b/Silicon/Socionext/SynQuacer/Drivers/Fip006Dxe/Fip006Dxe.inf
@@ -0,0 +1,79 @@
+## @file
+#  Socionext FIP006 High-Speed SPI Controller with NOR Flash Driver
+#
+#  Copyright (c) 2017, Socionext Inc. All rights reserved.
+#  Copyright (c) 2017, Linaro, Ltd. All rights reserved.
+#
+#  This program and the accompanying materials
+#  are licensed and made available under the terms and conditions of the BSD 
License
+#  which accompanies this distribution.  The full text of the license may be 
found at
+#  http://opensource.org/licenses/bsd-license.php
+#
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR 
IMPLIED.
+#
+##
+
+
+[Defines]
+  INF_VERSION= 0x0001001A
+  BASE_NAME  = Fip006Dxe
+  FILE_GUID  = 44F7D21F-C36F-4766-BC5B-C72E97E6897B
+  MODULE_TYPE= DXE_RUNTIME_DRIVER
+  VERSION_STRING = 0.1
+  ENTRY_POINT= NorFlashInitialise
+
+[Sources]
+  NorFlashBlockIoDxe.c
+  NorFlashDxe.c
+  NorFlashFvbDxe.c
+
+[Packages]
+  ArmPlatformPkg/ArmPlatformPkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+  MdePkg/MdePkg.dec
+  Silicon/Socionext/SynQuacer/Drivers/Fip006Dxe/Fip006Dxe.dec
+
+[LibraryClasses]
+  BaseLib
+  BaseMemoryLib
+  DebugLib
+  DevicePathLib
+  DxeServicesTableLib
+  HobLib
+  IoLib
+  MemoryAllocationLib
+  NorFlashPlatformLib
+  UefiBootServicesTableLib
+  UefiDriverEntryPoint
+  UefiLib
+  UefiRuntimeLib
+  UefiRuntimeServicesTableLib
+
+[Guids]
+  gEfiAuthenticatedVariableGuid
+  gEfiEventVirtualAddressChangeGuid
+  gEfiSystemNvDataFvGuid
+  gEfiVariableGuid
+
+[Protocols]
+  gEfiBlockIoProtocolGuid
+  gEfiDevicePathProtocolGuid
+  gEfiDiskIoProtocolGuid
+  gEfiFirmwareVolumeBlockProtocolGuid
+
+[FixedPcd]
+  gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase
+  gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize
+  gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase
+  gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize
+  gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase
+  gEfiMdeModuleP

[edk2] [PATCH edk2-platforms v3 06/27] Platform: add support for Socionext SynQuacer eval board

[Ard Biesheuvel]

This is a barebones port based on the .DSC/.FDF and ArmPlatformLib
code provided by Socionext. It can boot into the UiApp menu screen
or the UEFI Shell, but lacks support for any peripherals.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel 
---
 Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.dsc   | 
432 
 Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.fdf   | 
290 +
 Silicon/Socionext/SynQuacer/Library/SynQuacerLib/AArch64/SynQuacerHelper.S |  
87 
 Silicon/Socionext/SynQuacer/Library/SynQuacerLib/Arm/SynQuacerHelper.S |  
87 
 Silicon/Socionext/SynQuacer/Library/SynQuacerLib/SynQuacer.c   | 
125 ++
 Silicon/Socionext/SynQuacer/Library/SynQuacerLib/SynQuacerLib.inf  |  
43 ++
 6 files changed, 1064 insertions(+)

diff --git a/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.dsc 
b/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.dsc
new file mode 100644
index ..3dc8aa7461d6
--- /dev/null
+++ b/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.dsc
@@ -0,0 +1,432 @@
+#
+#  Copyright (c) 2013-2014, ARM Limited. All rights reserved.
+#  Copyright (c) 2017, Linaro Limited. All rights reserved.
+#
+#  This program and the accompanying materials
+#  are licensed and made available under the terms and conditions of the BSD 
License
+#  which accompanies this distribution.  The full text of the license may be 
found at
+#  http://opensource.org/licenses/bsd-license.php
+#
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR 
IMPLIED.
+#
+
+
+#
+# Defines Section - statements that will be processed to create a Makefile.
+#
+
+[Defines]
+  PLATFORM_NAME  = SynQuacerEvalBoard
+  PLATFORM_GUID  = a8180daa-fb8b-11e5-ab24-9fc3167c073d
+  PLATFORM_VERSION   = 0.1
+  DSC_SPECIFICATION  = 0x0001001B
+  OUTPUT_DIRECTORY   = Build/$(PLATFORM_NAME)
+  SUPPORTED_ARCHITECTURES= AARCH64|ARM
+  BUILD_TARGETS  = DEBUG|RELEASE
+  SKUID_IDENTIFIER   = DEFAULT
+  FLASH_DEFINITION   = 
Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.fdf
+
+[BuildOptions]
+  RELEASE_*_*_CC_FLAGS  = -DMDEPKG_NDEBUG -U_FORTIFY_SOURCE -D_FORTIFY_SOURCE=0
+
+[BuildOptions.common.EDKII.DXE_CORE,BuildOptions.common.EDKII.DXE_DRIVER,BuildOptions.common.EDKII.UEFI_DRIVER,BuildOptions.common.EDKII.UEFI_APPLICATION]
+  GCC:*_*_*_DLINK_FLAGS = -z common-page-size=0x1000
+
+[BuildOptions.common.EDKII.DXE_RUNTIME_DRIVER]
+  GCC:*_*_ARM_DLINK_FLAGS = -z common-page-size=0x1000
+  GCC:*_*_AARCH64_DLINK_FLAGS = -z common-page-size=0x1
+
+[LibraryClasses.common]
+  
ArmPlatformLib|Silicon/Socionext/SynQuacer/Library/SynQuacerLib/SynQuacerLib.inf
+  ArmHvcLib|ArmPkg/Library/ArmHvcLib/ArmHvcLib.inf
+  ArmSmcLib|ArmPkg/Library/ArmSmcLib/ArmSmcLib.inf
+
+  TimerLib|ArmPkg/Library/ArmArchTimerLib/ArmArchTimerLib.inf
+  FileHandleLib|MdePkg/Library/UefiFileHandleLib/UefiFileHandleLib.inf
+
+!if $(TARGET) == RELEASE
+  DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf
+!else
+  DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf
+!endif
+  
DebugPrintErrorLevelLib|MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.inf
+
+  BaseMemoryLib|MdePkg/Library/BaseMemoryLibOptDxe/BaseMemoryLibOptDxe.inf
+
+  # Networking Requirements
+  NetLib|MdeModulePkg/Library/DxeNetLib/DxeNetLib.inf
+  DpcLib|MdeModulePkg/Library/DxeDpcLib/DxeDpcLib.inf
+  UdpIoLib|MdeModulePkg/Library/DxeUdpIoLib/DxeUdpIoLib.inf
+  IpIoLib|MdeModulePkg/Library/DxeIpIoLib/DxeIpIoLib.inf
+
+  # ARM Architectural Libraries
+  
CacheMaintenanceLib|ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMaintenanceLib.inf
+  
DefaultExceptionHandlerLib|ArmPkg/Library/DefaultExceptionHandlerLib/DefaultExceptionHandlerLib.inf
+  CpuExceptionHandlerLib|ArmPkg/Library/ArmExceptionLib/ArmExceptionLib.inf
+  ArmDisassemblerLib|ArmPkg/Library/ArmDisassemblerLib/ArmDisassemblerLib.inf
+  ArmLib|ArmPkg/Library/ArmLib/ArmBaseLib.inf
+  ArmMmuLib|ArmPkg/Library/ArmMmuLib/ArmMmuBaseLib.inf
+  ArmGicLib|ArmPkg/Drivers/ArmGic/ArmGicLib.inf
+  ArmGicArchLib|ArmPkg/Library/ArmGicArchLib/ArmGicArchLib.inf
+  
ArmPlatformStackLib|ArmPlatformPkg/Library/ArmPlatformStackLib/ArmPlatformStackLib.inf
+  ArmSmcLib|ArmPkg/Library/ArmSmcLib/ArmSmcLib.inf
+  
ArmGenericTimerCounterLib|ArmPkg/Library/ArmGenericTimerPhyCounterLib/ArmGenericTimerPhyCounterLib.inf
+
+  BaseLib|MdePkg/Library/BaseLib/BaseLib.inf
+  
SynchronizationLib|MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.inf
+  
PerformanceLib|MdePkg/Library/BasePerformance

[edk2] [PATCH edk2-platforms v3 11/27] Platform/SynQuacerEvalBoard: add NETSEC driver

[Ard Biesheuvel]

Add the NETSEC driver to the SynQuacerEvalBoard platform.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel 
Reviewed-by: Leif Lindholm 
---
 Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.dsc | 47 

 Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.fdf | 25 +++
 2 files changed, 72 insertions(+)

diff --git a/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.dsc 
b/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.dsc
index 519a078e15dc..f8579e5739b5 100644
--- a/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.dsc
+++ b/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.dsc
@@ -114,6 +114,9 @@ [LibraryClasses.common]
   
SerialPortLib|ArmPlatformPkg/Library/PL011SerialPortLib/PL011SerialPortLib.inf
   PL011UartLib|ArmPlatformPkg/Drivers/PL011Uart/PL011Uart.inf
 
+  HttpLib|MdeModulePkg/Library/DxeHttpLib/DxeHttpLib.inf
+  TcpIoLib|MdeModulePkg/Library/DxeTcpIoLib/DxeTcpIoLib.inf
+
   NULL|ArmPkg/Library/CompilerIntrinsicsLib/CompilerIntrinsicsLib.inf
   NULL|MdePkg/Library/BaseStackCheckLib/BaseStackCheckLib.inf
 
@@ -230,6 +233,22 @@ [PcdsFixedAtBuild.common]
   gArmTokenSpaceGuid.PcdGenericWatchdogControlBase|0x2a44
   gArmTokenSpaceGuid.PcdGenericWatchdogRefreshBase|0x2a45
 
+  #
+  # NETSEC Info
+  #
+  gNetsecDxeTokenSpaceGuid.PcdEncTxDescNum|128
+  gNetsecDxeTokenSpaceGuid.PcdDecRxDescNum|128
+  gNetsecDxeTokenSpaceGuid.PcdJumboPacket|0
+  gNetsecDxeTokenSpaceGuid.PcdFlowCtrl|0
+  gNetsecDxeTokenSpaceGuid.PcdFlowCtrlStartThreshold|36
+  gNetsecDxeTokenSpaceGuid.PcdFlowCtrlStopThreshold|48
+  gNetsecDxeTokenSpaceGuid.PcdPauseTime|256
+
+  gSynQuacerTokenSpaceGuid.PcdNetsecEepromBase|0x1000
+  gSynQuacerTokenSpaceGuid.PcdNetsecPhyAddress|1
+
+  gEfiNetworkPkgTokenSpaceGuid.PcdAllowHttpConnections|TRUE
+
   gEfiMdePkgTokenSpaceGuid.PcdMaximumUnicodeStringLength|100
   gEfiMdePkgTokenSpaceGuid.PcdMaximumAsciiStringLength|100
   gEfiMdePkgTokenSpaceGuid.PcdMaximumLinkedListLength|100
@@ -482,3 +501,31 @@ [Components.common]
   # RNG
   #
   Silicon/Openmoko/ChaosKeyDxe/ChaosKeyDxe.inf
+
+  #
+  # Networking stack
+  #
+  MdeModulePkg/Universal/Network/DpcDxe/DpcDxe.inf
+  MdeModulePkg/Universal/Network/ArpDxe/ArpDxe.inf
+  MdeModulePkg/Universal/Network/Dhcp4Dxe/Dhcp4Dxe.inf
+  MdeModulePkg/Universal/Network/Ip4Dxe/Ip4Dxe.inf
+  MdeModulePkg/Universal/Network/SnpDxe/SnpDxe.inf
+  MdeModulePkg/Universal/Network/MnpDxe/MnpDxe.inf
+  MdeModulePkg/Universal/Network/VlanConfigDxe/VlanConfigDxe.inf
+  MdeModulePkg/Universal/Network/Mtftp4Dxe/Mtftp4Dxe.inf
+  MdeModulePkg/Universal/Network/Udp4Dxe/Udp4Dxe.inf
+  NetworkPkg/Ip6Dxe/Ip6Dxe.inf
+  NetworkPkg/TcpDxe/TcpDxe.inf
+  NetworkPkg/Udp6Dxe/Udp6Dxe.inf
+  NetworkPkg/Dhcp6Dxe/Dhcp6Dxe.inf
+  NetworkPkg/Mtftp6Dxe/Mtftp6Dxe.inf
+  NetworkPkg/UefiPxeBcDxe/UefiPxeBcDxe.inf
+  NetworkPkg/IScsiDxe/IScsiDxe.inf
+  NetworkPkg/DnsDxe/DnsDxe.inf
+  NetworkPkg/HttpUtilitiesDxe/HttpUtilitiesDxe.inf
+  NetworkPkg/HttpDxe/HttpDxe.inf
+  NetworkPkg/HttpBootDxe/HttpBootDxe.inf
+  Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/NetsecDxe.inf {
+
+  DmaLib|EmbeddedPkg/Library/NonCoherentDmaLib/NonCoherentDmaLib.inf
+  }
diff --git a/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.fdf 
b/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.fdf
index 838963eff612..3e1af577371a 100644
--- a/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.fdf
+++ b/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.fdf
@@ -173,6 +173,31 @@ [FV.FvMain]
   #
   INF Silicon/Openmoko/ChaosKeyDxe/ChaosKeyDxe.inf
 
+  #
+  # Networking stack
+  #
+  INF MdeModulePkg/Universal/Network/DpcDxe/DpcDxe.inf
+  INF MdeModulePkg/Universal/Network/ArpDxe/ArpDxe.inf
+  INF MdeModulePkg/Universal/Network/Dhcp4Dxe/Dhcp4Dxe.inf
+  INF MdeModulePkg/Universal/Network/Ip4Dxe/Ip4Dxe.inf
+  INF MdeModulePkg/Universal/Network/MnpDxe/MnpDxe.inf
+  INF MdeModulePkg/Universal/Network/SnpDxe/SnpDxe.inf
+  INF MdeModulePkg/Universal/Network/VlanConfigDxe/VlanConfigDxe.inf
+  INF MdeModulePkg/Universal/Network/Mtftp4Dxe/Mtftp4Dxe.inf
+  INF MdeModulePkg/Universal/Network/Udp4Dxe/Udp4Dxe.inf
+  INF NetworkPkg/Ip6Dxe/Ip6Dxe.inf
+  INF NetworkPkg/TcpDxe/TcpDxe.inf
+  INF NetworkPkg/Udp6Dxe/Udp6Dxe.inf
+  INF NetworkPkg/Dhcp6Dxe/Dhcp6Dxe.inf
+  INF NetworkPkg/Mtftp6Dxe/Mtftp6Dxe.inf
+  INF NetworkPkg/UefiPxeBcDxe/UefiPxeBcDxe.inf
+  INF NetworkPkg/IScsiDxe/IScsiDxe.inf
+  INF NetworkPkg/DnsDxe/DnsDxe.inf
+  INF NetworkPkg/HttpUtilitiesDxe/HttpUtilitiesDxe.inf
+  INF NetworkPkg/HttpDxe/HttpDxe.inf
+  INF NetworkPkg/HttpBootDxe/HttpBootDxe.inf
+  INF Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/NetsecDxe.inf
+
 [FV.FVMAIN_PEI]
 FvAlignment= 16
 ERASE_POLARITY = 1
-- 
2.11.0

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[edk2] [PATCH edk2-platforms v3 13/27] Silicon/SynQuacer: add device tree support for eval board

[Ard Biesheuvel]

Add a device tree description of the SynQuacer SoC, and expose it for
the SynQuacerEvalBoard platforms. This includes the menu option in the
UEFI boot menu to switch between ACPI and DT.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel 
Reviewed-by: Leif Lindholm 
---
 Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.dsc  |   9 +
 Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.fdf  |  12 +
 Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi | 514 

 Silicon/Socionext/SynQuacer/DeviceTree/SynQuacerEvalBoard.dts |  21 +
 Silicon/Socionext/SynQuacer/DeviceTree/SynQuacerEvalBoard.inf |  33 ++
 5 files changed, 589 insertions(+)

diff --git a/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.dsc 
b/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.dsc
index 02db912562bd..ac90c718d003 100644
--- a/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.dsc
+++ b/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.dsc
@@ -544,3 +544,12 @@ [Components.common]
   MdeModulePkg/Universal/Acpi/AcpiPlatformDxe/AcpiPlatformDxe.inf
   Silicon/Socionext/SynQuacer/AcpiTables/AcpiTables.inf
   
MdeModulePkg/Universal/Acpi/BootGraphicsResourceTableDxe/BootGraphicsResourceTableDxe.inf
+
+  #
+  # DT support
+  #
+  Silicon/Socionext/SynQuacer/DeviceTree/SynQuacerEvalBoard.inf
+  EmbeddedPkg/Drivers/DtPlatformDxe/DtPlatformDxe.inf {
+
+  
DtPlatformDtbLoaderLib|EmbeddedPkg/Library/DxeDtPlatformDtbLoaderLibDefault/DxeDtPlatformDtbLoaderLibDefault.inf
+  }
diff --git a/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.fdf 
b/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.fdf
index 2935f19139b6..961482b12e62 100644
--- a/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.fdf
+++ b/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.fdf
@@ -1,3 +1,4 @@
+
 #
 #  Copyright (c) 2013-2014, ARM Limited. All rights reserved.
 #  Copyright (c) 2017, Linaro Limited. All rights reserved.
@@ -206,6 +207,12 @@ [FV.FvMain]
   INF RuleOverride = ACPITABLE 
Silicon/Socionext/SynQuacer/AcpiTables/AcpiTables.inf
   INF 
MdeModulePkg/Universal/Acpi/BootGraphicsResourceTableDxe/BootGraphicsResourceTableDxe.inf
 
+  #
+  # DT support
+  #
+  INF EmbeddedPkg/Drivers/DtPlatformDxe/DtPlatformDxe.inf
+  INF RuleOverride = DTB 
Silicon/Socionext/SynQuacer/DeviceTree/SynQuacerEvalBoard.inf
+
 [FV.FVMAIN_PEI]
 FvAlignment= 16
 ERASE_POLARITY = 1
@@ -368,3 +375,8 @@ [Rule.Common.USER_DEFINED.ACPITABLE]
 RAW ACPI   |.acpi
 RAW ASL|.aml
   }
+
+[Rule.Common.USER_DEFINED.DTB]
+  FILE FREEFORM = $(NAMED_GUID) {
+RAW BIN|.dtb
+  }
diff --git a/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi 
b/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi
new file mode 100644
index ..3aef10294662
--- /dev/null
+++ b/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi
@@ -0,0 +1,514 @@
+/** @file
+ * Copyright (c) 2017, Linaro Limited. All rights reserved.
+ *
+ * This program and the accompanying materials are licensed and made
+ * available under the terms and conditions of the BSD License which
+ * accompanies this distribution.  The full text of the license may be
+ * found at http://opensource.org/licenses/bsd-license.php
+ *
+ * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR
+ * IMPLIED.
+ */
+
+#define GIC_SPI 0
+#define GIC_PPI 1
+
+#define IRQ_TYPE_NONE   0
+#define IRQ_TYPE_EDGE_RISING1
+#define IRQ_TYPE_EDGE_FALLING   2
+#define IRQ_TYPE_EDGE_BOTH  (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)
+#define IRQ_TYPE_LEVEL_HIGH 4
+#define IRQ_TYPE_LEVEL_LOW  8
+
+/ {
+#address-cells = <2>;
+#size-cells = <2>;
+interrupt-parent = <&gic>;
+dma-ranges = <0x0 0x0 0x0 0x0 0x100 0x0>;
+
+aliases {
+serial0 = &soc_uart0;
+};
+
+chosen {
+stdout-path = "serial0:115200n8";
+};
+
+cpus {
+#address-cells = <1>;
+#size-cells = <0>;
+
+CPU0: cpu@0 {
+device_type = "cpu";
+compatible = "arm,cortex-a53","arm,armv8";
+reg = <0x0>;
+enable-method = "psci";
+//cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
+};
+CPU1: cpu@1 {
+device_type = "cpu";
+compatible = "arm,cortex-a53","arm,armv8";
+reg = <0x1>;
+enable-method = "psci";
+//cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
+};
+CPU2: cpu@100 {
+device_type = "cpu";
+compatible = "arm,cortex-a53","arm,armv8";
+reg = <0x100>;
+enable-method = "psci";
+//cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
+};
+CPU3: cpu@101 {
+device_type =

[edk2] [PATCH edk2-platforms v3 08/27] Silicon/SynQuacer: implement PciHostBridgeLib support

[Ard Biesheuvel]

Implement the glue library that exposes the PCIe root complexes to
the generic PCI host bridge driver. Since that driver is the first
one to access the PCI config space, put the low level init code for
the RCs into this library's constructor.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel 
---
 
Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLib.c
| 225 +++
 
Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLib.inf
  |  50 +++
 
Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLibConstructor.c
 | 390 
 3 files changed, 665 insertions(+)

diff --git 
a/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLib.c
 
b/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLib.c
new file mode 100644
index ..42cdce24b2c4
--- /dev/null
+++ 
b/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLib.c
@@ -0,0 +1,225 @@
+/** @file
+  PCI Host Bridge Library instance for Socionext SynQuacer ARM SOC
+
+  Copyright (c) 2017, Linaro Ltd. All rights reserved.
+
+  This program and the accompanying materials are licensed and made available
+  under the terms and conditions of the BSD License which accompanies this
+  distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php.
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT
+  WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#pragma pack(1)
+typedef struct {
+  ACPI_HID_DEVICE_PATH AcpiDevicePath;
+  EFI_DEVICE_PATH_PROTOCOL EndDevicePath;
+} EFI_PCI_ROOT_BRIDGE_DEVICE_PATH;
+#pragma pack ()
+
+STATIC CONST EFI_PCI_ROOT_BRIDGE_DEVICE_PATH mEfiPciRootBridgeDevicePath[] = {
+  {
+{
+  {
+ACPI_DEVICE_PATH,
+ACPI_DP,
+{
+  (UINT8)(sizeof (ACPI_HID_DEVICE_PATH)),
+  (UINT8)(sizeof (ACPI_HID_DEVICE_PATH) >> 8)
+}
+  },
+  EISA_PNP_ID (0x0A08), // PCI Express
+  0
+},
+
+{
+  END_DEVICE_PATH_TYPE,
+  END_ENTIRE_DEVICE_PATH_SUBTYPE,
+  {
+END_DEVICE_PATH_LENGTH,
+0
+  }
+}
+  },
+  {
+{
+  {
+ACPI_DEVICE_PATH,
+ACPI_DP,
+{
+  (UINT8)(sizeof(ACPI_HID_DEVICE_PATH)),
+  (UINT8)(sizeof(ACPI_HID_DEVICE_PATH) >> 8)
+}
+  },
+  EISA_PNP_ID (0x0A08), // PCI Express
+  1
+},
+
+{
+  END_DEVICE_PATH_TYPE,
+  END_ENTIRE_DEVICE_PATH_SUBTYPE,
+  {
+END_DEVICE_PATH_LENGTH,
+0
+  }
+}
+  }
+};
+
+GLOBAL_REMOVE_IF_UNREFERENCED
+CHAR16 *mPciHostBridgeLibAcpiAddressSpaceTypeStr[] = {
+  L"Mem", L"I/O", L"Bus"
+};
+
+#ifndef MDE_CPU_ARM
+#define PCI_ALLOCATION_ATTRIBUTES   EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM | 
\
+EFI_PCI_HOST_BRIDGE_MEM64_DECODE
+#else
+#define PCI_ALLOCATION_ATTRIBUTES   EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM
+#endif
+
+STATIC PCI_ROOT_BRIDGE mPciRootBridges[] = {
+  {
+0,  // Segment
+0,  // Supports
+0,  // Attributes
+TRUE,   // DmaAbove4G
+FALSE,  // NoExtendedConfigSpace
+FALSE,  // ResourceAssigned
+PCI_ALLOCATION_ATTRIBUTES,  // AllocationAttributes
+{ SYNQUACER_PCI_SEG0_BUSNUM_MIN,
+  SYNQUACER_PCI_SEG0_BUSNUM_MAX },  // Bus
+{ SYNQUACER_PCI_SEG0_PORTIO_MIN,
+  SYNQUACER_PCI_SEG0_PORTIO_MAX },  // Io
+{ SYNQUACER_PCI_SEG0_MMIO32_MIN,
+  SYNQUACER_PCI_SEG0_MMIO32_MAX },  // Mem
+{ SYNQUACER_PCI_SEG0_MMIO64_MIN,
+  SYNQUACER_PCI_SEG0_MMIO64_MAX },  // MemAbove4G
+{ MAX_UINT64, 0x0 },// PMem
+{ MAX_UINT64, 0x0 },// PMemAbove4G
+(EFI_DEVICE_PATH_PROTOCOL *)&mEfiPciRootBridgeDevicePath[0]
+  }, {
+1,  // Segment
+0,  // Supports
+0,  // Attributes
+TRUE,   // DmaAbove4G
+FALSE,  // NoExtendedConfigSpace
+FALSE,  // ResourceAssigned
+PCI_ALLOCATION_ATTRIBUTES,  // AllocationAttributes
+{ SYNQUACER_PCI_SEG1_BUSNUM_MIN,
+  SYNQUACER_PCI_SEG1_BUSNUM_MAX },  // Bus
+{ SYNQUACER_PCI_SEG1_PORTIO_MIN,
+  SYNQUACER_PCI_SEG1_PORTIO_MAX },  // Io
+{ SYNQUACER_PCI_SEG1_MMIO32_MIN,
+  SYNQUACER_P

[edk2] [PATCH edk2-platforms v3 10/27] Platform/SynQuacerEvalBoard: add PCI support

[Ard Biesheuvel]

Wire up the various drivers and libraries for the SynQuacerEvalBoard
platform. Also enable the usual PCI suspects: XHCI, SATA and NVME,
and the various bus, partition and file system drivers that we need
to make use of PCIe devices.

Given how PCI support enables USB support too, and taking the lack of
a RNG on this SoC into account, let's enable the ChaosKey driver as
well.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel 
---
 Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.dsc | 52 

 Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.fdf | 41 
+++
 2 files changed, 93 insertions(+)

diff --git a/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.dsc 
b/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.dsc
index 3dc8aa7461d6..519a078e15dc 100644
--- a/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.dsc
+++ b/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.dsc
@@ -100,6 +100,7 @@ [LibraryClasses.common]
   DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf
   SortLib|MdeModulePkg/Library/UefiSortLib/UefiSortLib.inf
   UefiUsbLib|MdePkg/Library/UefiUsbLib/UefiUsbLib.inf
+  UefiScsiLib|MdePkg/Library/UefiScsiLib/UefiScsiLib.inf
 
   # BDS Libraries
   
UefiBootManagerLib|MdeModulePkg/Library/UefiBootManagerLib/UefiBootManagerLib.inf
@@ -151,6 +152,12 @@ [LibraryClasses.common.DXE_DRIVER]
   
SecurityManagementLib|MdeModulePkg/Library/DxeSecurityManagementLib/DxeSecurityManagementLib.inf
   PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.inf
 
+  #
+  # PCI
+  #
+  
PciSegmentLib|Silicon/Socionext/SynQuacer/Library/SynQuacerPciSegmentLib/SynQuacerPciSegmentLib.inf
+  
PciHostBridgeLib|Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLib.inf
+
 [LibraryClasses.common.UEFI_APPLICATION]
   PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.inf
   HiiLib|MdeModulePkg/Library/UefiHiiLib/UefiHiiLib.inf
@@ -193,6 +200,7 @@ [PcdsFixedAtBuild.common]
   gSynQuacerTokenSpaceGuid.PcdDramInfoBase|0x2E00FFC0
 
   gEmbeddedTokenSpaceGuid.PcdPrePiCpuMemorySize|40
+  gEmbeddedTokenSpaceGuid.PcdPrePiCpuIoSize|24
 
   # 12x 2-core processor clusters
   gArmPlatformTokenSpaceGuid.PcdCoreCount|2
@@ -430,3 +438,47 @@ [Components.common]
   NULL|MdeModulePkg/Library/BootManagerUiLib/BootManagerUiLib.inf
   
NULL|MdeModulePkg/Library/BootMaintenanceManagerUiLib/BootMaintenanceManagerUiLib.inf
   }
+
+  #
+  # PCI
+  #
+  
Silicon/Socionext/SynQuacer/Drivers/SynQuacerPciCpuIo2Dxe/SynQuacerPciCpuIo2Dxe.inf
+  MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf {
+
+gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x8010004F
+  }
+  MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
+  MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf
+  MdeModulePkg/Universal/EbcDxe/EbcDxe.inf
+
+  #
+  # AHCI Support
+  #
+  MdeModulePkg/Bus/Pci/SataControllerDxe/SataControllerDxe.inf
+  MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf
+  MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf
+  MdeModulePkg/Bus/Scsi/ScsiBusDxe/ScsiBusDxe.inf
+  MdeModulePkg/Bus/Scsi/ScsiDiskDxe/ScsiDiskDxe.inf
+
+  #
+  # USB
+  #
+  MdeModulePkg/Bus/Pci/UhciDxe/UhciDxe.inf
+  MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf
+  MdeModulePkg/Bus/Pci/XhciDxe/XhciDxe.inf
+  MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf
+  MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf
+  MdeModulePkg/Bus/Usb/UsbKbDxe/UsbKbDxe.inf
+
+  #
+  # FAT filesystem + GPT/MBR partitioning
+  #
+  MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf
+  MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf
+  MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf
+  FatPkg/EnhancedFatDxe/Fat.inf
+
+  #
+  # RNG
+  #
+  Silicon/Openmoko/ChaosKeyDxe/ChaosKeyDxe.inf
diff --git a/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.fdf 
b/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.fdf
index f74e22c31aa5..838963eff612 100644
--- a/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.fdf
+++ b/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.fdf
@@ -132,6 +132,47 @@ [FV.FvMain]
   INF MdeModulePkg/Universal/BdsDxe/BdsDxe.inf
   INF MdeModulePkg/Application/UiApp/UiApp.inf
 
+  #
+  # PCI
+  #
+  INF 
Silicon/Socionext/SynQuacer/Drivers/SynQuacerPciCpuIo2Dxe/SynQuacerPciCpuIo2Dxe.inf
+  INF MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf
+  INF MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
+  INF MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf
+  INF MdeModulePkg/Universal/EbcDxe/EbcDxe.inf
+
+  #
+  # AHCI Support
+  #
+  INF MdeModulePkg/Bus/Pci/SataControllerDxe/SataControllerDxe.inf
+  INF MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf
+  INF MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf
+  INF MdeModulePkg/Bus/Scsi/ScsiBusDxe/ScsiBusDxe.inf
+  INF MdeModulePkg/Bus/Scsi/ScsiDiskDxe/ScsiDisk

[edk2] [PATCH edk2-platforms v3 14/27] Silicon/SynQuacer: add NorFlashPlatformLib implementation

[Ard Biesheuvel]

Add the platform glue for the NOR flash driver.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel 
Reviewed-by: Leif Lindholm 
---
 Silicon/Socionext/SynQuacer/Library/NorFlashSynQuacerLib/NorFlashSynQuacer.c   
   | 70 
 
Silicon/Socionext/SynQuacer/Library/NorFlashSynQuacerLib/NorFlashSynQuacerLib.inf
 | 41 
 2 files changed, 111 insertions(+)

diff --git 
a/Silicon/Socionext/SynQuacer/Library/NorFlashSynQuacerLib/NorFlashSynQuacer.c 
b/Silicon/Socionext/SynQuacer/Library/NorFlashSynQuacerLib/NorFlashSynQuacer.c
new file mode 100644
index ..816d8ba33f8c
--- /dev/null
+++ 
b/Silicon/Socionext/SynQuacer/Library/NorFlashSynQuacerLib/NorFlashSynQuacer.c
@@ -0,0 +1,70 @@
+/** @file
+
+ Copyright (c) 2011-2014, ARM Ltd. All rights reserved.
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD 
License
+ which accompanies this distribution.  The full text of the license may be 
found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+ **/
+
+#include 
+#include 
+#include 
+#include 
+
+#include 
+
+STATIC NOR_FLASH_DESCRIPTION mNorFlashDevices[] = {
+  {
+// UEFI code region
+SYNQUACER_SPI_NOR_BASE, // device base
+FixedPcdGet64 (PcdFdBaseAddress),   // region base
+FixedPcdGet32 (PcdFdSize),  // region size
+SIZE_64KB,  // block size
+{
+  0x19c118b0, 0xc423, 0x42be, { 0xb8, 0x0f, 0x70, 0x6f, 0x1f, 0xcb, 0x59, 
0x9a }
+}
+  },
+  {
+// Environment variable region
+SYNQUACER_SPI_NOR_BASE, // device base
+FixedPcdGet32 (PcdFlashNvStorageVariableBase),  // region base
+FixedPcdGet32 (PcdFlashNvStorageVariableSize) +
+FixedPcdGet32 (PcdFlashNvStorageFtwWorkingSize) +
+FixedPcdGet32 (PcdFlashNvStorageFtwSpareSize),  // region size
+SIZE_64KB,  // block size
+{
+  0x3105bd7a, 0x82c3, 0x486f, { 0xb1, 0x03, 0x1e, 0x09, 0x54, 0xec, 0x85, 
0x75 }
+}
+  },
+};
+
+EFI_STATUS
+NorFlashPlatformInitialization (
+  VOID
+  )
+{
+  return EFI_SUCCESS;
+}
+
+EFI_STATUS
+NorFlashPlatformGetDevices (
+  OUT NOR_FLASH_DESCRIPTION   **NorFlashDevices,
+  OUT UINT32  *Count
+  )
+{
+  if (NorFlashDevices == NULL ||
+  Count == NULL) {
+return EFI_INVALID_PARAMETER;
+  }
+
+  *Count = ARRAY_SIZE (mNorFlashDevices);
+  *NorFlashDevices = mNorFlashDevices;
+
+  return EFI_SUCCESS;
+}
diff --git 
a/Silicon/Socionext/SynQuacer/Library/NorFlashSynQuacerLib/NorFlashSynQuacerLib.inf
 
b/Silicon/Socionext/SynQuacer/Library/NorFlashSynQuacerLib/NorFlashSynQuacerLib.inf
new file mode 100644
index ..2a8fd209f5e3
--- /dev/null
+++ 
b/Silicon/Socionext/SynQuacer/Library/NorFlashSynQuacerLib/NorFlashSynQuacerLib.inf
@@ -0,0 +1,41 @@
+#/** @file
+#
+#  Copyright (c) 2011 - 2014, ARM Ltd. All rights reserved.
+#  This program and the accompanying materials
+#  are licensed and made available under the terms and conditions of the BSD 
License
+#  which accompanies this distribution.  The full text of the license may be 
found at
+#  http://opensource.org/licenses/bsd-license.php
+#
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR 
IMPLIED.
+#
+#**/
+
+[Defines]
+  INF_VERSION= 0x0001001A
+  BASE_NAME  = NorFlashSynQuacerLib
+  FILE_GUID  = 8279227C-C555-4D75-B439-D8A959635CDD
+  MODULE_TYPE= BASE
+  VERSION_STRING = 1.0
+  LIBRARY_CLASS  = NorFlashPlatformLib
+
+[Sources]
+  NorFlashSynQuacer.c
+
+[Packages]
+  ArmPlatformPkg/ArmPlatformPkg.dec
+  ArmPkg/ArmPkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+  MdePkg/MdePkg.dec
+  Silicon/Socionext/SynQuacer/SynQuacer.dec
+
+[LibraryClasses]
+  BaseLib
+
+[FixedPcd]
+  gArmTokenSpaceGuid.PcdFdBaseAddress
+  gArmTokenSpaceGuid.PcdFdSize
+  gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase
+  gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize
+  gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize
+  gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize
-- 
2.11.0

___
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[edk2] [PATCH edk2-platforms v3 07/27] Silicon/SynQuacer: implement PciSegmentLib to support dual RCs

[Ard Biesheuvel]

Having two distinct root complexes is not supported by the standard
set of PciLib/PciExpressLib/PciSegmentLib, so let's reimplement one
of the latter specifically for this platform (and forget about the
others).

This also allows us to implement the Synopsys Designware PCIe specific
workaround for PCI config space accesses to devices 1 and up on bus 0.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel 
Reviewed-by: Leif Lindholm 
---
 Silicon/Socionext/SynQuacer/Library/SynQuacerPciSegmentLib/PciSegmentLib.c 
   | 1398 
 
Silicon/Socionext/SynQuacer/Library/SynQuacerPciSegmentLib/SynQuacerPciSegmentLib.inf
 |   35 +
 2 files changed, 1433 insertions(+)

diff --git 
a/Silicon/Socionext/SynQuacer/Library/SynQuacerPciSegmentLib/PciSegmentLib.c 
b/Silicon/Socionext/SynQuacer/Library/SynQuacerPciSegmentLib/PciSegmentLib.c
new file mode 100644
index ..62f3b2015d2b
--- /dev/null
+++ b/Silicon/Socionext/SynQuacer/Library/SynQuacerPciSegmentLib/PciSegmentLib.c
@@ -0,0 +1,1398 @@
+/** @file
+  PCI Segment Library for SynQuacer SoC with multiple RCs
+
+  Copyright (c) 2007 - 2012, Intel Corporation. All rights reserved.
+  Copyright (c) 2017, Linaro, Ltd. All rights reserved.
+
+  This program and the accompanying materials are
+  licensed and made available under the terms and conditions of
+  the BSD License which accompanies this distribution.  The full
+  text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php.
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include 
+
+#include 
+#include 
+#include 
+#include 
+
+#include 
+
+typedef enum {
+  PciCfgWidthUint8  = 0,
+  PciCfgWidthUint16,
+  PciCfgWidthUint32,
+  PciCfgWidthMax
+} PCI_CFG_WIDTH;
+
+/**
+  Assert the validity of a PCI Segment address.
+  A valid PCI Segment address should not contain 1's in bits 28..31 and 48..63
+
+  @param  A The address to validate.
+  @param  M Additional bits to assert to be zero.
+
+**/
+#define ASSERT_INVALID_PCI_SEGMENT_ADDRESS(A,M) \
+  ASSERT (((A) & (0xf000ULL | (M))) == 0)
+
+STATIC
+UINT64
+PciSegmentLibGetConfigBase (
+  IN  UINT64  Address
+  )
+{
+  switch ((UINT16)(Address >> 32)) {
+  case 0:
+return SYNQUACER_PCI_SEG0_CONFIG_BASE;
+  case 1:
+return SYNQUACER_PCI_SEG1_CONFIG_BASE;
+  default:
+ASSERT (FALSE);
+  }
+
+  return 0;
+}
+
+/**
+  Internal worker function to read a PCI configuration register.
+
+  @param  Address The address that encodes the PCI Bus, Device, Function and
+  Register.
+  @param  Width   The width of data to read
+
+  @return The value read from the PCI configuration register.
+
+**/
+STATIC
+UINT32
+PciSegmentLibReadWorker (
+  IN  UINT64  Address,
+  IN  PCI_CFG_WIDTH   Width
+  )
+{
+  UINT64Base;
+
+  Base = PciSegmentLibGetConfigBase (Address);
+
+  // ignore devices > 0 on bus 0
+  if ((Address & 0xff0) == 0 && (Address & 0xf8000) != 0) {
+return 0x;
+  }
+
+  switch (Width) {
+  case PciCfgWidthUint8:
+return MmioRead8 (Base + (UINT32)Address);
+  case PciCfgWidthUint16:
+return MmioRead16 (Base + (UINT32)Address);
+  case PciCfgWidthUint32:
+return MmioRead32 (Base + (UINT32)Address);
+  default:
+ASSERT (FALSE);
+  }
+
+  return 0;
+}
+
+/**
+  Internal worker function to writes a PCI configuration register.
+
+  @param  Address The address that encodes the PCI Bus, Device, Function and
+  Register.
+  @param  Width   The width of data to write
+  @param  DataThe value to write.
+
+  @return The value written to the PCI configuration register.
+
+**/
+STATIC
+UINT32
+PciSegmentLibWriteWorker (
+  IN  UINT64  Address,
+  IN  PCI_CFG_WIDTH   Width,
+  IN  UINT32  Data
+  )
+{
+  UINT64Base;
+
+  Base = PciSegmentLibGetConfigBase (Address);
+
+  // ignore devices > 0 on bus 0
+  if ((Address & 0xff0) == 0 && (Address & 0xf8000) != 0) {
+return Data;
+  }
+
+  switch (Width) {
+  case PciCfgWidthUint8:
+MmioWrite8 (Base + (UINT32)Address, Data);
+break;
+  case PciCfgWidthUint16:
+MmioWrite16 (Base + (UINT32)Address, Data);
+break;
+  case PciCfgWidthUint32:
+MmioWrite32 (Base + (UINT32)Address, Data);
+break;
+  default:
+ASSERT (FALSE);
+  }
+
+  return Data;
+}
+
+/**
+  Register a PCI device so PCI configuration registers may be accessed after
+  SetVirtualAddressMap().
+
+  If any reserved bits in Address are set, then ASSERT().
+
+  @param  Address The address that encodes the PCI Bus, Device, Function and
+  Register.
+
+  @retval RETURN_SUCCESS   The PCI device was registered for runtime 
access.
+  @retval RETURN_UNSUPPORTED   An attempt was made to call this function
+  

[edk2] [PATCH edk2-platforms v3 09/27] Silicon/SynQuacer: implement EFI_CPU_IO2_PROTOCOL

[Ard Biesheuvel]

The SynQuacer SOC has two separate PCIe RCs, which means there is
no single value for the translation offset between I/O port accesses
and MMIO accesses. So add a special implementation of EFI_CPU_IO2_PROTOCOL
that takes the two disjoint I/O windows into account.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel 
Reviewed-by: Leif Lindholm 
---
 
Silicon/Socionext/SynQuacer/Drivers/SynQuacerPciCpuIo2Dxe/SynQuacerPciCpuIo2Dxe.c
   | 590 
 
Silicon/Socionext/SynQuacer/Drivers/SynQuacerPciCpuIo2Dxe/SynQuacerPciCpuIo2Dxe.inf
 |  50 ++
 2 files changed, 640 insertions(+)

diff --git 
a/Silicon/Socionext/SynQuacer/Drivers/SynQuacerPciCpuIo2Dxe/SynQuacerPciCpuIo2Dxe.c
 
b/Silicon/Socionext/SynQuacer/Drivers/SynQuacerPciCpuIo2Dxe/SynQuacerPciCpuIo2Dxe.c
new file mode 100644
index ..6ef44b11bb7d
--- /dev/null
+++ 
b/Silicon/Socionext/SynQuacer/Drivers/SynQuacerPciCpuIo2Dxe/SynQuacerPciCpuIo2Dxe.c
@@ -0,0 +1,590 @@
+/** @file
+  Produces the CPU I/O 2 Protocol.
+
+Copyright (c) 2009 - 2012, Intel Corporation. All rights reserved.
+Copyright (c) 2016 - 2017, Linaro Ltd. All rights reserved.
+
+This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD 
License
+which accompanies this distribution.  The full text of the license may be 
found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include 
+
+#include 
+#include 
+
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define MAX_IO_PORT_ADDRESS   SYNQUACER_PCI_SEG1_PORTIO_MAX
+
+//
+// Handle for the CPU I/O 2 Protocol
+//
+STATIC EFI_HANDLE  mHandle = NULL;
+
+//
+// Lookup table for increment values based on transfer widths
+//
+STATIC CONST UINT8 mInStride[] = {
+  1, // EfiCpuIoWidthUint8
+  2, // EfiCpuIoWidthUint16
+  4, // EfiCpuIoWidthUint32
+  8, // EfiCpuIoWidthUint64
+  0, // EfiCpuIoWidthFifoUint8
+  0, // EfiCpuIoWidthFifoUint16
+  0, // EfiCpuIoWidthFifoUint32
+  0, // EfiCpuIoWidthFifoUint64
+  1, // EfiCpuIoWidthFillUint8
+  2, // EfiCpuIoWidthFillUint16
+  4, // EfiCpuIoWidthFillUint32
+  8  // EfiCpuIoWidthFillUint64
+};
+
+//
+// Lookup table for increment values based on transfer widths
+//
+STATIC CONST UINT8 mOutStride[] = {
+  1, // EfiCpuIoWidthUint8
+  2, // EfiCpuIoWidthUint16
+  4, // EfiCpuIoWidthUint32
+  8, // EfiCpuIoWidthUint64
+  1, // EfiCpuIoWidthFifoUint8
+  2, // EfiCpuIoWidthFifoUint16
+  4, // EfiCpuIoWidthFifoUint32
+  8, // EfiCpuIoWidthFifoUint64
+  0, // EfiCpuIoWidthFillUint8
+  0, // EfiCpuIoWidthFillUint16
+  0, // EfiCpuIoWidthFillUint32
+  0  // EfiCpuIoWidthFillUint64
+};
+
+/**
+  Check parameters to a CPU I/O 2 Protocol service request.
+
+  The I/O operations are carried out exactly as requested. The caller is 
responsible
+  for satisfying any alignment and I/O width restrictions that a PI System on a
+  platform might require. For example on some platforms, width requests of
+  EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other hand, will
+  be handled by the driver.
+
+  @param[in] MmioOperation  TRUE for an MMIO operation, FALSE for I/O Port 
operation.
+  @param[in] Width  Signifies the width of the I/O or Memory operation.
+  @param[in] AddressThe base address of the I/O operation.
+  @param[in] Count  The number of I/O operations to perform. The 
number of
+bytes moved is Width size * Count, starting at 
Address.
+  @param[in] Buffer For read operations, the destination buffer to 
store the results.
+For write operations, the source buffer from which 
to write data.
+
+  @retval EFI_SUCCESSThe parameters for this request pass the 
checks.
+  @retval EFI_INVALID_PARAMETER  Width is invalid for this PI system.
+  @retval EFI_INVALID_PARAMETER  Buffer is NULL.
+  @retval EFI_UNSUPPORTEDThe Buffer is not aligned for the given Width.
+  @retval EFI_UNSUPPORTEDThe address range specified by Address, Width,
+ and Count is not valid for this PI system.
+
+**/
+STATIC
+EFI_STATUS
+CpuIoCheckParameter (
+  IN BOOLEANMmioOperation,
+  IN EFI_CPU_IO_PROTOCOL_WIDTH  Width,
+  IN UINT64 Address,
+  IN UINTN  Count,
+  IN VOID   *Buffer
+  )
+{
+  UINT64  MaxCount;
+  UINT64  Limit;
+
+  //
+  // Check to see if Buffer is NULL
+  //
+  if (Buffer == NULL) {
+ASSERT (FALSE);
+return EFI_INVALID_PARAMETER;
+  }
+
+  //
+  // Check to see if Width is in the valid range
+  //
+  if ((UINT32)Width >= EfiCpuIoWidthMaximum) {
+ASSERT (FALSE);
+return EFI_INVALID_PARAMETER;
+  }
+
+  //
+  // For FIFO type, the target address won't increase during the access,
+  // so treat Co

[edk2] [PATCH edk2-platforms v3 00/27] add support for Socionext Synquacer

[Ard Biesheuvel]

This adds support for the Socionext Synquacer SC2A11 evaluation board
and revision 0.1 of the Developer Box.

It implements support for the core peripherals (CPU, GIC, serial), and
for the two PCIe RCs present on this board. (Note that the EVB requires
PCI slot CN2 to be populated or it will not boot).

Both ACPI and DT hardware descriptions are provided. In ACPI mode, Debian
stretch can be booted and installed on PCIe based peripherals, and
requires a PCIe based network card that already has upstream support. (On
the Developer box, only the x16 slot is supported in this case)

The DT description contains references to drivers that are not upstream
yet, and will be merged into Linux v4.15 at the earliest. No other OS
support is currently planned (as far as I am aware)

The non-volatile EFI variable store is backed by the SPI NOR flash,
which is therefore not exposed to the OS. Note that it occupies the
'devtree' partition, which must be wiped before use.

A driver for the NETSEC network interface is included, which means
network boot is supported as well. (Note that this driver deviates
in coding style. This code is based on the platform independent
driver provided by Socionext, and making cosmetic changes to it
will only make it more difficult to track upstream changes)

Changes since v2:
- converted NETSEC driver to UEFI driver model
- added a platform DXE driver that declares the non-discoverable NETSEC
  device for the UEFI driver model driver to bind to
- remove hardcoded DRAM information - everything is now retrieved from
  ARM Trusted Firmware
- added DT descriptions of the GPIO and interrupt controller IP blocks
- addressed various style issues and merge errors highlighted by Leif

Notably unchanged:
- the SPI NOR driver - I simply don't have the information to convert it
  to using symbolic constants

Notable gaps in functionality:
- no support yet for the I2C RTC on the Developer box

Ard Biesheuvel (26):
  Silicon/SynQuacer: add package with platform headers
  Silicon/Socionext: add driver for NETSEC network controller
  Silicon/Socionext: add PlatformPeilib implementation for SynQuacer
  Silicon/SynQuacer: implement a platform DXE driver
  Silicon/SynQuacer: add MemoryInitPeiLib implementation
  Platform: add support for Socionext SynQuacer eval board
  Silicon/SynQuacer: implement PciSegmentLib to support dual RCs
  Silicon/SynQuacer: implement PciHostBridgeLib support
  Silicon/SynQuacer: implement EFI_CPU_IO2_PROTOCOL
  Platform/SynQuacerEvalBoard: add PCI support
  Platform/SynQuacerEvalBoard: add NETSEC driver
  Silicon/SynQuacer: add ACPI support
  Silicon/SynQuacer: add device tree support for eval board
  Silicon/SynQuacer: add NorFlashPlatformLib implementation
  Platform/SynQuacer: incorporate NOR flash and variable drivers
  Silicon/SynQuacer: implement PlatformFlashAccessLib
  SynQuacer/SynQuacerMemoryInitPeiLib: add capsule support
  Socionext/SynQuacerEvalBoard: wire up basic capsule support
  Socionext/SynQuacerEvalBoard: switch to execute in place
  Platform/SynQuacerEvalBoard: add signed capsule update support
  Silicon/SynQuacer/AcpiTables: hide PCI domain #0
  Silicon/SynQuacerPciHostBridgeLib: add workaround to support 32-bit
only cards
  Platform/Socionext: add support for Socionext Developer Box rev 0.1
  Platform/DeveloperBox: add ConsolePrefDxe driver
  Silicon/SynQuacer: add description of GPIO block to device tree
  Silicon/SynQuacer: add description of EXIU to the device tree

Pipat Methavanitpong (1):
  Silicon/Socionext: add driver for SPI NOR flash

 Platform/Socionext/DeveloperBox/DeveloperBox.dsc   
   |  637 +
 Platform/Socionext/DeveloperBox/DeveloperBox.fdf   
   |  492 +++
 
Platform/Socionext/DeveloperBox/SystemFirmwareDescriptor/SystemFirmwareDescriptor.aslc
|   80 ++
 
Platform/Socionext/DeveloperBox/SystemFirmwareDescriptor/SystemFirmwareDescriptor.inf
 |   46 +
 
Platform/Socionext/DeveloperBox/SystemFirmwareDescriptor/SystemFirmwareDescriptorPei.c
|   68 +
 
Platform/Socionext/DeveloperBox/SystemFirmwareUpdateConfig/SystemFirmwareUpdateConfig.ini
 |   25 +
 Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.dsc   
   |  608 
 Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.fdf   
   |  475 +++
 
Platform/Socionext/SynQuacerEvalBoard/SystemFirmwareDescriptor/SystemFirmwareDescriptor.aslc
  |   80 ++
 
Platform/Socionext/SynQuacerEvalBoard/SystemFirmwareDescriptor/SystemFirmwareDescriptor.inf
   |   46 +
 
Platform/Socionext/SynQuacerEvalBoard/SystemFirmwareDescriptor/SystemFirmwareDescriptorPei.c
  |   68 +
 
Platform/Socionext/SynQuac

[edk2] [PATCH edk2-platforms v3 05/27] Silicon/SynQuacer: add MemoryInitPeiLib implementation

[Ard Biesheuvel]

Implement MemoryInitPeiLib based on the newly added DramInfo
PPI, which retrieves the DRAM information from lower level
firmware.

Note that the firmware volumes in SPI NOR are mapped with
different attributes: the FV containing the PEI modules that
may execute in place is mapped as uncached memory, given that
it requires executable permissions. The FV containing the
compressed DXE modules is mapped with device attributes for
performance (!), and copied into DRAM by the platform PEIM
once permanent memory is installed.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel 
---
 
Silicon/Socionext/SynQuacer/Library/SynQuacerMemoryInitPeiLib/SynQuacerMemoryInitPeiLib.c
   | 186 
 
Silicon/Socionext/SynQuacer/Library/SynQuacerMemoryInitPeiLib/SynQuacerMemoryInitPeiLib.inf
 |  67 +++
 2 files changed, 253 insertions(+)

diff --git 
a/Silicon/Socionext/SynQuacer/Library/SynQuacerMemoryInitPeiLib/SynQuacerMemoryInitPeiLib.c
 
b/Silicon/Socionext/SynQuacer/Library/SynQuacerMemoryInitPeiLib/SynQuacerMemoryInitPeiLib.c
new file mode 100644
index ..e9a266f0997a
--- /dev/null
+++ 
b/Silicon/Socionext/SynQuacer/Library/SynQuacerMemoryInitPeiLib/SynQuacerMemoryInitPeiLib.c
@@ -0,0 +1,186 @@
+/** @file
+*
+*  Copyright (c) 2011-2015, ARM Limited. All rights reserved.
+*  Copyright (c) 2017, Linaro, Ltd. All rights reserved.
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD 
License
+*  which accompanies this distribution.  The full text of the license may be 
found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR 
IMPLIED.
+*
+**/
+
+#include 
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+#include 
+
+#include 
+
+#define ARM_MEMORY_REGION(Base, Size) \
+  { (Base), (Base), (Size), ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK }
+
+#define ARM_UNCACHED_REGION(Base, Size) \
+  { (Base), (Base), (Size), ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED }
+
+#define ARM_DEVICE_REGION(Base, Size) \
+  { (Base), (Base), (Size), ARM_MEMORY_REGION_ATTRIBUTE_DEVICE }
+
+VOID
+BuildMemoryTypeInformationHob (
+  VOID
+  );
+
+STATIC CONST EFI_RESOURCE_ATTRIBUTE_TYPE mDramResourceAttributes =
+  EFI_RESOURCE_ATTRIBUTE_PRESENT |
+  EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
+  EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |
+  EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |
+  EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE |
+  EFI_RESOURCE_ATTRIBUTE_TESTED;
+
+STATIC CONST ARM_MEMORY_REGION_DESCRIPTOR mVirtualMemoryTable[] = {
+  // Memory mapped SPI NOR flash
+  // Mapped with device attributes for performance (!)
+  ARM_DEVICE_REGION (FixedPcdGet64 (PcdFdBaseAddress),
+ FixedPcdGet32 (PcdFdSize)),
+
+  // Memory mapped SPI NOR flash - XIP region
+  // Sub-region of the preceding one - supersede with normal-nc attributes
+  ARM_UNCACHED_REGION (FixedPcdGet64 (PcdFvBaseAddress),
+   FixedPcdGet32 (PcdFvSize)),
+
+  // SynQuacer OnChip peripherals
+  ARM_DEVICE_REGION (SYNQUACER_PERIPHERALS_BASE,
+ SYNQUACER_PERIPHERALS_SZ),
+
+  // SynQuacer OnChip non-secure SRAM
+  ARM_UNCACHED_REGION (SYNQUACER_NON_SECURE_SRAM_BASE,
+   SYNQUACER_NON_SECURE_SRAM_SZ),
+
+  // SynQuacer GIC-500
+  ARM_DEVICE_REGION (SYNQUACER_GIC500_DIST_BASE, SYNQUACER_GIC500_DIST_SIZE),
+  ARM_DEVICE_REGION (SYNQUACER_GIC500_RDIST_BASE, SYNQUACER_GIC500_RDIST_SIZE),
+
+  // SynQuacer eMMC(SDH30)
+  ARM_DEVICE_REGION (SYNQUACER_EMMC_BASE, SYNQUACER_EMMC_BASE_SZ),
+
+  // SynQuacer EEPROM - could point to NOR flash as well
+  ARM_DEVICE_REGION (FixedPcdGet32 (PcdNetsecEepromBase),
+ SYNQUACER_EEPROM_BASE_SZ),
+
+  // SynQuacer NETSEC
+  ARM_DEVICE_REGION (SYNQUACER_NETSEC_BASE, SYNQUACER_NETSEC_BASE_SZ),
+
+  // PCIe control registers
+  ARM_DEVICE_REGION (SYNQUACER_PCIE_BASE, SYNQUACER_PCIE_SIZE),
+
+  // PCIe config space
+  ARM_DEVICE_REGION (SYNQUACER_PCI_SEG0_CONFIG_BASE,
+ SYNQUACER_PCI_SEG0_CONFIG_SIZE),
+  ARM_DEVICE_REGION (SYNQUACER_PCI_SEG1_CONFIG_BASE,
+ SYNQUACER_PCI_SEG1_CONFIG_SIZE),
+
+  // PCIe I/O space
+  ARM_DEVICE_REGION (SYNQUACER_PCI_SEG0_PORTIO_MEMBASE,
+ SYNQUACER_PCI_SEG0_PORTIO_MEMSIZE),
+  ARM_DEVICE_REGION (SYNQUACER_PCI_SEG1_PORTIO_MEMBASE,
+ SYNQUACER_PCI_SEG1_PORTIO_MEMSIZE),
+};
+
+STATIC
+EFI_STATUS
+DeclareDram (
+  OUT ARM_MEMORY_REGION_DESCRIPTOR**VirtualMemoryTable
+  )
+{
+  SYNQUACER_DRAM_INFO_PPI   *DramInfo;
+  EFI_STATUSStatus;
+  UINTN Idx;
+  UINTN RegionCount;
+  UINT64Base;
+  UINT64Size;
+  ARM_M

[edk2] [PATCH edk2-platforms v3 01/27] Silicon/SynQuacer: add package with platform headers

[Ard Biesheuvel]

Add a package .DEC description for SynQuacer with an [Includes]
section, and add header files containing descriptions of the
platform's memory map and PCIe configuration. No code yet.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel 
Reviewed-by: Leif Lindholm 
---
 Silicon/Socionext/SynQuacer/Include/Platform/MemoryMap.h | 60 
+++
 Silicon/Socionext/SynQuacer/Include/Platform/Pcie.h  | 63 

 Silicon/Socionext/SynQuacer/SynQuacer.dec| 20 +++
 3 files changed, 143 insertions(+)

diff --git a/Silicon/Socionext/SynQuacer/Include/Platform/MemoryMap.h 
b/Silicon/Socionext/SynQuacer/Include/Platform/MemoryMap.h
new file mode 100644
index ..1ccd3122cdda
--- /dev/null
+++ b/Silicon/Socionext/SynQuacer/Include/Platform/MemoryMap.h
@@ -0,0 +1,60 @@
+/** @file
+  Physical memory map for SynQuacer
+
+  Copyright (c) 2017, Linaro Ltd. All rights reserved.
+
+  This program and the accompanying materials are licensed and made available
+  under the terms and conditions of the BSD License which accompanies this
+  distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php.
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT
+  WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _SYNQUACER_PLATFORM_MEMORYMAP_H_
+#define _SYNQUACER_PLATFORM_MEMORYMAP_H_
+
+// Memory mapped SPI NOR
+#define SYNQUACER_SPI_NOR_BASE  0x0800
+#define SYNQUACER_SPI_NOR_SIZE  SIZE_128MB
+
+// On-Chip non-secure ROM
+#define SYNQUACER_NON_SECURE_ROM_BASE   0x1F00
+#define SYNQUACER_NON_SECURE_ROM_SZ SIZE_512KB
+
+// On-Chip Peripherals
+#define SYNQUACER_PERIPHERALS_BASE  0x2000
+#define SYNQUACER_PERIPHERALS_SZ0x0E00
+
+// On-Chip non-secure SRAM
+#define SYNQUACER_NON_SECURE_SRAM_BASE  0x2E00
+#define SYNQUACER_NON_SECURE_SRAM_SZSIZE_64KB
+
+// GIC-500
+#define SYNQUACER_GIC500_DIST_BASE  FixedPcdGet64 (PcdGicDistributorBase)
+#define SYNQUACER_GIC500_DIST_SIZE  SIZE_256KB
+#define SYNQUACER_GIC500_RDIST_BASE FixedPcdGet64 
(PcdGicRedistributorsBase)
+#define SYNQUACER_GIC500_RDIST_SIZE SIZE_8MB
+
+// GPIO block
+#define SYNQUACER_GPIO_BASE 0x5100
+#define SYNQUACER_GPIO_SIZE SIZE_4KB
+
+// eMMC(SDH30)
+#define SYNQUACER_EMMC_BASE 0x5230
+#define SYNQUACER_EMMC_BASE_SZ  SIZE_4KB
+
+#define SYNQUACER_EEPROM_BASE   0x1000
+#define SYNQUACER_EEPROM_BASE_SZSIZE_64KB
+
+// NETSEC
+#define SYNQUACER_NETSEC_BASE   0x522D
+#define SYNQUACER_NETSEC_BASE_SZSIZE_64KB
+
+// PCI
+#define SYNQUACER_PCIE_BASE 0x5820
+#define SYNQUACER_PCIE_SIZE 0x0020
+
+#endif
diff --git a/Silicon/Socionext/SynQuacer/Include/Platform/Pcie.h 
b/Silicon/Socionext/SynQuacer/Include/Platform/Pcie.h
new file mode 100644
index ..d2a3f9acbf49
--- /dev/null
+++ b/Silicon/Socionext/SynQuacer/Include/Platform/Pcie.h
@@ -0,0 +1,63 @@
+/** @file
+  PCI memory configuration for SynQuacer
+
+  Copyright (c) 2017, Linaro Ltd. All rights reserved.
+
+  This program and the accompanying materials are licensed and made available
+  under the terms and conditions of the BSD License which accompanies this
+  distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php.
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT
+  WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _SYNQUACER_PLATFORM_PCI_H_
+#define _SYNQUACER_PLATFORM_PCI_H_
+
+#define SYNQUACER_PCI_SEG0_CONFIG_BASE  0x6000
+#define SYNQUACER_PCI_SEG0_CONFIG_SIZE  0x07f0
+#define SYNQUACER_PCI_SEG0_DBI_BASE 0x583d
+#define SYNQUACER_PCI_SEG0_EXS_BASE 0x5839
+
+#define SYNQUACER_PCI_SEG0_BUSNUM_MIN   0x0
+#define SYNQUACER_PCI_SEG0_BUSNUM_MAX   0x7e
+
+#define SYNQUACER_PCI_SEG0_PORTIO_MIN   0x0
+#define SYNQUACER_PCI_SEG0_PORTIO_MAX   0x
+#define SYNQUACER_PCI_SEG0_PORTIO_SIZE  0x1
+#define SYNQUACER_PCI_SEG0_PORTIO_MEMBASE   0x67f0
+#define SYNQUACER_PCI_SEG0_PORTIO_MEMSIZE   SYNQUACER_PCI_SEG0_PORTIO_SIZE
+
+#define SYNQUACER_PCI_SEG0_MMIO32_MIN   0x6800
+#define SYNQUACER_PCI_SEG0_MMIO32_MAX   0x6fff
+#define SYNQUACER_PCI_SEG0_MMIO32_SIZE  0x0800
+
+#define SYNQUACER_PCI_SEG0_MMIO64_MIN   0x3e
+#define SYNQUACER_PCI_SEG0_MMIO64_MAX   0x3e
+#define SYNQUACER_PCI_SEG0_MMIO64_SIZE  0x1
+
+#define SYNQUACER_PCI_SEG1_CONFIG_BASE  0x7000
+#define SYNQUACER_PCI_SEG1_CONFIG_SIZE  0x07f0
+#define SYNQUACER_PCI_SEG1_DBI_BASE 0x583c
+#define SYNQUACER_PCI_SEG1_EXS_BASE 0x5838
+
+#define SYNQUACER_PCI_SEG1_BUSNUM_MIN   0x0
+#def

[edk2] [PATCH edk2-platforms v3 04/27] Silicon/SynQuacer: implement a platform DXE driver

[Ard Biesheuvel]

This implements a driver that will take care of platform specific
initialization, such as declaring non-discoverable devices. For
the moment, this is limited to declaring the presence of the NETSEC
controller.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel 
---
 Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.c   | 106 

 Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.inf |  52 
++
 Silicon/Socionext/SynQuacer/SynQuacer.dec   |   3 +
 3 files changed, 161 insertions(+)

diff --git a/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.c 
b/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.c
new file mode 100644
index ..86e81bc3593c
--- /dev/null
+++ b/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.c
@@ -0,0 +1,106 @@
+/** @file
+  SynQuacer DXE platform driver.
+
+  Copyright (c) 2017, Linaro, Ltd. All rights reserved.
+
+  This program and the accompanying materials are licensed and made available
+  under the terms and conditions of the BSD License which accompanies this
+  distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+**/
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+STATIC EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR mNetsecDesc[] = {
+  {
+ACPI_ADDRESS_SPACE_DESCRIPTOR,// Desc
+sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) - 3,   // Len
+ACPI_ADDRESS_SPACE_TYPE_MEM,  // ResType
+0,// GenFlag
+0,// SpecificFlag
+32,   // AddrSpaceGranularity
+SYNQUACER_NETSEC_BASE,// AddrRangeMin
+SYNQUACER_NETSEC_BASE +
+SYNQUACER_NETSEC_BASE_SZ - 1, // AddrRangeMax
+0,// AddrTranslationOffset
+SYNQUACER_NETSEC_BASE_SZ, // AddrLen
+  }, {
+ACPI_ADDRESS_SPACE_DESCRIPTOR,// Desc
+sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) - 3,   // Len
+ACPI_ADDRESS_SPACE_TYPE_MEM,  // ResType
+0,// GenFlag
+0,// SpecificFlag
+32,   // AddrSpaceGranularity
+FixedPcdGet32 (PcdNetsecEepromBase),  // AddrRangeMin
+FixedPcdGet32 (PcdNetsecEepromBase) +
+SYNQUACER_EEPROM_BASE_SZ - 1, // AddrRangeMax
+0,// AddrTranslationOffset
+SYNQUACER_EEPROM_BASE_SZ, // AddrLen
+  }, {
+ACPI_ADDRESS_SPACE_DESCRIPTOR,// Desc
+sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) - 3,   // Len
+ACPI_ADDRESS_SPACE_TYPE_MEM,  // ResType
+0,// GenFlag
+0,// SpecificFlag
+32,   // AddrSpaceGranularity
+FixedPcdGet32 (PcdNetsecPhyAddress),  // AddrRangeMin
+FixedPcdGet32 (PcdNetsecPhyAddress),  // AddrRangeMax
+0,// AddrTranslationOffset
+1,// AddrLen
+  }, {
+ACPI_END_TAG_DESCRIPTOR   // Desc
+  }
+};
+
+STATIC
+EFI_STATUS
+RegisterNetsec (
+  VOID
+  )
+{
+  NON_DISCOVERABLE_DEVICE *Device;
+  EFI_STATUS  Status;
+  EFI_HANDLE  Handle;
+
+  Device = (NON_DISCOVERABLE_DEVICE *)AllocateZeroPool (sizeof (*Device));
+  if (Device == NULL) {
+return EFI_OUT_OF_RESOURCES;
+  }
+
+  Device->Type = &gNetsecNonDiscoverableDeviceGuid;
+  Device->DmaType = NonDiscoverableDeviceDmaTypeNonCoherent;
+  Device->Resources = mNetsecDesc;
+
+  Handle = NULL;
+  Status = gBS->InstallMultipleProtocolInterfaces (&Handle,
+  &gEdkiiNonDiscoverableDeviceProtocolGuid, Device,
+  NULL);
+  if (EFI_ERROR (Status)) {
+goto FreeDevice;
+  }
+  return EFI_SUCCESS;
+
+FreeDevice:
+  FreePool (Device);
+
+  return Status;
+}
+
+EFI_STATUS
+EFIAPI
+PlatformDxeEntryPoint (
+  IN EFI_HANDLE ImageHandle,
+  IN EFI_SYSTEM_TABLE   *SystemTable
+  )
+{
+  return RegisterNetsec ();
+}
diff --git a/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.inf 
b/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.inf
new file mode 100644
index ..59a3d1fb47f4
--- /dev/null

[edk2] [PATCH edk2-platforms v3 03/27] Silicon/Socionext: add PlatformPeilib implementation for SynQuacer

[Ard Biesheuvel]

Create a specialized PlatformPeiLib implementation that invokes the
platform specific firmware interface (currently, just a data structure
left in SRAM) to set the ARM standard PcdSystemMemoryBase|Size PCDs,
and expose the information via a newly added DramInfo PPI.

It is also in charge of copying the secondary compressed firmware
volume to DRAM before decompressing it. This works around a performance
issue regarding mapping the NOR flash with normal uncached attributes.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel 
---
 Silicon/Socionext/SynQuacer/Include/Platform/DramInfo.h
 |  30 
 Silicon/Socionext/SynQuacer/Include/Ppi/DramInfo.h 
 |  64 
 
Silicon/Socionext/SynQuacer/Library/SynQuacerPlatformPeiLib/SynQuacerPlatformPeiLib.c
   | 161 
 
Silicon/Socionext/SynQuacer/Library/SynQuacerPlatformPeiLib/SynQuacerPlatformPeiLib.inf
 |  53 +++
 Silicon/Socionext/SynQuacer/SynQuacer.dec  
 |  12 ++
 5 files changed, 320 insertions(+)

diff --git a/Silicon/Socionext/SynQuacer/Include/Platform/DramInfo.h 
b/Silicon/Socionext/SynQuacer/Include/Platform/DramInfo.h
new file mode 100644
index ..f7691bdade4a
--- /dev/null
+++ b/Silicon/Socionext/SynQuacer/Include/Platform/DramInfo.h
@@ -0,0 +1,30 @@
+/** @file
+  Data structure for passing DRAM information from lower level firmware
+
+  Copyright (c) 2017, Linaro Ltd. All rights reserved.
+
+  This program and the accompanying materials are licensed and made available
+  under the terms and conditions of the BSD License which accompanies this
+  distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php.
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT
+  WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _SYNQUACER_PLATFORM_DRAM_INFO_H_
+#define _SYNQUACER_PLATFORM_DRAM_INFO_H_
+
+typedef struct {
+  UINT64Base;
+  UINT64Size;
+} DRAM_INFO_ENTRY;
+
+typedef struct {
+  UINT32NumRegions;
+  UINT32Reserved;
+  DRAM_INFO_ENTRY   Entry[3];
+} DRAM_INFO;
+
+#endif
diff --git a/Silicon/Socionext/SynQuacer/Include/Ppi/DramInfo.h 
b/Silicon/Socionext/SynQuacer/Include/Ppi/DramInfo.h
new file mode 100644
index ..6453e121317d
--- /dev/null
+++ b/Silicon/Socionext/SynQuacer/Include/Ppi/DramInfo.h
@@ -0,0 +1,64 @@
+/** @file
+  DRAM info PPI to retrieve DRAM information from lower level firmware
+
+  Copyright (c) 2017, Linaro Ltd. All rights reserved.
+
+  This program and the accompanying materials are licensed and made available
+  under the terms and conditions of the BSD License which accompanies this
+  distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php.
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT
+  WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef  _SYNQUACER_DRAMINFO_PPI_
+#define  _SYNQUACER_DRAMINFO_PPI_
+
+#define SYNQUACER_DRAMINFO_PPI_GUID \
+  { 0x3e1d7356, 0xdda4, 0x4b1a, { 0x93, 0x46, 0xbf, 0x89, 0x1c, 0x86, 0x46, 
0xcc } }
+
+/**
+  Retrieve the number of discontiguous DRAM regions
+
+  @param[out] RegionCount   The number of available DRAM regions
+
+  @retval EFI_SUCCESS   The data was successfully returned.
+  @retval EFI_INVALID_PARAMETER RegionCount == NULL
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI * DRAMINFO_GET_REGION_COUNT) (
+  OUT   UINTN *RegionCount
+  );
+
+/**
+  Retrieve the base and size of a DRAM region
+
+  @param[in]  RegionIndex   The 0-based index of the region to retrieve
+  @param[out] Base  The base of the requested region
+  @param[out] Size  The size of the requested region
+
+  @retval EFI_SUCCESS   The data was successfully returned.
+  @retval EFI_INVALID_PARAMETER Base == NULL or Size == NULL
+  @retval EFI_NOT_FOUND No region exists with index >= RegionIndex
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI * DRAMINFO_GET_REGION) (
+  INUINTN RegionIndex,
+  OUT   UINT64*Base,
+  OUT   UINT64*Size
+  );
+
+typedef struct {
+  DRAMINFO_GET_REGION_COUNT   GetRegionCount;
+  DRAMINFO_GET_REGION GetRegion;
+} SYNQUACER_DRAM_INFO_PPI;
+
+extern EFI_GUID gSynQuacerDramInfoPpiGuid;
+
+#endif
diff --git 
a/Silicon/Socionext/SynQuacer/Library/SynQuacerPlatformPeiLib/SynQuacerPlatformPeiLib.c
 
b/Silicon/Socionext/SynQuacer/Library/SynQuacerPlatformPeiLib/SynQuacerPlatformPeiLib.c
new file mode 100644
index ..d83f2ec524e5
--- /dev/null
+++ 
b/Silicon/Socionext/SynQuacer/Library/SynQuacerPlatformPeiLib/SynQuacerPlatformPeiLib.c
@@ -0,0 +1,161 @@
+/** @file
+*
+*  Copyright (c) 2011-2014, ARM Limited. All rig

[edk2] [PATCH v2 1/1] EmbeddedPkg: Implement NorFlashInfoLib

[Marcin Wojtas]

The SPI NOR flash drivers which base on ArmPlatformPkg's
NorFlashDxe usually make use of static declarations of the
flash instances with their type and parameters. As a result
it implies hardcoding the exact way of flash handling, not to
mention the code does not look very nice. Much better solution
would be obtaining the flash ID and hence its description
in runtime.

Because JEDEC compliant SPI NOR devices allow to obtain their ID
with READ_ID command (0x9f), implement a NorFlashInfoLib that gives
an access to the NOR flash data, such as name, page size, sector
(block) size and others, of more than 50 different models.
The new library user should pass an output array from issuing
READ_ID command to the NorFlashGetInfo () routine - if the
match is found, an allocated (optionally for RT) pool with
the flash description copy will be returned.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Marcin Wojtas 

=
Patch available in the github:
https://github.com/MarvellEmbeddedProcessors/edk2/commits/norlib-upstream-r20171031

Changelog:
v1 -> v2
  * In flash info flags: s/NF_/NOR_FLASH_/
  * Rename routines to NorFlashGetInfo and NorFlashPrintInfo
  * Fix NorFlashGetInfo description.
  * Improve commit log (fix typos and other minor improvements)

---
 EmbeddedPkg/EmbeddedPkg.dec |   1 +
 EmbeddedPkg/Include/Library/NorFlashInfoLib.h   |  84 
 EmbeddedPkg/Library/NorFlashInfoLib/NorFlashInfoLib.c   | 225 

 EmbeddedPkg/Library/NorFlashInfoLib/NorFlashInfoLib.inf |  34 +++
 4 files changed, 344 insertions(+)

diff --git a/EmbeddedPkg/EmbeddedPkg.dec b/EmbeddedPkg/EmbeddedPkg.dec
index 52482af..aa551ab 100644
--- a/EmbeddedPkg/EmbeddedPkg.dec
+++ b/EmbeddedPkg/EmbeddedPkg.dec
@@ -45,6 +45,7 @@
   EblNetworkLib|Include/Library/EblNetworkLib.h
   GdbSerialLib|Include/Library/GdbSerialLib.h
   DebugAgentTimerLib|Include/Library/DebugAgentTimerLib.h
+  NorFlashInfoLib|Include/Library/NorFlashInfoLib.h
 
   DtPlatformDtbLoaderLib|Include/Library/DtPlatformDtbLoaderLib.h
 
diff --git a/EmbeddedPkg/Include/Library/NorFlashInfoLib.h 
b/EmbeddedPkg/Include/Library/NorFlashInfoLib.h
new file mode 100644
index 000..e28c169
--- /dev/null
+++ b/EmbeddedPkg/Include/Library/NorFlashInfoLib.h
@@ -0,0 +1,84 @@
+/** @file
+*
+*  Copyright (c) 2017 Marvell International Ltd.
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD 
License
+*  which accompanies this distribution.  The full text of the license may be 
found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR 
IMPLIED.
+*
+**/
+
+#ifndef __NOR_FLASH_ID_LIB_H__
+#define __NOR_FLASH_ID_LIB_H__
+
+#include 
+
+#define NOR_FLASH_MAX_ID_LEN6
+
+typedef struct {
+  /* Device name */
+  UINT16 *Name;
+
+  /*
+   * JEDEC ID
+   */
+  UINT8  Id[NOR_FLASH_MAX_ID_LEN];
+  UINT8  IdLen;
+
+  UINT16 PageSize;
+
+  /*
+   * Below parameters can be referred as BlockSize
+   * and BlockCount, when treating the NorFlash as
+   * block device.
+   */
+  UINT32 SectorSize;
+  UINT32 SectorCount;
+
+  UINT16 Flags;
+#define NOR_FLASH_ERASE_4K (1 << 0)  /* Use 4096B erase blocks and 
CMD_ERASE_4K */
+#define NOR_FLASH_WRITE_FSR(1 << 1)  /* Use flag status register for write 
*/
+#define NOR_FLASH_4B_ADDR  (1 << 2)  /* Use 4B addressing */
+} NOR_FLASH_INFO;
+
+/**
+  Return an allocated copy pool of the NOR flash information structure.
+
+  @param[in]   Id Pointer to an array with JEDEC ID 
obtained
+  from the NOR flash with READ_ID command
+  (0x9f)
+  @param[in out]   FlashInfo  Pointer to NOR flash information 
structure
+  @param[in]   AllocateForRuntime A flag specifying a type of a copy pool
+  allocation (TRUE for runtime, FALSE for
+  normal)
+
+  @retval   EFI_SUCCESS   Operation completed successfully
+  @retval   EFI_NOT_FOUND No matching entry in NOR ID table found
+  @retval   EFI_OUT_OF_RESOURCES  No pool memory available
+
+**/
+EFI_STATUS
+EFIAPI
+NorFlashGetInfo (
+  IN UINT8*Id,
+  IN OUT NOR_FLASH_INFO  **FlashInfo,
+  IN BOOLEAN   AllocateForRuntime
+  );
+
+/**
+  Print NOR flash information basing on data stored in
+  the NOR_FLASH_INFO structure.
+
+  @param[in]   FlashInfo  Pointer to NOR flash information 
structure
+
+**/
+VOID
+EFIAPI
+NorFlashPrintInfo (
+  IN NOR_FLASH_INFO  *Info
+  );
+#endif
diff --git a/EmbeddedPkg/Library/NorFlashInfoLib/NorFlashInfoLib.c 
b/EmbeddedPkg/Library/NorFlashInfoLib/NorFlashInfoLib.c
new file mode 100644
index 000.

[edk2] Build error in StdLib with VS 2015 compiler

[Karunakar P]

Hello All,

Facing an build error with Stdlib module when built with VS 2015 compiler.

e:\test\StdLib\Include\sys/EfiCdefs.h(357): error C2220: warning treated as 
error - no 'object' file generated
e:\test\StdLib\Include\sys/EfiCdefs.h(357): warning C4117: macro name 
'__STDC_HOSTED__' is reserved, '#define' ignored

below change resolving this error. Would you please review and provide comments.

#ifndef __STDC_HOSTED__
#define __STDC_HOSTED__ 1
#endif


Thank You,
Karunakar
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Re: [edk2] [platforms: PATCH 1/6] Marvell/Drivers: MvSpiFlash: Improve ReadId

[Marcin Wojtas]

2017-10-31 10:07 GMT+01:00 Leif Lindholm :
> On Tue, Oct 31, 2017 at 04:59:30AM +0100, Marcin Wojtas wrote:
>> Fix the ReadId routine by using master's ReadWrite callback
>> instead of the raw Transfer - no longer swapping and byte
>> shifting is needed. Simplify code by using local array
>> instead of dynamic allocation. Moreover store the FlashId
>> in an UINT8 array PCD instead of the concatenated UINT32
>> format - this way less overhead in the driver is needed
>> for comparing the buffers.
>>
>> The new handling allowed for cleaning Fupdate and Sf
>> shell commands FlashProbe routines.
>>
>> Contributed-under: TianoCore Contribution Agreement 1.1
>> Signed-off-by: Marcin Wojtas 
>> ---
>>  Platform/Marvell/Applications/FirmwareUpdate/FUpdate.c | 22 +++
>>  Platform/Marvell/Applications/SpiTool/SpiFlashCmd.c| 37 
>> ++
>>  Platform/Marvell/Armada/Armada70x0.dsc |  2 +-
>>  Platform/Marvell/Drivers/Spi/Devices/MvSpiFlash.c  | 41 
>> 
>>  Platform/Marvell/Drivers/Spi/Devices/MvSpiFlash.h  |  2 +
>>  Platform/Marvell/Include/Protocol/SpiFlash.h   |  3 ++
>>  Platform/Marvell/Marvell.dec   |  2 +-
>>  7 files changed, 48 insertions(+), 61 deletions(-)
>>
>> diff --git a/Platform/Marvell/Applications/FirmwareUpdate/FUpdate.c 
>> b/Platform/Marvell/Applications/FirmwareUpdate/FUpdate.c
>> index 664411a..d70645d 100644
>> --- a/Platform/Marvell/Applications/FirmwareUpdate/FUpdate.c
>> +++ b/Platform/Marvell/Applications/FirmwareUpdate/FUpdate.c
>> @@ -94,28 +94,16 @@ SpiFlashProbe (
>>)
>>  {
>>EFI_STATUS   Status;
>> -  UINT32   IdBuffer, Id, RefId;
>> +  UINT8   *FlashId;
>>
>> -  Id = PcdGet32 (PcdSpiFlashId);
>> -
>> -  IdBuffer = CMD_READ_ID & 0xff;
>> +  FlashId = (UINT8 *)PcdGetPtr (PcdSpiFlashId);
>>
>>// Read SPI flash ID
>> -  SpiFlashProtocol->ReadId (Slave, sizeof (UINT32), (UINT8 *)&IdBuffer);
>> -
>> -  // Swap and extract 3 bytes of the ID
>> -  RefId = SwapBytes32 (IdBuffer) >> 8;
>> -
>> -  if (RefId == 0) {
>> -Print (L"%s: No SPI flash detected");
>> -return EFI_DEVICE_ERROR;
>> -  } else if (RefId != Id) {
>> -Print (L"%s: Unsupported SPI flash detected with ID=%2x\n", 
>> CMD_NAME_STRING, RefId);
>> -return EFI_DEVICE_ERROR;
>> +  Status = SpiFlashProtocol->ReadId (Slave, NOR_FLASH_ID_DEFAULT_LEN, 
>> FlashId);
>
> Is the length not possible to calculate somehow?
> Having a MAX_LEN defined and then using a DEFAULT_LEN or explicitly
> extracting 3 bytes from somewhere feels suboptimal.
>

I know. It is however a change that was somewhat artificially
extracted, so that to make the next patch more readable
(NOR_FLASH_ID_DEFAULT_LEN is removed there). I will substitute it with
PcdGetSize (PcdSpiFlashId).

Marcin

> /
> Leif
>
>> +  if (EFI_ERROR (Status)) {
>> +return SHELL_ABORTED;
>>}
>>
>> -  Print (L"%s: Detected supported SPI flash with ID=%3x\n", 
>> CMD_NAME_STRING, RefId);
>> -
>>Status = SpiFlashProtocol->Init (SpiFlashProtocol, Slave);
>>if (EFI_ERROR(Status)) {
>>  Print (L"%s: Cannot initialize flash device\n", CMD_NAME_STRING);
>> diff --git a/Platform/Marvell/Applications/SpiTool/SpiFlashCmd.c 
>> b/Platform/Marvell/Applications/SpiTool/SpiFlashCmd.c
>> index 9321f6b..a12f2ec 100644
>> --- a/Platform/Marvell/Applications/SpiTool/SpiFlashCmd.c
>> +++ b/Platform/Marvell/Applications/SpiTool/SpiFlashCmd.c
>> @@ -166,37 +166,24 @@ FlashProbe (
>>)
>>  {
>>EFI_STATUS Status;
>> -  UINT8  IdBuffer[4];
>> -  UINT32 Id, RefId;
>> +  UINT8  *FlashId;
>>
>> -  Id = PcdGet32 (PcdSpiFlashId);
>> +  FlashId = (UINT8 *)PcdGetPtr (PcdSpiFlashId);
>>
>> -  IdBuffer[0] = CMD_READ_ID;
>> -
>> -  SpiFlashProtocol->ReadId (
>> -Slave,
>> -4,
>> -IdBuffer
>> -);
>> -
>> -  RefId = (IdBuffer[0] << 16) + (IdBuffer[1] << 8) + IdBuffer[2];
>> +  Status = SpiFlashProtocol->ReadId (Slave, NOR_FLASH_ID_DEFAULT_LEN, 
>> FlashId);
>> +  if (EFI_ERROR (Status)) {
>> +return SHELL_ABORTED;
>> +  }
>>
>> -  if (RefId == Id) {
>> -Print (L"sf: Detected supported SPI flash with ID=%3x\n", RefId);
>> -Status = SpiFlashProtocol->Init (SpiFlashProtocol, Slave);
>> -if (EFI_ERROR(Status)) {
>> -  Print (L"sf: Cannot initialize flash device\n");
>> -  return SHELL_ABORTED;
>> -}
>> -InitFlag = 0;
>> -return EFI_SUCCESS;
>> -  } else if (RefId != 0) {
>> -Print (L"sf: Unsupported SPI flash detected with ID=%2x\n", RefId);
>> +  Status = SpiFlashProtocol->Init (SpiFlashProtocol, Slave);
>> +  if (EFI_ERROR (Status)) {
>> +Print (L"sf: Cannot initialize flash device\n");
>>  return SHELL_ABORTED;
>>}
>>
>> -  Print (L"sf: No SPI flash detected");
>> -  return SHELL_ABORTED;
>> +  InitFlag = 0;
>> +
>> +  return SHELL_SUCCESS;
>>  }
>>
>>  SHELL_STATUS
>> diff --git a/Platform/Marvell/Armada/Armada70x0.dsc 
>> b/Platform/Marvell/Armada/Armada70x0.dsc
>> index 0396e8e..4d

Re: [edk2] [platforms: PATCH 1/6] Marvell/Drivers: MvSpiFlash: Improve ReadId

[Leif Lindholm]

On Tue, Oct 31, 2017 at 04:59:30AM +0100, Marcin Wojtas wrote:
> Fix the ReadId routine by using master's ReadWrite callback
> instead of the raw Transfer - no longer swapping and byte
> shifting is needed. Simplify code by using local array
> instead of dynamic allocation. Moreover store the FlashId
> in an UINT8 array PCD instead of the concatenated UINT32
> format - this way less overhead in the driver is needed
> for comparing the buffers.
> 
> The new handling allowed for cleaning Fupdate and Sf
> shell commands FlashProbe routines.
> 
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Marcin Wojtas 
> ---
>  Platform/Marvell/Applications/FirmwareUpdate/FUpdate.c | 22 +++
>  Platform/Marvell/Applications/SpiTool/SpiFlashCmd.c| 37 
> ++
>  Platform/Marvell/Armada/Armada70x0.dsc |  2 +-
>  Platform/Marvell/Drivers/Spi/Devices/MvSpiFlash.c  | 41 
> 
>  Platform/Marvell/Drivers/Spi/Devices/MvSpiFlash.h  |  2 +
>  Platform/Marvell/Include/Protocol/SpiFlash.h   |  3 ++
>  Platform/Marvell/Marvell.dec   |  2 +-
>  7 files changed, 48 insertions(+), 61 deletions(-)
> 
> diff --git a/Platform/Marvell/Applications/FirmwareUpdate/FUpdate.c 
> b/Platform/Marvell/Applications/FirmwareUpdate/FUpdate.c
> index 664411a..d70645d 100644
> --- a/Platform/Marvell/Applications/FirmwareUpdate/FUpdate.c
> +++ b/Platform/Marvell/Applications/FirmwareUpdate/FUpdate.c
> @@ -94,28 +94,16 @@ SpiFlashProbe (
>)
>  {
>EFI_STATUS   Status;
> -  UINT32   IdBuffer, Id, RefId;
> +  UINT8   *FlashId;
>  
> -  Id = PcdGet32 (PcdSpiFlashId);
> -
> -  IdBuffer = CMD_READ_ID & 0xff;
> +  FlashId = (UINT8 *)PcdGetPtr (PcdSpiFlashId);
>  
>// Read SPI flash ID
> -  SpiFlashProtocol->ReadId (Slave, sizeof (UINT32), (UINT8 *)&IdBuffer);
> -
> -  // Swap and extract 3 bytes of the ID
> -  RefId = SwapBytes32 (IdBuffer) >> 8;
> -
> -  if (RefId == 0) {
> -Print (L"%s: No SPI flash detected");
> -return EFI_DEVICE_ERROR;
> -  } else if (RefId != Id) {
> -Print (L"%s: Unsupported SPI flash detected with ID=%2x\n", 
> CMD_NAME_STRING, RefId);
> -return EFI_DEVICE_ERROR;
> +  Status = SpiFlashProtocol->ReadId (Slave, NOR_FLASH_ID_DEFAULT_LEN, 
> FlashId);

Is the length not possible to calculate somehow?
Having a MAX_LEN defined and then using a DEFAULT_LEN or explicitly
extracting 3 bytes from somewhere feels suboptimal.

/
Leif

> +  if (EFI_ERROR (Status)) {
> +return SHELL_ABORTED;
>}
>  
> -  Print (L"%s: Detected supported SPI flash with ID=%3x\n", CMD_NAME_STRING, 
> RefId);
> -
>Status = SpiFlashProtocol->Init (SpiFlashProtocol, Slave);
>if (EFI_ERROR(Status)) {
>  Print (L"%s: Cannot initialize flash device\n", CMD_NAME_STRING);
> diff --git a/Platform/Marvell/Applications/SpiTool/SpiFlashCmd.c 
> b/Platform/Marvell/Applications/SpiTool/SpiFlashCmd.c
> index 9321f6b..a12f2ec 100644
> --- a/Platform/Marvell/Applications/SpiTool/SpiFlashCmd.c
> +++ b/Platform/Marvell/Applications/SpiTool/SpiFlashCmd.c
> @@ -166,37 +166,24 @@ FlashProbe (
>)
>  {
>EFI_STATUS Status;
> -  UINT8  IdBuffer[4];
> -  UINT32 Id, RefId;
> +  UINT8  *FlashId;
>  
> -  Id = PcdGet32 (PcdSpiFlashId);
> +  FlashId = (UINT8 *)PcdGetPtr (PcdSpiFlashId);
>  
> -  IdBuffer[0] = CMD_READ_ID;
> -
> -  SpiFlashProtocol->ReadId (
> -Slave,
> -4,
> -IdBuffer
> -);
> -
> -  RefId = (IdBuffer[0] << 16) + (IdBuffer[1] << 8) + IdBuffer[2];
> +  Status = SpiFlashProtocol->ReadId (Slave, NOR_FLASH_ID_DEFAULT_LEN, 
> FlashId);
> +  if (EFI_ERROR (Status)) {
> +return SHELL_ABORTED;
> +  }
>  
> -  if (RefId == Id) {
> -Print (L"sf: Detected supported SPI flash with ID=%3x\n", RefId);
> -Status = SpiFlashProtocol->Init (SpiFlashProtocol, Slave);
> -if (EFI_ERROR(Status)) {
> -  Print (L"sf: Cannot initialize flash device\n");
> -  return SHELL_ABORTED;
> -}
> -InitFlag = 0;
> -return EFI_SUCCESS;
> -  } else if (RefId != 0) {
> -Print (L"sf: Unsupported SPI flash detected with ID=%2x\n", RefId);
> +  Status = SpiFlashProtocol->Init (SpiFlashProtocol, Slave);
> +  if (EFI_ERROR (Status)) {
> +Print (L"sf: Cannot initialize flash device\n");
>  return SHELL_ABORTED;
>}
>  
> -  Print (L"sf: No SPI flash detected");
> -  return SHELL_ABORTED;
> +  InitFlag = 0;
> +
> +  return SHELL_SUCCESS;
>  }
>  
>  SHELL_STATUS
> diff --git a/Platform/Marvell/Armada/Armada70x0.dsc 
> b/Platform/Marvell/Armada/Armada70x0.dsc
> index 0396e8e..4d5f55f 100644
> --- a/Platform/Marvell/Armada/Armada70x0.dsc
> +++ b/Platform/Marvell/Armada/Armada70x0.dsc
> @@ -94,7 +94,7 @@
>gMarvellTokenSpaceGuid.PcdSpiFlashAddressCycles|3
>gMarvellTokenSpaceGuid.PcdSpiFlashEraseSize|65536
>gMarvellTokenSpaceGuid.PcdSpiFlashPageSize|256
> -  gMarvellTokenSpaceGuid.PcdSpiFlashId|0x20BA18
> +  gMarvellTokenSpaceGuid.PcdSpiFlashId|{ 0x20, 0x

[edk2] [PATCH 0/2] CryptoPkg/BaseCryptLib: Correct CRT realloc Wrapper

[Long Qin]

There is one long-standing problem in current CRT realloc wrapper
implementation, which will cause the obvious buffer overflow issue
when re-allocating memory block.
One BZ report: https://bugzilla.tianocore.org/show_bug.cgi?id=605

This patch series is to fix this buffer overflow issue by introducing
one extra header to record the memory buffer size information.
And extra comments were also added to clarify the memory release routines
if the caller is required to free the memory block outside the function.

Long Qin (2):
  CryptoPkg/BaseCryptLib: Fix buffer overflow issue in realloc wrapper
  CryptoPkg/BaseCryptLib: Fix mismatched memory allocation/free

 CryptoPkg/Include/Library/BaseCryptLib.h   | 16 +++--
 CryptoPkg/Library/BaseCryptLib/Pk/CryptPkcs7Sign.c |  5 +-
 .../Library/BaseCryptLib/Pk/CryptPkcs7SignNull.c   |  3 +-
 .../Library/BaseCryptLib/Pk/CryptPkcs7Verify.c | 15 +++--
 .../Library/BaseCryptLib/Pk/CryptPkcs7VerifyNull.c | 13 ++--
 .../BaseCryptLib/SysCall/BaseMemAllocation.c   | 72 +++---
 6 files changed, 97 insertions(+), 27 deletions(-)

-- 
2.14.1.windows.1

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[edk2] [PATCH 1/2] CryptoPkg/BaseCryptLib: Fix buffer overflow issue in realloc wrapper

[Long Qin]

There is one long-standing problem in CRT realloc wrapper, which will
cause the obvious buffer overflow issue when re-allocating one bigger
memory block:
void *realloc (void *ptr, size_t size)
{
  //
  // BUG: hardcode OldSize == size! We have no any knowledge about
  // memory size of original pointer ptr.
  //
  return ReallocatePool ((UINTN) size, (UINTN) size, ptr);
}
This patch introduces one extra header to record the memory buffer size
information when allocating memory block from malloc routine, and re-wrap
the realloc() and free() routines to remove this BUG.

Cc: Laszlo Ersek 
Cc: Ting Ye 
Cc: Jian J Wang 
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Qin Long 
---
 .../BaseCryptLib/SysCall/BaseMemAllocation.c   | 72 +++---
 1 file changed, 65 insertions(+), 7 deletions(-)

diff --git a/CryptoPkg/Library/BaseCryptLib/SysCall/BaseMemAllocation.c 
b/CryptoPkg/Library/BaseCryptLib/SysCall/BaseMemAllocation.c
index f390e0d449..ed37a0ff39 100644
--- a/CryptoPkg/Library/BaseCryptLib/SysCall/BaseMemAllocation.c
+++ b/CryptoPkg/Library/BaseCryptLib/SysCall/BaseMemAllocation.c
@@ -16,6 +16,18 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER 
EXPRESS OR IMPLIED.
 #include 
 #include 
 
+//
+// Extra header to record the memory buffer size from malloc routine.
+//
+#define CRYPTMEM_HEAD_SIGNATURESIGNATURE_32('c','m','h','d')
+typedef struct {
+  UINT32Signature;
+  UINT32Reserved;
+  UINTN Size;
+} CRYPTMEM_HEAD;
+
+#define CRYPTMEM_OVERHEAD  sizeof(CRYPTMEM_HEAD)
+
 //
 // -- Memory-Allocation Routines --
 //
@@ -23,27 +35,73 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER 
EXPRESS OR IMPLIED.
 /* Allocates memory blocks */
 void *malloc (size_t size)
 {
-  return AllocatePool ((UINTN) size);
+  CRYPTMEM_HEAD  *PoolHdr;
+  UINTN  NewSize;
+  VOID   *Data;
+
+  //
+  // Adjust the size by the buffer header overhead
+  //
+  NewSize = (UINTN)(size) + CRYPTMEM_OVERHEAD;
+
+  Data  = AllocatePool (NewSize);
+  if (Data != NULL) {
+PoolHdr = (CRYPTMEM_HEAD *)Data;
+//
+// Record the memory brief information
+//
+PoolHdr->Signature = CRYPTMEM_HEAD_SIGNATURE;
+PoolHdr->Size  = size;
+  }
+  return (VOID *)(PoolHdr + 1);
 }
 
 /* Reallocate memory blocks */
 void *realloc (void *ptr, size_t size)
 {
-  //
-  // BUG: hardcode OldSize == size! We have no any knowledge about
-  // memory size of original pointer ptr.
-  //
-  return ReallocatePool ((UINTN) size, (UINTN) size, ptr);
+  CRYPTMEM_HEAD  *OldPoolHdr;
+  CRYPTMEM_HEAD  *NewPoolHdr;
+  UINTN  OldSize;
+  UINTN  NewSize;
+  VOID   *Data;
+
+  NewSize = (UINTN)size + CRYPTMEM_OVERHEAD;
+  Data = AllocatePool (NewSize);
+  if (Data != NULL) {
+NewPoolHdr = (CRYPTMEM_HEAD *)Data;
+NewPoolHdr->Signature = CRYPTMEM_HEAD_SIGNATURE;
+NewPoolHdr->Size  = size;
+if (ptr != NULL) {
+  //
+  // Retrieve the original size from the buffer header.
+  //
+  OldPoolHdr = (CRYPTMEM_HEAD *)ptr - 1;
+  ASSERT (OldPoolHdr->Signature == CRYPTMEM_HEAD_SIGNATURE);
+  OldSize = OldPoolHdr->Size;
+
+  //
+  // Duplicate the buffer content.
+  //
+  CopyMem ((VOID *)(NewPoolHdr + 1), ptr, MIN (OldSize, size));
+  FreePool ((VOID *)OldPoolHdr);
+}
+  }
+
+  return (VOID *)(NewPoolHdr + 1);
 }
 
 /* De-allocates or frees a memory block */
 void free (void *ptr)
 {
+  CRYPTMEM_HEAD  *PoolHdr;
+
   //
   // In Standard C, free() handles a null pointer argument transparently. This
   // is not true of FreePool() below, so protect it.
   //
   if (ptr != NULL) {
-FreePool (ptr);
+PoolHdr = (CRYPTMEM_HEAD *)ptr - 1;
+ASSERT (PoolHdr->Signature == CRYPTMEM_HEAD_SIGNATURE);
+FreePool (PoolHdr);
   }
 }
-- 
2.14.1.windows.1

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[edk2] [PATCH 2/2] CryptoPkg/BaseCryptLib: Fix mismatched memory allocation/free

[Long Qin]

The malloc/free (instead of AllocatePool/FreePool) were used directly
in some wrapper implementations, which was designed to leverage the
light-weight memory management routines at Runtime phase.
The malloc/free and AllocatePool/FreePool usages are required to be
matched, after extra memory size info header was introduced in malloc
wrapper.

This patch corrects two memory allocation cases, which requires the
caller to free the buffer with FreePool() outside the function call.

And some comments were also added to clarify the correct memory
release functions if it's the caller's responsibility to free the
memory buffer.

Cc: Laszlo Ersek 
Cc: Ting Ye 
Cc: Jian J Wang 
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Qin Long 
---
 CryptoPkg/Include/Library/BaseCryptLib.h | 16 ++--
 CryptoPkg/Library/BaseCryptLib/Pk/CryptPkcs7Sign.c   |  5 +++--
 CryptoPkg/Library/BaseCryptLib/Pk/CryptPkcs7SignNull.c   |  3 ++-
 CryptoPkg/Library/BaseCryptLib/Pk/CryptPkcs7Verify.c | 15 +--
 CryptoPkg/Library/BaseCryptLib/Pk/CryptPkcs7VerifyNull.c | 13 -
 5 files changed, 32 insertions(+), 20 deletions(-)

diff --git a/CryptoPkg/Include/Library/BaseCryptLib.h 
b/CryptoPkg/Include/Library/BaseCryptLib.h
index 5f67ecb709..e2b6a95666 100644
--- a/CryptoPkg/Include/Library/BaseCryptLib.h
+++ b/CryptoPkg/Include/Library/BaseCryptLib.h
@@ -2388,10 +2388,12 @@ Pkcs5HashPassword (
   @param[in]  P7Data   Pointer to the PKCS#7 message to verify.
   @param[in]  P7Length Length of the PKCS#7 message in bytes.
   @param[out] CertStackPointer to Signer's certificates retrieved from 
P7Data.
-   It's caller's responsibility to free the buffer.
+   It's caller's responsibility to free the buffer with
+   Pkcs7FreeSigners().
   @param[out] StackLength  Length of signer's certificates in bytes.
   @param[out] TrustedCert  Pointer to a trusted certificate from Signer's 
certificates.
-   It's caller's responsibility to free the buffer.
+   It's caller's responsibility to free the buffer with
+   Pkcs7FreeSigners().
   @param[out] CertLength   Length of the trusted certificate in bytes.
 
   @retval  TRUEThe operation is finished successfully.
@@ -2433,10 +2435,11 @@ Pkcs7FreeSigners (
   @param[in]  P7DataPointer to the PKCS#7 message.
   @param[in]  P7Length  Length of the PKCS#7 message in bytes.
   @param[out] SignerChainCerts  Pointer to the certificates list chained to 
signer's
-certificate. It's caller's responsibility to 
free the buffer.
+certificate. It's caller's responsibility to 
free the buffer
+with Pkcs7FreeSigners().
   @param[out] ChainLength   Length of the chained certificates list buffer 
in bytes.
   @param[out] UnchainCerts  Pointer to the unchained certificates lists. 
It's caller's
-responsibility to free the buffer.
+responsibility to free the buffer with 
Pkcs7FreeSigners().
   @param[out] UnchainLength Length of the unchained certificates list 
buffer in bytes.
 
   @retval  TRUE The operation is finished successfully.
@@ -2472,7 +2475,8 @@ Pkcs7GetCertificatesList (
   @param[in]  OtherCerts   Pointer to an optional additional set of 
certificates to
include in the PKCS#7 signedData (e.g. any 
intermediate
CAs in the chain).
-  @param[out] SignedData   Pointer to output PKCS#7 signedData.
+  @param[out] SignedData   Pointer to output PKCS#7 signedData. It's 
caller's
+   responsibility to free the buffer with 
FreePool().
   @param[out] SignedDataSize   Size of SignedData in bytes.
 
   @retval TRUE PKCS#7 data signing succeeded.
@@ -2540,7 +2544,7 @@ Pkcs7Verify (
   @param[in]   P7Data   Pointer to the PKCS#7 signed data to process.
   @param[in]   P7Length Length of the PKCS#7 signed data in bytes.
   @param[out]  Content  Pointer to the extracted content from the PKCS#7 
signedData.
-It's caller's responsibility to free the buffer.
+It's caller's responsibility to free the buffer 
with FreePool().
   @param[out]  ContentSize  The size of the extracted content in bytes.
 
   @retval TRUE  The P7Data was correctly formatted for processing.
diff --git a/CryptoPkg/Library/BaseCryptLib/Pk/CryptPkcs7Sign.c 
b/CryptoPkg/Library/BaseCryptLib/Pk/CryptPkcs7Sign.c
index d3b1a907aa..0f61d4b4ad 100644
--- a/CryptoPkg/Library/BaseCryptLib/Pk/CryptPkcs7Sign.c
+++ b/CryptoPkg/Library/BaseCryptLib/Pk/CryptPkcs7Sign.c
@@ -34,7 +34,8 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHE

Re: [edk2] [PATCH] BaseTools/tools_def: suppress GCC predefined macros in DTB compilation

[Ard Biesheuvel]

On 31 October 2017 at 05:41, Gao, Liming  wrote:
> Ard:
>   I have no other comments.
>
> Reviewed-by: Liming Gao 
>

Thanks. I already pushed this as 8512fc5731df



>>-Original Message-
>>From: Ard Biesheuvel [mailto:ard.biesheu...@linaro.org]
>>Sent: Thursday, October 26, 2017 6:12 PM
>>To: edk2-devel@lists.01.org
>>Cc: leif.lindh...@linaro.org; Gao, Liming ; Zhu,
>>Yonghong ; Ard Biesheuvel
>>
>>Subject: [PATCH] BaseTools/tools_def: suppress GCC predefined macros in
>>DTB compilation
>>
>>The standard GCC preprocessor we use to preprocess device tree sources
>>files has a whole bunch of macros predefined, among which
>>
>>This causes a property like 'linux,code' to be converted into '1,code'
>>which is obviously wrong. So let's get rid of all the predefined macros
>>by passing -undef to the preprocessor command line.
>>
>>Contributed-under: TianoCore Contribution Agreement 1.1
>>Signed-off-by: Ard Biesheuvel 
>>---
>> BaseTools/Conf/tools_def.template | 2 +-
>> 1 file changed, 1 insertion(+), 1 deletion(-)
>>
>>diff --git a/BaseTools/Conf/tools_def.template
>>b/BaseTools/Conf/tools_def.template
>>index df7c109438fd..98df0ffc9294 100755
>>--- a/BaseTools/Conf/tools_def.template
>>+++ b/BaseTools/Conf/tools_def.template
>>@@ -4369,7 +4369,7 @@ DEFINE GCC_VFRPP_FLAGS = -x c -E -P -
>>DVFRCOMPILE --include $(DEST_DI
>> DEFINE GCC_ASLPP_FLAGS = -x c -E -include AutoGen.h
>> DEFINE GCC_ASLCC_FLAGS = -x c
>> DEFINE GCC_WINDRES_FLAGS   = -J rc -O coff
>>-DEFINE GCC_DTCPP_FLAGS = -E -x assembler-with-cpp -imacros
>>$(DEST_DIR_DEBUG)/AutoGen.h -nostdinc
>>+DEFINE GCC_DTCPP_FLAGS = -E -x assembler-with-cpp -imacros
>>$(DEST_DIR_DEBUG)/AutoGen.h -nostdinc -undef
>> DEFINE GCC_IA32_RC_FLAGS   = -I binary -O elf32-i386  -B 
>> i386--
>>rename-section .data=.hii
>> DEFINE GCC_X64_RC_FLAGS= -I binary -O elf64-x86-64-B 
>> i386--
>>rename-section .data=.hii
>> DEFINE GCC_IPF_RC_FLAGS= -I binary -O elf64-ia64-little   -B 
>> ia64--
>>rename-section .data=.hii
>>--
>>2.11.0
>
___
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Re: [edk2] [PATCH] MdeModulePkg/PciBus: Disable BME of all devices when entering RT

[Yao, Jiewen]

The patch seems good. But the commit message is quite confusing.

Disabling BME does not have any assumption on the existence of IOMMU protection.
No matter a platform with IOMMU protection, or without IOMMU protection, this 
solution always works.

I suggest to change commit message to be:

The patch ensures all DMA transactions are blocked at ExitBootService.
If a platform enables IOMMU before and need disable IOMMU at ExitBootService, 
the IOMMU should be disabled after PCI bus driver disable BME. 


Thank you
Yao Jiewen

> -Original Message-
> From: Ni, Ruiyu
> Sent: Tuesday, October 31, 2017 3:54 PM
> To: edk2-devel@lists.01.org
> Cc: Michael Turner ; Kinney, Michael D
> ; Yao, Jiewen 
> Subject: [PATCH] MdeModulePkg/PciBus: Disable BME of all devices when
> entering RT
> 
> The patch assumes IOMMU protections are disabled after PciBus
> disables the BMT bit in Command register.
> It ensures all DMA transactions are protected by IOMMU.
> 
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Michael Turner 
> Signed-off-by: Ruiyu Ni 
> Cc: Michael D Kinney 
> Cc: Jiewen Yao 
> ---
>  MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h   |  2 +
>  MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf  |  3 +
>  MdeModulePkg/Bus/Pci/PciBusDxe/PciDeviceSupport.c | 86
> +++
>  3 files changed, 91 insertions(+)
> 
> diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h
> b/MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h
> index 55eb3a5a80..79b5b71082 100644
> --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h
> +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h
> @@ -18,6 +18,8 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND,
> EITHER EXPRESS OR IMPLIED.
> 
>  #include 
> 
> +#include 
> +
>  #include 
>  #include 
>  #include 
> diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
> b/MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
> index 97608bfcf2..d5b8fab3ca 100644
> --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
> +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
> @@ -80,6 +80,9 @@ [LibraryClasses]
>DebugLib
>PeCoffLib
> 
> +[Guids]
> +  gEfiEventExitBootServicesGuid   ##
> SOMETIMES_CONSUMES ## Event
> +
>  [Protocols]
>gEfiPciHotPlugRequestProtocolGuid   ##
> SOMETIMES_PRODUCES
>gEfiPciIoProtocolGuid   ## BY_START
> diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciDeviceSupport.c
> b/MdeModulePkg/Bus/Pci/PciBusDxe/PciDeviceSupport.c
> index 97bb971a59..b5530a13d1 100644
> --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciDeviceSupport.c
> +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciDeviceSupport.c
> @@ -21,6 +21,72 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY
> KIND, EITHER EXPRESS OR IMPLIED.
>  LIST_ENTRY  mPciDevicePool;
> 
>  /**
> + Disable Bus Master Enable bit in all devices in the list.
> +
> + @param Devices  A device list.
> +**/
> +VOID
> +DisableBmeOnTree (
> +  IN LIST_ENTRY  *Devices
> +  )
> +{
> +  LIST_ENTRY  *Link;
> +  PCI_IO_DEVICE   *PciIoDevice;
> +  UINT16   Command;
> +
> +  for ( Link = GetFirstNode (Devices)
> +  ; !IsNull (Devices, Link)
> +  ; Link = GetNextNode (Devices, Link)
> +  ) {
> +PciIoDevice = PCI_IO_DEVICE_FROM_LINK (Link);
> +//
> +// Turn off all children's Bus Master, if any
> +//
> +DisableBmeOnTree (&PciIoDevice->ChildList);
> +
> +//
> +// If this is a device that supports BME, disable BME on this device.
> +//
> +if ((PciIoDevice->Supports & EFI_PCI_IO_ATTRIBUTE_BUS_MASTER) != 0) {
> +  PCI_READ_COMMAND_REGISTER(PciIoDevice, &Command);
> +  if ((Command & EFI_PCI_COMMAND_BUS_MASTER) != 0) {
> +Command &= ~EFI_PCI_COMMAND_BUS_MASTER;
> +PCI_SET_COMMAND_REGISTER (PciIoDevice, Command);
> +DEBUG ((
> +  EFI_D_INFO,"  %02x   %02x  %02x %04x\n",
> +  PciIoDevice->BusNumber, PciIoDevice->DeviceNumber,
> PciIoDevice->FunctionNumber,
> +  Command
> +  ));
> +  }
> +}
> +  }
> +}
> +
> +/**
> +  Exit Boot Services Event notification handler.
> +
> +  Disable Bus Master on any that were enabled during BDS.
> +
> +  @param[in]  Event Event whose notification function is being invoked.
> +  @param[in]  Context   Pointer to the notification function's context.
> +
> +**/
> +VOID
> +EFIAPI
> +OnExitBootServices (
> +  IN  EFI_EVENT Event,
> +  IN  VOID  *Context
> +  )
> +{
> +  DEBUG ((
> +DEBUG_INFO,
> +"PciBus: Disable Bus Master of all devices...\n"
> +"  Bus# Device# Function#  NewCommand\n"
> +));
> +  DisableBmeOnTree(&mPciDevicePool);
> +}
> +
> +/**
>Initialize the PCI devices pool.
> 
>  **/
> @@ -29,7 +95,27 @@ InitializePciDevicePool (
>VOID
>)
>  {
> +  EFI_EVENT   ExitBootServicesEvent;
> +  EFI_STATUS  Status;
> +
>InitializeListHead (&mPciDevicePool);
> +
> +  //
> +  // DisableBME on ExitBootServices should be synchonized with any IOMMU
> 

Re: [edk2] [PATCH 1/1] EmbeddedPkg: Implement NorFlashLib

[Marcin Wojtas]

Hi Leif,

2017-10-31 8:58 GMT+01:00 Leif Lindholm :
> On Mon, Oct 30, 2017 at 09:30:25PM +0100, Marcin Wojtas wrote:
>> The SPI NOR flash drivers which base on ArmPlatformPkg's
>> NorFlashDxe usually make use of static declarations of the
>> flash instances with their type and parameters. As a result
>> it implies hardcoding the exact way flash handling, not to
>> mention the code does not look very nice. Much better solution
>> would be obtaining the flash ID and hence its description
>> in runtime.
>>
>> Because JEDEC compliant SPI NOR devices allow to obtain their ID
>> with READ_ID command (0x9f), implement a NorFlashLib that gives
>> access to the NOR flash data, such as name, page size, sector
>> (block) size and others, of more than 50 different models.
>> The new library user should pass an output array issuing
>> READ_ID command to the GetNorFlashInfo () routine - if the
>> match is found, an allocated (optionally for RT) pool with
>> the flash description will be returned.
>>
>> Contributed-under: TianoCore Contribution Agreement 1.1
>> Signed-off-by: Marcin Wojtas 
>> ---
>>  EmbeddedPkg/EmbeddedPkg.dec |   1 +
>>  EmbeddedPkg/Include/Library/NorFlashInfoLib.h   |  84 
>>  EmbeddedPkg/Library/NorFlashInfoLib/NorFlashInfoLib.c   | 225 
>> 
>>  EmbeddedPkg/Library/NorFlashInfoLib/NorFlashInfoLib.inf |  34 +++
>>  4 files changed, 344 insertions(+)
>>
>> diff --git a/EmbeddedPkg/EmbeddedPkg.dec b/EmbeddedPkg/EmbeddedPkg.dec
>> index 52482af..aa551ab 100644
>> --- a/EmbeddedPkg/EmbeddedPkg.dec
>> +++ b/EmbeddedPkg/EmbeddedPkg.dec
>> @@ -45,6 +45,7 @@
>>EblNetworkLib|Include/Library/EblNetworkLib.h
>>GdbSerialLib|Include/Library/GdbSerialLib.h
>>DebugAgentTimerLib|Include/Library/DebugAgentTimerLib.h
>> +  NorFlashInfoLib|Include/Library/NorFlashInfoLib.h
>>
>>DtPlatformDtbLoaderLib|Include/Library/DtPlatformDtbLoaderLib.h
>>
>> diff --git a/EmbeddedPkg/Include/Library/NorFlashInfoLib.h 
>> b/EmbeddedPkg/Include/Library/NorFlashInfoLib.h
>> new file mode 100644
>> index 000..ae0e45f
>> --- /dev/null
>> +++ b/EmbeddedPkg/Include/Library/NorFlashInfoLib.h
>> @@ -0,0 +1,84 @@
>> +/** @file
>> +*
>> +*  Copyright (c) 2017 Marvell International Ltd.
>> +*
>> +*  This program and the accompanying materials
>> +*  are licensed and made available under the terms and conditions of the 
>> BSD License
>> +*  which accompanies this distribution.  The full text of the license may 
>> be found at
>> +*  http://opensource.org/licenses/bsd-license.php
>> +*
>> +*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
>> +*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR 
>> IMPLIED.
>> +*
>> +**/
>> +
>> +#ifndef __NOR_FLASH_ID_LIB_H__
>> +#define __NOR_FLASH_ID_LIB_H__
>> +
>> +#include 
>> +
>> +#define NOR_FLASH_MAX_ID_LEN6
>> +
>> +typedef struct {
>> +  /* Device name */
>> +  UINT16 *Name;
>> +
>> +  /*
>> +   * JEDEC ID
>> +   */
>> +  UINT8  Id[NOR_FLASH_MAX_ID_LEN];
>> +  UINT8  IdLen;
>> +
>> +  UINT16 PageSize;
>> +
>> +  /*
>> +   * Below parameters can be referred as BlockSize
>> +   * and BlockCount, when treating the NorFlash as
>> +   * block device.
>> +   */
>> +  UINT32 SectorSize;
>> +  UINT32 SectorCount;
>> +
>> +  UINT16 Flags;
>> +#define NF_ERASE_4K  1 << 0  /* Use 4096B erase blocks and CMD_ERASE_4K 
>> */
>> +#define NF_WRITE_FSR 1 << 1  /* Use flag status register for write */
>> +#define NF_4B_ADDR   1 << 2  /* Use 4B addressing */
>
> I think these should keep a NOR_FLASH_ prefix, like the rest of the file.
>
>> +} NOR_FLASH_INFO;
>> +
>> +/**
>> +  Return a pool allocated copy of the NOR flash .
>> +
>> +  @param[in]   Id Pointer to an array with JEDEC ID 
>> obtained
>> +  from the NOR flash with READ_ID 
>> command
>> +  (0x9f)
>> +  @param[in out]   FlashInfo  Pointer to NOR flash information 
>> structure
>> +  @param[in]   AllocateForRuntime A flag specifying a type of a copy 
>> pool
>> +  allocation (TRUE for runtime, FALSE 
>> for
>> +  normal)
>> +
>> +  @retval   EFI_SUCCESS   Operation completed successfully
>> +  @retval   EFI_NOT_FOUND No matching entry in NOR ID table 
>> found
>> +  @retval   EFI_OUT_OF_RESOURCES  No pool memory available
>> +
>> +**/
>> +EFI_STATUS
>> +EFIAPI
>> +GetNorFlashInfo (
>
> NorFlashGetInfo?
>
>> +  IN UINT8*Id,
>> +  IN OUT NOR_FLASH_INFO  **FlashInfo,
>> +  IN BOOLEAN   AllocateForRuntime
>> +  );
>> +
>> +/**
>> +  Print NOR flash information basing on data stored in
>> +  the NOR_FLASH_INFO structure.
>> +
>> +  @param[in]   FlashInfo  Pointer to NOR flash information 
>> structure
>> +
>> +**/
>> +VOID
>> +EFIAPI
>> +PrintNorFlashInfo (
>
> NorFlashPrintInfo?
>
>

Re: [edk2] [PATCH 1/1] EmbeddedPkg: Implement NorFlashLib

[Leif Lindholm]

On Mon, Oct 30, 2017 at 09:30:25PM +0100, Marcin Wojtas wrote:
> The SPI NOR flash drivers which base on ArmPlatformPkg's
> NorFlashDxe usually make use of static declarations of the
> flash instances with their type and parameters. As a result
> it implies hardcoding the exact way flash handling, not to
> mention the code does not look very nice. Much better solution
> would be obtaining the flash ID and hence its description
> in runtime.
> 
> Because JEDEC compliant SPI NOR devices allow to obtain their ID
> with READ_ID command (0x9f), implement a NorFlashLib that gives
> access to the NOR flash data, such as name, page size, sector
> (block) size and others, of more than 50 different models.
> The new library user should pass an output array issuing
> READ_ID command to the GetNorFlashInfo () routine - if the
> match is found, an allocated (optionally for RT) pool with
> the flash description will be returned.
> 
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Marcin Wojtas 
> ---
>  EmbeddedPkg/EmbeddedPkg.dec |   1 +
>  EmbeddedPkg/Include/Library/NorFlashInfoLib.h   |  84 
>  EmbeddedPkg/Library/NorFlashInfoLib/NorFlashInfoLib.c   | 225 
> 
>  EmbeddedPkg/Library/NorFlashInfoLib/NorFlashInfoLib.inf |  34 +++
>  4 files changed, 344 insertions(+)
> 
> diff --git a/EmbeddedPkg/EmbeddedPkg.dec b/EmbeddedPkg/EmbeddedPkg.dec
> index 52482af..aa551ab 100644
> --- a/EmbeddedPkg/EmbeddedPkg.dec
> +++ b/EmbeddedPkg/EmbeddedPkg.dec
> @@ -45,6 +45,7 @@
>EblNetworkLib|Include/Library/EblNetworkLib.h
>GdbSerialLib|Include/Library/GdbSerialLib.h
>DebugAgentTimerLib|Include/Library/DebugAgentTimerLib.h
> +  NorFlashInfoLib|Include/Library/NorFlashInfoLib.h
>  
>DtPlatformDtbLoaderLib|Include/Library/DtPlatformDtbLoaderLib.h
>  
> diff --git a/EmbeddedPkg/Include/Library/NorFlashInfoLib.h 
> b/EmbeddedPkg/Include/Library/NorFlashInfoLib.h
> new file mode 100644
> index 000..ae0e45f
> --- /dev/null
> +++ b/EmbeddedPkg/Include/Library/NorFlashInfoLib.h
> @@ -0,0 +1,84 @@
> +/** @file
> +*
> +*  Copyright (c) 2017 Marvell International Ltd.
> +*
> +*  This program and the accompanying materials
> +*  are licensed and made available under the terms and conditions of the BSD 
> License
> +*  which accompanies this distribution.  The full text of the license may be 
> found at
> +*  http://opensource.org/licenses/bsd-license.php
> +*
> +*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR 
> IMPLIED.
> +*
> +**/
> +
> +#ifndef __NOR_FLASH_ID_LIB_H__
> +#define __NOR_FLASH_ID_LIB_H__
> +
> +#include 
> +
> +#define NOR_FLASH_MAX_ID_LEN6
> +
> +typedef struct {
> +  /* Device name */
> +  UINT16 *Name;
> +
> +  /*
> +   * JEDEC ID
> +   */
> +  UINT8  Id[NOR_FLASH_MAX_ID_LEN];
> +  UINT8  IdLen;
> +
> +  UINT16 PageSize;
> +
> +  /*
> +   * Below parameters can be referred as BlockSize
> +   * and BlockCount, when treating the NorFlash as
> +   * block device.
> +   */
> +  UINT32 SectorSize;
> +  UINT32 SectorCount;
> +
> +  UINT16 Flags;
> +#define NF_ERASE_4K  1 << 0  /* Use 4096B erase blocks and CMD_ERASE_4K 
> */
> +#define NF_WRITE_FSR 1 << 1  /* Use flag status register for write */
> +#define NF_4B_ADDR   1 << 2  /* Use 4B addressing */

I think these should keep a NOR_FLASH_ prefix, like the rest of the file.

> +} NOR_FLASH_INFO;
> +
> +/**
> +  Return a pool allocated copy of the NOR flash .
> +
> +  @param[in]   Id Pointer to an array with JEDEC ID 
> obtained
> +  from the NOR flash with READ_ID command
> +  (0x9f)
> +  @param[in out]   FlashInfo  Pointer to NOR flash information 
> structure
> +  @param[in]   AllocateForRuntime A flag specifying a type of a copy pool
> +  allocation (TRUE for runtime, FALSE for
> +  normal)
> +
> +  @retval   EFI_SUCCESS   Operation completed successfully
> +  @retval   EFI_NOT_FOUND No matching entry in NOR ID table found
> +  @retval   EFI_OUT_OF_RESOURCES  No pool memory available
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +GetNorFlashInfo (

NorFlashGetInfo?

> +  IN UINT8*Id,
> +  IN OUT NOR_FLASH_INFO  **FlashInfo,
> +  IN BOOLEAN   AllocateForRuntime
> +  );
> +
> +/**
> +  Print NOR flash information basing on data stored in
> +  the NOR_FLASH_INFO structure.
> +
> +  @param[in]   FlashInfo  Pointer to NOR flash information 
> structure
> +
> +**/
> +VOID
> +EFIAPI
> +PrintNorFlashInfo (

NorFlashPrintInfo?

> +  IN NOR_FLASH_INFO  *Info
> +  );
> +#endif
> diff --git a/EmbeddedPkg/Library/NorFlashInfoLib/NorFlashInfoLib.c 
> b/EmbeddedPkg/Library/NorFlashInfoLib/NorFlashInfoLib.c
> new file mode 100644
> index

[edk2] [PATCH] MdeModulePkg/PciBus: Disable BME of all devices when entering RT

[Ruiyu Ni]

The patch assumes IOMMU protections are disabled after PciBus
disables the BMT bit in Command register.
It ensures all DMA transactions are protected by IOMMU.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Michael Turner 
Signed-off-by: Ruiyu Ni 
Cc: Michael D Kinney 
Cc: Jiewen Yao 
---
 MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h   |  2 +
 MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf  |  3 +
 MdeModulePkg/Bus/Pci/PciBusDxe/PciDeviceSupport.c | 86 +++
 3 files changed, 91 insertions(+)

diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h 
b/MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h
index 55eb3a5a80..79b5b71082 100644
--- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h
+++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h
@@ -18,6 +18,8 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER 
EXPRESS OR IMPLIED.
 
 #include 
 
+#include 
+
 #include 
 #include 
 #include 
diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf 
b/MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
index 97608bfcf2..d5b8fab3ca 100644
--- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
+++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
@@ -80,6 +80,9 @@ [LibraryClasses]
   DebugLib
   PeCoffLib
 
+[Guids]
+  gEfiEventExitBootServicesGuid   ## SOMETIMES_CONSUMES ## 
Event
+
 [Protocols]
   gEfiPciHotPlugRequestProtocolGuid   ## SOMETIMES_PRODUCES
   gEfiPciIoProtocolGuid   ## BY_START
diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciDeviceSupport.c 
b/MdeModulePkg/Bus/Pci/PciBusDxe/PciDeviceSupport.c
index 97bb971a59..b5530a13d1 100644
--- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciDeviceSupport.c
+++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciDeviceSupport.c
@@ -21,6 +21,72 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER 
EXPRESS OR IMPLIED.
 LIST_ENTRY  mPciDevicePool;
 
 /**
+ Disable Bus Master Enable bit in all devices in the list.
+
+ @param Devices  A device list.
+**/
+VOID
+DisableBmeOnTree (
+  IN LIST_ENTRY  *Devices
+  )
+{
+  LIST_ENTRY  *Link;
+  PCI_IO_DEVICE   *PciIoDevice;
+  UINT16   Command;
+
+  for ( Link = GetFirstNode (Devices)
+  ; !IsNull (Devices, Link)
+  ; Link = GetNextNode (Devices, Link)
+  ) {
+PciIoDevice = PCI_IO_DEVICE_FROM_LINK (Link);
+//
+// Turn off all children's Bus Master, if any
+//
+DisableBmeOnTree (&PciIoDevice->ChildList);
+
+//
+// If this is a device that supports BME, disable BME on this device.
+//
+if ((PciIoDevice->Supports & EFI_PCI_IO_ATTRIBUTE_BUS_MASTER) != 0) {
+  PCI_READ_COMMAND_REGISTER(PciIoDevice, &Command);
+  if ((Command & EFI_PCI_COMMAND_BUS_MASTER) != 0) {
+Command &= ~EFI_PCI_COMMAND_BUS_MASTER;
+PCI_SET_COMMAND_REGISTER (PciIoDevice, Command);
+DEBUG ((
+  EFI_D_INFO,"  %02x   %02x  %02x %04x\n",
+  PciIoDevice->BusNumber, PciIoDevice->DeviceNumber, 
PciIoDevice->FunctionNumber,
+  Command
+  ));
+  }
+}
+  }
+}
+
+/**
+  Exit Boot Services Event notification handler.
+
+  Disable Bus Master on any that were enabled during BDS.
+
+  @param[in]  Event Event whose notification function is being invoked.
+  @param[in]  Context   Pointer to the notification function's context.
+
+**/
+VOID
+EFIAPI
+OnExitBootServices (
+  IN  EFI_EVENT Event,
+  IN  VOID  *Context
+  )
+{
+  DEBUG ((
+DEBUG_INFO,
+"PciBus: Disable Bus Master of all devices...\n"
+"  Bus# Device# Function#  NewCommand\n"
+));
+  DisableBmeOnTree(&mPciDevicePool);
+}
+
+/**
   Initialize the PCI devices pool.
 
 **/
@@ -29,7 +95,27 @@ InitializePciDevicePool (
   VOID
   )
 {
+  EFI_EVENT   ExitBootServicesEvent;
+  EFI_STATUS  Status;
+
   InitializeListHead (&mPciDevicePool);
+
+  //
+  // DisableBME on ExitBootServices should be synchonized with any IOMMU 
ExitBootServices routine.
+  // DisableBME should be run before the IOMMU protections are disabled.
+  // One way to do this is to ensure that the IOMMU ExitBootServices callback 
runs at TPL_CALLBACK.
+  //
+  Status = gBS->CreateEventEx (
+  EVT_NOTIFY_SIGNAL,
+  TPL_NOTIFY,
+  OnExitBootServices,
+  NULL,
+  &gEfiEventExitBootServicesGuid,
+  &ExitBootServicesEvent
+  );
+  if (EFI_ERROR (Status)) {
+DEBUG ((DEBUG_ERROR, "PciBus: Unable to hook ExitBootServices event - 
%r\n", Status));
+  }
 }
 
 /**
-- 
2.12.2.windows.2

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