[edk2] [PATCH] UefiCpuPkg/SecCore: Wrong Debug Information for SecCore

[Chasel, Chiu]

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1533

When SecCore and PeiCore in different FV, current
implementation still assuming SecCore and PeiCore are in
the same FV.
To fix this issue 2 FVs will be input parameters for
FindAndReportEntryPoints () and SecCore and PeiCore will
be found in each FV and correct debug information will
be reported.

Test: Booted with internal platform successfully.

Cc: Eric Dong 
Cc: Ray Ni 
Cc: Laszlo Ersek 
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Chasel Chiu 
---
 UefiCpuPkg/SecCore/FindPeiCore.c | 60 
++--
 UefiCpuPkg/SecCore/SecMain.c | 10 --
 UefiCpuPkg/SecCore/SecMain.h |  8 +---
 3 files changed, 43 insertions(+), 35 deletions(-)

diff --git a/UefiCpuPkg/SecCore/FindPeiCore.c b/UefiCpuPkg/SecCore/FindPeiCore.c
index bb9c434d1e..6f2046ad95 100644
--- a/UefiCpuPkg/SecCore/FindPeiCore.c
+++ b/UefiCpuPkg/SecCore/FindPeiCore.c
@@ -1,7 +1,7 @@
 /** @file
   Locate the entry point for the PEI Core
 
-  Copyright (c) 2008 - 2011, Intel Corporation. All rights reserved.
+  Copyright (c) 2008 - 2019, Intel Corporation. All rights reserved.
   This program and the accompanying materials
   are licensed and made available under the terms and conditions of the BSD 
License
   which accompanies this distribution.  The full text of the license may be 
found at
@@ -19,17 +19,17 @@
 /**
   Find core image base.
 
-  @param   BootFirmwareVolumePtrPoint to the boot firmware volume.
-  @param   SecCoreImageBase The base address of the SEC core image.
-  @param   PeiCoreImageBase The base address of the PEI core image.
+  @param   FirmwareVolumePtrPoint to the firmware volume for finding 
core image.
+  @param   FileType The FileType for searching, either SecCore 
or PeiCore.
+  @param   CoreImageBaseThe base address of the core image.
 
 **/
 EFI_STATUS
 EFIAPI
 FindImageBase (
-  IN  EFI_FIRMWARE_VOLUME_HEADER   *BootFirmwareVolumePtr,
-  OUT EFI_PHYSICAL_ADDRESS *SecCoreImageBase,
-  OUT EFI_PHYSICAL_ADDRESS *PeiCoreImageBase
+  IN  EFI_FIRMWARE_VOLUME_HEADER   *FirmwareVolumePtr,
+  IN  EFI_FV_FILETYPE  FileType,
+  OUT EFI_PHYSICAL_ADDRESS *CoreImageBase
   )
 {
   EFI_PHYSICAL_ADDRESSCurrentAddress;
@@ -40,16 +40,15 @@ FindImageBase (
   EFI_COMMON_SECTION_HEADER   *Section;
   EFI_PHYSICAL_ADDRESSEndOfSection;
 
-  *SecCoreImageBase = 0;
-  *PeiCoreImageBase = 0;
+  *CoreImageBase = 0;
 
-  CurrentAddress = (EFI_PHYSICAL_ADDRESS)(UINTN) BootFirmwareVolumePtr;
-  EndOfFirmwareVolume = CurrentAddress + BootFirmwareVolumePtr->FvLength;
+  CurrentAddress = (EFI_PHYSICAL_ADDRESS)(UINTN) FirmwareVolumePtr;
+  EndOfFirmwareVolume = CurrentAddress + FirmwareVolumePtr->FvLength;
 
   //
   // Loop through the FFS files in the Boot Firmware Volume
   //
-  for (EndOfFile = CurrentAddress + BootFirmwareVolumePtr->HeaderLength; ; ) {
+  for (EndOfFile = CurrentAddress + FirmwareVolumePtr->HeaderLength; ; ) {
 
 CurrentAddress = (EndOfFile + 7) & 0xfff8ULL;
 if (CurrentAddress > EndOfFirmwareVolume) {
@@ -75,10 +74,9 @@ FindImageBase (
 }
 
 //
-// Look for SEC Core / PEI Core files
+// Look for particular Core file (either SEC Core or PEI Core)
 //
-if (File->Type != EFI_FV_FILETYPE_SECURITY_CORE &&
-File->Type != EFI_FV_FILETYPE_PEI_CORE) {
+if (File->Type != FileType) {
   continue;
 }
 
@@ -115,17 +113,11 @@ FindImageBase (
   // Look for executable sections
   //
   if (Section->Type == EFI_SECTION_PE32 || Section->Type == 
EFI_SECTION_TE) {
-if (File->Type == EFI_FV_FILETYPE_SECURITY_CORE) {
+if (File->Type == FileType) {
   if (IS_SECTION2 (Section)) {
-*SecCoreImageBase = (PHYSICAL_ADDRESS) (UINTN) ((UINT8 *) Section 
+ sizeof (EFI_COMMON_SECTION_HEADER2));
+*CoreImageBase = (PHYSICAL_ADDRESS) (UINTN) ((UINT8 *) Section + 
sizeof (EFI_COMMON_SECTION_HEADER2));
   } else {
-*SecCoreImageBase = (PHYSICAL_ADDRESS) (UINTN) ((UINT8 *) Section 
+ sizeof (EFI_COMMON_SECTION_HEADER));
-  }
-} else {
-  if (IS_SECTION2 (Section)) {
-*PeiCoreImageBase = (PHYSICAL_ADDRESS) (UINTN) ((UINT8 *) Section 
+ sizeof (EFI_COMMON_SECTION_HEADER2));
-  } else {
-*PeiCoreImageBase = (PHYSICAL_ADDRESS) (UINTN) ((UINT8 *) Section 
+ sizeof (EFI_COMMON_SECTION_HEADER));
+*CoreImageBase = (PHYSICAL_ADDRESS) (UINTN) ((UINT8 *) Section + 
sizeof (EFI_COMMON_SECTION_HEADER));
   }
 }
 break;
@@ -133,9 +125,9 @@ FindImageBase (
 }
 
 //
-// Both SEC Core and PEI Core images found
+// Either SEC Core or PEI Core images found
 //
-if (*SecCoreImageBase != 0 &&

[edk2] [PATCH v3 2/3] MdeModulePkg/PeiMain: Support EFI_PEI_CORE_FV_LOCATION_PPI

[Chasel, Chiu]

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1524

When shadowing PeiCore the EFI_PEI_CORE_FV_LOCATION_PPI
should be checked to see if PeiCore not in BFV, otherwise
just shadowing PeiCore from BFV.

Test: Verified on internal platform and booting successfully.

Cc: Jian J Wang 
Cc: Hao Wu 
Cc: Ray Ni 
Cc: Star Zeng 
Cc: Liming Gao 
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Chasel Chiu 
---
 MdeModulePkg/Core/Pei/PeiMain/PeiMain.c | 53 
-
 MdeModulePkg/Core/Pei/PeiMain.h |  3 ++-
 MdeModulePkg/Core/Pei/PeiMain.inf   |  3 ++-
 3 files changed, 44 insertions(+), 15 deletions(-)

diff --git a/MdeModulePkg/Core/Pei/PeiMain/PeiMain.c 
b/MdeModulePkg/Core/Pei/PeiMain/PeiMain.c
index 4da80a8222..a7da90e149 100644
--- a/MdeModulePkg/Core/Pei/PeiMain/PeiMain.c
+++ b/MdeModulePkg/Core/Pei/PeiMain/PeiMain.c
@@ -1,7 +1,7 @@
 /** @file
   Pei Core Main Entry Point
 
-Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.
 This program and the accompanying materials
 are licensed and made available under the terms and conditions of the BSD 
License
 which accompanies this distribution.  The full text of the license may be 
found at
@@ -80,22 +80,49 @@ ShadowPeiCore (
   IN PEI_CORE_INSTANCE  *PrivateData
   )
 {
-  EFI_PEI_FILE_HANDLE  PeiCoreFileHandle;
-  EFI_PHYSICAL_ADDRESS EntryPoint;
-  EFI_STATUS   Status;
-  UINT32   AuthenticationState;
+  EFI_PEI_FILE_HANDLE  PeiCoreFileHandle;
+  EFI_PHYSICAL_ADDRESS EntryPoint;
+  EFI_STATUS   Status;
+  UINT32   AuthenticationState;
+  UINTNIndex;
+  EFI_PEI_CORE_FV_LOCATION_PPI *PeiCoreFvLocationPpi;
+  UINTNPeiCoreFvIndex;
 
   PeiCoreFileHandle = NULL;
-
   //
-  // Find the PEI Core in the BFV
+  // Default PeiCore is in BFV
+  //
+  PeiCoreFvIndex = 0;
+  //
+  // Find the PEI Core either from EFI_PEI_CORE_FV_LOCATION_PPI indicated FV 
or BFV
+  //
+  Status = PeiServicesLocatePpi (
+ &gEfiPeiCoreFvLocationPpiGuid,
+ 0,
+ NULL,
+ (VOID **) &PeiCoreFvLocationPpi
+ );
+  if (!EFI_ERROR (Status) && (PeiCoreFvLocationPpi->PeiCoreFvLocation != 
NULL)) {
+//
+// If PeiCoreFvLocation present, the PEI Core should be found from 
indicated FV
+//
+for (Index = 0; Index < PrivateData->FvCount; Index ++) {
+  if (PrivateData->Fv[Index].FvHandle == 
PeiCoreFvLocationPpi->PeiCoreFvLocation) {
+PeiCoreFvIndex = Index;
+break;
+  }
+}
+ASSERT (Index < PrivateData->FvCount);
+  }
+  //
+  // Find PEI Core from the given FV index
   //
-  Status = PrivateData->Fv[0].FvPpi->FindFileByType (
-   PrivateData->Fv[0].FvPpi,
-   EFI_FV_FILETYPE_PEI_CORE,
-   PrivateData->Fv[0].FvHandle,
-   &PeiCoreFileHandle
-   );
+  Status = PrivateData->Fv[PeiCoreFvIndex].FvPpi->FindFileByType (
+
PrivateData->Fv[PeiCoreFvIndex].FvPpi,
+EFI_FV_FILETYPE_PEI_CORE,
+
PrivateData->Fv[PeiCoreFvIndex].FvHandle,
+&PeiCoreFileHandle
+);
   ASSERT_EFI_ERROR (Status);
 
   //
diff --git a/MdeModulePkg/Core/Pei/PeiMain.h b/MdeModulePkg/Core/Pei/PeiMain.h
index 322e7cd845..a61da73fd8 100644
--- a/MdeModulePkg/Core/Pei/PeiMain.h
+++ b/MdeModulePkg/Core/Pei/PeiMain.h
@@ -1,7 +1,7 @@
 /** @file
   Definition of Pei Core Structures and Services
 
-Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.
 This program and the accompanying materials
 are licensed and made available under the terms and conditions of the BSD 
License
 which accompanies this distribution.  The full text of the license may be 
found at
@@ -31,6 +31,7 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER 
EXPRESS OR IMPLIED.
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
diff --git a/MdeModulePkg/Core/Pei/PeiMain.inf 
b/MdeModulePkg/Core/Pei/PeiMain.inf
index 140cb1..5bab2aab8c 100644
--- a/MdeModulePkg/Core/Pei/PeiMain.inf
+++ b/MdeModulePkg/Core/Pei/PeiMain.inf
@@ -6,7 +6,7 @@
 # 2) Dispatch PEIM from discovered FV.
 # 3) Handoff control to DxeIpl to load DXE core and enter DXE phase.
 #
-# Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+# Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved

[edk2] [PATCH v3 0/3] Support EFI_PEI_CORE_FV_LOCATION_PPI

[Chasel, Chiu]

PI spec 1.7 section 6.3.9 has defined a PPI to support the scenario
that PEI Foundation not in BFV. EFI_PEI_CORE_FV_LOCATION_PPI reports
the FV which contains PEI Foundation and should be passed by SEC as
part of PPI list. Otherwise PEI Foundation shall assume that it
resides in BFV.

Patch1: Add EFI_PEI_CORE_FV_LOCATION_PPI definition.
Patch2: Support PeiCore not in BFV scenario when shadowing.
Patch3: SecCore to find PeiCore from either non-BFV or BFV.

Cc: Michael D Kinney 
Cc: Liming Gao 
Cc: Jian J Wang 
Cc: Hao Wu 
Cc: Ray Ni 
Cc: Star Zeng 
Cc: Eric Dong 
Cc: Laszlo Ersek 

Chasel, Chiu (3):
  MdePkg: Support EFI_PEI_CORE_FV_LOCATION_PPI
  MdeModulePkg/PeiMain: Support EFI_PEI_CORE_FV_LOCATION_PPI
  UefiCpuPkg/SecCore: Support EFI_PEI_CORE_FV_LOCATION_PPI

 MdeModulePkg/Core/Pei/PeiMain/PeiMain.c | 53 
-
 UefiCpuPkg/SecCore/SecMain.c| 35 
+--
 MdeModulePkg/Core/Pei/PeiMain.h |  3 ++-
 MdeModulePkg/Core/Pei/PeiMain.inf   |  3 ++-
 MdePkg/Include/Ppi/PeiCoreFvLocation.h  | 48 

 MdePkg/MdePkg.dec   | 11 +--
 UefiCpuPkg/SecCore/SecCore.inf  |  3 ++-
 UefiCpuPkg/SecCore/SecMain.h|  3 ++-
 8 files changed, 134 insertions(+), 25 deletions(-)
 create mode 100644 MdePkg/Include/Ppi/PeiCoreFvLocation.h

-- 
2.13.3.windows.1

___
edk2-devel mailing list
edk2-devel@lists.01.org
https://lists.01.org/mailman/listinfo/edk2-devel

[edk2] [PATCH v3 1/3] MdePkg: Support EFI_PEI_CORE_FV_LOCATION_PPI

[Chasel, Chiu]

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1524

Add EFI_PEI_CORE_FV_LOCATION_PPI definition basing on
PI spec 1.7, Section 6.3.9.
This PPI can support the secnario that PEI Foundation
not in BFV.

Cc: Michael D Kinney 
Cc: Liming Gao 
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Chasel Chiu 
---
 MdePkg/Include/Ppi/PeiCoreFvLocation.h | 48 

 MdePkg/MdePkg.dec  | 11 +--
 2 files changed, 57 insertions(+), 2 deletions(-)

diff --git a/MdePkg/Include/Ppi/PeiCoreFvLocation.h 
b/MdePkg/Include/Ppi/PeiCoreFvLocation.h
new file mode 100644
index 00..3bea6819ec
--- /dev/null
+++ b/MdePkg/Include/Ppi/PeiCoreFvLocation.h
@@ -0,0 +1,48 @@
+/** @file
+  Header file for Pei Core FV Location PPI.
+
+  This PPI contains a pointer to the firmware volume which contains the PEI 
Foundation.
+  If the PEI Foundation does not reside in the BFV, then SEC must pass this 
PPI as a part
+  of the PPI list provided to the PEI Foundation Entry Point, otherwise the 
PEI Foundation
+  shall assume that it resides within the BFV.
+
+  Copyright (c) 2019, Intel Corporation. All rights reserved.
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD 
License
+  which accompanies this distribution.  The full text of the license may be 
found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+  @par Revision Reference:
+  This PPI is defined in UEFI Platform Initialization Specification 1.7 Volume 
1:
+  Standards
+
+**/
+
+
+#ifndef _EFI_PEI_CORE_FV_LOCATION_H_
+#define _EFI_PEI_CORE_FV_LOCATION_H_
+
+///
+/// Global ID for EFI_PEI_CORE_FV_LOCATION_PPI
+///
+#define EFI_PEI_CORE_FV_LOCATION_GUID \
+  { \
+0x52888eae, 0x5b10, 0x47d0, {0xa8, 0x7f, 0xb8, 0x22, 0xab, 0xa0, 0xca, 
0xf4 } \
+  }
+
+///
+/// This PPI provides location of EFI PeiCoreFv.
+///
+typedef struct {
+  ///
+  /// Pointer to the first byte of the firmware volume which contains the PEI 
Foundation.
+  ///
+  VOID*PeiCoreFvLocation;
+} EFI_PEI_CORE_FV_LOCATION_PPI;
+
+extern EFI_GUID gEfiPeiCoreFvLocationPpiGuid;
+
+#endif // _EFI_PEI_CORE_FV_LOCATION_H_
diff --git a/MdePkg/MdePkg.dec b/MdePkg/MdePkg.dec
index a485408310..c859b4a511 100644
--- a/MdePkg/MdePkg.dec
+++ b/MdePkg/MdePkg.dec
@@ -2,9 +2,9 @@
 # This Package provides all definitions, library classes and libraries 
instances.
 #
 # It also provides the definitions(including PPIs/PROTOCOLs/GUIDs) of
-# EFI1.10/UEFI2.7/PI1.6 and some Industry Standards.
+# EFI1.10/UEFI2.7/PI1.7 and some Industry Standards.
 #
-# Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.
+# Copyright (c) 2007 - 2019, Intel Corporation. All rights reserved.
 # Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
 # (C) Copyright 2016 Hewlett Packard Enterprise Development LP
 #
@@ -929,6 +929,13 @@
   ## Include/Ppi/SecHobData.h
   gEfiSecHobDataPpiGuid = { 0x3ebdaf20, 0x6667, 0x40d8, {0xb4, 0xee, 0xf5, 
0x99, 0x9a, 0xc1, 0xb7, 0x1f } }
 
+  #
+  # PPIs defined in PI 1.7.
+  #
+
+  ## Include/Ppi/PeiCoreFvLocation.h
+  gEfiPeiCoreFvLocationPpiGuid   = { 0x52888eae, 0x5b10, 0x47d0, { 0xa8, 0x7f, 
0xb8, 0x22, 0xab, 0xa0, 0xca, 0xf4 }}
+
 [Protocols]
   ## Include/Protocol/Pcd.h
   gPcdProtocolGuid   = { 0x11B34006, 0xD85B, 0x4D0A, { 0xA2, 0x90, 
0xD5, 0xA5, 0x71, 0x31, 0x0E, 0xF7 }}
-- 
2.13.3.windows.1

___
edk2-devel mailing list
edk2-devel@lists.01.org
https://lists.01.org/mailman/listinfo/edk2-devel

[edk2] [PATCH v3 3/3] UefiCpuPkg/SecCore: Support EFI_PEI_CORE_FV_LOCATION_PPI

[Chasel, Chiu]

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1524

EFI_PEI_CORE_FV_LOCATION_PPI may be passed by platform
when PeiCore not in BFV so SecCore has to search PeiCore
either from the FV location provided by
EFI_PEI_CORE_FV_LOCATION_PPI or from BFV.

Test: Verified on internal platform and booting successfully.

Cc: Eric Dong 
Cc: Ray Ni 
Cc: Laszlo Ersek 
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Chasel Chiu 
---
 UefiCpuPkg/SecCore/SecMain.c   | 35 +--
 UefiCpuPkg/SecCore/SecCore.inf |  3 ++-
 UefiCpuPkg/SecCore/SecMain.h   |  3 ++-
 3 files changed, 33 insertions(+), 8 deletions(-)

diff --git a/UefiCpuPkg/SecCore/SecMain.c b/UefiCpuPkg/SecCore/SecMain.c
index b24e190617..d84eb675f5 100644
--- a/UefiCpuPkg/SecCore/SecMain.c
+++ b/UefiCpuPkg/SecCore/SecMain.c
@@ -1,7 +1,7 @@
 /** @file
   C functions in SEC
 
-  Copyright (c) 2008 - 2018, Intel Corporation. All rights reserved.
+  Copyright (c) 2008 - 2019, Intel Corporation. All rights reserved.
   This program and the accompanying materials
   are licensed and made available under the terms and conditions of the BSD 
License
   which accompanies this distribution.  The full text of the license may be 
found at
@@ -232,22 +232,45 @@ SecStartupPhase2(
   EFI_PEI_PPI_DESCRIPTOR  *AllSecPpiList;
   EFI_PEI_CORE_ENTRY_POINTPeiCoreEntryPoint;
 
+  PeiCoreEntryPoint = NULL;
   SecCoreData   = (EFI_SEC_PEI_HAND_OFF *) Context;
   AllSecPpiList = (EFI_PEI_PPI_DESCRIPTOR *) SecCoreData->PeiTemporaryRamBase;
+
   //
   // Find Pei Core entry point. It will report SEC and Pei Core debug 
information if remote debug
   // is enabled.
   //
-  FindAndReportEntryPoints ((EFI_FIRMWARE_VOLUME_HEADER *) 
SecCoreData->BootFirmwareVolumeBase, &PeiCoreEntryPoint);
-  if (PeiCoreEntryPoint == NULL)
-  {
-CpuDeadLoop ();
+  PpiList = SecPlatformMain (SecCoreData);
+  if (PpiList != NULL) {
+for (Index = 0;
+  (PpiList[Index].Flags & EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST) != 
EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST;
+  Index++) {
+  if (CompareGuid (PpiList[Index].Guid, &gEfiPeiCoreFvLocationPpiGuid) && 
(((EFI_PEI_CORE_FV_LOCATION_PPI *) PpiList[Index].Ppi)->PeiCoreFvLocation != 
0)) {
+FindAndReportEntryPoints ((EFI_FIRMWARE_VOLUME_HEADER *) 
((EFI_PEI_CORE_FV_LOCATION_PPI *) PpiList[Index].Ppi)->PeiCoreFvLocation, 
&PeiCoreEntryPoint);
+if (PeiCoreEntryPoint != NULL) {
+  break;
+} else {
+  //
+  // PeiCore not found
+  //
+  CpuDeadLoop ();
+}
+  }
+}
+  }
+  //
+  // If EFI_PEI_CORE_FV_LOCATION_PPI not found, try to locate PeiCore from BFV.
+  //
+  if (PeiCoreEntryPoint == NULL) {
+FindAndReportEntryPoints ((EFI_FIRMWARE_VOLUME_HEADER *) 
SecCoreData->BootFirmwareVolumeBase, &PeiCoreEntryPoint);
+if (PeiCoreEntryPoint == NULL) {
+  CpuDeadLoop ();
+}
   }
 
   //
   // Perform platform specific initialization before entering PeiCore.
   //
-  PpiList = SecPlatformMain (SecCoreData);
   if (PpiList != NULL) {
 //
 // Remove the terminal flag from the terminal PPI
diff --git a/UefiCpuPkg/SecCore/SecCore.inf b/UefiCpuPkg/SecCore/SecCore.inf
index 442f663911..fc1485b5cb 100644
--- a/UefiCpuPkg/SecCore/SecCore.inf
+++ b/UefiCpuPkg/SecCore/SecCore.inf
@@ -7,7 +7,7 @@
 #  protected mode, setup flat memory model, enable temporary memory and
 #  call into SecStartup().
 #
-#  Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+#  Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.
 #  This program and the accompanying materials
 #  are licensed and made available under the terms and conditions of the BSD 
License
 #  which accompanies this distribution.  The full text of the license may be 
found at
@@ -73,6 +73,7 @@
   ## NOTIFY
   ## SOMETIMES_CONSUMES
   gPeiSecPerformancePpiGuid
+  gEfiPeiCoreFvLocationPpiGuid
 
 [Guids]
   ## SOMETIMES_PRODUCES   ## HOB
diff --git a/UefiCpuPkg/SecCore/SecMain.h b/UefiCpuPkg/SecCore/SecMain.h
index 83244af119..80045d34f4 100644
--- a/UefiCpuPkg/SecCore/SecMain.h
+++ b/UefiCpuPkg/SecCore/SecMain.h
@@ -1,7 +1,7 @@
 /** @file
   Master header file for SecCore.
 
-  Copyright (c) 2008 - 2018, Intel Corporation. All rights reserved.
+  Copyright (c) 2008 - 2019, Intel Corporation. All rights reserved.
   This program and the accompanying materials
   are licensed and made available under the terms and conditions of the BSD 
License
   which accompanies this distribution.  The full text of the license may be 
found at
@@ -20,6 +20,7 @@
 #include 
 #include 
 #include 
+#include 
 
 #include 
 
-- 
2.13.3.windows.1

___
edk2-devel mailing list
edk2-devel@lists.01.org
https://lists.01.org/mailman/listinfo/edk2-devel

[edk2] [PATCH v2 3/3] UefiCpuPkg/SecCore: Support EFI_PEI_CORE_FV_LOCATION_PPI

[Chasel, Chiu]

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1524

EFI_PEI_CORE_FV_LOCATION_PPI may be passed by platform
when PeiCore not in BFV so SecCore has to search PeiCore
either from the FV location provided by
EFI_PEI_CORE_FV_LOCATION_PPI or from BFV.

Test: Verified on internal platform and booting successfully.

Cc: Eric Dong 
Cc: Ray Ni 
Cc: Laszlo Ersek 
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Chasel Chiu 
---
 UefiCpuPkg/SecCore/SecMain.c   | 35 +--
 UefiCpuPkg/SecCore/SecCore.inf |  3 ++-
 UefiCpuPkg/SecCore/SecMain.h   |  3 ++-
 3 files changed, 33 insertions(+), 8 deletions(-)

diff --git a/UefiCpuPkg/SecCore/SecMain.c b/UefiCpuPkg/SecCore/SecMain.c
index b24e190617..b99072599d 100644
--- a/UefiCpuPkg/SecCore/SecMain.c
+++ b/UefiCpuPkg/SecCore/SecMain.c
@@ -1,7 +1,7 @@
 /** @file
   C functions in SEC
 
-  Copyright (c) 2008 - 2018, Intel Corporation. All rights reserved.
+  Copyright (c) 2008 - 2019, Intel Corporation. All rights reserved.
   This program and the accompanying materials
   are licensed and made available under the terms and conditions of the BSD 
License
   which accompanies this distribution.  The full text of the license may be 
found at
@@ -228,26 +228,49 @@ SecStartupPhase2(
 {
   EFI_SEC_PEI_HAND_OFF*SecCoreData;
   EFI_PEI_PPI_DESCRIPTOR  *PpiList;
+  EFI_PEI_PPI_DESCRIPTOR  *PpiListTmp;
   UINT32  Index;
   EFI_PEI_PPI_DESCRIPTOR  *AllSecPpiList;
   EFI_PEI_CORE_ENTRY_POINTPeiCoreEntryPoint;
 
+  PeiCoreEntryPoint = NULL;
   SecCoreData   = (EFI_SEC_PEI_HAND_OFF *) Context;
   AllSecPpiList = (EFI_PEI_PPI_DESCRIPTOR *) SecCoreData->PeiTemporaryRamBase;
+
   //
   // Find Pei Core entry point. It will report SEC and Pei Core debug 
information if remote debug
   // is enabled.
   //
-  FindAndReportEntryPoints ((EFI_FIRMWARE_VOLUME_HEADER *) 
SecCoreData->BootFirmwareVolumeBase, &PeiCoreEntryPoint);
-  if (PeiCoreEntryPoint == NULL)
-  {
-CpuDeadLoop ();
+  PpiList = SecPlatformMain (SecCoreData);
+  PpiListTmp = PpiList;
+  for (;;) {
+if (CompareGuid (PpiListTmp->Guid, &gEfiPeiCoreFvLocationPpiGuid) && 
(((EFI_PEI_CORE_FV_LOCATION_PPI *) PpiListTmp->Ppi)->PeiCoreFvLocation != 0)) {
+  FindAndReportEntryPoints ((EFI_FIRMWARE_VOLUME_HEADER *) 
((EFI_PEI_CORE_FV_LOCATION_PPI *) PpiListTmp->Ppi)->PeiCoreFvLocation, 
&PeiCoreEntryPoint);
+  if (PeiCoreEntryPoint != NULL) {
+break;
+  }
+}
+if ((PpiListTmp->Flags & EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST) == 
EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST) {
+  //
+  // Continue until the end of the PPI List.
+  //
+  break;
+}
+PpiListTmp++;
+  }
+  //
+  // If EFI_PEI_CORE_FV_LOCATION_PPI not found or no PeiCore found by the 
pointer in provided PPI, try to locate PeiCore from BFV.
+  //
+  if (PeiCoreEntryPoint == NULL) {
+FindAndReportEntryPoints ((EFI_FIRMWARE_VOLUME_HEADER *) 
SecCoreData->BootFirmwareVolumeBase, &PeiCoreEntryPoint);
+if (PeiCoreEntryPoint == NULL) {
+  CpuDeadLoop ();
+}
   }
 
   //
   // Perform platform specific initialization before entering PeiCore.
   //
-  PpiList = SecPlatformMain (SecCoreData);
   if (PpiList != NULL) {
 //
 // Remove the terminal flag from the terminal PPI
diff --git a/UefiCpuPkg/SecCore/SecCore.inf b/UefiCpuPkg/SecCore/SecCore.inf
index 442f663911..fc1485b5cb 100644
--- a/UefiCpuPkg/SecCore/SecCore.inf
+++ b/UefiCpuPkg/SecCore/SecCore.inf
@@ -7,7 +7,7 @@
 #  protected mode, setup flat memory model, enable temporary memory and
 #  call into SecStartup().
 #
-#  Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+#  Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.
 #  This program and the accompanying materials
 #  are licensed and made available under the terms and conditions of the BSD 
License
 #  which accompanies this distribution.  The full text of the license may be 
found at
@@ -73,6 +73,7 @@
   ## NOTIFY
   ## SOMETIMES_CONSUMES
   gPeiSecPerformancePpiGuid
+  gEfiPeiCoreFvLocationPpiGuid
 
 [Guids]
   ## SOMETIMES_PRODUCES   ## HOB
diff --git a/UefiCpuPkg/SecCore/SecMain.h b/UefiCpuPkg/SecCore/SecMain.h
index 83244af119..80045d34f4 100644
--- a/UefiCpuPkg/SecCore/SecMain.h
+++ b/UefiCpuPkg/SecCore/SecMain.h
@@ -1,7 +1,7 @@
 /** @file
   Master header file for SecCore.
 
-  Copyright (c) 2008 - 2018, Intel Corporation. All rights reserved.
+  Copyright (c) 2008 - 2019, Intel Corporation. All rights reserved.
   This program and the accompanying materials
   are licensed and made available under the terms and conditions of the BSD 
License
   which accompanies this distribution.  The full text of the license may be 
found at
@@ -20,6 +20,7 @@
 #include 
 #include 
 #include 
+#include 
 
 #include 
 
-- 
2.13.3.windows.1

___
edk2-devel mailing list
edk2-devel@

[edk2] [PATCH v2 0/3] Support EFI_PEI_CORE_FV_LOCATION_PPI

[Chasel, Chiu]

PI spec 1.7 section 6.3.9 has defined a PPI to support the scenario
that PEI Foundation not in BFV. EFI_PEI_CORE_FV_LOCATION_PPI reports
the FV which contains PEI Foundation and should be passed by SEC as
part of PPI list. Otherwise PEI Foundation shall assume that it
resides in BFV.

Patch1: Add EFI_PEI_CORE_FV_LOCATION_PPI definition.
Patch2: Support PeiCore not in BFV scenario when shadowing.
Patch3: SecCore to find PeiCore from either non-BFV or BFV.

Cc: Michael D Kinney 
Cc: Liming Gao 
Cc: Jian J Wang 
Cc: Hao Wu 
Cc: Ray Ni 
Cc: Star Zeng 
Cc: Eric Dong 
Cc: Laszlo Ersek 

Chasel, Chiu (3):
  MdePkg: Support EFI_PEI_CORE_FV_LOCATION_PPI
  MdeModulePkg/PeiMain: Support EFI_PEI_CORE_FV_LOCATION_PPI
  UefiCpuPkg/SecCore: Support EFI_PEI_CORE_FV_LOCATION_PPI

 MdeModulePkg/Core/Pei/PeiMain/PeiMain.c | 58 
+-
 UefiCpuPkg/SecCore/SecMain.c| 35 
+--
 MdeModulePkg/Core/Pei/PeiMain.h |  3 ++-
 MdeModulePkg/Core/Pei/PeiMain.inf   |  3 ++-
 MdePkg/Include/Ppi/PeiCoreFvLocation.h  | 53 
+
 MdePkg/MdePkg.dec   | 11 +--
 UefiCpuPkg/SecCore/SecCore.inf  |  3 ++-
 UefiCpuPkg/SecCore/SecMain.h|  3 ++-
 8 files changed, 144 insertions(+), 25 deletions(-)
 create mode 100644 MdePkg/Include/Ppi/PeiCoreFvLocation.h

-- 
2.13.3.windows.1

___
edk2-devel mailing list
edk2-devel@lists.01.org
https://lists.01.org/mailman/listinfo/edk2-devel

[edk2] [PATCH v2 2/3] MdeModulePkg/PeiMain: Support EFI_PEI_CORE_FV_LOCATION_PPI

[Chasel, Chiu]

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1524

When shadowing PeiCore the EFI_PEI_CORE_FV_LOCATION_PPI
should be checked to see if PeiCore not in BFV, otherwise
just shadowing PeiCore from BFV.

Test: Verified on internal platform and booting successfully.

Cc: Jian J Wang 
Cc: Hao Wu 
Cc: Ray Ni 
Cc: Star Zeng 
Cc: Liming Gao 
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Chasel Chiu 
---
 MdeModulePkg/Core/Pei/PeiMain/PeiMain.c | 58 
+-
 MdeModulePkg/Core/Pei/PeiMain.h |  3 ++-
 MdeModulePkg/Core/Pei/PeiMain.inf   |  3 ++-
 3 files changed, 49 insertions(+), 15 deletions(-)

diff --git a/MdeModulePkg/Core/Pei/PeiMain/PeiMain.c 
b/MdeModulePkg/Core/Pei/PeiMain/PeiMain.c
index 4da80a8222..ba0f2b7b69 100644
--- a/MdeModulePkg/Core/Pei/PeiMain/PeiMain.c
+++ b/MdeModulePkg/Core/Pei/PeiMain/PeiMain.c
@@ -1,7 +1,7 @@
 /** @file
   Pei Core Main Entry Point
 
-Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.
 This program and the accompanying materials
 are licensed and made available under the terms and conditions of the BSD 
License
 which accompanies this distribution.  The full text of the license may be 
found at
@@ -80,23 +80,55 @@ ShadowPeiCore (
   IN PEI_CORE_INSTANCE  *PrivateData
   )
 {
-  EFI_PEI_FILE_HANDLE  PeiCoreFileHandle;
-  EFI_PHYSICAL_ADDRESS EntryPoint;
-  EFI_STATUS   Status;
-  UINT32   AuthenticationState;
+  EFI_PEI_FILE_HANDLE  PeiCoreFileHandle;
+  EFI_PHYSICAL_ADDRESS EntryPoint;
+  EFI_STATUS   Status;
+  UINT32   AuthenticationState;
+  UINTNIndex;
+  EFI_PEI_CORE_FV_LOCATION_PPI *PeiCoreFvLocationPpi;
 
   PeiCoreFileHandle = NULL;
 
   //
-  // Find the PEI Core in the BFV
+  // Find the PEI Core either from EFI_PEI_CORE_FV_LOCATION_PPI indicated FV 
or BFV
   //
-  Status = PrivateData->Fv[0].FvPpi->FindFileByType (
-   PrivateData->Fv[0].FvPpi,
-   EFI_FV_FILETYPE_PEI_CORE,
-   PrivateData->Fv[0].FvHandle,
-   &PeiCoreFileHandle
-   );
-  ASSERT_EFI_ERROR (Status);
+  Status = PeiServicesLocatePpi (
+ &gEfiPeiCoreFvLocationPpiGuid,
+ 0,
+ NULL,
+ (VOID **) &PeiCoreFvLocationPpi
+ );
+  if (!EFI_ERROR (Status) && (PeiCoreFvLocationPpi->PeiCoreFvLocation != 
NULL)) {
+//
+// If PeiCoreFvLocation present, the PEI Core should be found from 
indicated FV.
+//
+for (Index = 0; Index < PrivateData->FvCount; Index ++) {
+  if (PrivateData->Fv[Index].FvHandle != 
PeiCoreFvLocationPpi->PeiCoreFvLocation) {
+continue;
+  }
+  Status = PrivateData->Fv[Index].FvPpi->FindFileByType (
+   PrivateData->Fv[Index].FvPpi,
+   EFI_FV_FILETYPE_PEI_CORE,
+   PrivateData->Fv[Index].FvHandle,
+   &PeiCoreFileHandle
+   );
+  if (!EFI_ERROR (Status)) {
+break;
+  }
+}
+ASSERT (Index < PrivateData->FvCount);
+  } else {
+//
+// Find PEI Core from BFV
+//
+Status = PrivateData->Fv[0].FvPpi->FindFileByType (
+ PrivateData->Fv[0].FvPpi,
+ EFI_FV_FILETYPE_PEI_CORE,
+ PrivateData->Fv[0].FvHandle,
+ &PeiCoreFileHandle
+ );
+ASSERT_EFI_ERROR (Status);
+  }
 
   //
   // Shadow PEI Core into memory so it will run faster
diff --git a/MdeModulePkg/Core/Pei/PeiMain.h b/MdeModulePkg/Core/Pei/PeiMain.h
index 322e7cd845..38542ab072 100644
--- a/MdeModulePkg/Core/Pei/PeiMain.h
+++ b/MdeModulePkg/Core/Pei/PeiMain.h
@@ -1,7 +1,7 @@
 /** @file
   Definition of Pei Core Structures and Services
 
-Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.
 This program and the accompanying materials
 are licensed and made available under the terms and conditions of the BSD 
License
 which accompanies this distribution.  The full text of the license may be 
found at
@@ -49,6 +49,7 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER 
EXPRESS OR IMPLIED.
 #include 
 #include 
 #include 
+#include 
 
 ///
 /// It is an FFS type extension used for PeiFindFileEx. It indicates current
diff --git a/MdeModulePkg/Core/Pei/PeiMain.inf 
b/MdeModulePkg

[edk2] [PATCH v2 1/3] MdePkg: Support EFI_PEI_CORE_FV_LOCATION_PPI

[Chasel, Chiu]

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1524

Add EFI_PEI_CORE_FV_LOCATION_PPI definition basing on
PI spec 1.7, Section 6.3.9.
This PPI can support the secnario that PEI Foundation
not in BFV.

Cc: Michael D Kinney 
Cc: Liming Gao 
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Chasel Chiu 
---
 MdePkg/Include/Ppi/PeiCoreFvLocation.h | 53 
+
 MdePkg/MdePkg.dec  | 11 +--
 2 files changed, 62 insertions(+), 2 deletions(-)

diff --git a/MdePkg/Include/Ppi/PeiCoreFvLocation.h 
b/MdePkg/Include/Ppi/PeiCoreFvLocation.h
new file mode 100644
index 00..c7bbbfb265
--- /dev/null
+++ b/MdePkg/Include/Ppi/PeiCoreFvLocation.h
@@ -0,0 +1,53 @@
+/** @file
+  Header file for Pei Core FV Location PPI.
+
+  This PPI contains a pointer to the firmware volume which contains the PEI 
Foundation.
+  If the PEI Foundation does not reside in the BFV, then SEC must pass this 
PPI as a part
+  of the PPI list provided to the PEI Foundation Entry Point, otherwise the 
PEI Foundation
+  shall assume that it resides within the BFV.
+
+  Copyright (c) 2019, Intel Corporation. All rights reserved.
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD 
License
+  which accompanies this distribution.  The full text of the license may be 
found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+  @par Revision Reference:
+  This PPI is defined in UEFI Platform Initialization Specification 1.7 Volume 
1:
+  Standards
+
+**/
+
+
+#ifndef _EFI_PEI_CORE_FV_LOCATION_H_
+#define _EFI_PEI_CORE_FV_LOCATION_H_
+
+///
+/// Global ID for EFI_PEI_CORE_FV_LOCATION_PPI
+///
+#define EFI_PEI_CORE_FV_LOCATION_GUID \
+  { \
+0x52888eae, 0x5b10, 0x47d0, {0xa8, 0x7f, 0xb8, 0x22, 0xab, 0xa0, 0xca, 
0xf4 } \
+  }
+
+///
+/// Forward declaration for EFI_PEI_CORE_FV_LOCATION_PPI
+///
+typedef struct _EFI_PEI_CORE_FV_LOCATION_PPI EFI_PEI_CORE_FV_LOCATION_PPI;
+
+///
+/// This PPI provides location of EFI PeiCoreFv.
+///
+struct _EFI_PEI_CORE_FV_LOCATION_PPI {
+  ///
+  /// Pointer to the first byte of the firmware volume which contains the PEI 
Foundation.
+  ///
+  VOID*PeiCoreFvLocation;
+};
+
+extern EFI_GUID gEfiPeiCoreFvLocationPpiGuid;
+
+#endif // _EFI_PEI_CORE_FV_LOCATION_H_
diff --git a/MdePkg/MdePkg.dec b/MdePkg/MdePkg.dec
index a485408310..c859b4a511 100644
--- a/MdePkg/MdePkg.dec
+++ b/MdePkg/MdePkg.dec
@@ -2,9 +2,9 @@
 # This Package provides all definitions, library classes and libraries 
instances.
 #
 # It also provides the definitions(including PPIs/PROTOCOLs/GUIDs) of
-# EFI1.10/UEFI2.7/PI1.6 and some Industry Standards.
+# EFI1.10/UEFI2.7/PI1.7 and some Industry Standards.
 #
-# Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.
+# Copyright (c) 2007 - 2019, Intel Corporation. All rights reserved.
 # Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
 # (C) Copyright 2016 Hewlett Packard Enterprise Development LP
 #
@@ -929,6 +929,13 @@
   ## Include/Ppi/SecHobData.h
   gEfiSecHobDataPpiGuid = { 0x3ebdaf20, 0x6667, 0x40d8, {0xb4, 0xee, 0xf5, 
0x99, 0x9a, 0xc1, 0xb7, 0x1f } }
 
+  #
+  # PPIs defined in PI 1.7.
+  #
+
+  ## Include/Ppi/PeiCoreFvLocation.h
+  gEfiPeiCoreFvLocationPpiGuid   = { 0x52888eae, 0x5b10, 0x47d0, { 0xa8, 0x7f, 
0xb8, 0x22, 0xab, 0xa0, 0xca, 0xf4 }}
+
 [Protocols]
   ## Include/Protocol/Pcd.h
   gPcdProtocolGuid   = { 0x11B34006, 0xD85B, 0x4D0A, { 0xA2, 0x90, 
0xD5, 0xA5, 0x71, 0x31, 0x0E, 0xF7 }}
-- 
2.13.3.windows.1

___
edk2-devel mailing list
edk2-devel@lists.01.org
https://lists.01.org/mailman/listinfo/edk2-devel

[edk2] [PATCH 1/3] MdePkg: Support EFI_PEI_CORE_FV_LOCATION_PPI

[Chasel, Chiu]

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1524

Add EFI_PEI_CORE_FV_LOCATION_PPI definition basing on
PI spec 1.7, Section 6.3.9.
This PPI can support the secnario that PEI Foundation
not in BFV.

Cc: Michael D Kinney 
Cc: Liming Gao 
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Chasel Chiu 
---
 MdePkg/Include/Ppi/PeiCoreFvLocation.h | 53 
+
 MdePkg/MdePkg.dec  | 11 +--
 2 files changed, 62 insertions(+), 2 deletions(-)

diff --git a/MdePkg/Include/Ppi/PeiCoreFvLocation.h 
b/MdePkg/Include/Ppi/PeiCoreFvLocation.h
new file mode 100644
index 00..c7bbbfb265
--- /dev/null
+++ b/MdePkg/Include/Ppi/PeiCoreFvLocation.h
@@ -0,0 +1,53 @@
+/** @file
+  Header file for Pei Core FV Location PPI.
+
+  This PPI contains a pointer to the firmware volume which contains the PEI 
Foundation.
+  If the PEI Foundation does not reside in the BFV, then SEC must pass this 
PPI as a part
+  of the PPI list provided to the PEI Foundation Entry Point, otherwise the 
PEI Foundation
+  shall assume that it resides within the BFV.
+
+  Copyright (c) 2019, Intel Corporation. All rights reserved.
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD 
License
+  which accompanies this distribution.  The full text of the license may be 
found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+  @par Revision Reference:
+  This PPI is defined in UEFI Platform Initialization Specification 1.7 Volume 
1:
+  Standards
+
+**/
+
+
+#ifndef _EFI_PEI_CORE_FV_LOCATION_H_
+#define _EFI_PEI_CORE_FV_LOCATION_H_
+
+///
+/// Global ID for EFI_PEI_CORE_FV_LOCATION_PPI
+///
+#define EFI_PEI_CORE_FV_LOCATION_GUID \
+  { \
+0x52888eae, 0x5b10, 0x47d0, {0xa8, 0x7f, 0xb8, 0x22, 0xab, 0xa0, 0xca, 
0xf4 } \
+  }
+
+///
+/// Forward declaration for EFI_PEI_CORE_FV_LOCATION_PPI
+///
+typedef struct _EFI_PEI_CORE_FV_LOCATION_PPI EFI_PEI_CORE_FV_LOCATION_PPI;
+
+///
+/// This PPI provides location of EFI PeiCoreFv.
+///
+struct _EFI_PEI_CORE_FV_LOCATION_PPI {
+  ///
+  /// Pointer to the first byte of the firmware volume which contains the PEI 
Foundation.
+  ///
+  VOID*PeiCoreFvLocation;
+};
+
+extern EFI_GUID gEfiPeiCoreFvLocationPpiGuid;
+
+#endif // _EFI_PEI_CORE_FV_LOCATION_H_
diff --git a/MdePkg/MdePkg.dec b/MdePkg/MdePkg.dec
index a485408310..c859b4a511 100644
--- a/MdePkg/MdePkg.dec
+++ b/MdePkg/MdePkg.dec
@@ -2,9 +2,9 @@
 # This Package provides all definitions, library classes and libraries 
instances.
 #
 # It also provides the definitions(including PPIs/PROTOCOLs/GUIDs) of
-# EFI1.10/UEFI2.7/PI1.6 and some Industry Standards.
+# EFI1.10/UEFI2.7/PI1.7 and some Industry Standards.
 #
-# Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.
+# Copyright (c) 2007 - 2019, Intel Corporation. All rights reserved.
 # Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
 # (C) Copyright 2016 Hewlett Packard Enterprise Development LP
 #
@@ -929,6 +929,13 @@
   ## Include/Ppi/SecHobData.h
   gEfiSecHobDataPpiGuid = { 0x3ebdaf20, 0x6667, 0x40d8, {0xb4, 0xee, 0xf5, 
0x99, 0x9a, 0xc1, 0xb7, 0x1f } }
 
+  #
+  # PPIs defined in PI 1.7.
+  #
+
+  ## Include/Ppi/PeiCoreFvLocation.h
+  gEfiPeiCoreFvLocationPpiGuid   = { 0x52888eae, 0x5b10, 0x47d0, { 0xa8, 0x7f, 
0xb8, 0x22, 0xab, 0xa0, 0xca, 0xf4 }}
+
 [Protocols]
   ## Include/Protocol/Pcd.h
   gPcdProtocolGuid   = { 0x11B34006, 0xD85B, 0x4D0A, { 0xA2, 0x90, 
0xD5, 0xA5, 0x71, 0x31, 0x0E, 0xF7 }}
-- 
2.13.3.windows.1

___
edk2-devel mailing list
edk2-devel@lists.01.org
https://lists.01.org/mailman/listinfo/edk2-devel

[edk2] [PATCH 3/3] UefiCpuPkg/SecCore: Support EFI_PEI_CORE_FV_LOCATION_PPI

[Chasel, Chiu]

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1524

EFI_PEI_CORE_FV_LOCATION_PPI may be passed by platform
when PeiCore not in BFV so SecCore has to search PeiCore
either from the FV location provided by
EFI_PEI_CORE_FV_LOCATION_PPI or from BFV.

Test: Verified on internal platform and booting successfully.

Cc: Eric Dong 
Cc: Ray Ni 
Cc: Laszlo Ersek 
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Chasel Chiu 
---
 UefiCpuPkg/SecCore/SecMain.c   | 35 +--
 UefiCpuPkg/SecCore/SecCore.inf |  3 ++-
 UefiCpuPkg/SecCore/SecMain.h   |  3 ++-
 3 files changed, 33 insertions(+), 8 deletions(-)

diff --git a/UefiCpuPkg/SecCore/SecMain.c b/UefiCpuPkg/SecCore/SecMain.c
index b24e190617..b99072599d 100644
--- a/UefiCpuPkg/SecCore/SecMain.c
+++ b/UefiCpuPkg/SecCore/SecMain.c
@@ -1,7 +1,7 @@
 /** @file
   C functions in SEC
 
-  Copyright (c) 2008 - 2018, Intel Corporation. All rights reserved.
+  Copyright (c) 2008 - 2019, Intel Corporation. All rights reserved.
   This program and the accompanying materials
   are licensed and made available under the terms and conditions of the BSD 
License
   which accompanies this distribution.  The full text of the license may be 
found at
@@ -228,26 +228,49 @@ SecStartupPhase2(
 {
   EFI_SEC_PEI_HAND_OFF*SecCoreData;
   EFI_PEI_PPI_DESCRIPTOR  *PpiList;
+  EFI_PEI_PPI_DESCRIPTOR  *PpiListTmp;
   UINT32  Index;
   EFI_PEI_PPI_DESCRIPTOR  *AllSecPpiList;
   EFI_PEI_CORE_ENTRY_POINTPeiCoreEntryPoint;
 
+  PeiCoreEntryPoint = NULL;
   SecCoreData   = (EFI_SEC_PEI_HAND_OFF *) Context;
   AllSecPpiList = (EFI_PEI_PPI_DESCRIPTOR *) SecCoreData->PeiTemporaryRamBase;
+
   //
   // Find Pei Core entry point. It will report SEC and Pei Core debug 
information if remote debug
   // is enabled.
   //
-  FindAndReportEntryPoints ((EFI_FIRMWARE_VOLUME_HEADER *) 
SecCoreData->BootFirmwareVolumeBase, &PeiCoreEntryPoint);
-  if (PeiCoreEntryPoint == NULL)
-  {
-CpuDeadLoop ();
+  PpiList = SecPlatformMain (SecCoreData);
+  PpiListTmp = PpiList;
+  for (;;) {
+if (CompareGuid (PpiListTmp->Guid, &gEfiPeiCoreFvLocationPpiGuid) && 
(((EFI_PEI_CORE_FV_LOCATION_PPI *) PpiListTmp->Ppi)->PeiCoreFvLocation != 0)) {
+  FindAndReportEntryPoints ((EFI_FIRMWARE_VOLUME_HEADER *) 
((EFI_PEI_CORE_FV_LOCATION_PPI *) PpiListTmp->Ppi)->PeiCoreFvLocation, 
&PeiCoreEntryPoint);
+  if (PeiCoreEntryPoint != NULL) {
+break;
+  }
+}
+if ((PpiListTmp->Flags & EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST) == 
EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST) {
+  //
+  // Continue until the end of the PPI List.
+  //
+  break;
+}
+PpiListTmp++;
+  }
+  //
+  // If EFI_PEI_CORE_FV_LOCATION_PPI not found or no PeiCore found by the 
pointer in provided PPI, try to locate PeiCore from BFV.
+  //
+  if (PeiCoreEntryPoint == NULL) {
+FindAndReportEntryPoints ((EFI_FIRMWARE_VOLUME_HEADER *) 
SecCoreData->BootFirmwareVolumeBase, &PeiCoreEntryPoint);
+if (PeiCoreEntryPoint == NULL) {
+  CpuDeadLoop ();
+}
   }
 
   //
   // Perform platform specific initialization before entering PeiCore.
   //
-  PpiList = SecPlatformMain (SecCoreData);
   if (PpiList != NULL) {
 //
 // Remove the terminal flag from the terminal PPI
diff --git a/UefiCpuPkg/SecCore/SecCore.inf b/UefiCpuPkg/SecCore/SecCore.inf
index 442f663911..fc1485b5cb 100644
--- a/UefiCpuPkg/SecCore/SecCore.inf
+++ b/UefiCpuPkg/SecCore/SecCore.inf
@@ -7,7 +7,7 @@
 #  protected mode, setup flat memory model, enable temporary memory and
 #  call into SecStartup().
 #
-#  Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+#  Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.
 #  This program and the accompanying materials
 #  are licensed and made available under the terms and conditions of the BSD 
License
 #  which accompanies this distribution.  The full text of the license may be 
found at
@@ -73,6 +73,7 @@
   ## NOTIFY
   ## SOMETIMES_CONSUMES
   gPeiSecPerformancePpiGuid
+  gEfiPeiCoreFvLocationPpiGuid
 
 [Guids]
   ## SOMETIMES_PRODUCES   ## HOB
diff --git a/UefiCpuPkg/SecCore/SecMain.h b/UefiCpuPkg/SecCore/SecMain.h
index 83244af119..80045d34f4 100644
--- a/UefiCpuPkg/SecCore/SecMain.h
+++ b/UefiCpuPkg/SecCore/SecMain.h
@@ -1,7 +1,7 @@
 /** @file
   Master header file for SecCore.
 
-  Copyright (c) 2008 - 2018, Intel Corporation. All rights reserved.
+  Copyright (c) 2008 - 2019, Intel Corporation. All rights reserved.
   This program and the accompanying materials
   are licensed and made available under the terms and conditions of the BSD 
License
   which accompanies this distribution.  The full text of the license may be 
found at
@@ -20,6 +20,7 @@
 #include 
 #include 
 #include 
+#include 
 
 #include 
 
-- 
2.13.3.windows.1

___
edk2-devel mailing list
edk2-devel@

[edk2] [PATCH 2/3] MdeModulePkg/PeiMain: Support EFI_PEI_CORE_FV_LOCATION_PPI

[Chasel, Chiu]

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1524

When shadowing PeiCore the EFI_PEI_CORE_FV_LOCATION_PPI
should be checked to see if PeiCore not in BFV, otherwise
just shadowing PeiCore from BFV.

Test: Verified on internal platform and booting successfully.

Cc: Jian J Wang 
Cc: Hao Wu 
Cc: Ray Ni 
Cc: Star Zeng 
Cc: Liming Gao 
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Chasel Chiu 
---
 MdeModulePkg/Core/Pei/PeiMain/PeiMain.c | 58 
+-
 MdeModulePkg/Core/Pei/PeiMain.h |  3 ++-
 MdeModulePkg/Core/Pei/PeiMain.inf   |  3 ++-
 3 files changed, 49 insertions(+), 15 deletions(-)

diff --git a/MdeModulePkg/Core/Pei/PeiMain/PeiMain.c 
b/MdeModulePkg/Core/Pei/PeiMain/PeiMain.c
index 4da80a8222..408f24c216 100644
--- a/MdeModulePkg/Core/Pei/PeiMain/PeiMain.c
+++ b/MdeModulePkg/Core/Pei/PeiMain/PeiMain.c
@@ -1,7 +1,7 @@
 /** @file
   Pei Core Main Entry Point
 
-Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.
 This program and the accompanying materials
 are licensed and made available under the terms and conditions of the BSD 
License
 which accompanies this distribution.  The full text of the license may be 
found at
@@ -80,23 +80,55 @@ ShadowPeiCore (
   IN PEI_CORE_INSTANCE  *PrivateData
   )
 {
-  EFI_PEI_FILE_HANDLE  PeiCoreFileHandle;
-  EFI_PHYSICAL_ADDRESS EntryPoint;
-  EFI_STATUS   Status;
-  UINT32   AuthenticationState;
+  EFI_PEI_FILE_HANDLE  PeiCoreFileHandle;
+  EFI_PHYSICAL_ADDRESS EntryPoint;
+  EFI_STATUS   Status;
+  UINT32   AuthenticationState;
+  UINTNIndex;
+  EFI_PEI_CORE_FV_LOCATION_PPI *PeiCoreFvLocationPpi;
 
   PeiCoreFileHandle = NULL;
 
   //
-  // Find the PEI Core in the BFV
+  // Find the PEI Core either from EFI_PEI_CORE_FV_LOCATION_PPI indicated FV 
or BFV
   //
-  Status = PrivateData->Fv[0].FvPpi->FindFileByType (
-   PrivateData->Fv[0].FvPpi,
-   EFI_FV_FILETYPE_PEI_CORE,
-   PrivateData->Fv[0].FvHandle,
-   &PeiCoreFileHandle
-   );
-  ASSERT_EFI_ERROR (Status);
+  Status = PeiServicesLocatePpi (
+ &gEfiPeiCoreFvLocationPpiGuid,
+ 0,
+ NULL,
+ (VOID **) &PeiCoreFvLocationPpi
+ );
+  if (!EFI_ERROR (Status) && (PeiCoreFvLocationPpi->PeiCoreFvLocation != 
NULL)) {
+//
+// If PeiCoreFvLocation present, the PEI Core should be found from 
indicated FV.
+//
+for (Index = 0; Index < PrivateData->FvCount; Index ++) {
+  if ((UINT32) PrivateData->Fv[Index].FvHandle != (UINT32) 
PeiCoreFvLocationPpi->PeiCoreFvLocation) {
+continue;
+  }
+  Status = PrivateData->Fv[Index].FvPpi->FindFileByType (
+   PrivateData->Fv[Index].FvPpi,
+   EFI_FV_FILETYPE_PEI_CORE,
+   PrivateData->Fv[Index].FvHandle,
+   &PeiCoreFileHandle
+   );
+  if (!EFI_ERROR (Status)) {
+break;
+  }
+}
+ASSERT (Index < PrivateData->FvCount);
+  } else {
+//
+// Find PEI Core from BFV
+//
+Status = PrivateData->Fv[0].FvPpi->FindFileByType (
+ PrivateData->Fv[0].FvPpi,
+ EFI_FV_FILETYPE_PEI_CORE,
+ PrivateData->Fv[0].FvHandle,
+ &PeiCoreFileHandle
+ );
+ASSERT_EFI_ERROR (Status);
+  }
 
   //
   // Shadow PEI Core into memory so it will run faster
diff --git a/MdeModulePkg/Core/Pei/PeiMain.h b/MdeModulePkg/Core/Pei/PeiMain.h
index 322e7cd845..38542ab072 100644
--- a/MdeModulePkg/Core/Pei/PeiMain.h
+++ b/MdeModulePkg/Core/Pei/PeiMain.h
@@ -1,7 +1,7 @@
 /** @file
   Definition of Pei Core Structures and Services
 
-Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.
 This program and the accompanying materials
 are licensed and made available under the terms and conditions of the BSD 
License
 which accompanies this distribution.  The full text of the license may be 
found at
@@ -49,6 +49,7 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER 
EXPRESS OR IMPLIED.
 #include 
 #include 
 #include 
+#include 
 
 ///
 /// It is an FFS type extension used for PeiFindFileEx. It indicates current
diff --git a/MdeModulePkg/Core/Pei/PeiMain.inf 
b/Mde

[edk2] [PATCH 0/3] Support EFI_PEI_CORE_FV_LOCATION_PPI

[Chasel, Chiu]

PI spec 1.7 section 6.3.9 has defined a PPI to support the scenario
that PEI Foundation not in BFV. EFI_PEI_CORE_FV_LOCATION_PPI reports
the FV which contains PEI Foundation and should be passed by SEC as
part of PPI list. Otherwise PEI Foundation shall assume that it
resides in BFV.

Patch1: Add EFI_PEI_CORE_FV_LOCATION_PPI definition.
Patch2: Support PeiCore not in BFV scenario when shadowing.
Patch3: SecCore to find PeiCore from either non-BFV or BFV.

Cc: Michael D Kinney 
Cc: Liming Gao 
Cc: Jian J Wang 
Cc: Hao Wu 
Cc: Ray Ni 
Cc: Star Zeng 
Cc: Eric Dong 
Cc: Laszlo Ersek 

Chasel, Chiu (3):
  MdePkg: Support EFI_PEI_CORE_FV_LOCATION_PPI
  MdeModulePkg/PeiMain: Support EFI_PEI_CORE_FV_LOCATION_PPI
  UefiCpuPkg/SecCore: Support EFI_PEI_CORE_FV_LOCATION_PPI

 MdeModulePkg/Core/Pei/PeiMain/PeiMain.c | 58 
+-
 UefiCpuPkg/SecCore/SecMain.c| 35 
+--
 MdeModulePkg/Core/Pei/PeiMain.h |  3 ++-
 MdeModulePkg/Core/Pei/PeiMain.inf   |  3 ++-
 MdePkg/Include/Ppi/PeiCoreFvLocation.h  | 53 
+
 MdePkg/MdePkg.dec   | 11 +--
 UefiCpuPkg/SecCore/SecCore.inf  |  3 ++-
 UefiCpuPkg/SecCore/SecMain.h|  3 ++-
 8 files changed, 144 insertions(+), 25 deletions(-)
 create mode 100644 MdePkg/Include/Ppi/PeiCoreFvLocation.h

-- 
2.13.3.windows.1

___
edk2-devel mailing list
edk2-devel@lists.01.org
https://lists.01.org/mailman/listinfo/edk2-devel

[edk2] [PATCH] IntelFsp2Pkg: FSP can utilize bootloader stack

[Chasel, Chiu]

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1485

Current FSP utilizes pre-allocated temporary memory from
boot loader for both heap and stack. To reduce overall
temporary memory usage FSP may share the same stack with
boot loader and only needs a smaller memory for heap,
no separate memory required for stack.
Setting PcdFspHeapSizePercentage to 0 to enable FSP sharing
stack with boot loader, in this case boot loader stack
has to be large enough for FSP to use. Default is 50
(half memory heap and half memory stack) for backward
compatible with original model.

Test: Verified on internal platform and booting successfully
  with both modes.

Cc: Nate DeSimone 
Cc: Star Zeng 
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Chasel Chiu 
---
 IntelFsp2Pkg/FspSecCore/SecMain.c  | 86 
++
 IntelFsp2Pkg/FspSecCore/FspSecCoreM.inf|  3 ++-
 IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryM.nasm | 52 
++--
 IntelFsp2Pkg/FspSecCore/Ia32/ReadEsp.nasm  | 28 

 IntelFsp2Pkg/IntelFsp2Pkg.dec  |  4 
 5 files changed, 154 insertions(+), 19 deletions(-)

diff --git a/IntelFsp2Pkg/FspSecCore/SecMain.c 
b/IntelFsp2Pkg/FspSecCore/SecMain.c
index 70460a3c8b..b0b5dda711 100644
--- a/IntelFsp2Pkg/FspSecCore/SecMain.c
+++ b/IntelFsp2Pkg/FspSecCore/SecMain.c
@@ -1,6 +1,6 @@
 /** @file
 
-  Copyright (c) 2014 - 2018, Intel Corporation. All rights reserved.
+  Copyright (c) 2014 - 2019, Intel Corporation. All rights reserved.
   This program and the accompanying materials
   are licensed and made available under the terms and conditions of the BSD 
License
   which accompanies this distribution.  The full text of the license may be 
found at
@@ -38,6 +38,19 @@ UINT64  mIdtEntryTemplate = 0x8e08ffe4ULL;
 
 /**
 
+  Return value of esp
+
+  @return  value of esp
+
+**/
+UINT32
+EFIAPI
+AsmReadEsp (
+  VOID
+  );
+
+/**
+
   Entry point to the C language phase of SEC. After the SEC assembly
   code has initialized some temporary memory and set up the stack,
   the control is transferred to this function.
@@ -83,7 +96,26 @@ SecStartup (
   //
   InitializeFloatingPointUnits ();
 
+  //
+  // Scenario 1 memory map when running on bootloader stack
+  //
+  // |---|>
+  // |Idt Table  |
+  // |---|
+  // |PeiService Pointer |
+  // |---|
+  // |   |
+  // |   |
+  // |  Heap |
+  // |   |
+  // |   |
+  // |---|>  TempRamBase
+  // |Bootloader stack   |
+  // |---|
 
+  //
+  // Scenario 2 memory map when running FSP on a separate stack
+  //
   // |---|>
   // |Idt Table  |
   // |---|
@@ -135,11 +167,19 @@ SecStartup (
   SecCoreData.BootFirmwareVolumeSize = (UINT32)((EFI_FIRMWARE_VOLUME_HEADER 
*)BootFirmwareVolume)->FvLength;
 
   SecCoreData.TemporaryRamBase   = (VOID*)(UINTN) TempRamBase;
-  SecCoreData.TemporaryRamSize   = SizeOfRam;
-  SecCoreData.PeiTemporaryRamBase= SecCoreData.TemporaryRamBase;
-  SecCoreData.PeiTemporaryRamSize= SecCoreData.TemporaryRamSize * PcdGet8 
(PcdFspHeapSizePercentage) / 100;
-  SecCoreData.StackBase  = 
(VOID*)(UINTN)((UINTN)SecCoreData.TemporaryRamBase + 
SecCoreData.PeiTemporaryRamSize);
-  SecCoreData.StackSize  = SecCoreData.TemporaryRamSize - 
SecCoreData.PeiTemporaryRamSize;
+  if (PcdGet8 (PcdFspHeapSizePercentage) == 0) {
+SecCoreData.TemporaryRamSize   = SizeOfRam; // stack size that is 
going to be copied to the permanent memory
+SecCoreData.PeiTemporaryRamBase= SecCoreData.TemporaryRamBase;
+SecCoreData.PeiTemporaryRamSize= SecCoreData.TemporaryRamSize;
+SecCoreData.StackBase  = (VOID *)GetFspEntryStack(); // Share 
the same boot loader stack
+SecCoreData.StackSize  = 0;
+  } else {
+SecCoreData.TemporaryRamSize   = SizeOfRam;
+SecCoreData.PeiTemporaryRamBase= SecCoreData.TemporaryRamBase;
+SecCoreData.PeiTemporaryRamSize= SecCoreData.TemporaryRamSize * 
PcdGet8 (PcdFspHeapSizePercentage) / 100;
+SecCoreData.StackBase  = 
(VOID*)(UINTN)((UINTN)SecCoreData.TemporaryRamBase + 
SecCoreData.PeiTemporaryRamSize);
+SecCoreData.StackSize  = SecCoreData.TemporaryRamSize - 
SecCoreData.PeiTemporaryRamSize;
+  }
 
   DEBUG ((DEBUG_INFO, "Fsp BootFirmwareVolumeBase - 0x%x\n", 
SecCoreData.BootFirmwareVolumeBase));
   DEBUG ((DEBUG_INFO, "Fsp BootFirmwareVolumeSize - 0x%x\n", 
SecCoreData.BootFirmwareVolumeSize));
@@ -194,15 +234,37 @@ SecTemporaryRamSupport (
   UINTN HeapSize;
   UINTN StackSize;
 
-  HeapSize   = CopySize * PcdGet8 (PcdFspHeapSize

[edk2] [PATCH] IntelFsp2Pkg: Add function to get bootloader stack pointer

[Chasel, Chiu]

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1391

FSP on-going enhancement for stack utilization required
to know bootloader stack pointer and this pointer can be
retrieved by first input parameter address when FSP-M
entry API invoked by bootloader.

Test: Verified on internal platform and booting successfully

Cc: Nate DeSimone 
Cc: Star Zeng 
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Chasel Chiu 
---
 IntelFsp2Pkg/Library/BaseFspCommonLib/FspCommonLib.c | 27 
++-
 IntelFsp2Pkg/Include/Library/FspCommonLib.h  | 21 -
 2 files changed, 38 insertions(+), 10 deletions(-)

diff --git a/IntelFsp2Pkg/Library/BaseFspCommonLib/FspCommonLib.c 
b/IntelFsp2Pkg/Library/BaseFspCommonLib/FspCommonLib.c
index 64ffba1d16..2f2861281c 100644
--- a/IntelFsp2Pkg/Library/BaseFspCommonLib/FspCommonLib.c
+++ b/IntelFsp2Pkg/Library/BaseFspCommonLib/FspCommonLib.c
@@ -1,6 +1,6 @@
 /** @file
 
-  Copyright (c) 2014 - 2018, Intel Corporation. All rights reserved.
+  Copyright (c) 2014 - 2019, Intel Corporation. All rights reserved.
   This program and the accompanying materials
   are licensed and made available under the terms and conditions of the BSD 
License
   which accompanies this distribution.  The full text of the license may be 
found at
@@ -87,9 +87,9 @@ GetFspGlobalDataPointer (
 }
 
 /**
-  This function gets back the FSP API first parameter passed by the bootlaoder.
+  This function gets back the FSP API first parameter passed by the bootloader.
 
-  @retval ApiParameter FSP API first parameter passed by the bootlaoder.
+  @retval ApiParameter FSP API first parameter passed by the bootloader.
 **/
 UINT32
 EFIAPI
@@ -104,9 +104,26 @@ GetFspApiParameter (
 }
 
 /**
-  This function gets back the FSP API second parameter passed by the 
bootlaoder.
+  This function returns the FSP entry stack pointer from address of the first 
API parameter
 
-  @retval ApiParameter FSP API second parameter passed by the bootlaoder.
+  @retval FSP entry stack pointer.
+**/
+VOID*
+EFIAPI
+GetFspEntryStack (
+  VOID
+  )
+{
+  FSP_GLOBAL_DATA  *FspData;
+
+  FspData  = GetFspGlobalDataPointer ();
+  return (VOID*)(FspData->CoreStack + CONTEXT_STACK_OFFSET(ApiParam[0]));
+}
+
+/**
+  This function gets back the FSP API second parameter passed by the 
bootloader.
+
+  @retval ApiParameter FSP API second parameter passed by the bootloader.
 **/
 UINT32
 EFIAPI
diff --git a/IntelFsp2Pkg/Include/Library/FspCommonLib.h 
b/IntelFsp2Pkg/Include/Library/FspCommonLib.h
index 1c99be3b1f..e98b180fca 100644
--- a/IntelFsp2Pkg/Include/Library/FspCommonLib.h
+++ b/IntelFsp2Pkg/Include/Library/FspCommonLib.h
@@ -1,6 +1,6 @@
 /** @file
 
-  Copyright (c) 2014 - 2018, Intel Corporation. All rights reserved.
+  Copyright (c) 2014 - 2019, Intel Corporation. All rights reserved.
   This program and the accompanying materials
   are licensed and made available under the terms and conditions of the BSD 
License
   which accompanies this distribution.  The full text of the license may be 
found at
@@ -40,9 +40,9 @@ GetFspGlobalDataPointer (
   );
 
 /**
-  This function gets back the FSP API first parameter passed by the bootlaoder.
+  This function gets back the FSP API first parameter passed by the bootloader.
 
-  @retval ApiParameter FSP API first parameter passed by the bootlaoder.
+  @retval ApiParameter FSP API first parameter passed by the bootloader.
 **/
 UINT32
 EFIAPI
@@ -51,9 +51,9 @@ GetFspApiParameter (
   );
 
 /**
-  This function gets back the FSP API second parameter passed by the 
bootlaoder.
+  This function gets back the FSP API second parameter passed by the 
bootloader.
 
-  @retval ApiParameter FSP API second parameter passed by the bootlaoder.
+  @retval ApiParameter FSP API second parameter passed by the bootloader.
 **/
 UINT32
 EFIAPI
@@ -61,6 +61,17 @@ GetFspApiParameter2 (
   VOID
   );
 
+
+/**
+  This function returns the FSP entry stack pointer from address of the first 
API parameter
+
+  @retval FSP entry stack pointer.
+**/
+VOID*
+EFIAPI
+GetFspEntryStack (
+  VOID
+  );
 /**
   This function sets the FSP API parameter in the stack.
 
-- 
2.13.3.windows.1

___
edk2-devel mailing list
edk2-devel@lists.01.org
https://lists.01.org/mailman/listinfo/edk2-devel

[edk2] [PATCH] IntelFsp2Pkg: Remove unused keyword in new PPI header

[Chasel, Chiu]

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1477

There was unused keyword added in FspmArchConfigPpi.h
header block and should be removed.

Cc: Nate DeSimone 
Cc: Star Zeng 
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Chasel Chiu 
---
 IntelFsp2Pkg/Include/Ppi/FspmArchConfigPpi.h | 1 -
 1 file changed, 1 deletion(-)

diff --git a/IntelFsp2Pkg/Include/Ppi/FspmArchConfigPpi.h 
b/IntelFsp2Pkg/Include/Ppi/FspmArchConfigPpi.h
index 5bedb95aa7..0268f43b1e 100644
--- a/IntelFsp2Pkg/Include/Ppi/FspmArchConfigPpi.h
+++ b/IntelFsp2Pkg/Include/Ppi/FspmArchConfigPpi.h
@@ -1,7 +1,6 @@
 /** @file
   Header file for FSP-M Arch Config PPI for Dispatch mode
 
- @copyright
   Copyright (c) 2019, Intel Corporation. All rights reserved.
 
   This program and the accompanying materials are licensed and made available 
under
-- 
2.13.3.windows.1

___
edk2-devel mailing list
edk2-devel@lists.01.org
https://lists.01.org/mailman/listinfo/edk2-devel

[edk2] [PATCH v2] MinPlatformPkg: Support TCO base locked by FSP

[Chasel, Chiu]

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1457

Per security recommendation TCO Base should be
initialized and locked by FSP and MinPlatform should
support both TCO Base locked and not locked scenarios.

Cc: Michael A Kubacki 
Cc: Jiewen Yao 
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Chasel Chiu 
---
 Silicon/Intel/KabylakeSiliconPkg/Library/SiliconInitLib/SiliconInitPreMem.c
 |  8 +---
 
Silicon/Intel/KabylakeSiliconPkg/Pch/Library/PeiDxeSmmPchCycleDecodingLib/PchCycleDecodingLib.c
 | 48 
 Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Library/PchCycleDecodingLib.h 
 | 18 +-
 3 files changed, 62 insertions(+), 12 deletions(-)

diff --git 
a/Silicon/Intel/KabylakeSiliconPkg/Library/SiliconInitLib/SiliconInitPreMem.c 
b/Silicon/Intel/KabylakeSiliconPkg/Library/SiliconInitLib/SiliconInitPreMem.c
index 616584ffe7..bb21872e1e 100644
--- 
a/Silicon/Intel/KabylakeSiliconPkg/Library/SiliconInitLib/SiliconInitPreMem.c
+++ 
b/Silicon/Intel/KabylakeSiliconPkg/Library/SiliconInitLib/SiliconInitPreMem.c
@@ -1,7 +1,7 @@
 /** @file
   Source code file for Platform Init Pre-Memory PEI module
 
-Copyright (c) 2017, Intel Corporation. All rights reserved.
+Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.
 This program and the accompanying materials are licensed and made available 
under
 the terms and conditions of the BSD License that accompanies this distribution.
 The full text of the license may be found at
@@ -80,9 +80,11 @@ EarlySiliconInit (
   PchPwrmBaseSet (PCH_PWRM_BASE_ADDRESS);
 
   ///
-  /// Program TCO BASE
+  /// Program TCO BASE if it is present and not locked
   ///
-  PchTcoBaseSet (PcdGet16 (PcdTcoBaseAddress));
+  if (PchIsTcoBaseSetValid ()) {
+PchTcoBaseSet (PcdGet16 (PcdTcoBaseAddress));
+  }
 
   ///
   /// LPC I/O Configuration
diff --git 
a/Silicon/Intel/KabylakeSiliconPkg/Pch/Library/PeiDxeSmmPchCycleDecodingLib/PchCycleDecodingLib.c
 
b/Silicon/Intel/KabylakeSiliconPkg/Pch/Library/PeiDxeSmmPchCycleDecodingLib/PchCycleDecodingLib.c
index 68b0b5dd4b..d7e91f947b 100644
--- 
a/Silicon/Intel/KabylakeSiliconPkg/Pch/Library/PeiDxeSmmPchCycleDecodingLib/PchCycleDecodingLib.c
+++ 
b/Silicon/Intel/KabylakeSiliconPkg/Pch/Library/PeiDxeSmmPchCycleDecodingLib/PchCycleDecodingLib.c
@@ -1,7 +1,7 @@
 /** @file
   PCH cycle deocding configuration and query library.
 
-Copyright (c) 2017, Intel Corporation. All rights reserved.
+Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.
 This program and the accompanying materials are licensed and made available 
under
 the terms and conditions of the BSD License that accompanies this distribution.
 The full text of the license may be found at
@@ -306,6 +306,36 @@ PchPwrmBaseGet (
 }
 
 /**
+  Check if TCO Base register is present and unlocked.
+  This should be called before calling PchTcoBaseSet ()
+
+  @retval BOOLEAN   FALSE = Either TCO base is locked or 
Smbus not present
+TRUE  = TCO base is not locked
+
+**/
+BOOLEAN
+EFIAPI
+PchIsTcoBaseSetValid (
+  VOID
+  )
+{
+  UINTN SmbusBase;
+
+  SmbusBase = MmPciBase (
+DEFAULT_PCI_BUS_NUMBER_PCH,
+PCI_DEVICE_NUMBER_PCH_SMBUS,
+PCI_FUNCTION_NUMBER_PCH_SMBUS
+);
+  if (MmioRead16 (SmbusBase) == 0x) {
+return FALSE;
+  }
+  //
+  // Verify TCO base is not locked.
+  //
+  return ((MmioRead8 (SmbusBase + R_PCH_SMBUS_TCOCTL) & 
B_PCH_SMBUS_TCOCTL_TCO_BASE_LOCK) == 0);
+}
+
+/**
   Set PCH TCO base address.
   This cycle decoding is allowed to set when DMIC.SRL is 0.
   Programming steps:
@@ -318,7 +348,8 @@ PchPwrmBaseGet (
 
   @retval EFI_SUCCESS   Successfully completed.
   @retval EFI_INVALID_PARAMETER Invalid base address passed.
-  @retval EFI_UNSUPPORTED   DMIC.SRL is set.
+  @retval EFI_UNSUPPORTED   DMIC.SRL is set, or Smbus device not 
present
+  @retval EFI_DEVICE_ERROR  TCO Base register is locked already
 **/
 EFI_STATUS
 EFIAPI
@@ -353,16 +384,17 @@ PchTcoBaseSet (
   //
   // Verify TCO base is not locked.
   //
-  if ((MmioRead8 (SmbusBase + R_PCH_SMBUS_TCOCTL) & 
B_PCH_SMBUS_TCOCTL_TCO_BASE_LOCK) != 0) {
+  if (!PchIsTcoBaseSetValid ()) {
 ASSERT (FALSE);
 return EFI_DEVICE_ERROR;
   }
   //
   // Disable TCO in SMBUS Device first before changing base address.
+  // Byte access to not touch the TCO_BASE_LOCK bit
   //
-  MmioAnd16 (
-SmbusBase + R_PCH_SMBUS_TCOCTL,
-(UINT16) ~B_PCH_SMBUS_TCOCTL_TCO_BASE_EN
+  MmioAnd8 (
+SmbusBase + R_PCH_SMBUS_TCOCTL + 1,
+(UINT8) ~(B_PCH_SMBUS_TCOCTL_TCO_BASE_EN >> 8)
 );
   //
   // Program TCO in SMBUS Device
@@ -373,11 +405,11 @@ PchTcoBaseSet (
 Address
 );
   //
-  // Enable TCO in SMBUS Device
+  // Enable TCO i

[edk2] [PATCH] MinPlatformPkg: Correct typo in INF

[Chasel, Chiu]

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1468

SiliconPolicyInitLibNull.inf and SiliconPolicyUpdateLibNull.inf
both had wrong BASE_NAME and LIBRARY_CLASS, so correct them to
align with file naming and the purpose.

Cc: Michael A Kubacki 
Cc: Jiewen Yao 
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Chasel Chiu 
---
 
Platform/Intel/MinPlatformPkg/PlatformInit/Library/SiliconPolicyInitLibNull/SiliconPolicyInitLibNull.inf
 | 6 +++---
 
Platform/Intel/MinPlatformPkg/PlatformInit/Library/SiliconPolicyUpdateLibNull/SiliconPolicyUpdateLibNull.inf
 | 6 +++---
 2 files changed, 6 insertions(+), 6 deletions(-)

diff --git 
a/Platform/Intel/MinPlatformPkg/PlatformInit/Library/SiliconPolicyInitLibNull/SiliconPolicyInitLibNull.inf
 
b/Platform/Intel/MinPlatformPkg/PlatformInit/Library/SiliconPolicyInitLibNull/SiliconPolicyInitLibNull.inf
index 593d1490f1..ae696ccc90 100644
--- 
a/Platform/Intel/MinPlatformPkg/PlatformInit/Library/SiliconPolicyInitLibNull/SiliconPolicyInitLibNull.inf
+++ 
b/Platform/Intel/MinPlatformPkg/PlatformInit/Library/SiliconPolicyInitLibNull/SiliconPolicyInitLibNull.inf
@@ -1,7 +1,7 @@
 ## @file
 # Component information file for Silicon Init Library
 #
-# Copyright (c) 2017, Intel Corporation. All rights reserved.
+# Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.
 #
 # This program and the accompanying materials are licensed and made available 
under
 # the terms and conditions of the BSD License which accompanies this 
distribution.
@@ -15,11 +15,11 @@
 
 [Defines]
   INF_VERSION= 0x00010005
-  BASE_NAME  = SiliconInitLibNull
+  BASE_NAME  = SiliconPolicyInitLibNull
   FILE_GUID  = 81B55810-E3DE-4E3E-8477-B8768232193A
   MODULE_TYPE= BASE
   VERSION_STRING = 1.0
-  LIBRARY_CLASS  = SiliconInitLib
+  LIBRARY_CLASS  = SiliconPolicyInitLib
 
 [LibraryClasses]
   BaseLib
diff --git 
a/Platform/Intel/MinPlatformPkg/PlatformInit/Library/SiliconPolicyUpdateLibNull/SiliconPolicyUpdateLibNull.inf
 
b/Platform/Intel/MinPlatformPkg/PlatformInit/Library/SiliconPolicyUpdateLibNull/SiliconPolicyUpdateLibNull.inf
index ab03602297..d2018881bb 100644
--- 
a/Platform/Intel/MinPlatformPkg/PlatformInit/Library/SiliconPolicyUpdateLibNull/SiliconPolicyUpdateLibNull.inf
+++ 
b/Platform/Intel/MinPlatformPkg/PlatformInit/Library/SiliconPolicyUpdateLibNull/SiliconPolicyUpdateLibNull.inf
@@ -1,7 +1,7 @@
 ## @file
 # Component information file for Silicon Update Library
 #
-# Copyright (c) 2017, Intel Corporation. All rights reserved.
+# Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.
 #
 # This program and the accompanying materials are licensed and made available 
under
 # the terms and conditions of the BSD License which accompanies this 
distribution.
@@ -15,11 +15,11 @@
 
 [Defines]
   INF_VERSION= 0x00010005
-  BASE_NAME  = SiliconUpdateLibNull
+  BASE_NAME  = SiliconPolicyUpdateLibNull
   FILE_GUID  = 7D4AA651-D23B-42FC-ABE4-8A2FDF260B9F
   MODULE_TYPE= BASE
   VERSION_STRING = 1.0
-  LIBRARY_CLASS  = SiliconUpdateLib
+  LIBRARY_CLASS  = SiliconPolicyUpdateLib
 
 [LibraryClasses]
   BaseLib
-- 
2.13.3.windows.1

___
edk2-devel mailing list
edk2-devel@lists.01.org
https://lists.01.org/mailman/listinfo/edk2-devel

[edk2] [PATCH v3] IntelFsp2Pkg: Add FspmArchConfigPpi to support Dispatch mode

[Chasel, Chiu]

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1381

In Dispatch mode FSP may consume PPI directly so creating
FSPM_ARCH_CONFIG_PPI to align with FSPM_ARCH_UPD.
Also Keeps new structure size 8 bytes alignment as other
structures.

Test: Verified on internal platform to boot with this PPI
installed successfully.

Cc: Nate DeSimone 
Cc: Star Zeng 
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Chasel Chiu 
---
 IntelFsp2Pkg/Include/Ppi/FspmArchConfigPpi.h | 54 
++
 IntelFsp2Pkg/IntelFsp2Pkg.dec|  3 +++
 2 files changed, 57 insertions(+)

diff --git a/IntelFsp2Pkg/Include/Ppi/FspmArchConfigPpi.h 
b/IntelFsp2Pkg/Include/Ppi/FspmArchConfigPpi.h
new file mode 100644
index 00..5bedb95aa7
--- /dev/null
+++ b/IntelFsp2Pkg/Include/Ppi/FspmArchConfigPpi.h
@@ -0,0 +1,54 @@
+/** @file
+  Header file for FSP-M Arch Config PPI for Dispatch mode
+
+ @copyright
+  Copyright (c) 2019, Intel Corporation. All rights reserved.
+
+  This program and the accompanying materials are licensed and made available 
under
+  the terms and conditions of the BSD License which accompanies this 
distribution.
+  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _FSPM_ARCH_CONFIG_PPI_H_
+#define _FSPM_ARCH_CONFIG_PPI_H_
+
+#define FSPM_ARCH_CONFIG_PPI_REVISION 0x1
+
+///
+/// Global ID for the FSPM_ARCH_CONFIG_PPI.
+///
+#define FSPM_ARCH_CONFIG_GUID \
+  { \
+0x824d5a3a, 0xaf92, 0x4c0c, { 0x9f, 0x19, 0x19, 0x52, 0x6d, 0xca, 0x4a, 
0xbb } \
+  }
+
+///
+/// This PPI provides FSP-M Arch Config PPI.
+///
+typedef struct {
+  ///
+  /// Revision of the structure
+  ///
+  UINT8 Revision;
+  UINT8 Reserved[3];
+  ///
+  /// Pointer to the non-volatile storage (NVS) data buffer.
+  /// If it is NULL it indicates the NVS data is not available.
+  ///
+  VOID  *NvsBufferPtr;
+  ///
+  /// Size of memory to be reserved by FSP below "top
+  /// of low usable memory" for bootloader usage.
+  ///
+  UINT32BootLoaderTolumSize;
+  UINT8 Reserved1[4];
+} FSPM_ARCH_CONFIG_PPI;
+
+extern EFI_GUID gFspmArchConfigPpiGuid;
+
+#endif // _FSPM_ARCH_CONFIG_PPI_H_
diff --git a/IntelFsp2Pkg/IntelFsp2Pkg.dec b/IntelFsp2Pkg/IntelFsp2Pkg.dec
index 50496241da..de1bece562 100644
--- a/IntelFsp2Pkg/IntelFsp2Pkg.dec
+++ b/IntelFsp2Pkg/IntelFsp2Pkg.dec
@@ -70,6 +70,9 @@
   gFspPerformanceDataGuid   = { 0x56ed21b6, 0xba23, 0x429e, { 
0x89, 0x32, 0x37, 0x6d, 0x8e, 0x18, 0x2e, 0xe3 } }
   gFspEventEndOfFirmwareGuid= { 0xbd44f629, 0xeae7, 0x4198, { 
0x87, 0xf1, 0x39, 0xfa, 0xb0, 0xfd, 0x71, 0x7e } }
 
+[Ppis]
+  gFspmArchConfigPpiGuid= { 0x824d5a3a, 0xaf92, 0x4c0c, { 
0x9f, 0x19, 0x19, 0x52, 0x6d, 0xca, 0x4a, 0xbb } }
+
 [PcdsFixedAtBuild]
   gIntelFsp2PkgTokenSpaceGuid.PcdGlobalDataPointerAddress 
|0xFED00108|UINT32|0x0001
   gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamBase 
|0xFEF0|UINT32|0x10001001
-- 
2.13.3.windows.1

___
edk2-devel mailing list
edk2-devel@lists.01.org
https://lists.01.org/mailman/listinfo/edk2-devel

[edk2] [PATCH] MinPlatformPkg: Support TCO base locked by FSP

[Chasel, Chiu]

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1457

Per security recommendation TCO Base should be
initialized and locked by FSP and MinPlatform should
support both TCO Base locked and not locked scenarios.

Cc: Nate DeSimone 
Cc: Star Zeng 
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Chasel Chiu 
---
 
Silicon/Intel/KabylakeSiliconPkg/Pch/Library/PeiDxeSmmPchCycleDecodingLib/PchCycleDecodingLib.c
 | 17 +
 1 file changed, 9 insertions(+), 8 deletions(-)

diff --git 
a/Silicon/Intel/KabylakeSiliconPkg/Pch/Library/PeiDxeSmmPchCycleDecodingLib/PchCycleDecodingLib.c
 
b/Silicon/Intel/KabylakeSiliconPkg/Pch/Library/PeiDxeSmmPchCycleDecodingLib/PchCycleDecodingLib.c
index 68b0b5dd4b..e135ef1f3e 100644
--- 
a/Silicon/Intel/KabylakeSiliconPkg/Pch/Library/PeiDxeSmmPchCycleDecodingLib/PchCycleDecodingLib.c
+++ 
b/Silicon/Intel/KabylakeSiliconPkg/Pch/Library/PeiDxeSmmPchCycleDecodingLib/PchCycleDecodingLib.c
@@ -1,7 +1,7 @@
 /** @file
   PCH cycle deocding configuration and query library.
 
-Copyright (c) 2017, Intel Corporation. All rights reserved.
+Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.
 This program and the accompanying materials are licensed and made available 
under
 the terms and conditions of the BSD License that accompanies this distribution.
 The full text of the license may be found at
@@ -352,17 +352,18 @@ PchTcoBaseSet (
   }
   //
   // Verify TCO base is not locked.
+  // If it is locked already, skip following steps.
   //
   if ((MmioRead8 (SmbusBase + R_PCH_SMBUS_TCOCTL) & 
B_PCH_SMBUS_TCOCTL_TCO_BASE_LOCK) != 0) {
-ASSERT (FALSE);
-return EFI_DEVICE_ERROR;
+return EFI_SUCCESS;
   }
   //
   // Disable TCO in SMBUS Device first before changing base address.
+  // Byte access to not touch the TCO_BASE_LOCK bit
   //
-  MmioAnd16 (
-SmbusBase + R_PCH_SMBUS_TCOCTL,
-(UINT16) ~B_PCH_SMBUS_TCOCTL_TCO_BASE_EN
+  MmioAnd8 (
+SmbusBase + R_PCH_SMBUS_TCOCTL + 1,
+(UINT8) ~(B_PCH_SMBUS_TCOCTL_TCO_BASE_EN >> 8)
 );
   //
   // Program TCO in SMBUS Device
@@ -373,11 +374,11 @@ PchTcoBaseSet (
 Address
 );
   //
-  // Enable TCO in SMBUS Device
+  // Enable TCO in SMBUS Device and lock TCO BASE
   //
   MmioOr16 (
 SmbusBase + R_PCH_SMBUS_TCOCTL,
-B_PCH_SMBUS_TCOCTL_TCO_BASE_EN
+B_PCH_SMBUS_TCOCTL_TCO_BASE_EN | B_PCH_SMBUS_TCOCTL_TCO_BASE_LOCK
 );
   //
   // Program "TCO Base Address" PCR[DMI] + 2778h[15:5, 1] to [SMBUS PCI offset 
50h[15:5], 1].
-- 
2.13.3.windows.1

___
edk2-devel mailing list
edk2-devel@lists.01.org
https://lists.01.org/mailman/listinfo/edk2-devel

[edk2] [PATCH] BaseTools/GenFv: Support SecCore and PeiCore in different FV

[Chasel, Chiu]

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1423

There is usage model that SecCore and PeiCore are in different FVs.
Update BaseTools to support this usage model.

Test: Verified on internal platform with the case SecCore and
PeiCore in different FVs and built/booted successfully.

Cc: Bob Feng 
Cc: Liming Gao 
Cc: Yonghong Zhu 
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Chasel Chiu 
---
 BaseTools/Source/C/GenFv/GenFvInternalLib.c | 82 
+-
 1 file changed, 41 insertions(+), 41 deletions(-)

diff --git a/BaseTools/Source/C/GenFv/GenFvInternalLib.c 
b/BaseTools/Source/C/GenFv/GenFvInternalLib.c
index 6a874f4e94..32bbcce0a6 100644
--- a/BaseTools/Source/C/GenFv/GenFvInternalLib.c
+++ b/BaseTools/Source/C/GenFv/GenFvInternalLib.c
@@ -1655,43 +1655,42 @@ Returns:
   //
   // Find the PEI Core
   //
+  PeiCorePhysicalAddress = 0;
   Status = GetFileByType (EFI_FV_FILETYPE_PEI_CORE, 1, &PeiCoreFile);
-  if (EFI_ERROR (Status) || PeiCoreFile == NULL) {
-Error (NULL, 0, 3000, "Invalid", "could not find the PEI core in the FV.");
-return EFI_ABORTED;
-  }
-  //
-  // PEI Core found, now find PE32 or TE section
-  //
-  Status = GetSectionByType (PeiCoreFile, EFI_SECTION_PE32, 1, &Pe32Section);
-  if (Status == EFI_NOT_FOUND) {
-Status = GetSectionByType (PeiCoreFile, EFI_SECTION_TE, 1, &Pe32Section);
-  }
+  if (!EFI_ERROR (Status) && (PeiCoreFile != NULL)) {
+//
+// PEI Core found, now find PE32 or TE section
+//
+Status = GetSectionByType (PeiCoreFile, EFI_SECTION_PE32, 1, &Pe32Section);
+if (Status == EFI_NOT_FOUND) {
+  Status = GetSectionByType (PeiCoreFile, EFI_SECTION_TE, 1, &Pe32Section);
+}
 
-  if (EFI_ERROR (Status)) {
-Error (NULL, 0, 3000, "Invalid", "could not find either a PE32 or a TE 
section in PEI core file.");
-return EFI_ABORTED;
-  }
+if (EFI_ERROR (Status)) {
+  Error (NULL, 0, 3000, "Invalid", "could not find either a PE32 or a TE 
section in PEI core file.");
+  return EFI_ABORTED;
+}
 
-  SecHeaderSize = GetSectionHeaderLength(Pe32Section.CommonHeader);
-  Status = GetPe32Info (
-(VOID *) ((UINTN) Pe32Section.Pe32Section + SecHeaderSize),
-&EntryPoint,
-&BaseOfCode,
-&MachineType
-);
+SecHeaderSize = GetSectionHeaderLength(Pe32Section.CommonHeader);
+Status = GetPe32Info (
+  (VOID *) ((UINTN) Pe32Section.Pe32Section + SecHeaderSize),
+  &EntryPoint,
+  &BaseOfCode,
+  &MachineType
+  );
 
-  if (EFI_ERROR (Status)) {
-Error (NULL, 0, 3000, "Invalid", "could not get the PE32 entry point for 
the PEI core.");
-return EFI_ABORTED;
+if (EFI_ERROR (Status)) {
+  Error (NULL, 0, 3000, "Invalid", "could not get the PE32 entry point for 
the PEI core.");
+  return EFI_ABORTED;
+}
+//
+// Physical address is FV base + offset of PE32 + offset of the entry point
+//
+PeiCorePhysicalAddress = FvInfo->BaseAddress;
+PeiCorePhysicalAddress += (UINTN) Pe32Section.Pe32Section + SecHeaderSize 
- (UINTN) FvImage->FileImage;
+PeiCorePhysicalAddress += EntryPoint;
+DebugMsg (NULL, 0, 9, "PeiCore physical entry point address", "Address = 
0x%llX", (unsigned long long) PeiCorePhysicalAddress);
   }
-  //
-  // Physical address is FV base + offset of PE32 + offset of the entry point
-  //
-  PeiCorePhysicalAddress = FvInfo->BaseAddress;
-  PeiCorePhysicalAddress += (UINTN) Pe32Section.Pe32Section + SecHeaderSize - 
(UINTN) FvImage->FileImage;
-  PeiCorePhysicalAddress += EntryPoint;
-  DebugMsg (NULL, 0, 9, "PeiCore physical entry point address", "Address = 
0x%llX", (unsigned long long) PeiCorePhysicalAddress);
 
   if (MachineType == EFI_IMAGE_MACHINE_IA64) {
 //
@@ -1749,16 +1748,17 @@ Returns:
 *SecCoreEntryAddressPtr = SecCorePhysicalAddress;
 
   } else if (MachineType == EFI_IMAGE_MACHINE_IA32 || MachineType == 
EFI_IMAGE_MACHINE_X64) {
-//
-// Get the location to update
-//
-Ia32ResetAddressPtr  = (UINT32 *) ((UINTN) FvImage->Eof - 
IA32_PEI_CORE_ENTRY_OFFSET);
-
-//
-// Write lower 32 bits of physical address for Pei Core entry
-//
-*Ia32ResetAddressPtr = (UINT32) PeiCorePhysicalAddress;
+if (PeiCorePhysicalAddress != 0) {
+  //
+  // Get the location to update
+  //
+  Ia32ResetAddressPtr  = (UINT32 *) ((UINTN) FvImage->Eof - 
IA32_PEI_CORE_ENTRY_OFFSET);
 
+  //
+  // Write lower 32 bits of physical address for Pei Core entry
+  //
+  *Ia32ResetAddressPtr = (UINT32) PeiCorePhysicalAddress;
+}
 //
 // Write SecCore Entry point relative address into the jmp instruction in 
reset vector.
 //
-- 
2.13.3.windows.1

___
edk2-devel mailing list
edk2-devel@lists.01.org
https://lists.01.org/mailman/listinfo/edk2-devel

[edk2] [PATCH v2] IntelFsp2Pkg: Add FspmArchConfigPpi to support Dispatch mode

[Chasel, Chiu]

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1381

In Dispatch mode FSP may consume PPI directly so creating
FSPM_ARCH_CONFIG_PPI to align with FSPM_ARCH_UPD.

Test: Verified on internal platform to boot with this PPI
installed successfully.

Cc: Nate DeSimone 
Cc: Star Zeng 
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Chasel Chiu 
---
 IntelFsp2Pkg/Include/Ppi/FspmArchConfigPpi.h | 54 
++
 IntelFsp2Pkg/IntelFsp2Pkg.dec|  3 +++
 2 files changed, 57 insertions(+)

diff --git a/IntelFsp2Pkg/Include/Ppi/FspmArchConfigPpi.h 
b/IntelFsp2Pkg/Include/Ppi/FspmArchConfigPpi.h
new file mode 100644
index 00..7f13805df6
--- /dev/null
+++ b/IntelFsp2Pkg/Include/Ppi/FspmArchConfigPpi.h
@@ -0,0 +1,54 @@
+/** @file
+  Header file for FSP-M Arch Config PPI for Dispatch mode
+
+ @copyright
+  Copyright (c) 2018, Intel Corporation. All rights reserved.
+
+  This program and the accompanying materials are licensed and made available 
under
+  the terms and conditions of the BSD License which accompanies this 
distribution.
+  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _FSPM_ARCH_CONFIG_PPI_H_
+#define _FSPM_ARCH_CONFIG_PPI_H_
+
+#define FSPM_ARCH_CONFIG_PPI_REVISION 0x1
+
+///
+/// Global ID for the FSPM_ARCH_CONFIG_PPI.
+///
+#define FSPM_ARCH_CONFIG_GUID \
+  { \
+0x824d5a3a, 0xaf92, 0x4c0c, { 0x9f, 0x19, 0x19, 0x52, 0x6d, 0xca, 0x4a, 
0xbb } \
+  }
+
+///
+/// This PPI provides FSP-M Arch Config PPI.
+///
+typedef struct {
+  ///
+  /// Revision of the structure
+  ///
+  UINT8 Revision;
+  UINT8 Reserved[3];
+  ///
+  /// Pointer to the non-volatile storage (NVS) data buffer.
+  /// If it is NULL it indicates the NVS data is not available.
+  ///
+  VOID  *NvsBufferPtr;
+  ///
+  /// Size of memory to be reserved by FSP below "top
+  /// of low usable memory" for bootloader usage.
+  ///
+  UINT32BootLoaderTolumSize;
+  UINT8 Reserved1[8];
+} FSPM_ARCH_CONFIG_PPI;
+
+extern EFI_GUID gFspmArchConfigPpiGuid;
+
+#endif // _FSPM_ARCH_CONFIG_PPI_H_
diff --git a/IntelFsp2Pkg/IntelFsp2Pkg.dec b/IntelFsp2Pkg/IntelFsp2Pkg.dec
index 50496241da..de1bece562 100644
--- a/IntelFsp2Pkg/IntelFsp2Pkg.dec
+++ b/IntelFsp2Pkg/IntelFsp2Pkg.dec
@@ -70,6 +70,9 @@
   gFspPerformanceDataGuid   = { 0x56ed21b6, 0xba23, 0x429e, { 
0x89, 0x32, 0x37, 0x6d, 0x8e, 0x18, 0x2e, 0xe3 } }
   gFspEventEndOfFirmwareGuid= { 0xbd44f629, 0xeae7, 0x4198, { 
0x87, 0xf1, 0x39, 0xfa, 0xb0, 0xfd, 0x71, 0x7e } }
 
+[Ppis]
+  gFspmArchConfigPpiGuid= { 0x824d5a3a, 0xaf92, 0x4c0c, { 
0x9f, 0x19, 0x19, 0x52, 0x6d, 0xca, 0x4a, 0xbb } }
+
 [PcdsFixedAtBuild]
   gIntelFsp2PkgTokenSpaceGuid.PcdGlobalDataPointerAddress 
|0xFED00108|UINT32|0x0001
   gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamBase 
|0xFEF0|UINT32|0x10001001
-- 
2.13.3.windows.1

___
edk2-devel mailing list
edk2-devel@lists.01.org
https://lists.01.org/mailman/listinfo/edk2-devel

[edk2] [PATCH] IntelFsp2Pkg: Add FspmArchConfigPpi to support Dispatch mode

[Chasel, Chiu]

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1381

In Dispatch mode FSP may consume PPI directly so creating
FSPM_ARCH_CONFIG_PPI to align with FSPM_ARCH_UPD.

Test: Verified on internal platform to boot with this PPI
installed successfully.

Cc: Nate DeSimone 
Cc: Star Zeng 
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Chasel Chiu 
---
 IntelFsp2Pkg/Include/Ppi/FspmArchConfigPpi.h | 41 
+
 IntelFsp2Pkg/IntelFsp2Pkg.dec|  3 +++
 2 files changed, 44 insertions(+)

diff --git a/IntelFsp2Pkg/Include/Ppi/FspmArchConfigPpi.h 
b/IntelFsp2Pkg/Include/Ppi/FspmArchConfigPpi.h
new file mode 100644
index 00..5b3dac5b04
--- /dev/null
+++ b/IntelFsp2Pkg/Include/Ppi/FspmArchConfigPpi.h
@@ -0,0 +1,41 @@
+/** @file
+  Header file for FSP-M Arch Config PPI
+
+ @copyright
+  Copyright (c) 2018, Intel Corporation. All rights reserved.
+
+  This program and the accompanying materials are licensed and made available 
under
+  the terms and conditions of the BSD License which accompanies this 
distribution.
+  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _FSPM_ARCH_CONFIG_PPI_H_
+#define _FSPM_ARCH_CONFIG_PPI_H_
+
+///
+/// Global ID for the FSPM_ARCH_CONFIG_PPI.
+///
+#define FSPM_ARCH_CONFIG_GUID \
+  { \
+0x824d5a3a, 0xaf92, 0x4c0c, { 0x9f, 0x19, 0x19, 0x52, 0x6d, 0xca, 0x4a, 
0xbb } \
+  }
+
+///
+/// This PPI provides FSP-M Arch Config PPI.
+///
+typedef struct {
+  UINT8 Revision;
+  UINT8 Reserved[3];
+  VOID  *NvsBufferPtr;
+  UINT32BootLoaderTolumSize;
+  UINT8 Reserved1[8];
+} FSPM_ARCH_CONFIG_PPI;
+
+extern EFI_GUID gFspmArchConfigPpiGuid;
+
+#endif // _FSPM_ARCH_CONFIG_PPI_H_
diff --git a/IntelFsp2Pkg/IntelFsp2Pkg.dec b/IntelFsp2Pkg/IntelFsp2Pkg.dec
index 50496241da..de1bece562 100644
--- a/IntelFsp2Pkg/IntelFsp2Pkg.dec
+++ b/IntelFsp2Pkg/IntelFsp2Pkg.dec
@@ -70,6 +70,9 @@
   gFspPerformanceDataGuid   = { 0x56ed21b6, 0xba23, 0x429e, { 
0x89, 0x32, 0x37, 0x6d, 0x8e, 0x18, 0x2e, 0xe3 } }
   gFspEventEndOfFirmwareGuid= { 0xbd44f629, 0xeae7, 0x4198, { 
0x87, 0xf1, 0x39, 0xfa, 0xb0, 0xfd, 0x71, 0x7e } }
 
+[Ppis]
+  gFspmArchConfigPpiGuid= { 0x824d5a3a, 0xaf92, 0x4c0c, { 
0x9f, 0x19, 0x19, 0x52, 0x6d, 0xca, 0x4a, 0xbb } }
+
 [PcdsFixedAtBuild]
   gIntelFsp2PkgTokenSpaceGuid.PcdGlobalDataPointerAddress 
|0xFED00108|UINT32|0x0001
   gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamBase 
|0xFEF0|UINT32|0x10001001
-- 
2.13.3.windows.1

___
edk2-devel mailing list
edk2-devel@lists.01.org
https://lists.01.org/mailman/listinfo/edk2-devel

[edk2] [PATCH v2] Maintainers.txt: Change package maintainer of IntelFsp*Pkg

[Chasel, Chiu]

Cc: Jiewen Yao 
Cc: Desimone Nathaniel L 
Cc: Zeng Star 
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Chasel Chiu 
---
 Maintainers.txt | 14 ++
 1 file changed, 10 insertions(+), 4 deletions(-)

diff --git a/Maintainers.txt b/Maintainers.txt
index 9a36f0232b..63edf01d56 100644
--- a/Maintainers.txt
+++ b/Maintainers.txt
@@ -147,21 +147,27 @@ M: Liming Gao 
 
 IntelFsp2Pkg
 W: https://github.com/tianocore/tianocore.github.io/wiki/IntelFsp2Pkg
-M: Jiewen Yao 
 M: Chasel Chiu 
+R: Nate DeSimone 
+R: Star Zeng 
 
 IntelFsp2WrapperPkg
 W: https://github.com/tianocore/tianocore.github.io/wiki/IntelFsp2WrapperPkg
-M: Jiewen Yao 
 M: Chasel Chiu 
+R: Nate DeSimone 
+R: Star Zeng 
 
 IntelFspPkg
 W: https://github.com/tianocore/tianocore.github.io/wiki/IntelFspPkg
-M: Jiewen Yao 
+M: Chasel Chiu 
+R: Nate DeSimone 
+R: Star Zeng 
 
 IntelFspWrapperPkg
 W: https://github.com/tianocore/tianocore.github.io/wiki/IntelFspWrapperPkg
-M: Jiewen Yao 
+M: Chasel Chiu 
+R: Nate DeSimone 
+R: Star Zeng 
 
 IntelSiliconPkg
 W: https://github.com/tianocore/tianocore.github.io/wiki/IntelSiliconPkg
-- 
2.13.3.windows.1

___
edk2-devel mailing list
edk2-devel@lists.01.org
https://lists.01.org/mailman/listinfo/edk2-devel

[edk2] [PATCH] Maintainers.txt: Change package maintainer of IntelFsp*Pkg

[Chasel, Chiu]

Cc: Jiewen Yao 
Cc: Desimone Nathaniel L 
Cc: Zeng Star 
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Chasel Chiu 
---
 Maintainers.txt | 14 ++
 1 file changed, 10 insertions(+), 4 deletions(-)

diff --git a/Maintainers.txt b/Maintainers.txt
index 9a36f0232b..1ed4166d63 100644
--- a/Maintainers.txt
+++ b/Maintainers.txt
@@ -147,21 +147,27 @@ M: Liming Gao 
 
 IntelFsp2Pkg
 W: https://github.com/tianocore/tianocore.github.io/wiki/IntelFsp2Pkg
-M: Jiewen Yao 
 M: Chasel Chiu 
+R: Desimone Nathaniel L 
+R: Zeng Star 
 
 IntelFsp2WrapperPkg
 W: https://github.com/tianocore/tianocore.github.io/wiki/IntelFsp2WrapperPkg
-M: Jiewen Yao 
 M: Chasel Chiu 
+R: Desimone Nathaniel L 
+R: Zeng Star 
 
 IntelFspPkg
 W: https://github.com/tianocore/tianocore.github.io/wiki/IntelFspPkg
-M: Jiewen Yao 
+M: Chasel Chiu 
+R: Desimone Nathaniel L 
+R: Zeng Star 
 
 IntelFspWrapperPkg
 W: https://github.com/tianocore/tianocore.github.io/wiki/IntelFspWrapperPkg
-M: Jiewen Yao 
+M: Chasel Chiu 
+R: Desimone Nathaniel L 
+R: Zeng Star 
 
 IntelSiliconPkg
 W: https://github.com/tianocore/tianocore.github.io/wiki/IntelSiliconPkg
-- 
2.13.3.windows.1

___
edk2-devel mailing list
edk2-devel@lists.01.org
https://lists.01.org/mailman/listinfo/edk2-devel

[edk2] [PATCH v2 1/2] IntelFsp2WrapperPkg: Fix line ending format issue

[Chasel, Chiu]

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1352

Fixed line ending format wrong issues on some files.

Test: Verified building successfully.

Cc: Jiewen Yao 
Cc: Desimone Nathaniel L 
Cc: Wu Hao A 
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Chasel Chiu 
---
 IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.c   | 32 

 IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.c   | 24 

 IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.inf |  4 ++--
 IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.inf |  4 ++--
 IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dec | 22 
+++---
 5 files changed, 43 insertions(+), 43 deletions(-)

diff --git a/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.c 
b/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.c
index e25854c080..fa0441ce6c 100644
--- a/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.c
+++ b/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.c
@@ -3,7 +3,7 @@
   register TemporaryRamDonePpi to call TempRamExit API, and register 
MemoryDiscoveredPpi
   notify to call FspSiliconInit API.
 
-  Copyright (c) 2014 - 2018, Intel Corporation. All rights reserved.
+  Copyright (c) 2014 - 2018, Intel Corporation. All rights reserved.
   This program and the accompanying materials
   are licensed and made available under the terms and conditions of the BSD 
License
   which accompanies this distribution.  The full text of the license may be 
found at
@@ -65,7 +65,7 @@ PeiFspMemoryInit (
   FspHobListPtr = NULL;
   FspmUpdDataPtr = NULL;
 
-  FspmHeaderPtr = (FSP_INFO_HEADER *) FspFindFspHeader (PcdGet32 
(PcdFspmBaseAddress));
+  FspmHeaderPtr = (FSP_INFO_HEADER *) FspFindFspHeader (PcdGet32 
(PcdFspmBaseAddress));
   DEBUG ((DEBUG_INFO, "FspmHeaderPtr - 0x%x\n", FspmHeaderPtr));
   if (FspmHeaderPtr == NULL) {
 return EFI_DEVICE_ERROR;
@@ -155,20 +155,20 @@ FspmWrapperInit (
 {
   EFI_STATUS   Status;
 
-  Status = EFI_SUCCESS;
-
-  if (FixedPcdGet8 (PcdFspModeSelection) == 1) {
-Status = PeiFspMemoryInit ();
-ASSERT_EFI_ERROR (Status);
-  } else {
-PeiServicesInstallFvInfoPpi (
-  NULL,
-  (VOID *)(UINTN) PcdGet32 (PcdFspmBaseAddress),
-  (UINT32)((EFI_FIRMWARE_VOLUME_HEADER *) (UINTN) PcdGet32 
(PcdFspmBaseAddress))->FvLength,
-  NULL,
-  NULL
-  );
-  }
+  Status = EFI_SUCCESS;
+
+  if (FixedPcdGet8 (PcdFspModeSelection) == 1) {
+Status = PeiFspMemoryInit ();
+ASSERT_EFI_ERROR (Status);
+  } else {
+PeiServicesInstallFvInfoPpi (
+  NULL,
+  (VOID *)(UINTN) PcdGet32 (PcdFspmBaseAddress),
+  (UINT32)((EFI_FIRMWARE_VOLUME_HEADER *) (UINTN) PcdGet32 
(PcdFspmBaseAddress))->FvLength,
+  NULL,
+  NULL
+  );
+  }
 
   return Status;
 }
diff --git a/IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.c 
b/IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.c
index 69cf568380..87dd61e5c5 100644
--- a/IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.c
+++ b/IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.c
@@ -3,7 +3,7 @@
   register TemporaryRamDonePpi to call TempRamExit API, and register 
MemoryDiscoveredPpi
   notify to call FspSiliconInit API.
 
-  Copyright (c) 2014 - 2018, Intel Corporation. All rights reserved.
+  Copyright (c) 2014 - 2018, Intel Corporation. All rights reserved.
   This program and the accompanying materials
   are licensed and made available under the terms and conditions of the BSD 
License
   which accompanies this distribution.  The full text of the license may be 
found at
@@ -349,17 +349,17 @@ FspsWrapperPeimEntryPoint (
 {
   DEBUG ((DEBUG_INFO, "FspsWrapperPeimEntryPoint\n"));
 
-  if (FixedPcdGet8 (PcdFspModeSelection) == 1) {
-FspsWrapperInit ();
-  } else {
-PeiServicesInstallFvInfoPpi (
-  NULL,
-  (VOID *)(UINTN) PcdGet32 (PcdFspsBaseAddress),
-  (UINT32)((EFI_FIRMWARE_VOLUME_HEADER *) (UINTN) PcdGet32 
(PcdFspsBaseAddress))->FvLength,
-  NULL,
-  NULL
-  );
-  }
+  if (FixedPcdGet8 (PcdFspModeSelection) == 1) {
+FspsWrapperInit ();
+  } else {
+PeiServicesInstallFvInfoPpi (
+  NULL,
+  (VOID *)(UINTN) PcdGet32 (PcdFspsBaseAddress),
+  (UINT32)((EFI_FIRMWARE_VOLUME_HEADER *) (UINTN) PcdGet32 
(PcdFspsBaseAddress))->FvLength,
+  NULL,
+  NULL
+  );
+  }
 
   return EFI_SUCCESS;
 }
diff --git a/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.inf 
b/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.inf
index f4b7ef8db6..b3776a80f3 100644
--- a/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.inf
+++ b/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.inf
@@ -6,7 +6,7 @@
 # register TemporaryRamDonePpi to call TempRamExit API, and register 
MemoryDiscoveredPpi
 # notify to call FspSiliconInit API.
 #
-#  Copyright (c) 2014 - 2018, Intel Corporation. All rights reserved.
+#  Copyright (c) 2014 - 2018, Intel Corporation. 

[edk2] [PATCH v2 2/2] IntelFsp2WrapperPkg: Fix constant if statements issue

[Chasel, Chiu]

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1351

Internal code quality scanning found 2 constant if
statements related to FixedPcdGet8 () usage.
Since the PCD can be PatchableInModule too, it should be
changed to PcdGet8 () to fix this issue.

Test: Verified on internal platform and booted successfully.

Cc: Jiewen Yao 
Cc: Desimone Nathaniel L 
Cc: Wu Hao A 
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Chasel Chiu 
---
 IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.c | 2 +-
 IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.c | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.c 
b/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.c
index fa0441ce6c..18f04b541a 100644
--- a/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.c
+++ b/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.c
@@ -157,7 +157,7 @@ FspmWrapperInit (
 
   Status = EFI_SUCCESS;
 
-  if (FixedPcdGet8 (PcdFspModeSelection) == 1) {
+  if (PcdGet8 (PcdFspModeSelection) == 1) {
 Status = PeiFspMemoryInit ();
 ASSERT_EFI_ERROR (Status);
   } else {
diff --git a/IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.c 
b/IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.c
index 87dd61e5c5..d748b21f7c 100644
--- a/IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.c
+++ b/IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.c
@@ -349,7 +349,7 @@ FspsWrapperPeimEntryPoint (
 {
   DEBUG ((DEBUG_INFO, "FspsWrapperPeimEntryPoint\n"));
 
-  if (FixedPcdGet8 (PcdFspModeSelection) == 1) {
+  if (PcdGet8 (PcdFspModeSelection) == 1) {
 FspsWrapperInit ();
   } else {
 PeiServicesInstallFvInfoPpi (
-- 
2.13.3.windows.1

___
edk2-devel mailing list
edk2-devel@lists.01.org
https://lists.01.org/mailman/listinfo/edk2-devel

[edk2] [PATCH v2 0/2] Fix constant if statement issue

[Chasel, Chiu]

Internal code quality scanning found 2 constant if
statements related to FixedPcdGet8 () usage.
Since the PCD can be PatchableInModule too, it should be
changed to PcdGet8 () to fix this issue.
Also fixed the line ending format issue from previous
patch.

Patch1 fixed line ending format issue on some files
Patch2 fixed constant if statement issue.

Cc: Jiewen Yao 
Cc: Desimone Nathaniel L 
Cc: Wu Hao A 

Chasel, Chiu (2):
  IntelFsp2WrapperPkg: Fix line ending format issue
  IntelFsp2WrapperPkg: Fix constant if statements issue

 IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.c   | 32 

 IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.c   | 24 

 IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.inf |  4 ++--
 IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.inf |  4 ++--
 IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dec | 22 
+++---
 5 files changed, 43 insertions(+), 43 deletions(-)

-- 
2.13.3.windows.1

___
edk2-devel mailing list
edk2-devel@lists.01.org
https://lists.01.org/mailman/listinfo/edk2-devel

[edk2] [PATCH] IntelFsp2WrapperPkg: Fix line ending format issue

[Chasel, Chiu]

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1352

Fixed line ending format wrong issues on some files.

Test: Verified building successfully.

Cc: Jiewen Yao 
Cc: Desimone Nathaniel L 
Cc: Wu Hao A 
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Chasel Chiu 
---
 IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.c   | 32 

 IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.inf |  4 ++--
 IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dec | 22 
+++---
 3 files changed, 29 insertions(+), 29 deletions(-)

diff --git a/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.c 
b/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.c
index e25854c080..fa0441ce6c 100644
--- a/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.c
+++ b/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.c
@@ -3,7 +3,7 @@
   register TemporaryRamDonePpi to call TempRamExit API, and register 
MemoryDiscoveredPpi
   notify to call FspSiliconInit API.
 
-  Copyright (c) 2014 - 2018, Intel Corporation. All rights reserved.
+  Copyright (c) 2014 - 2018, Intel Corporation. All rights reserved.
   This program and the accompanying materials
   are licensed and made available under the terms and conditions of the BSD 
License
   which accompanies this distribution.  The full text of the license may be 
found at
@@ -65,7 +65,7 @@ PeiFspMemoryInit (
   FspHobListPtr = NULL;
   FspmUpdDataPtr = NULL;
 
-  FspmHeaderPtr = (FSP_INFO_HEADER *) FspFindFspHeader (PcdGet32 
(PcdFspmBaseAddress));
+  FspmHeaderPtr = (FSP_INFO_HEADER *) FspFindFspHeader (PcdGet32 
(PcdFspmBaseAddress));
   DEBUG ((DEBUG_INFO, "FspmHeaderPtr - 0x%x\n", FspmHeaderPtr));
   if (FspmHeaderPtr == NULL) {
 return EFI_DEVICE_ERROR;
@@ -155,20 +155,20 @@ FspmWrapperInit (
 {
   EFI_STATUS   Status;
 
-  Status = EFI_SUCCESS;
-
-  if (FixedPcdGet8 (PcdFspModeSelection) == 1) {
-Status = PeiFspMemoryInit ();
-ASSERT_EFI_ERROR (Status);
-  } else {
-PeiServicesInstallFvInfoPpi (
-  NULL,
-  (VOID *)(UINTN) PcdGet32 (PcdFspmBaseAddress),
-  (UINT32)((EFI_FIRMWARE_VOLUME_HEADER *) (UINTN) PcdGet32 
(PcdFspmBaseAddress))->FvLength,
-  NULL,
-  NULL
-  );
-  }
+  Status = EFI_SUCCESS;
+
+  if (FixedPcdGet8 (PcdFspModeSelection) == 1) {
+Status = PeiFspMemoryInit ();
+ASSERT_EFI_ERROR (Status);
+  } else {
+PeiServicesInstallFvInfoPpi (
+  NULL,
+  (VOID *)(UINTN) PcdGet32 (PcdFspmBaseAddress),
+  (UINT32)((EFI_FIRMWARE_VOLUME_HEADER *) (UINTN) PcdGet32 
(PcdFspmBaseAddress))->FvLength,
+  NULL,
+  NULL
+  );
+  }
 
   return Status;
 }
diff --git a/IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.inf 
b/IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.inf
index 1e63f407cb..910286982b 100644
--- a/IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.inf
+++ b/IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.inf
@@ -6,7 +6,7 @@
 # register TemporaryRamDonePpi to call TempRamExit API, and register 
MemoryDiscoveredPpi
 # notify to call FspSiliconInit API.
 #
-#  Copyright (c) 2014 - 2018, Intel Corporation. All rights reserved.
+#  Copyright (c) 2014 - 2018, Intel Corporation. All rights reserved.
 #
 #  This program and the accompanying materials
 #  are licensed and made available under the terms and conditions of the BSD 
License
@@ -68,7 +68,7 @@
 [Pcd]
   gIntelFsp2WrapperTokenSpaceGuid.PcdFspsBaseAddress ## CONSUMES
   gIntelFsp2WrapperTokenSpaceGuid.PcdFspsUpdDataAddress  ## CONSUMES
-  gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection## CONSUMES
+  gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection## CONSUMES
 
 [Guids]
   gFspHobGuid   ## CONSUMES ## HOB
diff --git a/IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dec 
b/IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dec
index b901562bb3..96f2858fb4 100644
--- a/IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dec
+++ b/IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dec
@@ -71,7 +71,7 @@
   ## Indicate the PEI memory size platform want to report
   
gIntelFsp2WrapperTokenSpaceGuid.PcdPeiRecoveryMinMemSize|0x300|UINT32|0x4005
 
-  ## This is the base address of FSP-T
+  ## This is the base address of FSP-T
   
gIntelFsp2WrapperTokenSpaceGuid.PcdFsptBaseAddress|0x|UINT32|0x0300
 
   ## This PCD indicates if FSP APIs are skipped from FSP wrapper.
@@ -92,17 +92,17 @@
   # @Prompt Skip FSP API from FSP wrapper.
   gIntelFsp2WrapperTokenSpaceGuid.PcdSkipFspApi|0x|UINT32|0x4009
 
-  ## This PCD decides how Wrapper code utilizes FSP
-  # 0: DISPATCH mode (FSP Wrapper will load PeiCore from FSP without calling 
FSP API)
-  # 1: API mode (FSP Wrapper will call FSP API)
-  #
-  
gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection|0x0001|UINT8|0x400A
-
+  ## This PCD decides how Wrapper code utilizes FSP
+  # 0: DISPATCH mode (FSP Wrapper will load PeiCore from FSP without calling 
FSP API)
+  # 

[edk2] [PATCH] IntelFsp2WrapperPkg: Revert 90c5bc08

[Chasel, Chiu]

Commit message issue and reverted commit
90c5bc081d15d077606131a61114ddfdefe62e61.

Will re-submit with correct formats.

Cc: Jiewen Yao 
Cc: Star Zeng 
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Chasel Chiu 
---
 IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.c   | 20 

 IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.c   | 14 ++
 IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.inf |  3 +--
 IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.inf |  3 +--
 IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dec | 13 ++---
 5 files changed, 10 insertions(+), 43 deletions(-)

diff --git a/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.c 
b/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.c
index fa0441ce6c..7b7c5f5d86 100644
--- a/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.c
+++ b/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.c
@@ -3,7 +3,7 @@
   register TemporaryRamDonePpi to call TempRamExit API, and register 
MemoryDiscoveredPpi
   notify to call FspSiliconInit API.
 
-  Copyright (c) 2014 - 2018, Intel Corporation. All rights reserved.
+  Copyright (c) 2014 - 2017, Intel Corporation. All rights reserved.
   This program and the accompanying materials
   are licensed and made available under the terms and conditions of the BSD 
License
   which accompanies this distribution.  The full text of the license may be 
found at
@@ -65,7 +65,7 @@ PeiFspMemoryInit (
   FspHobListPtr = NULL;
   FspmUpdDataPtr = NULL;
 
-  FspmHeaderPtr = (FSP_INFO_HEADER *) FspFindFspHeader (PcdGet32 
(PcdFspmBaseAddress));
+  FspmHeaderPtr = (FSP_INFO_HEADER *)FspFindFspHeader (PcdGet32 
(PcdFspmBaseAddress));
   DEBUG ((DEBUG_INFO, "FspmHeaderPtr - 0x%x\n", FspmHeaderPtr));
   if (FspmHeaderPtr == NULL) {
 return EFI_DEVICE_ERROR;
@@ -155,20 +155,8 @@ FspmWrapperInit (
 {
   EFI_STATUS   Status;
 
-  Status = EFI_SUCCESS;
-
-  if (FixedPcdGet8 (PcdFspModeSelection) == 1) {
-Status = PeiFspMemoryInit ();
-ASSERT_EFI_ERROR (Status);
-  } else {
-PeiServicesInstallFvInfoPpi (
-  NULL,
-  (VOID *)(UINTN) PcdGet32 (PcdFspmBaseAddress),
-  (UINT32)((EFI_FIRMWARE_VOLUME_HEADER *) (UINTN) PcdGet32 
(PcdFspmBaseAddress))->FvLength,
-  NULL,
-  NULL
-  );
-  }
+  Status = PeiFspMemoryInit ();
+  ASSERT_EFI_ERROR (Status);
 
   return Status;
 }
diff --git a/IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.c 
b/IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.c
index 87dd61e5c5..70dac7a414 100644
--- a/IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.c
+++ b/IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.c
@@ -3,7 +3,7 @@
   register TemporaryRamDonePpi to call TempRamExit API, and register 
MemoryDiscoveredPpi
   notify to call FspSiliconInit API.
 
-  Copyright (c) 2014 - 2018, Intel Corporation. All rights reserved.
+  Copyright (c) 2014 - 2017, Intel Corporation. All rights reserved.
   This program and the accompanying materials
   are licensed and made available under the terms and conditions of the BSD 
License
   which accompanies this distribution.  The full text of the license may be 
found at
@@ -349,17 +349,7 @@ FspsWrapperPeimEntryPoint (
 {
   DEBUG ((DEBUG_INFO, "FspsWrapperPeimEntryPoint\n"));
 
-  if (FixedPcdGet8 (PcdFspModeSelection) == 1) {
-FspsWrapperInit ();
-  } else {
-PeiServicesInstallFvInfoPpi (
-  NULL,
-  (VOID *)(UINTN) PcdGet32 (PcdFspsBaseAddress),
-  (UINT32)((EFI_FIRMWARE_VOLUME_HEADER *) (UINTN) PcdGet32 
(PcdFspsBaseAddress))->FvLength,
-  NULL,
-  NULL
-  );
-  }
+  FspsWrapperInit ();
 
   return EFI_SUCCESS;
 }
diff --git a/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.inf 
b/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.inf
index b3776a80f3..542356b582 100644
--- a/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.inf
+++ b/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.inf
@@ -6,7 +6,7 @@
 # register TemporaryRamDonePpi to call TempRamExit API, and register 
MemoryDiscoveredPpi
 # notify to call FspSiliconInit API.
 #
-#  Copyright (c) 2014 - 2018, Intel Corporation. All rights reserved.
+#  Copyright (c) 2014 - 2017, Intel Corporation. All rights reserved.
 #
 #  This program and the accompanying materials
 #  are licensed and made available under the terms and conditions of the BSD 
License
@@ -61,7 +61,6 @@
 [Pcd]
   gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress ## CONSUMES
   gIntelFsp2WrapperTokenSpaceGuid.PcdFspmUpdDataAddress  ## CONSUMES
-  gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection## CONSUMES
 
 [Sources]
   FspmWrapperPeim.c
diff --git a/IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.inf 
b/IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.inf
index 910286982b..cd87a99c40 100644
--- a/IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.inf
+++ b/IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.inf
@

[edk2] [PATCH v2] IntelFsp2WrapperPkg: Support FSP Dispatch mode

[Chasel, Chiu]

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1300

Provides PCD selection for FSP Wrapper to support Dispatch
mode. Also PcdFspmBaseAddress should support Dynamic for
recovery scenario (multiple FSP-M binary in flash)

Test: Verified on internal platform and both API and
  DISPATCH modes booted successfully.

Cc: Jiewen Yao 
Cc: Desimone Nathaniel L 
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Chasel Chiu 
---
 IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.c   | 20 

 IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.c   | 14 --
 IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.inf |  3 ++-
 IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.inf |  3 ++-
 IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dec | 13 +++--
 5 files changed, 43 insertions(+), 10 deletions(-)

diff --git a/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.c 
b/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.c
index 7b7c5f5d86..fa0441ce6c 100644
--- a/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.c
+++ b/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.c
@@ -3,7 +3,7 @@
   register TemporaryRamDonePpi to call TempRamExit API, and register 
MemoryDiscoveredPpi
   notify to call FspSiliconInit API.
 
-  Copyright (c) 2014 - 2017, Intel Corporation. All rights reserved.
+  Copyright (c) 2014 - 2018, Intel Corporation. All rights reserved.
   This program and the accompanying materials
   are licensed and made available under the terms and conditions of the BSD 
License
   which accompanies this distribution.  The full text of the license may be 
found at
@@ -65,7 +65,7 @@ PeiFspMemoryInit (
   FspHobListPtr = NULL;
   FspmUpdDataPtr = NULL;
 
-  FspmHeaderPtr = (FSP_INFO_HEADER *)FspFindFspHeader (PcdGet32 
(PcdFspmBaseAddress));
+  FspmHeaderPtr = (FSP_INFO_HEADER *) FspFindFspHeader (PcdGet32 
(PcdFspmBaseAddress));
   DEBUG ((DEBUG_INFO, "FspmHeaderPtr - 0x%x\n", FspmHeaderPtr));
   if (FspmHeaderPtr == NULL) {
 return EFI_DEVICE_ERROR;
@@ -155,8 +155,20 @@ FspmWrapperInit (
 {
   EFI_STATUS   Status;
 
-  Status = PeiFspMemoryInit ();
-  ASSERT_EFI_ERROR (Status);
+  Status = EFI_SUCCESS;
+
+  if (FixedPcdGet8 (PcdFspModeSelection) == 1) {
+Status = PeiFspMemoryInit ();
+ASSERT_EFI_ERROR (Status);
+  } else {
+PeiServicesInstallFvInfoPpi (
+  NULL,
+  (VOID *)(UINTN) PcdGet32 (PcdFspmBaseAddress),
+  (UINT32)((EFI_FIRMWARE_VOLUME_HEADER *) (UINTN) PcdGet32 
(PcdFspmBaseAddress))->FvLength,
+  NULL,
+  NULL
+  );
+  }
 
   return Status;
 }
diff --git a/IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.c 
b/IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.c
index 70dac7a414..87dd61e5c5 100644
--- a/IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.c
+++ b/IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.c
@@ -3,7 +3,7 @@
   register TemporaryRamDonePpi to call TempRamExit API, and register 
MemoryDiscoveredPpi
   notify to call FspSiliconInit API.
 
-  Copyright (c) 2014 - 2017, Intel Corporation. All rights reserved.
+  Copyright (c) 2014 - 2018, Intel Corporation. All rights reserved.
   This program and the accompanying materials
   are licensed and made available under the terms and conditions of the BSD 
License
   which accompanies this distribution.  The full text of the license may be 
found at
@@ -349,7 +349,17 @@ FspsWrapperPeimEntryPoint (
 {
   DEBUG ((DEBUG_INFO, "FspsWrapperPeimEntryPoint\n"));
 
-  FspsWrapperInit ();
+  if (FixedPcdGet8 (PcdFspModeSelection) == 1) {
+FspsWrapperInit ();
+  } else {
+PeiServicesInstallFvInfoPpi (
+  NULL,
+  (VOID *)(UINTN) PcdGet32 (PcdFspsBaseAddress),
+  (UINT32)((EFI_FIRMWARE_VOLUME_HEADER *) (UINTN) PcdGet32 
(PcdFspsBaseAddress))->FvLength,
+  NULL,
+  NULL
+  );
+  }
 
   return EFI_SUCCESS;
 }
diff --git a/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.inf 
b/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.inf
index 542356b582..b3776a80f3 100644
--- a/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.inf
+++ b/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.inf
@@ -6,7 +6,7 @@
 # register TemporaryRamDonePpi to call TempRamExit API, and register 
MemoryDiscoveredPpi
 # notify to call FspSiliconInit API.
 #
-#  Copyright (c) 2014 - 2017, Intel Corporation. All rights reserved.
+#  Copyright (c) 2014 - 2018, Intel Corporation. All rights reserved.
 #
 #  This program and the accompanying materials
 #  are licensed and made available under the terms and conditions of the BSD 
License
@@ -61,6 +61,7 @@
 [Pcd]
   gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress ## CONSUMES
   gIntelFsp2WrapperTokenSpaceGuid.PcdFspmUpdDataAddress  ## CONSUMES
+  gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection## CONSUMES
 
 [Sources]
   FspmWrapperPeim.c
diff --git a/IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.inf 
b/IntelFsp2

[edk2] [PATCH] IntelFsp2WrapperPkg: Support FSP Dispatch mode

[Chasel, Chiu]

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1300

Provides PCD selection for FSP Wrapper to support Dispatch
mode. Also PcdFspmBaseAddress should support Dynamic for
recovery scenario (multiple FSP-M binary in flash)

Test: Verified on internal platform and both API and
  DISPATCH modes booted successfully.

Cc: Jiewen Yao 
Cc: Desimone Nathaniel L 
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Chasel Chiu 
---
 IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.c   | 16 ++--
 IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.c   | 14 --
 IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.inf |  3 ++-
 IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.inf |  3 ++-
 IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dec | 13 +++--
 5 files changed, 41 insertions(+), 8 deletions(-)

diff --git a/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.c 
b/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.c
index 7b7c5f5d86..8128a26873 100644
--- a/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.c
+++ b/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.c
@@ -3,7 +3,7 @@
   register TemporaryRamDonePpi to call TempRamExit API, and register 
MemoryDiscoveredPpi
   notify to call FspSiliconInit API.
 
-  Copyright (c) 2014 - 2017, Intel Corporation. All rights reserved.
+  Copyright (c) 2014 - 2018, Intel Corporation. All rights reserved.
   This program and the accompanying materials
   are licensed and made available under the terms and conditions of the BSD 
License
   which accompanies this distribution.  The full text of the license may be 
found at
@@ -65,7 +65,7 @@ PeiFspMemoryInit (
   FspHobListPtr = NULL;
   FspmUpdDataPtr = NULL;
 
-  FspmHeaderPtr = (FSP_INFO_HEADER *)FspFindFspHeader (PcdGet32 
(PcdFspmBaseAddress));
+  FspmHeaderPtr = (FSP_INFO_HEADER *) FspFindFspHeader (PcdGet32 
(PcdFspmBaseAddress));
   DEBUG ((DEBUG_INFO, "FspmHeaderPtr - 0x%x\n", FspmHeaderPtr));
   if (FspmHeaderPtr == NULL) {
 return EFI_DEVICE_ERROR;
@@ -155,8 +155,20 @@ FspmWrapperInit (
 {
   EFI_STATUS   Status;
 
+  Status = EFI_SUCCESS;
+
+#if FixedPcdGet8 (PcdFspModeSelection) == 1
   Status = PeiFspMemoryInit ();
   ASSERT_EFI_ERROR (Status);
+#else
+  PeiServicesInstallFvInfoPpi (
+NULL,
+(VOID *)(UINTN) PcdGet32 (PcdFspmBaseAddress),
+(UINT32)((EFI_FIRMWARE_VOLUME_HEADER *) (UINTN) PcdGet32 
(PcdFspmBaseAddress))->FvLength,
+NULL,
+NULL
+);
+#endif
 
   return Status;
 }
diff --git a/IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.c 
b/IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.c
index 70dac7a414..d11655df89 100644
--- a/IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.c
+++ b/IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.c
@@ -3,7 +3,7 @@
   register TemporaryRamDonePpi to call TempRamExit API, and register 
MemoryDiscoveredPpi
   notify to call FspSiliconInit API.
 
-  Copyright (c) 2014 - 2017, Intel Corporation. All rights reserved.
+  Copyright (c) 2014 - 2018, Intel Corporation. All rights reserved.
   This program and the accompanying materials
   are licensed and made available under the terms and conditions of the BSD 
License
   which accompanies this distribution.  The full text of the license may be 
found at
@@ -349,7 +349,17 @@ FspsWrapperPeimEntryPoint (
 {
   DEBUG ((DEBUG_INFO, "FspsWrapperPeimEntryPoint\n"));
 
-  FspsWrapperInit ();
+#if FixedPcdGet8 (PcdFspModeSelection) == 1
+FspsWrapperInit ();
+#else
+PeiServicesInstallFvInfoPpi (
+  NULL,
+  (VOID *)(UINTN) PcdGet32 (PcdFspsBaseAddress),
+  (UINT32)((EFI_FIRMWARE_VOLUME_HEADER *) (UINTN) PcdGet32 
(PcdFspsBaseAddress))->FvLength,
+  NULL,
+  NULL
+  );
+#endif
 
   return EFI_SUCCESS;
 }
diff --git a/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.inf 
b/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.inf
index 542356b582..b3776a80f3 100644
--- a/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.inf
+++ b/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.inf
@@ -6,7 +6,7 @@
 # register TemporaryRamDonePpi to call TempRamExit API, and register 
MemoryDiscoveredPpi
 # notify to call FspSiliconInit API.
 #
-#  Copyright (c) 2014 - 2017, Intel Corporation. All rights reserved.
+#  Copyright (c) 2014 - 2018, Intel Corporation. All rights reserved.
 #
 #  This program and the accompanying materials
 #  are licensed and made available under the terms and conditions of the BSD 
License
@@ -61,6 +61,7 @@
 [Pcd]
   gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress ## CONSUMES
   gIntelFsp2WrapperTokenSpaceGuid.PcdFspmUpdDataAddress  ## CONSUMES
+  gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection## CONSUMES
 
 [Sources]
   FspmWrapperPeim.c
diff --git a/IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.inf 
b/IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.inf
index cd87a99c40..910286982b 100644
--- a/IntelFsp2

[edk2] [PATCH v2] IntelFsp2Pkg: Fixed potentially NULL pointer accessing

[Chasel, Chiu]

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1280

When copying IDT table in SecMain, the pointer might be
NULL so added the check to fix it.

Test: Verified on internal platform and boots successfully.

Cc: Jiewen Yao 
Cc: Desimone Nathaniel L 
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Chasel Chiu 
---
 IntelFsp2Pkg/FspSecCore/SecMain.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/IntelFsp2Pkg/FspSecCore/SecMain.c 
b/IntelFsp2Pkg/FspSecCore/SecMain.c
index f319c68cc5..70460a3c8b 100644
--- a/IntelFsp2Pkg/FspSecCore/SecMain.c
+++ b/IntelFsp2Pkg/FspSecCore/SecMain.c
@@ -100,7 +100,7 @@ SecStartup (
   // |---|>  TempRamBase
   IdtTableInStack.PeiService  = NULL;
   AsmReadIdtr (&IdtDescriptor);
-  if ((IdtDescriptor.Base == 0) && (IdtDescriptor.Limit == 0x)) {
+  if (IdtDescriptor.Base == 0) {
 ExceptionHandler = FspGetExceptionHandler(mIdtEntryTemplate);
 for (Index = 0; Index < FixedPcdGet8(PcdFspMaxInterruptSupported); Index 
++) {
   CopyMem ((VOID*)&IdtTableInStack.IdtTable[Index], 
(VOID*)&ExceptionHandler, sizeof (UINT64));
@@ -113,8 +113,9 @@ SecStartup (
   // ERROR: IDT table size from boot loader is larger than FSP can 
support, DeadLoop here!
   //
   CpuDeadLoop();
+} else {
+  CopyMem ((VOID *) (UINTN) &IdtTableInStack.IdtTable, (VOID *) 
IdtDescriptor.Base, IdtSize);
 }
-CopyMem ((VOID *) (UINTN) &IdtTableInStack.IdtTable, (VOID *) 
IdtDescriptor.Base, IdtSize);
   }
   IdtDescriptor.Base  = (UINTN) &IdtTableInStack.IdtTable;
   IdtDescriptor.Limit = (UINT16)(IdtSize - 1);
-- 
2.13.3.windows.1

___
edk2-devel mailing list
edk2-devel@lists.01.org
https://lists.01.org/mailman/listinfo/edk2-devel

[edk2] [PATCH] IntelFsp2Pkg: Fixed potentially NULL pointer accessing

[Chasel, Chiu]

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1280

When copying IDT table in SecMain, the pointer might be
NULL so added the check to fix it.

Test: Verified on internal platform and boots successfully.

Cc: Jiewen Yao 
Cc: Desimone Nathaniel L 
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Chasel Chiu 
---
 IntelFsp2Pkg/FspSecCore/SecMain.c | 8 +++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/IntelFsp2Pkg/FspSecCore/SecMain.c 
b/IntelFsp2Pkg/FspSecCore/SecMain.c
index f319c68cc5..aed8893ff0 100644
--- a/IntelFsp2Pkg/FspSecCore/SecMain.c
+++ b/IntelFsp2Pkg/FspSecCore/SecMain.c
@@ -113,8 +113,14 @@ SecStartup (
   // ERROR: IDT table size from boot loader is larger than FSP can 
support, DeadLoop here!
   //
   CpuDeadLoop();
+} else if (IdtDescriptor.Base == 0)  {
+  //
+  // ERROR: IDT table Base should not be zero, DeadLoop here!
+  //
+  CpuDeadLoop();
+} else {
+  CopyMem ((VOID *) (UINTN) &IdtTableInStack.IdtTable, (VOID *) 
IdtDescriptor.Base, IdtSize);
 }
-CopyMem ((VOID *) (UINTN) &IdtTableInStack.IdtTable, (VOID *) 
IdtDescriptor.Base, IdtSize);
   }
   IdtDescriptor.Base  = (UINTN) &IdtTableInStack.IdtTable;
   IdtDescriptor.Limit = (UINT16)(IdtSize - 1);
-- 
2.13.3.windows.1

___
edk2-devel mailing list
edk2-devel@lists.01.org
https://lists.01.org/mailman/listinfo/edk2-devel

[edk2] [PATCH] IntelFsp2Pkg: Fix GCC49/XCODE build failure

[Chasel, Chiu]

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1276

Fixed potentially uninitialized variable build failure
caused by commit: b1cc6f672f3b924cdb190e5b92db3b47f46a8911

Test: Verified on internal platform and boots successfully.

Cc: Jiewen Yao 
Cc: Desimone Nathaniel L 
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Chasel Chiu 
---
 IntelFsp2Pkg/FspSecCore/SecMain.c | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/IntelFsp2Pkg/FspSecCore/SecMain.c 
b/IntelFsp2Pkg/FspSecCore/SecMain.c
index ddbfc4fcdf..f319c68cc5 100644
--- a/IntelFsp2Pkg/FspSecCore/SecMain.c
+++ b/IntelFsp2Pkg/FspSecCore/SecMain.c
@@ -107,13 +107,12 @@ SecStartup (
 }
 IdtSize = sizeof (IdtTableInStack.IdtTable);
   } else {
-if (IdtDescriptor.Limit + 1 > sizeof (IdtTableInStack.IdtTable)) {
+IdtSize = IdtDescriptor.Limit + 1;
+if (IdtSize > sizeof (IdtTableInStack.IdtTable)) {
   //
   // ERROR: IDT table size from boot loader is larger than FSP can 
support, DeadLoop here!
   //
   CpuDeadLoop();
-} else {
-  IdtSize = IdtDescriptor.Limit + 1;
 }
 CopyMem ((VOID *) (UINTN) &IdtTableInStack.IdtTable, (VOID *) 
IdtDescriptor.Base, IdtSize);
   }
-- 
2.13.3.windows.1

___
edk2-devel mailing list
edk2-devel@lists.01.org
https://lists.01.org/mailman/listinfo/edk2-devel

[edk2] [PATCH v2] IntelFsp2Pkg: FSP should not override IDT

[Chasel, Chiu]

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1265

FSP should not override IDT table when it is initialized
by boot loader. IDT should be re-initialized in FSP only
when it is invalid.
To mitigate temporary memory usage a PCD
PcdFspMaxInterruptSupported created for platform to decide
how many interrupts the FSP IDT table can support.

Test: Verified on internal platform and boots successfully.

Cc: Jiewen Yao 
Cc: Desimone Nathaniel L 
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Chasel Chiu 
---
 IntelFsp2Pkg/FspSecCore/FspSecCoreM.inf |  1 +
 IntelFsp2Pkg/FspSecCore/SecMain.c   | 24 +++-
 IntelFsp2Pkg/FspSecCore/SecMain.h   |  6 ++
 IntelFsp2Pkg/IntelFsp2Pkg.dec   |  4 
 4 files changed, 26 insertions(+), 9 deletions(-)

diff --git a/IntelFsp2Pkg/FspSecCore/FspSecCoreM.inf 
b/IntelFsp2Pkg/FspSecCore/FspSecCoreM.inf
index c61af10b8a..dafe6f5993 100644
--- a/IntelFsp2Pkg/FspSecCore/FspSecCoreM.inf
+++ b/IntelFsp2Pkg/FspSecCore/FspSecCoreM.inf
@@ -62,6 +62,7 @@
   gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamSize  ## CONSUMES
   gIntelFsp2PkgTokenSpaceGuid.PcdFspTemporaryRamSize   ## CONSUMES
   gIntelFsp2PkgTokenSpaceGuid.PcdFspHeapSizePercentage ## CONSUMES
+  gIntelFsp2PkgTokenSpaceGuid.PcdFspMaxInterruptSupported  ## CONSUMES
 
 [Ppis]
   gEfiTemporaryRamSupportPpiGuid  ## PRODUCES
diff --git a/IntelFsp2Pkg/FspSecCore/SecMain.c 
b/IntelFsp2Pkg/FspSecCore/SecMain.c
index 37fd4dfdeb..ddbfc4fcdf 100644
--- a/IntelFsp2Pkg/FspSecCore/SecMain.c
+++ b/IntelFsp2Pkg/FspSecCore/SecMain.c
@@ -70,6 +70,7 @@ SecStartup (
   UINT32  Index;
   FSP_GLOBAL_DATA PeiFspData;
   UINT64  ExceptionHandler;
+  UINTN   IdtSize;
 
   //
   // Process all libraries constructor function linked to SecCore.
@@ -98,13 +99,26 @@ SecStartup (
   // |   |
   // |---|>  TempRamBase
   IdtTableInStack.PeiService  = NULL;
-  ExceptionHandler = FspGetExceptionHandler(mIdtEntryTemplate);
-  for (Index = 0; Index < SEC_IDT_ENTRY_COUNT; Index ++) {
-CopyMem ((VOID*)&IdtTableInStack.IdtTable[Index], 
(VOID*)&ExceptionHandler, sizeof (UINT64));
+  AsmReadIdtr (&IdtDescriptor);
+  if ((IdtDescriptor.Base == 0) && (IdtDescriptor.Limit == 0x)) {
+ExceptionHandler = FspGetExceptionHandler(mIdtEntryTemplate);
+for (Index = 0; Index < FixedPcdGet8(PcdFspMaxInterruptSupported); Index 
++) {
+  CopyMem ((VOID*)&IdtTableInStack.IdtTable[Index], 
(VOID*)&ExceptionHandler, sizeof (UINT64));
+}
+IdtSize = sizeof (IdtTableInStack.IdtTable);
+  } else {
+if (IdtDescriptor.Limit + 1 > sizeof (IdtTableInStack.IdtTable)) {
+  //
+  // ERROR: IDT table size from boot loader is larger than FSP can 
support, DeadLoop here!
+  //
+  CpuDeadLoop();
+} else {
+  IdtSize = IdtDescriptor.Limit + 1;
+}
+CopyMem ((VOID *) (UINTN) &IdtTableInStack.IdtTable, (VOID *) 
IdtDescriptor.Base, IdtSize);
   }
-
   IdtDescriptor.Base  = (UINTN) &IdtTableInStack.IdtTable;
-  IdtDescriptor.Limit = (UINT16)(sizeof (IdtTableInStack.IdtTable) - 1);
+  IdtDescriptor.Limit = (UINT16)(IdtSize - 1);
 
   AsmWriteIdtr (&IdtDescriptor);
 
diff --git a/IntelFsp2Pkg/FspSecCore/SecMain.h 
b/IntelFsp2Pkg/FspSecCore/SecMain.h
index 291bc5ca5c..19ac2fbfc1 100644
--- a/IntelFsp2Pkg/FspSecCore/SecMain.h
+++ b/IntelFsp2Pkg/FspSecCore/SecMain.h
@@ -1,6 +1,6 @@
 /** @file
 
-  Copyright (c) 2014 - 2016, Intel Corporation. All rights reserved.
+  Copyright (c) 2014 - 2018, Intel Corporation. All rights reserved.
   This program and the accompanying materials
   are licensed and made available under the terms and conditions of the BSD 
License
   which accompanies this distribution.  The full text of the license may be 
found at
@@ -29,8 +29,6 @@
 #include 
 #include 
 
-#define SEC_IDT_ENTRY_COUNT34
-
 typedef VOID (*PEI_CORE_ENTRY) ( \
   IN CONST  EFI_SEC_PEI_HAND_OFF*SecCoreData, \
   IN CONST  EFI_PEI_PPI_DESCRIPTOR  *PpiList \
@@ -38,7 +36,7 @@ typedef VOID (*PEI_CORE_ENTRY) ( \
 
 typedef struct _SEC_IDT_TABLE {
   EFI_PEI_SERVICES  *PeiService;
-  UINT64IdtTable[SEC_IDT_ENTRY_COUNT];
+  UINT64IdtTable[FixedPcdGet8 (PcdFspMaxInterruptSupported)];
 } SEC_IDT_TABLE;
 
 /**
diff --git a/IntelFsp2Pkg/IntelFsp2Pkg.dec b/IntelFsp2Pkg/IntelFsp2Pkg.dec
index 5b037d65e2..50496241da 100644
--- a/IntelFsp2Pkg/IntelFsp2Pkg.dec
+++ b/IntelFsp2Pkg/IntelFsp2Pkg.dec
@@ -86,6 +86,10 @@
   # x % of FSP temporary memory will be used for heap
   # (100 - x) % of FSP temporary memory will be used for stack
   gIntelFsp2PkgTokenSpaceGuid.PcdFspHeapSizePercentage|50| 
UINT8|0x1004
+  #
+  # Maximal Interrupt supported in IDT table.
+  #
+  gIntelFsp2PkgTokenSpaceGuid.PcdFspMaxInterruptSupported |34| 
UINT8|0x100

[edk2] [PATCH] IntelFsp2Pkg: FSP should not override IDT

[Chasel, Chiu]

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1265

FSP should not override IDT table when it is initialized
by boot loader. IDT should be re-initialized in FSP only
when it is invalid.

Test: Verified on internal platform and boots successfully.

Cc: Jiewen Yao 
Cc: Desimone Nathaniel L 
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Chasel Chiu 
---
 IntelFsp2Pkg/FspSecCore/SecMain.c | 22 +-
 1 file changed, 17 insertions(+), 5 deletions(-)

diff --git a/IntelFsp2Pkg/FspSecCore/SecMain.c 
b/IntelFsp2Pkg/FspSecCore/SecMain.c
index 37fd4dfdeb..5912221204 100644
--- a/IntelFsp2Pkg/FspSecCore/SecMain.c
+++ b/IntelFsp2Pkg/FspSecCore/SecMain.c
@@ -70,6 +70,7 @@ SecStartup (
   UINT32  Index;
   FSP_GLOBAL_DATA PeiFspData;
   UINT64  ExceptionHandler;
+  UINTN   IdtSize;
 
   //
   // Process all libraries constructor function linked to SecCore.
@@ -98,13 +99,24 @@ SecStartup (
   // |   |
   // |---|>  TempRamBase
   IdtTableInStack.PeiService  = NULL;
-  ExceptionHandler = FspGetExceptionHandler(mIdtEntryTemplate);
-  for (Index = 0; Index < SEC_IDT_ENTRY_COUNT; Index ++) {
-CopyMem ((VOID*)&IdtTableInStack.IdtTable[Index], 
(VOID*)&ExceptionHandler, sizeof (UINT64));
+  AsmReadIdtr (&IdtDescriptor);
+  if ((IdtDescriptor.Base == 0) && (IdtDescriptor.Limit == 0x)) {
+ExceptionHandler = FspGetExceptionHandler(mIdtEntryTemplate);
+for (Index = 0; Index < SEC_IDT_ENTRY_COUNT; Index ++) {
+  CopyMem ((VOID*)&IdtTableInStack.IdtTable[Index], 
(VOID*)&ExceptionHandler, sizeof (UINT64));
+}
+IdtSize = sizeof (IdtTableInStack.IdtTable);
+  } else {
+// Get minimum size
+if (IdtDescriptor.Limit + 1 > sizeof (IdtTableInStack.IdtTable)) {
+  IdtSize = sizeof (IdtTableInStack.IdtTable);
+} else {
+  IdtSize = IdtDescriptor.Limit + 1;
+}
+CopyMem ((VOID *) (UINTN) &IdtTableInStack.IdtTable, (VOID *) 
IdtDescriptor.Base, IdtSize);
   }
-
   IdtDescriptor.Base  = (UINTN) &IdtTableInStack.IdtTable;
-  IdtDescriptor.Limit = (UINT16)(sizeof (IdtTableInStack.IdtTable) - 1);
+  IdtDescriptor.Limit = (UINT16)(IdtSize - 1);
 
   AsmWriteIdtr (&IdtDescriptor);
 
-- 
2.13.3.windows.1

___
edk2-devel mailing list
edk2-devel@lists.01.org
https://lists.01.org/mailman/listinfo/edk2-devel

[edk2] [PATCH v3] IntelFsp2Pkg: Support FSP Dispatch mode

[Chasel, Chiu]

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1241

Add support for both API (original mode) and DISPATCH mode:
1. Add FspMode field from reserved byte of Global
   Data Structure to tell which mode is selected by boot
   loader. If boot loader invoking FSP-M API this field
   will remain as default 0 (API mode), otherwise platform
   FSP should set this field to 1 (Dispatch mode) when
   initializing Global Data Structure.
2. gFspInApiModePpiGuid will be instaled when FSP running in API
   mode and modules only for API mode should have this in depex.
3. If it is DISPATCH mode, FSP will return to PEI dispatcher,
   not directly return to boot loader.
4. DISPATCH mode supports DXE NotifyPhase drivers so FSP
   will not wait for PEI NotifyPhase callbacks, instead it
   will install gFspReadyForNotifyPhasePpiGuid PPI for
   platform to complete late initialization before transferring
   to DXE.

Test: Verified FSP API and DISPATCH modes on 2 internal
  platforms and both boot successfully.

Cc: Jiewen Yao 
Cc: Desimone Nathaniel L 
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Chasel Chiu 
---
 IntelFsp2Pkg/FspNotifyPhase/FspNotifyPhasePeim.c   | 59 +---
 IntelFsp2Pkg/FspNotifyPhase/FspNotifyPhasePeim.inf |  3 +-
 IntelFsp2Pkg/FspSecCore/FspSecCoreM.inf|  2 +-
 IntelFsp2Pkg/FspSecCore/SecMain.c  |  5 ++
 IntelFsp2Pkg/Include/FspGlobalData.h   |  8 ++-
 IntelFsp2Pkg/IntelFsp2Pkg.dec  | 12 
 .../Library/BaseFspCommonLib/FspCommonLib.c| 22 +++---
 .../Library/BaseFspPlatformLib/FspPlatformNotify.c | 78 +-
 8 files changed, 122 insertions(+), 67 deletions(-)

diff --git a/IntelFsp2Pkg/FspNotifyPhase/FspNotifyPhasePeim.c 
b/IntelFsp2Pkg/FspNotifyPhase/FspNotifyPhasePeim.c
index 52435fa0b2..cbea3a7eaa 100644
--- a/IntelFsp2Pkg/FspNotifyPhase/FspNotifyPhasePeim.c
+++ b/IntelFsp2Pkg/FspNotifyPhase/FspNotifyPhasePeim.c
@@ -48,6 +48,12 @@ CONST EFI_PEI_PPI_DESCRIPTOR gEndOfPeiSignalPpi = {
   NULL
 };
 
+CONST EFI_PEI_PPI_DESCRIPTOR gFspReadyForNotifyPhasePpi = {
+  (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
+  &gFspReadyForNotifyPhasePpiGuid,
+  NULL
+};
+
 /**
 
This function waits for FSP notify.
@@ -88,13 +94,15 @@ WaitForNotify (
   //
   FspWaitForNotify ();
 
-  //
-  // Should not come here
-  //
-  while (TRUE) {
-DEBUG ((DEBUG_ERROR, "No FSP API should be called after FSP is DONE!\n"));
-SetFspApiReturnStatus (EFI_UNSUPPORTED);
-Pei2LoaderSwitchStack ();
+  if (GetFspGlobalDataPointer ()->FspMode == FSP_IN_API_MODE) {
+//
+// Should not come here
+//
+while (TRUE) {
+  DEBUG ((DEBUG_ERROR, "No FSP API should be called after FSP is 
DONE!\n"));
+  SetFspApiReturnStatus (EFI_UNSUPPORTED);
+  Pei2LoaderSwitchStack ();
+}
   }
 
   return EFI_SUCCESS;
@@ -121,22 +129,27 @@ FspNotifyPhasePeimEntryPoint (
 
   DEBUG ((DEBUG_INFO | DEBUG_INIT, "The entry of FspNotificationPeim\n"));
 
-  //
-  // Locate old DXE IPL PPI
-  //
-  Status = PeiServicesLocatePpi (
-&gEfiDxeIplPpiGuid,
-0,
-&OldDescriptor,
-&OldDxeIplPpi
-);
-  ASSERT_EFI_ERROR (Status);
-
-  //
-  // Re-install the DXE IPL PPI to wait for notify
-  //
-  Status = PeiServicesReInstallPpi (OldDescriptor, &mInstallDxeIplPpi);
-  ASSERT_EFI_ERROR (Status);
+  if (GetFspGlobalDataPointer ()->FspMode == FSP_IN_API_MODE) {
+//
+// Locate old DXE IPL PPI
+//
+Status = PeiServicesLocatePpi (
+  &gEfiDxeIplPpiGuid,
+  0,
+  &OldDescriptor,
+  &OldDxeIplPpi
+  );
+ASSERT_EFI_ERROR (Status);
+
+//
+// Re-install the DXE IPL PPI to wait for notify
+//
+Status = PeiServicesReInstallPpi (OldDescriptor, &mInstallDxeIplPpi);
+ASSERT_EFI_ERROR (Status);
+  } else {
+Status = PeiServicesInstallPpi (&gFspReadyForNotifyPhasePpi);
+ASSERT_EFI_ERROR (Status);
+  }
 
   return EFI_SUCCESS;
 }
diff --git a/IntelFsp2Pkg/FspNotifyPhase/FspNotifyPhasePeim.inf 
b/IntelFsp2Pkg/FspNotifyPhase/FspNotifyPhasePeim.inf
index a0bc37580d..b0f6768cfa 100644
--- a/IntelFsp2Pkg/FspNotifyPhase/FspNotifyPhasePeim.inf
+++ b/IntelFsp2Pkg/FspNotifyPhase/FspNotifyPhasePeim.inf
@@ -1,7 +1,7 @@
 ## @file
 # Component information file for the FSP notify phase PEI module.
 #
-#  Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.
+#  Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.
 #  This program and the accompanying materials
 #  are licensed and made available under the terms and conditions of the BSD 
License
 #  which accompanies this distribution.  The full text of the license may be 
found at
@@ -37,6 +37,7 @@
 [Ppis]
   gEfiDxeIplPpiGuid   ## PRODUCES
   gEfiEndOfPeiSignalPpiGuid 

[edk2] [PATCH v2] IntelFsp2Pkg: Support FSP Dispatch mode

[Chasel, Chiu]

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1241

Add support for both API (original mode) and DISPATCH mode:
1. Add FspApiModeEnabled field from reserved byte of Global
   Data Structure to tell which mode is selected by boot
   loader. If boot loader invoking FSP-M API this field
   will be initialized to 1, otherwise platform FSP should
   set this field to 0 when initializing Global Data
   Structure for DISPATCH mode.
2. gFspApiModePpiGuid will be instaled when FSP running in API
   mode and modules only for API mode should have this in depex.
3. If it is DISPATCH mode, FSP will return to PEI dispatcher,
   not directly return to boot loader.
4. DISPATCH mode supports DXE NotifyPhase drivers so FSP
   will not wait for PEI NotifyPhase callbacks, instead it
   will install gFspReadyForNotifyPhasePpiGuid PPI for
   platform to complete late initialization before transferring
   to DXE.

Test: Verified FSP API and DISPATCH modes on 2 internal
  platforms and both boot successfully.

Cc: Jiewen Yao 
Cc: Desimone Nathaniel L 
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Chasel Chiu 
---
 IntelFsp2Pkg/FspNotifyPhase/FspNotifyPhasePeim.c   | 59 +---
 IntelFsp2Pkg/FspNotifyPhase/FspNotifyPhasePeim.inf |  3 +-
 IntelFsp2Pkg/FspSecCore/FspSecCoreM.inf|  2 +-
 IntelFsp2Pkg/FspSecCore/SecFsp.c   |  6 +-
 IntelFsp2Pkg/FspSecCore/SecMain.c  |  5 ++
 IntelFsp2Pkg/Include/FspGlobalData.h   |  5 +-
 IntelFsp2Pkg/IntelFsp2Pkg.dec  | 11 +++
 .../Library/BaseFspCommonLib/FspCommonLib.c| 22 +++---
 .../Library/BaseFspPlatformLib/FspPlatformNotify.c | 78 +-
 9 files changed, 122 insertions(+), 69 deletions(-)

diff --git a/IntelFsp2Pkg/FspNotifyPhase/FspNotifyPhasePeim.c 
b/IntelFsp2Pkg/FspNotifyPhase/FspNotifyPhasePeim.c
index 52435fa0b2..0f8743ade2 100644
--- a/IntelFsp2Pkg/FspNotifyPhase/FspNotifyPhasePeim.c
+++ b/IntelFsp2Pkg/FspNotifyPhase/FspNotifyPhasePeim.c
@@ -48,6 +48,12 @@ CONST EFI_PEI_PPI_DESCRIPTOR gEndOfPeiSignalPpi = {
   NULL
 };
 
+CONST EFI_PEI_PPI_DESCRIPTOR gFspReadyForNotifyPhasePpi = {
+  (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
+  &gFspReadyForNotifyPhasePpiGuid,
+  NULL
+};
+
 /**
 
This function waits for FSP notify.
@@ -88,13 +94,15 @@ WaitForNotify (
   //
   FspWaitForNotify ();
 
-  //
-  // Should not come here
-  //
-  while (TRUE) {
-DEBUG ((DEBUG_ERROR, "No FSP API should be called after FSP is DONE!\n"));
-SetFspApiReturnStatus (EFI_UNSUPPORTED);
-Pei2LoaderSwitchStack ();
+  if (GetFspGlobalDataPointer ()->FspApiModeEnabled == TRUE) {
+//
+// Should not come here
+//
+while (TRUE) {
+  DEBUG ((DEBUG_ERROR, "No FSP API should be called after FSP is 
DONE!\n"));
+  SetFspApiReturnStatus (EFI_UNSUPPORTED);
+  Pei2LoaderSwitchStack ();
+}
   }
 
   return EFI_SUCCESS;
@@ -121,22 +129,27 @@ FspNotifyPhasePeimEntryPoint (
 
   DEBUG ((DEBUG_INFO | DEBUG_INIT, "The entry of FspNotificationPeim\n"));
 
-  //
-  // Locate old DXE IPL PPI
-  //
-  Status = PeiServicesLocatePpi (
-&gEfiDxeIplPpiGuid,
-0,
-&OldDescriptor,
-&OldDxeIplPpi
-);
-  ASSERT_EFI_ERROR (Status);
-
-  //
-  // Re-install the DXE IPL PPI to wait for notify
-  //
-  Status = PeiServicesReInstallPpi (OldDescriptor, &mInstallDxeIplPpi);
-  ASSERT_EFI_ERROR (Status);
+  if (GetFspGlobalDataPointer ()->FspApiModeEnabled == TRUE) {
+//
+// Locate old DXE IPL PPI
+//
+Status = PeiServicesLocatePpi (
+  &gEfiDxeIplPpiGuid,
+  0,
+  &OldDescriptor,
+  &OldDxeIplPpi
+  );
+ASSERT_EFI_ERROR (Status);
+
+//
+// Re-install the DXE IPL PPI to wait for notify
+//
+Status = PeiServicesReInstallPpi (OldDescriptor, &mInstallDxeIplPpi);
+ASSERT_EFI_ERROR (Status);
+  } else {
+Status = PeiServicesInstallPpi (&gFspReadyForNotifyPhasePpi);
+ASSERT_EFI_ERROR (Status);
+  }
 
   return EFI_SUCCESS;
 }
diff --git a/IntelFsp2Pkg/FspNotifyPhase/FspNotifyPhasePeim.inf 
b/IntelFsp2Pkg/FspNotifyPhase/FspNotifyPhasePeim.inf
index a0bc37580d..b0f6768cfa 100644
--- a/IntelFsp2Pkg/FspNotifyPhase/FspNotifyPhasePeim.inf
+++ b/IntelFsp2Pkg/FspNotifyPhase/FspNotifyPhasePeim.inf
@@ -1,7 +1,7 @@
 ## @file
 # Component information file for the FSP notify phase PEI module.
 #
-#  Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.
+#  Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.
 #  This program and the accompanying materials
 #  are licensed and made available under the terms and conditions of the BSD 
License
 #  which accompanies this distribution.  The full text of the license may be 
found at
@@ -37,6 +37,7 @@
 [Ppis]
   gEfiDxeIplPpiGuid 

[edk2] [PATCH] IntelFsp2Pkg: Support FSP API mode indicator

[Chasel, Chiu]

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1241

FSP will support both API and DISPATCH mode and require one
field from Global Data Structure to tell which mode is
selected by boot loader.
Use one reserved byte for FSP API mode indicator -
FspApiModeEnabled and maintain backward compatibility:
1. If platform FSP supports DISPATCH mode, it must
   initialize this new field.
2. If platform FSP does not support DISPATCH mode,
   this new field has no effect/not used.

Test: Verified compiling without issue.

Cc: Jiewen Yao 
Cc: Desimone Nathaniel L 
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Chasel Chiu 
---
 IntelFsp2Pkg/Include/FspGlobalData.h | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/IntelFsp2Pkg/Include/FspGlobalData.h 
b/IntelFsp2Pkg/Include/FspGlobalData.h
index 7de26606a7..ccc9ecd78a 100644
--- a/IntelFsp2Pkg/Include/FspGlobalData.h
+++ b/IntelFsp2Pkg/Include/FspGlobalData.h
@@ -1,6 +1,6 @@
 /** @file
 
-  Copyright (c) 2014 - 2016, Intel Corporation. All rights reserved.
+  Copyright (c) 2014 - 2018, Intel Corporation. All rights reserved.
   This program and the accompanying materials
   are licensed and made available under the terms and conditions of the BSD 
License
   which accompanies this distribution.  The full text of the license may be 
found at
@@ -54,7 +54,8 @@ typedef struct  {
VOID   *MemoryInitUpdPtr;
VOID   *SiliconInitUpdPtr;
UINT8  ApiIdx;
-   UINT8  Reserved3[31];
+   UINT8  FspApiModeEnabled; // 1: API mode; 0: DISPATCH mode
+   UINT8  Reserved3[30];
UINT32 PerfSig;
UINT16 PerfLen;
UINT16 Reserved4;
-- 
2.13.3.windows.1

___
edk2-devel mailing list
edk2-devel@lists.01.org
https://lists.01.org/mailman/listinfo/edk2-devel

[edk2] [PATCH V2] IntelFsp2Pkg/GenCfgOpt.py: Support PCD input from command line

[Chasel, Chiu]

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1231

Build system already support override PCD value by command
line so add this support to GenCfgOpt.py
Also update revision to 0.53

Test: Verified UPD header files generated can reflect different
  PCD values from --pcd build command input

Cc: Jiewen Yao 
Cc: Gao Liming 
Cc: Zhu Yonghong 
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Chasel Chiu 
---
 IntelFsp2Pkg/Tools/GenCfgOpt.py | 17 -
 1 file changed, 16 insertions(+), 1 deletion(-)

diff --git a/IntelFsp2Pkg/Tools/GenCfgOpt.py b/IntelFsp2Pkg/Tools/GenCfgOpt.py
index 059cfcb7e4..15d33582ef 100644
--- a/IntelFsp2Pkg/Tools/GenCfgOpt.py
+++ b/IntelFsp2Pkg/Tools/GenCfgOpt.py
@@ -88,6 +88,8 @@ are permitted provided that the following conditions are met:
 **/
 """
 
+BuildOptionPcd = []
+
 class CLogicalExpression:
 def __init__(self):
 self.index= 0
@@ -561,6 +563,12 @@ EndList
 self._PcdsDict[Match.group(1)] = Match.group(2)
 if self.Debug:
 print "INFO : PCD %s = [ %s ]" % (Match.group(1), 
Match.group(2))
+i = 0
+while i < len(BuildOptionPcd):
+Match = re.match("\s*([\w\.]+)\s*\=\s*(\w+)", 
BuildOptionPcd[i])
+if Match:
+self._PcdsDict[Match.group(1)] = Match.group(2)
+i += 1
 else:
 Match = re.match("^\s*#\s+(!BSF|@Bsf|!HDR)\s+(.+)", DscLine)
 if Match:
@@ -1462,7 +1470,7 @@ EndList
 
 
 def Usage():
-print "GenCfgOpt Version 0.52"
+print "GenCfgOpt Version 0.53"
 print "Usage:"
 print "GenCfgOpt  UPDTXT  PlatformDscFile BuildFvDir 
[-D Macros]"
 print "GenCfgOpt  HEADER  PlatformDscFile BuildFvDir  InputHFile 
[-D Macros]"
@@ -1472,7 +1480,14 @@ def Main():
 #
 # Parse the options and args
 #
+i = 1
+
 GenCfgOpt = CGenCfgOpt()
+while i < len(sys.argv):
+if sys.argv[i].strip().lower() == "--pcd":
+BuildOptionPcd.append(sys.argv[i+1])
+i += 1
+i += 1
 argc = len(sys.argv)
 if argc < 4:
 Usage()
-- 
2.13.3.windows.1

___
edk2-devel mailing list
edk2-devel@lists.01.org
https://lists.01.org/mailman/listinfo/edk2-devel

[edk2] [PATCH] IntelFsp2Pkg/GenCfgOpt.py: Support PCD input from command line

[Chasel, Chiu]

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1231

Build system already support override PCD value by command
line so add this support to GenCfgOpt.py

Test: Verified UPD header files generated can reflect different
  PCD values from --pcd build command input

Cc: Jiewen Yao 
Cc: Gao Liming 
Cc: Zhu Yonghong 
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Chasel Chiu 
---
 IntelFsp2Pkg/Tools/GenCfgOpt.py | 15 +++
 1 file changed, 15 insertions(+)

diff --git a/IntelFsp2Pkg/Tools/GenCfgOpt.py b/IntelFsp2Pkg/Tools/GenCfgOpt.py
index 059cfcb7e4..efc2eea6ab 100644
--- a/IntelFsp2Pkg/Tools/GenCfgOpt.py
+++ b/IntelFsp2Pkg/Tools/GenCfgOpt.py
@@ -88,6 +88,8 @@ are permitted provided that the following conditions are met:
 **/
 """
 
+BuildOptionPcd = []
+
 class CLogicalExpression:
 def __init__(self):
 self.index= 0
@@ -561,6 +563,12 @@ EndList
 self._PcdsDict[Match.group(1)] = Match.group(2)
 if self.Debug:
 print "INFO : PCD %s = [ %s ]" % (Match.group(1), 
Match.group(2))
+i = 0
+while i < len(BuildOptionPcd):
+Match = re.match("\s*([\w\.]+)\s*\=\s*(\w+)", 
BuildOptionPcd[i])
+if Match:
+self._PcdsDict[Match.group(1)] = Match.group(2)
+i += 1
 else:
 Match = re.match("^\s*#\s+(!BSF|@Bsf|!HDR)\s+(.+)", DscLine)
 if Match:
@@ -1472,7 +1480,14 @@ def Main():
 #
 # Parse the options and args
 #
+i = 1
+
 GenCfgOpt = CGenCfgOpt()
+while i < len(sys.argv):
+if sys.argv[i].strip().lower() == "--pcd":
+BuildOptionPcd.append(sys.argv[i+1])
+i += 1
+i += 1
 argc = len(sys.argv)
 if argc < 4:
 Usage()
-- 
2.13.3.windows.1

___
edk2-devel mailing list
edk2-devel@lists.01.org
https://lists.01.org/mailman/listinfo/edk2-devel

[edk2] [PATCH] IntelFsp2(Wrapper)Pkg: Revert from e8208100 to 737f812b

[Chasel, Chiu]

Commit formats had issues so reverted 9 commits
from IntelFsp2Pkg and IntelFsp2WrapperPkg.
Will re-submit them with correct formats.

Cc: Jiewen Yao 
Cc: Star Zeng 
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Chasel Chiu 
---
 IntelFsp2Pkg/FspSecCore/FspSecCoreM.inf|  6 ++
 IntelFsp2Pkg/FspSecCore/FspSecCoreS.inf| 11 +++
 IntelFsp2Pkg/FspSecCore/FspSecCoreT.inf|  5 ++
 .../Library/BaseFspCommonLib/BaseFspCommonLib.inf  |  5 ++
 .../BaseFspPlatformLib/BaseFspPlatformLib.inf  |  9 +++
 .../BaseFspSwitchStackLib.inf  |  4 ++
 IntelFsp2Pkg/Tools/GenCfgOpt.py| 83 ++
 .../FspWrapperNotifyDxe/FspWrapperNotifyDxe.inf|  1 +
 .../BaseFspWrapperPlatformLibSample.inf|  3 +
 9 files changed, 51 insertions(+), 76 deletions(-)

diff --git a/IntelFsp2Pkg/FspSecCore/FspSecCoreM.inf 
b/IntelFsp2Pkg/FspSecCore/FspSecCoreM.inf
index c657862deb..0500a197f8 100644
--- a/IntelFsp2Pkg/FspSecCore/FspSecCoreM.inf
+++ b/IntelFsp2Pkg/FspSecCore/FspSecCoreM.inf
@@ -58,11 +58,17 @@
   FspSecPlatformLib
 
 [Pcd]
+  gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress   ## UNDEFINED
+  gIntelFsp2PkgTokenSpaceGuid.PcdGlobalDataPointerAddress  ## CONSUMES
   gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamBase  ## CONSUMES
   gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamSize  ## CONSUMES
   gIntelFsp2PkgTokenSpaceGuid.PcdFspTemporaryRamSize   ## CONSUMES
   gIntelFsp2PkgTokenSpaceGuid.PcdFspHeapSizePercentage ## CONSUMES
 
+[FixedPcd]
+  gIntelFsp2PkgTokenSpaceGuid.PcdFspMaxPatchEntry  ## CONSUMES
+  gIntelFsp2PkgTokenSpaceGuid.PcdFspMaxPerfEntry   ## CONSUMES
+
 [Ppis]
   gEfiTemporaryRamSupportPpiGuid  ## PRODUCES
 
diff --git a/IntelFsp2Pkg/FspSecCore/FspSecCoreS.inf 
b/IntelFsp2Pkg/FspSecCore/FspSecCoreS.inf
index dd3f8e56a0..a3563dd8cf 100644
--- a/IntelFsp2Pkg/FspSecCore/FspSecCoreS.inf
+++ b/IntelFsp2Pkg/FspSecCore/FspSecCoreS.inf
@@ -52,6 +52,17 @@
   FspCommonLib
   FspSecPlatformLib
 
+[Pcd]
+  gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress   ## UNDEFINED
+  gIntelFsp2PkgTokenSpaceGuid.PcdGlobalDataPointerAddress  ## CONSUMES
+  gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamBase  ## CONSUMES
+  gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamSize  ## CONSUMES
+  gIntelFsp2PkgTokenSpaceGuid.PcdFspTemporaryRamSize   ## CONSUMES
+
+[FixedPcd]
+  gIntelFsp2PkgTokenSpaceGuid.PcdFspMaxPatchEntry  ## CONSUMES
+  gIntelFsp2PkgTokenSpaceGuid.PcdFspMaxPerfEntry   ## CONSUMES
+
 [Ppis]
   gEfiTemporaryRamSupportPpiGuid  ## PRODUCES
 
diff --git a/IntelFsp2Pkg/FspSecCore/FspSecCoreT.inf 
b/IntelFsp2Pkg/FspSecCore/FspSecCoreT.inf
index aff4b23f88..cf6a1918a3 100644
--- a/IntelFsp2Pkg/FspSecCore/FspSecCoreT.inf
+++ b/IntelFsp2Pkg/FspSecCore/FspSecCoreT.inf
@@ -53,9 +53,14 @@
   FspSecPlatformLib
 
 [Pcd]
+  gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress   ## UNDEFINED
   gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamBase  ## CONSUMES
   gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamSize  ## CONSUMES
   gIntelFsp2PkgTokenSpaceGuid.PcdFspReservedBufferSize ## CONSUMES
 
+[FixedPcd]
+  gIntelFsp2PkgTokenSpaceGuid.PcdFspMaxPatchEntry  ## CONSUMES
+  gIntelFsp2PkgTokenSpaceGuid.PcdFspMaxPerfEntry   ## CONSUMES
+
 [Ppis]
   gEfiTemporaryRamSupportPpiGuid  ## PRODUCES
diff --git a/IntelFsp2Pkg/Library/BaseFspCommonLib/BaseFspCommonLib.inf 
b/IntelFsp2Pkg/Library/BaseFspCommonLib/BaseFspCommonLib.inf
index ff82f8040b..c9d98357e2 100644
--- a/IntelFsp2Pkg/Library/BaseFspCommonLib/BaseFspCommonLib.inf
+++ b/IntelFsp2Pkg/Library/BaseFspCommonLib/BaseFspCommonLib.inf
@@ -33,3 +33,8 @@
 [Pcd]
   gIntelFsp2PkgTokenSpaceGuid.PcdGlobalDataPointerAddress  ## CONSUMES
 
+[FixedPcd]
+  gIntelFsp2PkgTokenSpaceGuid.PcdFspMaxPatchEntry  ## CONSUMES
+  gIntelFsp2PkgTokenSpaceGuid.PcdFspMaxPerfEntry   ## CONSUMES
+  gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamBase  ## CONSUMES
+  gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamSize  ## CONSUMES
diff --git a/IntelFsp2Pkg/Library/BaseFspPlatformLib/BaseFspPlatformLib.inf 
b/IntelFsp2Pkg/Library/BaseFspPlatformLib/BaseFspPlatformLib.inf
index b9e8a61809..907482daed 100644
--- a/IntelFsp2Pkg/Library/BaseFspPlatformLib/BaseFspPlatformLib.inf
+++ b/IntelFsp2Pkg/Library/BaseFspPlatformLib/BaseFspPlatformLib.inf
@@ -35,6 +35,12 @@
   PerformanceLib
   ReportStatusCodeLib
 
+[Pcd]
+  gIntelFsp2PkgTokenSpaceGuid.PcdGlobalDataPointerAddress## CONSUMES
+  gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamBase## CONSUMES
+  gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamSize## CONSUMES
+  gIntelFsp2PkgTokenSpaceGuid.PcdFspTemporaryRamSize ## CONSUMES

[edk2] [PATCH] GenCfgOpt.py: remove tailing space from output file

[Chasel, Chiu]

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1212

UPD header files generated by GenCfgOpt.py may have
tailing white space from some of the UPD description in DSC,
especially when python script automatically switching lines
for long description string. This patch will always remove
tailing white space for UPD header files.

Test: Verified the patch can remove tailing space in
  output header files when UPD DSC contains intentional
  tailing white space.

Cc: Jiewen Yao 
Cc: Gao Liming 
Cc: Zhu Yonghong 
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Chasel Chiu 
---
 IntelFsp2Pkg/Tools/GenCfgOpt.py | 13 ++---
 1 file changed, 10 insertions(+), 3 deletions(-)

diff --git a/IntelFsp2Pkg/Tools/GenCfgOpt.py b/IntelFsp2Pkg/Tools/GenCfgOpt.py
index c9b7bc5373..7e61b00ab8 100644
--- a/IntelFsp2Pkg/Tools/GenCfgOpt.py
+++ b/IntelFsp2Pkg/Tools/GenCfgOpt.py
@@ -1,6 +1,6 @@
 ## @ GenCfgOpt.py
 #
-# Copyright (c) 2014 - 2017, Intel Corporation. All rights reserved.
+# Copyright (c) 2014 - 2018, Intel Corporation. All rights reserved.
 # This program and the accompanying materials are licensed and made available 
under
 # the terms and conditions of the BSD License that accompanies this 
distribution.
 # The full text of the license may be found at
@@ -976,6 +976,13 @@ EndList
 NewTextBody.extend(OldTextBody)
 return NewTextBody
 
+def WriteLinesWithoutTailingSpace (self, HeaderFd, Line):
+TxtBody2 = Line.splitlines(True)
+for Line2 in TxtBody2:
+Line2 = Line2.rstrip()
+Line2 += '\n'
+HeaderFd.write (Line2)
+return 0
 def CreateHeaderFile (self, InputHeaderFile):
 FvDir = self._FvDir
 
@@ -1175,7 +1182,7 @@ EndList
 Index += 1
 for Item in range(len(StructStart)):
 if Index >= StructStartWithComment[Item] and Index <= 
StructEnd[Item]:
-HeaderFd.write (Line)
+self.WriteLinesWithoutTailingSpace(HeaderFd, Line)
 HeaderFd.write("#pragma pack()\n\n")
 HeaderFd.write("#endif\n")
 HeaderFd.close()
@@ -1220,7 +1227,7 @@ EndList
 Index += 1
 for Item in range(len(StructStart)):
 if Index >= StructStartWithComment[Item] and Index <= 
StructEnd[Item]:
-HeaderFd.write (Line)
+self.WriteLinesWithoutTailingSpace(HeaderFd, Line)
 HeaderFd.write("#pragma pack()\n\n")
 HeaderFd.write("#endif\n")
 HeaderFd.close()
-- 
2.13.3.windows.1

___
edk2-devel mailing list
edk2-devel@lists.01.org
https://lists.01.org/mailman/listinfo/edk2-devel

[edk2] [PATCH] IntelFsp2Pkg/GenCfgOpt.py: Support UPD offset auto assignment

[Chasel, Chiu]

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1211

For reducing maintenance effort, the UPD offset can be
automatic assigned by GenCfgOpt.py following by alignment
requirements.

The usage model as below:
. If UPD offset in DSC file are all '*', GenCfgOpt.py will
  assign offset for all UPD automatically. In this case no
  need to manually hardcode offset to all UPD in DSC.

. If UPD offset in DSC file are all not '*', GenCfgOpt.py
  will use hardcoded offset directly (original usage model)

. Tool does not support mixing scenario so UPD offset in DSC
  should be all '*' or all hardcoded but not mixed.

In auto mode UPD offset will be assigned following natural
alignment (size aligned) rule and the whole structure size
will align to either 32bits or 64bits depends on maximal UPD
size in the structure.

Test: Verified by both UPD offset hardcoded or '*' in DSC and
  generated UPD header files are correct.

Cc: Jiewen Yao 
Cc: Gao Liming 
Cc: Zhu Yonghong 
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Chasel Chiu 
---
 IntelFsp2Pkg/Tools/GenCfgOpt.py | 68 +++--
 1 file changed, 65 insertions(+), 3 deletions(-)

diff --git a/IntelFsp2Pkg/Tools/GenCfgOpt.py b/IntelFsp2Pkg/Tools/GenCfgOpt.py
index c9b7bc5373..9b8943b702 100644
--- a/IntelFsp2Pkg/Tools/GenCfgOpt.py
+++ b/IntelFsp2Pkg/Tools/GenCfgOpt.py
@@ -1,6 +1,6 @@
 ## @ GenCfgOpt.py
 #
-# Copyright (c) 2014 - 2017, Intel Corporation. All rights reserved.
+# Copyright (c) 2014 - 2018, Intel Corporation. All rights reserved.
 # This program and the accompanying materials are licensed and made available 
under
 # the terms and conditions of the BSD License that accompanies this 
distribution.
 # The full text of the license may be found at
@@ -418,6 +418,8 @@ EndList
 return ""
 
 def ParseDscFile (self, DscFile, FvDir):
+Hardcode = False
+AutoAlign = False
 self._CfgItemList = []
 self._CfgPageDict = {}
 self._CfgBlkDict  = {}
@@ -438,6 +440,8 @@ EndList
 DscLines = DscFd.readlines()
 DscFd.close()
 
+MaxAlign = 32   #Default align to 32, but if there are 64 bit unit, 
align to 64
+SizeAlign = 0   #record the struct max align
 while len(DscLines):
 DscLine  = DscLines.pop(0).strip()
 Handle   = False
@@ -464,6 +468,7 @@ EndList
 ConfigDict['comment'] = ''
 ConfigDict['subreg']  = []
 IsUpdSect = True
+Offset= 0
 else:
 if IsDefSect or IsPcdSect or IsUpdSect or IsVpdSect:
 if re.match("^!else($|\s+#.+)", DscLine):
@@ -530,6 +535,7 @@ EndList
 NewDscLines = IncludeDsc.readlines()
 IncludeDsc.close()
 DscLines = NewDscLines + DscLines
+Offset = 0
 else:
 if DscLine.startswith('!'):
 print("ERROR: Unrecoginized 
directive for line '%s'" % DscLine)
@@ -620,13 +626,22 @@ EndList
 
 # Check VPD/UPD
 if IsUpdSect:
-Match = 
re.match("^([_a-zA-Z0-9]+).([_a-zA-Z0-9]+)\s*\|\s*(0x[0-9A-F]+)\s*\|\s*(\d+|0x[0-9a-fA-F]+)\s*\|\s*(.+)",DscLine)
+Match = 
re.match("^([_a-zA-Z0-9]+).([_a-zA-Z0-9]+)\s*\|\s*(0x[0-9A-F]+|\*)\s*\|\s*(\d+|0x[0-9a-fA-F]+)\s*\|\s*(.+)",DscLine)
 else:
 Match = 
re.match("^([_a-zA-Z0-9]+).([_a-zA-Z0-9]+)\s*\|\s*(0x[0-9A-F]+)(?:\s*\|\s*(.+))?",
  DscLine)
 if Match:
 ConfigDict['space']  = Match.group(1)
 ConfigDict['cname']  = Match.group(2)
-ConfigDict['offset'] = int (Match.group(3), 16)
+if Match.group(3) != '*':
+Hardcode = True
+Offset =  int (Match.group(3), 16)
+else:
+AutoAlign = True
+
+if Hardcode and AutoAlign:
+print("Hardcode and auto-align mixed mode is not 
supported by GenCfgOpt")
+raise SystemExit
+ConfigDict['offset'] = Offset
 if ConfigDict['order'] == -1:
 ConfigDict['order'] = ConfigDict['offset'] << 8
 else:
@@ -638,6 +653,7 @@ EndList
 Length  = int (Match.group(4), 16)
 else :
  

[edk2] [PATCH] IntelFsp2Pkg/GenCfgOpt.py: support FixedAtBuild PCD

[Chasel, Chiu]

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1210

FixedAtBuild PCD is suggested to be used instead
of FeatureFlag PCD so extend this tool to support.
Also skipped PCDs which commented out by '#'.

Test: Verified with FixedAtBuild PCD for including or
excluding lines in generated UPD header files successfully.

Cc: Jiewen Yao 
Cc: Gao Liming 
Cc: Zhu Yonghong 
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Chasel Chiu 
---
 IntelFsp2Pkg/Tools/GenCfgOpt.py | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/IntelFsp2Pkg/Tools/GenCfgOpt.py b/IntelFsp2Pkg/Tools/GenCfgOpt.py
index c9b7bc5373..32cf63ff03 100644
--- a/IntelFsp2Pkg/Tools/GenCfgOpt.py
+++ b/IntelFsp2Pkg/Tools/GenCfgOpt.py
@@ -1,6 +1,6 @@
 ## @ GenCfgOpt.py
 #
-# Copyright (c) 2014 - 2017, Intel Corporation. All rights reserved.
+# Copyright (c) 2014 - 2018, Intel Corporation. All rights reserved.
 # This program and the accompanying materials are licensed and made available 
under
 # the terms and conditions of the BSD License that accompanies this 
distribution.
 # The full text of the license may be found at
@@ -449,7 +449,7 @@ EndList
 IsUpdSect = False
 if  Match.group(1).lower() == "Defines".lower():
 IsDefSect = True
-if  Match.group(1).lower() == "PcdsFeatureFlag".lower():
+if  (Match.group(1).lower() == "PcdsFeatureFlag".lower() or 
Match.group(1).lower() == "PcdsFixedAtBuild".lower()):
 IsPcdSect = True
 elif Match.group(1).lower() == "PcdsDynamicVpd.Upd".lower():
 ConfigDict = {}
@@ -491,7 +491,7 @@ EndList
 IfStack.append(Result)
 ElifStack.append(0)
 else:
-Match  = re.match("!(if|elseif)\s+(.+)", DscLine)
+Match  = re.match("!(if|elseif)\s+(.+)", 
DscLine.split("#")[0])
 if Match:
 Result = self.EvaluateExpress(Match.group(2))
 if Match.group(1) == "if":
-- 
2.13.3.windows.1

___
edk2-devel mailing list
edk2-devel@lists.01.org
https://lists.01.org/mailman/listinfo/edk2-devel

[edk2] [PATCH] IntelFsp2Pkg/GenCfgOpt.py: support FixedAtBuild PCD

[Chasel, Chiu]

FixedAtBuild PCD is suggested to be used instead
of FeatureFlag PCD so extend this tool to support.
Also skipped PCDs which commented out by '#'.

Cc: Jiewen Yao 
Cc: Gao Liming 
Cc: Zhu Yonghong 
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Chasel Chiu 
---
 IntelFsp2Pkg/Tools/GenCfgOpt.py | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/IntelFsp2Pkg/Tools/GenCfgOpt.py b/IntelFsp2Pkg/Tools/GenCfgOpt.py
index c9b7bc5373..32cf63ff03 100644
--- a/IntelFsp2Pkg/Tools/GenCfgOpt.py
+++ b/IntelFsp2Pkg/Tools/GenCfgOpt.py
@@ -1,6 +1,6 @@
 ## @ GenCfgOpt.py
 #
-# Copyright (c) 2014 - 2017, Intel Corporation. All rights reserved.
+# Copyright (c) 2014 - 2018, Intel Corporation. All rights reserved.
 # This program and the accompanying materials are licensed and made available 
under
 # the terms and conditions of the BSD License that accompanies this 
distribution.
 # The full text of the license may be found at
@@ -449,7 +449,7 @@ EndList
 IsUpdSect = False
 if  Match.group(1).lower() == "Defines".lower():
 IsDefSect = True
-if  Match.group(1).lower() == "PcdsFeatureFlag".lower():
+if  (Match.group(1).lower() == "PcdsFeatureFlag".lower() or 
Match.group(1).lower() == "PcdsFixedAtBuild".lower()):
 IsPcdSect = True
 elif Match.group(1).lower() == "PcdsDynamicVpd.Upd".lower():
 ConfigDict = {}
@@ -491,7 +491,7 @@ EndList
 IfStack.append(Result)
 ElifStack.append(0)
 else:
-Match  = re.match("!(if|elseif)\s+(.+)", DscLine)
+Match  = re.match("!(if|elseif)\s+(.+)", 
DscLine.split("#")[0])
 if Match:
 Result = self.EvaluateExpress(Match.group(2))
 if Match.group(1) == "if":
-- 
2.13.3.windows.1

___
edk2-devel mailing list
edk2-devel@lists.01.org
https://lists.01.org/mailman/listinfo/edk2-devel

[edk2] [PATCH] IntelFsp2WrapperPkg: Add EFIAPI to AsmExecute32BitCode

[Chasel, Chiu]

AsmExecute32BitCode is assembly code and needs EFIAPI

Cc: Jiewen Yao 
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Chasel Chiu 
---
 IntelFsp2WrapperPkg/Library/BaseFspWrapperApiLib/X64/DispatchExecute.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git 
a/IntelFsp2WrapperPkg/Library/BaseFspWrapperApiLib/X64/DispatchExecute.c 
b/IntelFsp2WrapperPkg/Library/BaseFspWrapperApiLib/X64/DispatchExecute.c
index 061d381c1b..8f66c72698 100644
--- a/IntelFsp2WrapperPkg/Library/BaseFspWrapperApiLib/X64/DispatchExecute.c
+++ b/IntelFsp2WrapperPkg/Library/BaseFspWrapperApiLib/X64/DispatchExecute.c
@@ -3,7 +3,7 @@
   Provide a thunk function to transition from long mode to compatibility mode 
to execute 32-bit code and then transit
   back to long mode.
 
-  Copyright (c) 2014 - 2016, Intel Corporation. All rights reserved.
+  Copyright (c) 2014 - 2018, Intel Corporation. All rights reserved.
   This program and the accompanying materials
   are licensed and made available under the terms and conditions of the BSD 
License
   which accompanies this distribution.  The full text of the license may be 
found at
@@ -67,6 +67,7 @@ GLOBAL_REMOVE_IF_UNREFERENCED IA32_DESCRIPTOR mGdt = {
   @return status.
 **/
 UINT32
+EFIAPI
 AsmExecute32BitCode (
   IN UINT64   Function,
   IN UINT64   Param1,
-- 
2.13.3.windows.1

___
edk2-devel mailing list
edk2-devel@lists.01.org
https://lists.01.org/mailman/listinfo/edk2-devel

[edk2] [PATCH] IntelFsp2Pkg: SplitFspBin.py to support x64 drivers

[Chasel, Chiu]

FSP binary potentially can include X64 drivers to
simplify implementation or support new features so
update SplitFspBin.py to support x64 image headers.

Cc: Jiewen Yao 
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Chasel Chiu 
---
 IntelFsp2Pkg/Tools/SplitFspBin.py | 82 +--
 1 file changed, 70 insertions(+), 12 deletions(-)

diff --git a/IntelFsp2Pkg/Tools/SplitFspBin.py 
b/IntelFsp2Pkg/Tools/SplitFspBin.py
index e4c3aa6d0b..9b18720307 100644
--- a/IntelFsp2Pkg/Tools/SplitFspBin.py
+++ b/IntelFsp2Pkg/Tools/SplitFspBin.py
@@ -1,6 +1,6 @@
 ## @ FspTool.py
 #
-# Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.
+# Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved.
 # This program and the accompanying materials are licensed and made available 
under
 # the terms and conditions of the BSD License that accompanies this 
distribution.
 # The full text of the license may be found at
@@ -234,11 +234,51 @@ class EFI_IMAGE_OPTIONAL_HEADER32(Structure):
 ('DataDirectory', ARRAY(EFI_IMAGE_DATA_DIRECTORY, 16))
 ]
 
+class EFI_IMAGE_OPTIONAL_HEADER32_PLUS(Structure):
+_fields_ = [
+('Magic', c_uint16),
+('MajorLinkerVersion',c_uint8),
+('MinorLinkerVersion',c_uint8),
+('SizeOfCode',c_uint32),
+('SizeOfInitializedData', c_uint32),
+('SizeOfUninitializedData',   c_uint32),
+('AddressOfEntryPoint',   c_uint32),
+('BaseOfCode',c_uint32),
+('ImageBase', c_uint64),
+('SectionAlignment',  c_uint32),
+('FileAlignment', c_uint32),
+('MajorOperatingSystemVersion',   c_uint16),
+('MinorOperatingSystemVersion',   c_uint16),
+('MajorImageVersion', c_uint16),
+('MinorImageVersion', c_uint16),
+('MajorSubsystemVersion', c_uint16),
+('MinorSubsystemVersion', c_uint16),
+('Win32VersionValue', c_uint32),
+('SizeOfImage',   c_uint32),
+('SizeOfHeaders', c_uint32),
+('CheckSum' , c_uint32),
+('Subsystem', c_uint16),
+('DllCharacteristics',c_uint16),
+('SizeOfStackReserve',c_uint64),
+('SizeOfStackCommit' ,c_uint64),
+('SizeOfHeapReserve', c_uint64),
+('SizeOfHeapCommit' , c_uint64),
+('LoaderFlags' ,  c_uint32),
+('NumberOfRvaAndSizes',   c_uint32),
+('DataDirectory', ARRAY(EFI_IMAGE_DATA_DIRECTORY, 16))
+]
+
+class EFI_IMAGE_OPTIONAL_HEADER(Union):
+_fields_ = [
+('PeOptHdr', EFI_IMAGE_OPTIONAL_HEADER32),
+('PePlusOptHdr', EFI_IMAGE_OPTIONAL_HEADER32_PLUS)
+]
+
 class EFI_IMAGE_NT_HEADERS32(Structure):
 _fields_ = [
 ('Signature',c_uint32),
 ('FileHeader',   EFI_IMAGE_FILE_HEADER),
-('OptionalHeader',   EFI_IMAGE_OPTIONAL_HEADER32)
+('OptionalHeader',   EFI_IMAGE_OPTIONAL_HEADER)
 ]
 
 
@@ -527,16 +567,24 @@ class PeTeImage:
 tehdr  = EFI_TE_IMAGE_HEADER.from_buffer (data, 0)
 if   tehdr.Signature == 'VZ': # TE image
 self.TeHdr   = tehdr
-elif tehdr.Signature == 'MZ': # PE32 image
+elif tehdr.Signature == 'MZ': # PE image
 self.TeHdr   = None
 self.DosHdr  = EFI_IMAGE_DOS_HEADER.from_buffer (data, 0)
 self.PeHdr   = EFI_IMAGE_NT_HEADERS32.from_buffer (data, 
self.DosHdr.e_lfanew)
 if self.PeHdr.Signature != 0x4550:
 raise Exception("ERROR: Invalid PE32 header !")
-if self.PeHdr.FileHeader.SizeOfOptionalHeader < 
EFI_IMAGE_OPTIONAL_HEADER32.DataDirectory.offset:
-raise Exception("ERROR: Unsupported PE32 image !")
-if self.PeHdr.OptionalHeader.NumberOfRvaAndSizes <= 
EFI_IMAGE_DIRECTORY_ENTRY.BASERELOC:
-raise Exception("ERROR: No relocation information available !")
+if self.PeHdr.OptionalHeader.PeOptHdr.Magic == 0x10b: # PE32 image
+if self.PeHdr.FileHeader.SizeOfOptionalHeader < 
EFI_IMAGE_OPTIONAL_HEADER32.Dat

[edk2] [PATCH] IntelFsp2WrapperPkg: Support UPD allocation outside FspWrapper

[Chasel, Chiu]

UPD allocation and patching can be done outside FspWrapper
as implementation choice so adding a PCD to select between
original FspWrapper allocation model or outside model

Cc: Jiewen Yao 
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Chasel Chiu 
---
 .../FspmWrapperPeim/FspmWrapperPeim.c  | 25 ---
 .../FspmWrapperPeim/FspmWrapperPeim.inf|  3 +-
 .../FspsWrapperPeim/FspsWrapperPeim.c  | 84 +++---
 .../FspsWrapperPeim/FspsWrapperPeim.inf|  3 +-
 IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dec| 13 +++-
 5 files changed, 76 insertions(+), 52 deletions(-)

diff --git a/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.c 
b/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.c
index f1d1cd6421..7b7c5f5d86 100644
--- a/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.c
+++ b/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.c
@@ -3,7 +3,7 @@
   register TemporaryRamDonePpi to call TempRamExit API, and register 
MemoryDiscoveredPpi
   notify to call FspSiliconInit API.
 
-  Copyright (c) 2014 - 2016, Intel Corporation. All rights reserved.
+  Copyright (c) 2014 - 2017, Intel Corporation. All rights reserved.
   This program and the accompanying materials
   are licensed and made available under the terms and conditions of the BSD 
License
   which accompanies this distribution.  The full text of the license may be 
found at
@@ -63,20 +63,29 @@ PeiFspMemoryInit (
   DEBUG ((DEBUG_INFO, "PeiFspMemoryInit enter\n"));
 
   FspHobListPtr = NULL;
+  FspmUpdDataPtr = NULL;
 
-  //
-  // Copy default FSP-M UPD data from Flash
-  //
   FspmHeaderPtr = (FSP_INFO_HEADER *)FspFindFspHeader (PcdGet32 
(PcdFspmBaseAddress));
   DEBUG ((DEBUG_INFO, "FspmHeaderPtr - 0x%x\n", FspmHeaderPtr));
   if (FspmHeaderPtr == NULL) {
 return EFI_DEVICE_ERROR;
   }
 
-  FspmUpdDataPtr = (FSPM_UPD_COMMON *)AllocateZeroPool 
((UINTN)FspmHeaderPtr->CfgRegionSize);
-  ASSERT (FspmUpdDataPtr != NULL);
-  SourceData = (UINTN *)((UINTN)FspmHeaderPtr->ImageBase + 
(UINTN)FspmHeaderPtr->CfgRegionOffset);
-  CopyMem (FspmUpdDataPtr, SourceData, (UINTN)FspmHeaderPtr->CfgRegionSize);
+  if (PcdGet32 (PcdFspmUpdDataAddress) == 0 && (FspmHeaderPtr->CfgRegionSize 
!= 0) && (FspmHeaderPtr->CfgRegionOffset != 0)) {
+//
+// Copy default FSP-M UPD data from Flash
+//
+FspmUpdDataPtr = (FSPM_UPD_COMMON *)AllocateZeroPool 
((UINTN)FspmHeaderPtr->CfgRegionSize);
+ASSERT (FspmUpdDataPtr != NULL);
+SourceData = (UINTN *)((UINTN)FspmHeaderPtr->ImageBase + 
(UINTN)FspmHeaderPtr->CfgRegionOffset);
+CopyMem (FspmUpdDataPtr, SourceData, (UINTN)FspmHeaderPtr->CfgRegionSize);
+  } else {
+//
+// External UPD is ready, get the buffer from PCD pointer.
+//
+FspmUpdDataPtr = (FSPM_UPD_COMMON *)PcdGet32 (PcdFspmUpdDataAddress);
+ASSERT (FspmUpdDataPtr != NULL);
+  }
 
   DEBUG ((DEBUG_INFO, "UpdateFspmUpdData enter\n"));
   UpdateFspmUpdData ((VOID *)FspmUpdDataPtr);
diff --git a/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.inf 
b/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.inf
index 2b3d240d08..542356b582 100644
--- a/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.inf
+++ b/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.inf
@@ -59,7 +59,8 @@
   IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dec
 
 [Pcd]
-  gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress  ## CONSUMES
+  gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress ## CONSUMES
+  gIntelFsp2WrapperTokenSpaceGuid.PcdFspmUpdDataAddress  ## CONSUMES
 
 [Sources]
   FspmWrapperPeim.c
diff --git a/IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.c 
b/IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.c
index ddc19c7e8f..70dac7a414 100644
--- a/IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.c
+++ b/IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.c
@@ -3,7 +3,7 @@
   register TemporaryRamDonePpi to call TempRamExit API, and register 
MemoryDiscoveredPpi
   notify to call FspSiliconInit API.
 
-  Copyright (c) 2014 - 2016, Intel Corporation. All rights reserved.
+  Copyright (c) 2014 - 2017, Intel Corporation. All rights reserved.
   This program and the accompanying materials
   are licensed and made available under the terms and conditions of the BSD 
License
   which accompanies this distribution.  The full text of the license may be 
found at
@@ -44,14 +44,14 @@ extern EFI_PEI_NOTIFY_DESCRIPTOR mS3EndOfPeiNotifyDesc;
 extern EFI_GUID  gFspHobGuid;
 
 /**
-This function handles S3 resume task at the end of PEI
+  This function handles S3 resume task at the end of PEI
 
-@param[in] PeiServicesPointer to PEI Services Table.
-@param[in] NotifyDesc Pointer to the descriptor for the Notification event 
that
-caused this function to execute.
-@param[in] PpiPointer to the PPI data associated with this 
function.
+  @para

[edk2] [PATCH] IntelFsp2Pkg-Tools: Add FixedAtBuild PCD support in GenCfgOpt.py

[Chasel, Chiu]

Platform is eligible to use either PcdsFeatureFlag or
PcdsFixedAtBuild for build configuration and requires
GenCfgOpt.py support.

Cc: Jiewen Yao 
Cc: Maurice, Ma 
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Chasel Chiu 
---
 IntelFsp2Pkg/Tools/GenCfgOpt.py | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/IntelFsp2Pkg/Tools/GenCfgOpt.py b/IntelFsp2Pkg/Tools/GenCfgOpt.py
index 6dc1b10b34..64e0a3a985 100644
--- a/IntelFsp2Pkg/Tools/GenCfgOpt.py
+++ b/IntelFsp2Pkg/Tools/GenCfgOpt.py
@@ -457,7 +457,7 @@ EndList
 IsUpdSect = False
 if  Match.group(1).lower() == "Defines".lower():
 IsDefSect = True
-if  Match.group(1).lower() == "PcdsFeatureFlag".lower():
+if  (Match.group(1).lower() == "PcdsFeatureFlag".lower() or 
Match.group(1).lower() == "PcdsFixedAtBuild".lower()):
 IsPcdSect = True
 elif Match.group(1).lower() == "PcdsDynamicVpd.Upd".lower():
 ConfigDict = {}
-- 
2.13.3.windows.1

___
edk2-devel mailing list
edk2-devel@lists.01.org
https://lists.01.org/mailman/listinfo/edk2-devel

[edk2] [PATCH] IntelFsp2Pkg-Tools: GenCfgOpt.py shouldn't include specific UPD name

[Chasel, Chiu]

PcdSerialIoUartDebugEnable UPD is platform specific and should not
be included in generic GenCfgOpt.py script. Remove this and platform
DSC should control the default value instead.

Cc: Jiewen Yao 
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Chasel Chiu 
---
 IntelFsp2Pkg/Tools/GenCfgOpt.py | 12 
 1 file changed, 12 deletions(-)

diff --git a/IntelFsp2Pkg/Tools/GenCfgOpt.py b/IntelFsp2Pkg/Tools/GenCfgOpt.py
index 6dc1b10b34..c9b7bc5373 100644
--- a/IntelFsp2Pkg/Tools/GenCfgOpt.py
+++ b/IntelFsp2Pkg/Tools/GenCfgOpt.py
@@ -289,7 +289,6 @@ class CGenCfgOpt:
 def __init__(self):
 self.Debug  = False
 self.Error  = ''
-self.ReleaseMode= True
 
 self._GlobalDataDef = """
 GlobalDataDef
@@ -318,13 +317,6 @@ EndList
 self._FvDir   = ''
 self._MapVer  = 0
 
-def ParseBuildMode (self, OutputStr):
-if "RELEASE_" in OutputStr:
-self.ReleaseMode = True
-if "DEBUG_" in OutputStr:
-self.ReleaseMode = False
-return
-
 def ParseMacros (self, MacroDefStr):
 # ['-DABC=1', '-D', 'CFG_DEBUG=1', '-D', 'CFG_OUTDIR=Build']
 self._MacroDict = {}
@@ -815,9 +807,6 @@ EndList
 TxtFd.write("%s.UnusedUpdSpace%d|%s0x%04X|0x%04X|{0}\n" % 
(Item['space'], SpaceIdx, Default, NextOffset - StartAddr, Offset - NextOffset))
 SpaceIdx = SpaceIdx + 1
 NextOffset = Offset + Item['length']
-if Item['cname'] == 'PcdSerialIoUartDebugEnable':
-if self.ReleaseMode == False:
-Item['value'] = 0x01
 TxtFd.write("%s.%s|%s0x%04X|%s|%s\n" % 
(Item['space'],Item['cname'],Default,Item['offset'] - 
StartAddr,Item['length'],Item['value']))
 TxtFd.close()
 return 0
@@ -1437,7 +1426,6 @@ def Main():
 print "ERROR: Macro parsing failed !"
 return 3
 
-GenCfgOpt.ParseBuildMode(sys.argv[3])
 FvDir = sys.argv[3]
 if not os.path.exists(FvDir):
 os.makedirs(FvDir)
-- 
2.13.3.windows.1

___
edk2-devel mailing list
edk2-devel@lists.01.org
https://lists.01.org/mailman/listinfo/edk2-devel