from:"Maurice Ma"

[edk2] [PATCH v2] CorebootPayloadPkg/FbGop: Locate correct framebuffer device

2019-04-02 Thread Maurice Ma

BZ:https://bugzilla.tianocore.org/show_bug.cgi?id=1628

Current FbGop driver might bind to the wrong PCI device
if a system has multiple PCI display devices. The original
idea was to reuse the generic GraphicsOutputDxe to address
this issue. However, after exploring different approaches
discussed in the bugzilla, it turned out that the best
approach is to enhance the current FbGop driver to match
the PCI device BAR value with the framebuffer base address.
This patch implemented this enhancement by selecting the
PCI device with matched framebuffer base in its PCI BAR.

This has been tested with coreboot on QEMU and Apollo Lake
platform.

Cc: Prince Agyeman 
Cc: Benjamin You 
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Maurice Ma 
---
 CorebootPayloadPkg/FbGop/FbGop.c | 242 ---
 1 file changed, 129 insertions(+), 113 deletions(-)

diff --git a/CorebootPayloadPkg/FbGop/FbGop.c b/CorebootPayloadPkg/FbGop/FbGop.c
index 9a66943cbfc5..c83ad8863e2f 100644
--- a/CorebootPayloadPkg/FbGop/FbGop.c
+++ b/CorebootPayloadPkg/FbGop/FbGop.c
@@ -23,7 +23,7 @@ EFI_PIXEL_BITMASK  mPixelBitMask = {0xFF, 0x00FF00, 
0xFF, 0x00};
 //
 UINT64 mOriginalPciAttributes;
 BOOLEANmPciAttributesSaved = FALSE;
-
+FRAME_BUFFER_INFO *mFrameBufferInfo;
 
 //
 // EFI Driver Binding Protocol Instance
@@ -64,10 +64,12 @@ FbGopDriverBindingSupported (
   IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath
   )
 {
-  EFI_STATUSStatus;
+  EFI_STATUS Status;
   EFI_PCI_IO_PROTOCOL   *PciIo;
-  PCI_TYPE00Pci;
+  PCI_TYPE00 Pci;
   EFI_DEV_PATH  *Node;
+  UINT8  Index;
+  EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Resources;
 
   //
   // Open the IO Abstraction(s) needed to perform the supported test
@@ -101,28 +103,45 @@ FbGopDriverBindingSupported (
   }
 
   Status = EFI_UNSUPPORTED;
-  if (Pci.Hdr.ClassCode[2] == 0x03 || (Pci.Hdr.ClassCode[2] == 0x00 && 
Pci.Hdr.ClassCode[1] == 0x01)) {
+  if (IS_PCI_DISPLAY (&Pci) || IS_PCI_OLD_VGA (&Pci)) {
+//
+// Check if PCI BAR matches the framebuffer base
+//
+Status = EFI_UNSUPPORTED;
+for (Index = 0; Index < PCI_MAX_BAR; Index++) {
+  Status = PciIo->GetBarAttributes (PciIo, Index, NULL, (VOID**) 
&Resources);
+  if (!EFI_ERROR (Status)) {
+if ((Resources->Desc == ACPI_ADDRESS_SPACE_DESCRIPTOR) &&
+(Resources->Len == (UINT16) (sizeof 
(EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) - 3)) &&
+(Resources->ResType == ACPI_ADDRESS_SPACE_TYPE_MEM) &&
+(Resources->AddrRangeMin == mFrameBufferInfo->LinearFrameBuffer)) {
+  DEBUG ((DEBUG_INFO, "Found matched framebuffer PCI BAR !\n"));
+  Status = EFI_SUCCESS;
+  break;
+}
+  }
+}
 
-Status = EFI_SUCCESS;
-//
-// If this is a graphics controller,
-// go further check RemainingDevicePath validation
-//
-if (RemainingDevicePath != NULL) {
-  Node = (EFI_DEV_PATH *) RemainingDevicePath;
+if (!EFI_ERROR (Status)) {
   //
-  // Check if RemainingDevicePath is the End of Device Path Node, 
-  // if yes, return EFI_SUCCESS
+  // If this is a graphics controller,
+  // go further check RemainingDevicePath
   //
-  if (!IsDevicePathEnd (Node)) {
+  if (RemainingDevicePath != NULL) {
+Node = (EFI_DEV_PATH *) RemainingDevicePath;
 //
-// If RemainingDevicePath isn't the End of Device Path Node,
-// check its validation
+// Check if RemainingDevicePath is the End of Device Path Node,
+// if yes, return EFI_SUCCESS
 //
-if (Node->DevPath.Type != ACPI_DEVICE_PATH ||
-Node->DevPath.SubType != ACPI_ADR_DP ||
-DevicePathNodeLength(&Node->DevPath) < 
sizeof(ACPI_ADR_DEVICE_PATH)) {
-  Status = EFI_UNSUPPORTED;
+if (!IsDevicePathEnd (Node)) {
+  //
+  // Verify RemainingDevicePath
+  //
+  if (Node->DevPath.Type != ACPI_DEVICE_PATH ||
+  Node->DevPath.SubType != ACPI_ADR_DP ||
+  DevicePathNodeLength(&Node->DevPath) < 
sizeof(ACPI_ADR_DEVICE_PATH)) {
+Status = EFI_UNSUPPORTED;
+  }
 }
   }
 }
@@ -161,11 +180,11 @@ FbGopDriverBindingStart (
 {
   EFI_STATUSStatus;
   EFI_DEVICE_PATH_PROTOCOL  *ParentDevicePath;
-  EFI_PCI_IO_PROTOCOL   *PciIo;  
+  EFI_PCI_IO_PROTOCOL   *PciIo;
   UINT64Supports;
 
-  DEBUG ((EFI_D_INFO, "GOP START\n"));
-  
+  DEBUG ((DEBUG_INFO, "GOP START\n"));
+
   //
   // Initialize local variables
   //
@@ -209,7 +228,7 @@ FbGopDriverBindingStart (
   0,

[edk2] [PATCH] CorebootPayloadPkg/FbGop: Locate correct framebuffer device

2019-04-01 Thread Maurice Ma

BZ:https://bugzilla.tianocore.org/show_bug.cgi?id=1628

Current FbGop driver might bind to the wrong PCI device
if a system has multiple PCI display devices. The original
idea was to reuse the generic GraphicsOutputDxe to address
this issue. However, after exploring different approaches
discussed in the bugzilla, it turned out that the best
approach is to enhance the current FbGop driver to match
the PCI device BAR value with the framebuffer base address.
This patch implemented this enhancement by selecting the
PCI device with matched framebuffer base in its PCI BAR.

This has been tested with coreboot on QEMU and Apollo Lake
platform.

Cc: Prince Agyeman 
Cc: Benjamin You 
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Maurice Ma 
---
 CorebootPayloadPkg/FbGop/FbGop.c | 242 ---
 1 file changed, 129 insertions(+), 113 deletions(-)

diff --git a/CorebootPayloadPkg/FbGop/FbGop.c b/CorebootPayloadPkg/FbGop/FbGop.c
index 9a66943cbfc5..4c38b60daa42 100644
--- a/CorebootPayloadPkg/FbGop/FbGop.c
+++ b/CorebootPayloadPkg/FbGop/FbGop.c
@@ -23,7 +23,7 @@ EFI_PIXEL_BITMASK  mPixelBitMask = {0xFF, 0x00FF00, 
0xFF, 0x00};
 //
 UINT64 mOriginalPciAttributes;
 BOOLEANmPciAttributesSaved = FALSE;
-
+FRAME_BUFFER_INFO *mFrameBufferInfo;
 
 //
 // EFI Driver Binding Protocol Instance
@@ -64,10 +64,12 @@ FbGopDriverBindingSupported (
   IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath
   )
 {
-  EFI_STATUSStatus;
+  EFI_STATUS Status;
   EFI_PCI_IO_PROTOCOL   *PciIo;
-  PCI_TYPE00Pci;
+  PCI_TYPE00 Pci;
   EFI_DEV_PATH  *Node;
+  UINT8  Index;
+  EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Resources;
 
   //
   // Open the IO Abstraction(s) needed to perform the supported test
@@ -101,28 +103,45 @@ FbGopDriverBindingSupported (
   }
 
   Status = EFI_UNSUPPORTED;
-  if (Pci.Hdr.ClassCode[2] == 0x03 || (Pci.Hdr.ClassCode[2] == 0x00 && 
Pci.Hdr.ClassCode[1] == 0x01)) {
+  if (IS_PCI_DISPLAY (&Pci) || IS_PCI_VGA (&Pci)) {
+//
+// Check if PCI BAR matches the framebuffer base
+//
+Status = EFI_UNSUPPORTED;
+for (Index = 0; Index < PCI_MAX_BAR; Index++) {
+  Status = PciIo->GetBarAttributes (PciIo, Index, NULL, (VOID**) 
&Resources);
+  if (!EFI_ERROR (Status)) {
+if ((Resources->Desc == ACPI_ADDRESS_SPACE_DESCRIPTOR) &&
+(Resources->Len == (UINT16) (sizeof 
(EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) - 3)) &&
+(Resources->ResType == ACPI_ADDRESS_SPACE_TYPE_MEM) &&
+(Resources->AddrRangeMin == mFrameBufferInfo->LinearFrameBuffer)) {
+  DEBUG ((DEBUG_INFO, "Found matched framebuffer PCI BAR !\n"));
+  Status = EFI_SUCCESS;
+  break;
+}
+  }
+}
 
-Status = EFI_SUCCESS;
-//
-// If this is a graphics controller,
-// go further check RemainingDevicePath validation
-//
-if (RemainingDevicePath != NULL) {
-  Node = (EFI_DEV_PATH *) RemainingDevicePath;
+if (!EFI_ERROR (Status)) {
   //
-  // Check if RemainingDevicePath is the End of Device Path Node, 
-  // if yes, return EFI_SUCCESS
+  // If this is a graphics controller,
+  // go further check RemainingDevicePath
   //
-  if (!IsDevicePathEnd (Node)) {
+  if (RemainingDevicePath != NULL) {
+Node = (EFI_DEV_PATH *) RemainingDevicePath;
 //
-// If RemainingDevicePath isn't the End of Device Path Node,
-// check its validation
+// Check if RemainingDevicePath is the End of Device Path Node,
+// if yes, return EFI_SUCCESS
 //
-if (Node->DevPath.Type != ACPI_DEVICE_PATH ||
-Node->DevPath.SubType != ACPI_ADR_DP ||
-DevicePathNodeLength(&Node->DevPath) < 
sizeof(ACPI_ADR_DEVICE_PATH)) {
-  Status = EFI_UNSUPPORTED;
+if (!IsDevicePathEnd (Node)) {
+  //
+  // Verify RemainingDevicePath
+  //
+  if (Node->DevPath.Type != ACPI_DEVICE_PATH ||
+  Node->DevPath.SubType != ACPI_ADR_DP ||
+  DevicePathNodeLength(&Node->DevPath) < 
sizeof(ACPI_ADR_DEVICE_PATH)) {
+Status = EFI_UNSUPPORTED;
+  }
 }
   }
 }
@@ -161,11 +180,11 @@ FbGopDriverBindingStart (
 {
   EFI_STATUSStatus;
   EFI_DEVICE_PATH_PROTOCOL  *ParentDevicePath;
-  EFI_PCI_IO_PROTOCOL   *PciIo;  
+  EFI_PCI_IO_PROTOCOL   *PciIo;
   UINT64Supports;
 
-  DEBUG ((EFI_D_INFO, "GOP START\n"));
-  
+  DEBUG ((DEBUG_INFO, "GOP START\n"));
+
   //
   // Initialize local variables
   //
@@ -209,7 +228,7 @@ FbGopDriverBindingStart (
   0,

[edk2] [PATCH 1/1] CorebootPayloadPkg: Add APRIORI file in FDF file

2017-01-09 Thread Maurice Ma

Add APRIORI file to allow status code related DXE drivers to
be dispatched earlier so that debug message can also be seen
much earlier. With this, lots of DXE driver debug message will
be missing.

Cc: Prince Agyeman 
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Maurice Ma 
---
 CorebootPayloadPkg/CorebootPayloadPkg.fdf | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/CorebootPayloadPkg/CorebootPayloadPkg.fdf 
b/CorebootPayloadPkg/CorebootPayloadPkg.fdf
index 34c8f7feacd9..303e6268421e 100644
--- a/CorebootPayloadPkg/CorebootPayloadPkg.fdf
+++ b/CorebootPayloadPkg/CorebootPayloadPkg.fdf
@@ -79,6 +79,12 @@ READ_STATUS= TRUE
 READ_LOCK_CAP  = TRUE
 READ_LOCK_STATUS   = TRUE
 
+APRIORI DXE {
+  INF  MdeModulePkg/Universal/PCD/Dxe/Pcd.inf
+  INF  
MdeModulePkg/Universal/ReportStatusCodeRouter/RuntimeDxe/ReportStatusCodeRouterRuntimeDxe.inf
+  INF  
MdeModulePkg/Universal/StatusCodeHandler/RuntimeDxe/StatusCodeHandlerRuntimeDxe.inf
+}
+
 #
 # DXE Phase modules
 #
-- 
2.11.0.windows.1

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[edk2] [PATCH 1/1] CorebootPayloadPkg: Remove improper build flags in DSC file

2017-01-09 Thread Maurice Ma

Current CorebootPayloadPkgIa32X64.dsc contains "-flto" flag to
request GCC link time optimization. However, this feature is
only supported by newer GCC compiler, and it will break the
debug build with GCC4.8. To fix it, the extra compiling flags
are removed. It allows the default build flags set by the EDKII
build environment to be used.

With this fix, CorebootPayloadPkg 64bit debug build can pass
using GCC 4.8.

Cc: Prince Agyeman 
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Maurice Ma 
---
 CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc | 2 --
 1 file changed, 2 deletions(-)

diff --git a/CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc 
b/CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc
index c35f261d67be..6b16af63ba89 100644
--- a/CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc
+++ b/CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc
@@ -89,8 +89,6 @@
 
 [BuildOptions]
   *_*_*_CC_FLAGS = -D DISABLE_NEW_DEPRECATED_INTERFACES
-  GCC:DEBUG_*_*_CC_FLAGS = -Og -flto
-  GCC:DEBUG_*_*_DLINK_FLAGS  = -flto
   GCC:*_UNIXGCC_*_CC_FLAGS   = -DMDEPKG_NDEBUG
   GCC:RELEASE_*_*_CC_FLAGS   = -DMDEPKG_NDEBUG
   INTEL:RELEASE_*_*_CC_FLAGS = /D MDEPKG_NDEBUG
-- 
2.11.0.windows.1

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[edk2] [PATCH 2/2] CorebootPayloadPkg/CbSupportPei: Fix the memory map issue

2016-11-16 Thread Maurice Ma

When coreboot reports memory range across 1MB, the current code
cannot handle it properly. In this case the range should be
adjusted to start from 1MB instead since the memory resource
below 1MB has been preprocessed by CbSupportPei module.

This patch fixed the coreboot + UEFI payload hang issue when
running on QEMU due to incorrect memory map.

Cc: Prince Agyeman 
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Maurice Ma 
---
 CorebootModulePkg/CbSupportPei/CbSupportPei.c | 5 +
 1 file changed, 5 insertions(+)

diff --git a/CorebootModulePkg/CbSupportPei/CbSupportPei.c 
b/CorebootModulePkg/CbSupportPei/CbSupportPei.c
index 8fa0ac5c1efa..831de89b21d1 100755
--- a/CorebootModulePkg/CbSupportPei/CbSupportPei.c
+++ b/CorebootModulePkg/CbSupportPei/CbSupportPei.c
@@ -169,6 +169,11 @@ CbMemInfoCallback (
  EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |
  EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE;
 
+  if ((Base  < 0x10) && ((Base + Size) > 0x10)) {
+ Size -= (0x10 - Base);
+ Base  = 0x10;
+  }
+
   MemInfo = (CB_MEM_INFO *)Param;
   if (Base >= 0x10) {
 if (Type == CB_MEM_RAM) {
-- 
2.7.4.windows.1

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[edk2] [PATCH 1/2] CorebootPayloadPkg: Allow PciLib instance selection

2016-11-16 Thread Maurice Ma

On old platform without PCIe express support, the PciLib needs to
be mapped to PciLibCf8 instance to make it work.  On new platform
with PCIe express support, the PciLib needs to be mapped to
PciLibPciExpress to allow access to extended PCIe configuration
space. This patch allows to select the PciLib instance between
PciLibCf8 and PciLibPciExpress using the PCIE_BASE macro through
build command line.

Cc: Prince Agyeman 
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Maurice Ma 
---
 CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc| 5 +
 CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc | 5 +
 2 files changed, 10 insertions(+)

diff --git a/CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc 
b/CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc
index ad1a6dcf603c..460a721a4882 100644
--- a/CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc
+++ b/CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc
@@ -129,8 +129,13 @@
   PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf
   CpuLib|MdePkg/Library/BaseCpuLib/BaseCpuLib.inf
   IoLib|MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf
+!if $(PCIE_BASE) == 0
+  PciLib|MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf
+  PciCf8Lib|MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf
+!else
   PciLib|MdePkg/Library/BasePciLibPciExpress/BasePciLibPciExpress.inf
   PciExpressLib|MdePkg/Library/BasePciExpressLib/BasePciExpressLib.inf
+!endif
   PciSegmentLib|MdePkg/Library/BasePciSegmentLibPci/BasePciSegmentLibPci.inf
   PeCoffLib|MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf
   
PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.inf
diff --git a/CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc 
b/CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc
index c06cccbf889a..e68d7173b0ca 100644
--- a/CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc
+++ b/CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc
@@ -131,8 +131,13 @@
   PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf
   CpuLib|MdePkg/Library/BaseCpuLib/BaseCpuLib.inf
   IoLib|MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf
+!if $(PCIE_BASE) == 0
+  PciLib|MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf
+  PciCf8Lib|MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf
+!else
   PciLib|MdePkg/Library/BasePciLibPciExpress/BasePciLibPciExpress.inf
   PciExpressLib|MdePkg/Library/BasePciExpressLib/BasePciExpressLib.inf
+!endif
   PciSegmentLib|MdePkg/Library/BasePciSegmentLibPci/BasePciSegmentLibPci.inf
   PeCoffLib|MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf
   
PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.inf
-- 
2.7.4.windows.1

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[edk2] [PATCH] CorebootPayloadPkg: Fix GCC build issue on macro definition

2016-11-08 Thread Maurice Ma

The previous change to disable deprecated APIs in CorebootPayloadPkg
used "/D" instead of "-D".  It caused Linux GCC build error. Correct
it to use "-D" instead.

Cc: Prince Agyeman 
Cc: Rusty Coleman 
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Maurice Ma 
---
 CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc| 2 +-
 CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc 
b/CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc
index ad1a6dcf603c..d4b3f71157d7 100644
--- a/CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc
+++ b/CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc
@@ -88,7 +88,7 @@
   DEFINE SHELL_TYPE  = FULL_BIN
 
 [BuildOptions]
-  *_*_*_CC_FLAGS = /D DISABLE_NEW_DEPRECATED_INTERFACES
+  *_*_*_CC_FLAGS = -D DISABLE_NEW_DEPRECATED_INTERFACES
   GCC:*_UNIXGCC_*_CC_FLAGS   = -DMDEPKG_NDEBUG
   GCC:RELEASE_*_*_CC_FLAGS   = -DMDEPKG_NDEBUG
   INTEL:RELEASE_*_*_CC_FLAGS = /D MDEPKG_NDEBUG
diff --git a/CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc 
b/CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc
index c06cccbf889a..1e9bae9fb1e9 100644
--- a/CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc
+++ b/CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc
@@ -88,7 +88,7 @@
   DEFINE SHELL_TYPE  = FULL_BIN
 
 [BuildOptions]
-  *_*_*_CC_FLAGS = /D DISABLE_NEW_DEPRECATED_INTERFACES
+  *_*_*_CC_FLAGS = -D DISABLE_NEW_DEPRECATED_INTERFACES
   GCC:DEBUG_*_*_CC_FLAGS = -Og -flto
   GCC:DEBUG_*_*_DLINK_FLAGS  = -flto
   GCC:*_UNIXGCC_*_CC_FLAGS   = -DMDEPKG_NDEBUG
-- 
1.9.5.msysgit.0

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[edk2] [PATCH] CorebootPayloadPkg: Add an option to use HPET timer driver

2016-10-26 Thread Maurice Ma

The current CorebootPayloadPkg will use the legacy 8254 timer
driver as the default. However, on some platforms legacy timer
might not exist anymore. This patch adds HPET timer driver as
a build option.

Cc: Prince Agyeman 
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Maurice Ma 
---
 CorebootPayloadPkg/CorebootPayloadPkg.fdf|  6 +-
 CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc| 10 ++
 CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc | 12 +++-
 3 files changed, 26 insertions(+), 2 deletions(-)

diff --git a/CorebootPayloadPkg/CorebootPayloadPkg.fdf 
b/CorebootPayloadPkg/CorebootPayloadPkg.fdf
index d07fd30a103e..6a0b58f35a6b 100644
--- a/CorebootPayloadPkg/CorebootPayloadPkg.fdf
+++ b/CorebootPayloadPkg/CorebootPayloadPkg.fdf
@@ -88,7 +88,11 @@ INF 
MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf
 INF UefiCpuPkg/CpuDxe/CpuDxe.inf
 INF MdeModulePkg/Universal/BdsDxe/BdsDxe.inf
 INF MdeModulePkg/Application/UiApp/UiApp.inf
-INF PcAtChipsetPkg/8254TimerDxe/8254Timer.inf
+!if $(USE_HPET_TIMER) == TRUE
+INF PcAtChipsetPkg/HpetTimerDxe/HpetTimerDxe.inf
+!else  
+INF PcAtChipsetPkg/8254TimerDxe/8254Timer.inf  
+!endif 
 INF MdeModulePkg/Universal/Metronome/Metronome.inf
 INF MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf
 INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
diff --git a/CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc 
b/CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc
index 435743329674..2637a255e5d1 100644
--- a/CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc
+++ b/CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc
@@ -78,6 +78,11 @@
   DEFINE PCI_SERIAL_PARAMETERS= {0xff,0xff, 0x00,0x00, 
0x0,0x20,0x1c,0x00, 0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0, 0x00,0x01, 0x0,0x0, 
0x0,0x0, 0x0,0x0, 0xff,0xff}
 
   #
+  # Chipset options
+  #
+  DEFINE USE_HPET_TIMER   = FALSE
+
+  #
   # Shell options: [BUILD_SHELL, FULL_BIN, MIN_BIN, NONE, UEFI]
   #
   DEFINE SHELL_TYPE  = FULL_BIN
@@ -170,6 +175,7 @@
   
SerialPortLib|CorebootModulePkg/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.inf
   
PlatformHookLib|CorebootPayloadPkg/Library/PlatformHookLib/PlatformHookLib.inf
   
PlatformBootManagerLib|CorebootPayloadPkg/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf
+  IoApicLib|PcAtChipsetPkg/Library/BaseIoApicLib/BaseIoApicLib.inf
 
   #
   # Misc
@@ -386,7 +392,11 @@
   NULL|MdeModulePkg/Library/BootManagerUiLib/BootManagerUiLib.inf
   
NULL|MdeModulePkg/Library/BootMaintenanceManagerUiLib/BootMaintenanceManagerUiLib.inf
   }
+!if $(USE_HPET_TIMER) == TRUE
+  PcAtChipsetPkg/HpetTimerDxe/HpetTimerDxe.inf
+!else  
   PcAtChipsetPkg/8254TimerDxe/8254Timer.inf
+!endif
   MdeModulePkg/Universal/Metronome/Metronome.inf
   MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf
   MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
diff --git a/CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc 
b/CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc
index 3ddc81b457ce..4a5fc89c6f0c 100644
--- a/CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc
+++ b/CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc
@@ -78,6 +78,11 @@
   DEFINE PCI_SERIAL_PARAMETERS= {0xff,0xff, 0x00,0x00, 
0x0,0x20,0x1c,0x00, 0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0, 0x00,0x01, 0x0,0x0, 
0x0,0x0, 0x0,0x0, 0xff,0xff}
 
   #
+  # Chipset options
+  #
+  DEFINE USE_HPET_TIMER   = FALSE
+
+  #
   # Shell options: [BUILD_SHELL, FULL_BIN, MIN_BIN, NONE, UEFI]
   #
   DEFINE SHELL_TYPE  = FULL_BIN
@@ -172,6 +177,7 @@
   
SerialPortLib|CorebootModulePkg/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.inf
   
PlatformHookLib|CorebootPayloadPkg/Library/PlatformHookLib/PlatformHookLib.inf
   
PlatformBootManagerLib|CorebootPayloadPkg/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf
+  IoApicLib|PcAtChipsetPkg/Library/BaseIoApicLib/BaseIoApicLib.inf
 
   #
   # Misc
@@ -389,7 +395,11 @@
   NULL|MdeModulePkg/Library/BootManagerUiLib/BootManagerUiLib.inf
   
NULL|MdeModulePkg/Library/BootMaintenanceManagerUiLib/BootMaintenanceManagerUiLib.inf
   }
-  PcAtChipsetPkg/8254TimerDxe/8254Timer.inf
+!if $(USE_HPET_TIMER) == TRUE
+  PcAtChipsetPkg/HpetTimerDxe/HpetTimerDxe.inf
+!else  
+  PcAtChipsetPkg/8254TimerDxe/8254Timer.inf  
+!endif
   MdeModulePkg/Universal/Metronome/Metronome.inf
   MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf
   MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
-- 
1.9.5.msysgit.0

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[edk2] [PATCH] CorebootPayloadPkg DSC: Change the section alignment option

2016-10-26 Thread Maurice Ma

The current CorebootPayloadPkg will print the following message
"InsertImageRecord - Section Alignment(0x20) is not 4K" during
boot. It is caused by the section alignment arranged by the linker.
This patch change the alignment to 4K for runtime drivers.

Cc: Prince Agyeman 
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Maurice Ma 
---
 CorebootPayloadPkg/CorebootPayloadPkg.fdf| 1 +
 CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc| 3 +++
 CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc | 3 +++
 3 files changed, 7 insertions(+)

diff --git a/CorebootPayloadPkg/CorebootPayloadPkg.fdf 
b/CorebootPayloadPkg/CorebootPayloadPkg.fdf
index d07fd30a103e..aa50db0e5699 100644
--- a/CorebootPayloadPkg/CorebootPayloadPkg.fdf
+++ b/CorebootPayloadPkg/CorebootPayloadPkg.fdf
@@ -60,6 +60,7 @@ INF MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf
 
 [FV.DXEFV]
 BlockSize  = 0x1000
+FvForceRebase  = FALSE
 FvAlignment= 16
 ERASE_POLARITY = 1
 MEMORY_MAPPED  = TRUE
diff --git a/CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc 
b/CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc
index 435743329674..80d769be24e0 100644
--- a/CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc
+++ b/CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc
@@ -88,6 +88,9 @@
   INTEL:RELEASE_*_*_CC_FLAGS = /D MDEPKG_NDEBUG
   MSFT:RELEASE_*_*_CC_FLAGS  = /D MDEPKG_NDEBUG
 
+[BuildOptions.common.EDKII.DXE_RUNTIME_DRIVER]
+  MSFT:*_*_*_DLINK_FLAGS = /ALIGN:4096
+
 

 #
 # SKU Identification section - list of all SKU IDs supported by this Platform.
diff --git a/CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc 
b/CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc
index 3ddc81b457ce..dbb8d151d09c 100644
--- a/CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc
+++ b/CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc
@@ -90,6 +90,9 @@
   INTEL:RELEASE_*_*_CC_FLAGS = /D MDEPKG_NDEBUG
   MSFT:RELEASE_*_*_CC_FLAGS  = /D MDEPKG_NDEBUG
 
+[BuildOptions.common.EDKII.DXE_RUNTIME_DRIVER]
+  MSFT:*_*_*_DLINK_FLAGS = /ALIGN:4096
+
 

 #
 # SKU Identification section - list of all SKU IDs supported by this Platform.
-- 
1.9.5.msysgit.0

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[edk2] [PATCH] CorebootPayloadPkg: Switch to use StatusCode drvier in MdeModulePkg

2016-10-26 Thread Maurice Ma

The current CorebootPayloadPkg uses PEI/DXE StatusCode drivers from
IntelFrameworkModulePkg. This patch switches to use the StatusCode
driver from MdeModulePkg instead.

Cc: Prince Agyeman 
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Maurice Ma 
---
 CorebootPayloadPkg/CorebootPayloadPkg.fdf|  6 --
 CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc| 10 ++
 CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc | 10 ++
 3 files changed, 16 insertions(+), 10 deletions(-)

diff --git a/CorebootPayloadPkg/CorebootPayloadPkg.fdf 
b/CorebootPayloadPkg/CorebootPayloadPkg.fdf
index d07fd30a103e..6d2019de5b17 100644
--- a/CorebootPayloadPkg/CorebootPayloadPkg.fdf
+++ b/CorebootPayloadPkg/CorebootPayloadPkg.fdf
@@ -52,7 +52,8 @@ INF CorebootModulePkg/SecCore/SecCore.inf
 
 INF MdeModulePkg/Core/Pei/PeiMain.inf
 INF MdeModulePkg/Universal/PCD/Pei/Pcd.inf
-INF IntelFrameworkModulePkg/Universal/StatusCode/Pei/StatusCodePei.inf
+INF 
MdeModulePkg/Universal/ReportStatusCodeRouter/Pei/ReportStatusCodeRouterPei.inf
+INF MdeModulePkg/Universal/StatusCodeHandler/Pei/StatusCodeHandlerPei.inf
 INF CorebootModulePkg/CbSupportPei/CbSupportPei.inf
 INF MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf
 
@@ -82,7 +83,8 @@ READ_LOCK_STATUS   = TRUE
 #
 INF MdeModulePkg/Core/Dxe/DxeMain.inf
 INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf
-INF 
IntelFrameworkModulePkg/Universal/StatusCode/RuntimeDxe/StatusCodeRuntimeDxe.inf
+INF 
MdeModulePkg/Universal/ReportStatusCodeRouter/RuntimeDxe/ReportStatusCodeRouterRuntimeDxe.inf
+INF 
MdeModulePkg/Universal/StatusCodeHandler/RuntimeDxe/StatusCodeHandlerRuntimeDxe.inf
 
 INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf
 INF UefiCpuPkg/CpuDxe/CpuDxe.inf
diff --git a/CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc 
b/CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc
index 435743329674..155bbdfbf936 100644
--- a/CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc
+++ b/CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc
@@ -184,7 +184,7 @@
   DebugAgentLib|MdeModulePkg/Library/DebugAgentLibNull/DebugAgentLibNull.inf
 !endif
   CbParseLib|CorebootModulePkg/Library/CbParseLib/CbParseLib.inf
-  
DebugLib|IntelFrameworkModulePkg/Library/PeiDxeDebugLibReportStatusCode/PeiDxeDebugLibReportStatusCode.inf
+  
DebugLib|MdeModulePkg/Library/PeiDxeDebugLibReportStatusCode/PeiDxeDebugLibReportStatusCode.inf
   LockBoxLib|MdeModulePkg/Library/LockBoxNullLib/LockBoxNullLib.inf
   FileExplorerLib|MdeModulePkg/Library/FileExplorerLib/FileExplorerLib.inf
 
@@ -360,7 +360,8 @@
 
   PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
   }
-  IntelFrameworkModulePkg/Universal/StatusCode/Pei/StatusCodePei.inf
+  
MdeModulePkg/Universal/ReportStatusCodeRouter/Pei/ReportStatusCodeRouterPei.inf
+  MdeModulePkg/Universal/StatusCodeHandler/Pei/StatusCodeHandlerPei.inf
 
   CorebootModulePkg/CbSupportPei/CbSupportPei.inf
   MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf
@@ -371,7 +372,7 @@
   #
   MdeModulePkg/Core/Dxe/DxeMain.inf {
 
-  
NULL|IntelFrameworkModulePkg/Library/LzmaCustomDecompressLib/LzmaCustomDecompressLib.inf
+  
NULL|MdeModulePkg/Library/LzmaCustomDecompressLib/LzmaCustomDecompressLib.inf
   }
 
   #
@@ -404,7 +405,8 @@
   PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
   }
 
-  
IntelFrameworkModulePkg/Universal/StatusCode/RuntimeDxe/StatusCodeRuntimeDxe.inf
+  
MdeModulePkg/Universal/ReportStatusCodeRouter/RuntimeDxe/ReportStatusCodeRouterRuntimeDxe.inf
+  
MdeModulePkg/Universal/StatusCodeHandler/RuntimeDxe/StatusCodeHandlerRuntimeDxe.inf
   UefiCpuPkg/CpuIo2Dxe/CpuIo2Dxe.inf
   MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
   MdeModulePkg/Universal/MemoryTest/NullMemoryTestDxe/NullMemoryTestDxe.inf
diff --git a/CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc 
b/CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc
index 3ddc81b457ce..16484b165541 100644
--- a/CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc
+++ b/CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc
@@ -186,7 +186,7 @@
   DebugAgentLib|MdeModulePkg/Library/DebugAgentLibNull/DebugAgentLibNull.inf
 !endif
   CbParseLib|CorebootModulePkg/Library/CbParseLib/CbParseLib.inf
-  
DebugLib|IntelFrameworkModulePkg/Library/PeiDxeDebugLibReportStatusCode/PeiDxeDebugLibReportStatusCode.inf
+  
DebugLib|MdeModulePkg/Library/PeiDxeDebugLibReportStatusCode/PeiDxeDebugLibReportStatusCode.inf
   LockBoxLib|MdeModulePkg/Library/LockBoxNullLib/LockBoxNullLib.inf
   FileExplorerLib|MdeModulePkg/Library/FileExplorerLib/FileExplorerLib.inf
 
@@ -363,7 +363,8 @@
 
   PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
   }
-  IntelFrameworkModulePkg/Universal/StatusCode/Pei/StatusCodePei.inf
+  
MdeModulePkg/Universal/ReportStatusCodeRouter/Pei/ReportStatusCodeRouterPei.inf
+  MdeModulePkg/Universal/StatusCodeHandler/Pei/StatusCodeHandlerPei.inf
 
   CorebootModulePkg/CbSupportPei/CbSupportPei.inf
   MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf
@@ -374,7 +375,7 @@
   #
   MdeModulePkg

[edk2] [PATCH] CorebootPayloadPkg DSC: Add build option to disable deprecated APIs

2016-10-24 Thread Maurice Ma

Add the following definition in the [BuildOptions] section in package DSC
files to disable APIs that are deprecated. As a result replaced PcdSet32
with PcdSet32S accordingly to make the build pass.

[BuildOptions]
  *_*_*_CC_FLAGS = -D DISABLE_NEW_DEPRECATED_INTERFACES

Cc: Prince Agyeman 
Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=163
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Maurice Ma 
---
 CorebootModulePkg/CbSupportPei/CbSupportPei.c| 3 ++-
 CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc| 1 +
 CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc | 1 +
 3 files changed, 4 insertions(+), 1 deletion(-)

diff --git a/CorebootModulePkg/CbSupportPei/CbSupportPei.c 
b/CorebootModulePkg/CbSupportPei/CbSupportPei.c
index 366682b32d11..9d5803449e25 100755
--- a/CorebootModulePkg/CbSupportPei/CbSupportPei.c
+++ b/CorebootModulePkg/CbSupportPei/CbSupportPei.c
@@ -329,7 +329,8 @@ CbPeiEntryPoint (
   if ((CbParseGetCbHeader (1, &pCbHeader) == RETURN_SUCCESS)
 && ((UINTN)pCbHeader > BASE_4KB)) {
 DEBUG((EFI_D_ERROR, "Actual Coreboot header: %p.\n", pCbHeader));
-PcdSet32 (PcdCbHeaderPointer, (UINT32)(UINTN)pCbHeader);
+Status = PcdSet32S (PcdCbHeaderPointer, (UINT32)(UINTN)pCbHeader);
+ASSERT_EFI_ERROR (Status);
   }
 
   //
diff --git a/CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc 
b/CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc
index 435743329674..3f053317abb0 100644
--- a/CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc
+++ b/CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc
@@ -83,6 +83,7 @@
   DEFINE SHELL_TYPE  = FULL_BIN
 
 [BuildOptions]
+  *_*_*_CC_FLAGS = /D DISABLE_NEW_DEPRECATED_INTERFACES
   GCC:*_UNIXGCC_*_CC_FLAGS   = -DMDEPKG_NDEBUG
   GCC:RELEASE_*_*_CC_FLAGS   = -DMDEPKG_NDEBUG
   INTEL:RELEASE_*_*_CC_FLAGS = /D MDEPKG_NDEBUG
diff --git a/CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc 
b/CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc
index 3ddc81b457ce..763d1c53023a 100644
--- a/CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc
+++ b/CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc
@@ -83,6 +83,7 @@
   DEFINE SHELL_TYPE  = FULL_BIN
 
 [BuildOptions]
+  *_*_*_CC_FLAGS = /D DISABLE_NEW_DEPRECATED_INTERFACES
   GCC:DEBUG_*_*_CC_FLAGS = -Og -flto
   GCC:DEBUG_*_*_DLINK_FLAGS  = -flto
   GCC:*_UNIXGCC_*_CC_FLAGS   = -DMDEPKG_NDEBUG
-- 
1.9.5.msysgit.0

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[edk2] [PATCH] CorebootPayloadPkg/PciHostBridgeLib: Fix the wrong PCI resource limit

2016-10-17 Thread Maurice Ma

The current PCI resource limit calculation in CorebootPayloadPkg
PciHostBridgeLib is wrong. Adjusted it to match the PciHostBridge
driver's expectation.

Cc: Prince Agyeman 
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Maurice Ma 
---
 CorebootPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeSupport.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/CorebootPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeSupport.c 
b/CorebootPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeSupport.c
index 0f1c8cb1a210..6d94ff72c956 100644
--- a/CorebootPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeSupport.c
+++ b/CorebootPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeSupport.c
@@ -91,7 +91,7 @@ AdjustRootBridgeResource (
   // Align IO  resource at 4K  boundary
   //
   Mask= 0xFFFULL;
-  Io->Limit   = (Io->Limit + Mask) & ~Mask;
+  Io->Limit   = ((Io->Limit + Mask) & ~Mask) - 1;
   if (Io->Base != MAX_UINT64) {
 Io->Base &= ~Mask;
   }
@@ -100,7 +100,7 @@ AdjustRootBridgeResource (
   // Align MEM resource at 1MB boundary
   //
   Mask= 0xFULL;
-  Mem->Limit  = (Mem->Limit + Mask) & ~Mask;
+  Mem->Limit  = ((Mem->Limit + Mask) & ~Mask) - 1;
   if (Mem->Base != MAX_UINT64) {
 Mem->Base &= ~Mask;
   }
-- 
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[edk2] [PATCH] IntelFsp2Pkg/FspSecCore: Make FSP funcitons position independent

2016-10-12 Thread Maurice Ma

The current AsmGetFspInfoHeader function in FspHeader.nasm is
position dependent code since it uses absolute address. Change
to use relative address instead to make it position independent.

Cc: Jiewen Yao 
Cc: Giri P Mudusuru 
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Maurice Ma 
---
 IntelFsp2Pkg/FspSecCore/Ia32/FspHelper.nasm | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/IntelFsp2Pkg/FspSecCore/Ia32/FspHelper.nasm 
b/IntelFsp2Pkg/FspSecCore/Ia32/FspHelper.nasm
index a848dcbc0298..ad631943e32d 100644
--- a/IntelFsp2Pkg/FspSecCore/Ia32/FspHelper.nasm
+++ b/IntelFsp2Pkg/FspSecCore/Ia32/FspHelper.nasm
@@ -31,7 +31,7 @@ ASM_PFX(NextInstruction):
pop   eax
sub   eax, ASM_PFX(NextInstruction)
add   eax, ASM_PFX(AsmGetFspInfoHeader)
-   sub   eax, dword [ASM_PFX(FspInfoHeaderRelativeOff)]
+   sub   eax, dword [eax - ASM_PFX(AsmGetFspInfoHeader) + 
ASM_PFX(FspInfoHeaderRelativeOff)]
ret
 
 global ASM_PFX(AsmGetFspInfoHeaderNoStack)
-- 
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[edk2] [PATCH] IntelFsp2Pkg/Tools: Add PE32 section rebasing support

2016-10-04 Thread Maurice Ma

The current SplitFspBin.py can only support TE image format
rebasing in an FSP binary. This patch adds PE32 image format
rebasing support.

Cc: Jiewen Yao 
Cc: Giri P Mudusuru 
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Maurice Ma 
---
 IntelFsp2Pkg/Tools/SplitFspBin.py | 174 +++---
 1 file changed, 145 insertions(+), 29 deletions(-)

diff --git a/IntelFsp2Pkg/Tools/SplitFspBin.py 
b/IntelFsp2Pkg/Tools/SplitFspBin.py
index ef759f0dc46a..e4c3aa6d0b28 100644
--- a/IntelFsp2Pkg/Tools/SplitFspBin.py
+++ b/IntelFsp2Pkg/Tools/SplitFspBin.py
@@ -159,12 +159,102 @@ class EFI_TE_IMAGE_HEADER(Structure):
 ('DataDirectoryDebug',  EFI_IMAGE_DATA_DIRECTORY)
 ]
 
+class EFI_IMAGE_DOS_HEADER(Structure):
+_fields_ = [
+('e_magic',  c_uint16),
+('e_cblp',   c_uint16),
+('e_cp', c_uint16),
+('e_crlc',   c_uint16),
+('e_cparhdr',c_uint16),
+('e_minalloc',   c_uint16),
+('e_maxalloc',   c_uint16),
+('e_ss', c_uint16),
+('e_sp', c_uint16),
+('e_csum',   c_uint16),
+('e_ip', c_uint16),
+('e_cs', c_uint16),
+('e_lfarlc', c_uint16),
+('e_ovno',   c_uint16),
+('e_res',ARRAY(c_uint16, 4)),
+('e_oemid',  c_uint16),
+('e_oeminfo',c_uint16),
+('e_res2',   ARRAY(c_uint16, 10)),
+('e_lfanew', c_uint16)
+]
+
+class EFI_IMAGE_FILE_HEADER(Structure):
+_fields_ = [
+('Machine',   c_uint16),
+('NumberOfSections',  c_uint16),
+('TimeDateStamp', c_uint32),
+('PointerToSymbolTable',  c_uint32),
+('NumberOfSymbols',   c_uint32),
+('SizeOfOptionalHeader',  c_uint16),
+('Characteristics',   c_uint16)
+]
+
 class PE_RELOC_BLOCK_HEADER(Structure):
 _fields_ = [
 ('PageRVA',  c_uint32),
 ('BlockSize',c_uint32)
 ]
 
+class EFI_IMAGE_OPTIONAL_HEADER32(Structure):
+_fields_ = [
+('Magic', c_uint16),
+('MajorLinkerVersion',c_uint8),
+('MinorLinkerVersion',c_uint8),
+('SizeOfCode',c_uint32),
+('SizeOfInitializedData', c_uint32),
+('SizeOfUninitializedData',   c_uint32),
+('AddressOfEntryPoint',   c_uint32),
+('BaseOfCode',c_uint32),
+('BaseOfData',c_uint32),
+('ImageBase', c_uint32),
+('SectionAlignment',  c_uint32),
+('FileAlignment', c_uint32),
+('MajorOperatingSystemVersion',   c_uint16),
+('MinorOperatingSystemVersion',   c_uint16),
+('MajorImageVersion', c_uint16),
+('MinorImageVersion', c_uint16),
+('MajorSubsystemVersion', c_uint16),
+('MinorSubsystemVersion', c_uint16),
+('Win32VersionValue', c_uint32),
+('SizeOfImage',   c_uint32),
+('SizeOfHeaders', c_uint32),
+('CheckSum' , c_uint32),
+('Subsystem', c_uint16),
+('DllCharacteristics',c_uint16),
+('SizeOfStackReserve',c_uint32),
+('SizeOfStackCommit' ,c_uint32),
+('SizeOfHeapReserve', c_uint32),
+('SizeOfHeapCommit' , c_uint32),
+('LoaderFlags' ,  c_uint32),
+('NumberOfRvaAndSizes',   c_uint32),
+('DataDirectory', ARRAY(EFI_IMAGE_DATA_DIRECTORY, 16))
+]
+
+class EFI_IMAGE_NT_HEADERS32(Structure):
+_fields_ = [
+('Signature',c_uint32),
+('FileHeader',   EFI_IMAGE_FILE_HEADER),
+('OptionalHeader',   EFI_IMAGE_OPTIONAL_HEADER32)
+]
+
+
+class EFI_IMAGE_DIRECTORY_ENTRY:
+EXPORT = 0
+IMPORT = 1
+

[edk2] [PATCH] IntelFsp2Pkg: Only include required header files in FspEas.h

2016-08-04 Thread Maurice Ma

Current FspEas.h file includes Uefi.h which also refers to lots of other
UEFI header files not used by FSP consumer. It caused many unnecessary
header file overhead for a bootloader that consumes FSP, such as coreboot.
This change reduces the required header file number down to 3.

Cc: Jiewen Yao 
Cc: Giri P Mudusuru 
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Maurice Ma 
---
 IntelFsp2Pkg/Include/FspEas.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/IntelFsp2Pkg/Include/FspEas.h b/IntelFsp2Pkg/Include/FspEas.h
index 79bb0b8e8efc..00098a392699 100644
--- a/IntelFsp2Pkg/Include/FspEas.h
+++ b/IntelFsp2Pkg/Include/FspEas.h
@@ -16,7 +16,7 @@
 #ifndef _FSP_EAS_H_
 #define _FSP_EAS_H_

-#include 
+#include 
 #include 
 #include 
 #include 
-- 
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[edk2] [PATCH] CorebootModulePkg/SecCore: Adding NASM files in SecCore module

2016-08-02 Thread Maurice Ma

Ported MASM/GAS assembly files into NASM files and updated the
inf file to refer to NASM files.

This change has been tested with GCC 4.8 and VS2013 build.

Cc: Prince Agyeman 
Cc: Lee Leahy 
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Maurice Ma 
---
 CorebootModulePkg/SecCore/Ia32/SecEntry.nasm | 72 +
 CorebootModulePkg/SecCore/Ia32/Stack.nasm| 78 
 CorebootModulePkg/SecCore/SecCore.inf|  6 +--
 3 files changed, 152 insertions(+), 4 deletions(-)
 create mode 100644 CorebootModulePkg/SecCore/Ia32/SecEntry.nasm
 create mode 100644 CorebootModulePkg/SecCore/Ia32/Stack.nasm

diff --git a/CorebootModulePkg/SecCore/Ia32/SecEntry.nasm 
b/CorebootModulePkg/SecCore/Ia32/SecEntry.nasm
new file mode 100644
index ..2b9b80549900
--- /dev/null
+++ b/CorebootModulePkg/SecCore/Ia32/SecEntry.nasm
@@ -0,0 +1,72 @@
+;--
+;
+; Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.
+; This program and the accompanying materials
+; are licensed and made available under the terms and conditions of the BSD 
License
+; which accompanies this distribution.  The full text of the license may be 
found at
+; http://opensource.org/licenses/bsd-license.php.
+;
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+;
+; Abstract:
+;
+;   Entry point for the coreboot UEFI payload.
+;
+;--
+
+SECTION .text
+
+; C Functions
+extern  ASM_PFX(SecStartup)
+
+; Pcds
+extern  ASM_PFX(PcdGet32 (PcdPayloadFdMemBase))
+
+;
+; SecCore Entry Point
+;
+; Processor is in flat protected mode
+;
+; @param[in]  EAX   Initial value of the EAX register (BIST: Built-in Self 
Test)
+; @param[in]  DI'BP': boot-strap processor, or 'AP': application processor
+; @param[in]  EBP   Pointer to the start of the Boot Firmware Volume
+;
+; @return None  This routine does not return
+;
+global ASM_PFX(_ModuleEntryPoint)
+ASM_PFX(_ModuleEntryPoint):
+  ;
+  ; Disable all the interrupts
+  ;
+  cli
+  ;
+  ; Construct the temporary memory at 0x8, length 0x1
+  ;
+  mov esp, (BASE_512KB + SIZE_64KB)
+
+  ;
+  ; Pass BFV into the PEI Core
+  ;
+  pushDWORD [ASM_PFX(PcdGet32 (PcdPayloadFdMemBase))]
+
+  ;
+  ; Pass stack base into the PEI Core
+  ;
+  pushBASE_512KB
+
+  ;
+  ; Pass stack size into the PEI Core
+  ;
+  pushSIZE_64KB
+
+  ;
+  ; Pass Control into the PEI Core
+  ;
+  callASM_PFX(SecStartup)
+
+  ;
+  ; Should never return
+  ;
+  jmp $
+
diff --git a/CorebootModulePkg/SecCore/Ia32/Stack.nasm 
b/CorebootModulePkg/SecCore/Ia32/Stack.nasm
new file mode 100644
index ..c877e52e52b8
--- /dev/null
+++ b/CorebootModulePkg/SecCore/Ia32/Stack.nasm
@@ -0,0 +1,78 @@
+;--
+;
+; Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.
+; This program and the accompanying materials
+; are licensed and made available under the terms and conditions of the BSD 
License
+; which accompanies this distribution.  The full text of the license may be 
found at
+; http://opensource.org/licenses/bsd-license.php.
+;
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+;
+; Abstract:
+;
+;   Switch the stack from temporary memory to permanent memory.
+;
+;--
+
+SECTION .text
+
+;--
+; VOID
+; EFIAPI
+; SecSwitchStack (
+;   UINT32   TemporaryMemoryBase,
+;   UINT32   PermenentMemoryBase
+;   );
+;--
+global ASM_PFX(SecSwitchStack)
+ASM_PFX(SecSwitchStack):
+;
+; Save three register: eax, ebx, ecx
+;
+push  eax
+push  ebx
+push  ecx
+push  edx
+
+;
+; !!CAUTION!! this function address's is pushed into stack after
+; migration of whole temporary memory, so need save it to permanent
+; memory at first!
+;
+
+mov   ebx,  [esp + 20]  ; Save the first parameter
+mov   ecx,  [esp + 24]  ; Save the second parameter
+
+;
+; Save this function's return address into permanent memory at first.
+; Then, Fixup the esp point to permanent memory
+;
+mov   eax,  esp
+sub   eax,  ebx
+add   eax,  ecx
+mov   edx,  [esp]   ; copy pushed register's value to 
permanent memory
+mov   [eax], edx
+mov   edx,  [esp + 4]
+mov   [eax + 4], edx
+mov   edx,  [esp + 8]
+mov   [eax + 8], edx
+mov   edx

[edk2] [PATCH] IntelFsp2Pkg/Tools: Add FSP rebasing function into SplitFspBin tool

2016-05-27 Thread Maurice Ma

Enhanced the SplitFspBin tool in IntelFsp2Pkg to support:
  - Rebase FSP 2.0 components to a different base address
  - Display FSP 2.0 information header

Cc: Jiewen Yao 
Cc: Giri P Mudusuru 
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Maurice Ma 
---
 IntelFsp2Pkg/Tools/SplitFspBin.py | 830 ++
 1 file changed, 573 insertions(+), 257 deletions(-)

diff --git a/IntelFsp2Pkg/Tools/SplitFspBin.py 
b/IntelFsp2Pkg/Tools/SplitFspBin.py
index cc2b87ecc10a..ef759f0dc46a 100644
--- a/IntelFsp2Pkg/Tools/SplitFspBin.py
+++ b/IntelFsp2Pkg/Tools/SplitFspBin.py
@@ -20,18 +20,26 @@ import argparse
 from   ctypes import *
 
 """
-This utility supports some operations for Intel FSP image.
+This utility supports some operations for Intel FSP 2.0 image.
 It supports:
-- Split a FSP 2.0 compatibale image into individual FSP-T/M/S/C
-and generate the mapping header file.
+- Display FSP 2.0 information header
+- Split FSP 2.0 image into individual FSP-T/M/S/O component
+- Rebase FSP 2.0 components to a different base address
+- Generate FSP mapping C header file
+"""
+
+CopyRightHeaderFile = """/*
+ *
+ * Automatically generated file; DO NOT EDIT.
+ * FSP mapping file
+ *
+ */
 """
 
 class c_uint24(Structure):
 """Little-Endian 24-bit Unsigned Integer"""
 _pack_   = 1
-_fields_ = [
-('Data', (c_uint8 * 3))
-]
+_fields_ = [('Data', (c_uint8 * 3))]
 
 def __init__(self, val=0):
 self.set_value(val)
@@ -39,324 +47,632 @@ class c_uint24(Structure):
 def __str__(self, indent=0):
 return '0x%.6x' % self.value
 
-def get_value(self):
-return (
-(self.Data[0]  ) +
-(self.Data[1] <<  8) +
-(self.Data[2] << 16)
-)
+def __int__(self):
+return self.get_value()
 
 def set_value(self, val):
-self.Data[0] = (val  ) & 0xff
-self.Data[1] = (val >>  8) & 0xff
-self.Data[2] = (val >> 16) & 0xff
+self.Data[0:3] = Val2Bytes(val, 3)
+
+def get_value(self):
+return Bytes2Val(self.Data[0:3])
 
 value = property(get_value, set_value)
 
 class EFI_FIRMWARE_VOLUME_HEADER(Structure):
 _fields_ = [
-('ZeroVector', ARRAY(c_uint8, 16)),
-('FileSystemGuid', ARRAY(c_char, 16)),
-('FvLength',   c_uint64),
-('Signature',  c_uint32),
-('Attributes', c_uint32),
-('HeaderLength',   c_uint16),
-('Checksum',   c_uint16),
-('ExtHeaderOffset',c_uint16),
-('Reserved',   c_uint8),
-('Revision',   c_uint8)
+('ZeroVector',   ARRAY(c_uint8, 16)),
+('FileSystemGuid',   ARRAY(c_uint8, 16)),
+('FvLength', c_uint64),
+('Signature',ARRAY(c_char, 4)),
+('Attributes',   c_uint32),
+('HeaderLength', c_uint16),
+('Checksum', c_uint16),
+('ExtHeaderOffset',  c_uint16),
+('Reserved', c_uint8),
+('Revision', c_uint8)
 ]
 
 class EFI_FIRMWARE_VOLUME_EXT_HEADER(Structure):
 _fields_ = [
-('FvName', ARRAY(c_char, 16)),
-('ExtHeaderSize',  c_uint32)
+('FvName',   ARRAY(c_uint8, 16)),
+('ExtHeaderSize',c_uint32)
 ]
 
 class EFI_FFS_INTEGRITY_CHECK(Structure):
 _fields_ = [
-('Header', c_uint8),
-('File',   c_uint8)
+('Header',   c_uint8),
+('File', c_uint8)
 ]
 
 class EFI_FFS_FILE_HEADER(Structure):
 _fields_ = [
-('Name',   ARRAY(c_char, 16)),
-('IntegrityCheck', EFI_FFS_INTEGRITY_CHECK),
-('Type',   c_uint8),
-('Attributes', c_uint8),
-('Size',   c_uint24),
-('State',  c_uint8)
+('Name', ARRAY(c_uint8, 16)),
+('IntegrityCheck',   EFI_FFS_INTEGRITY_CHECK),
+('Type', c_uint8),
+('Attributes',   c_uint8),
+('Size',

[edk2] [PATCH] CorebootModulePkg/PciHostBridgeLib: Fix PCI 64bit memory BAR size issue

2016-05-26 Thread Maurice Ma

The current PCI 64bit memory BAR size calculation in PciHostBridgeLib
assumes all 32 bits in the upper BAR are fully writable. However,
platform might only support partial address programming, such as 40bit
PCI BAR address. In this case the complement cannot be used for size
calculation.  Instead, the lowest non-zero bit should be used for BAR
size calculation.

Cc: Prince Agyeman 
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Maurice Ma 
---
 CorebootPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeSupport.c | 6 +-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/CorebootPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeSupport.c 
b/CorebootPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeSupport.c
index a95ffcaf6490..0f1c8cb1a210 100644
--- a/CorebootPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeSupport.c
+++ b/CorebootPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeSupport.c
@@ -193,6 +193,7 @@ PcatPciRootBridgeParseBars (
   UINT32UpperValue;
   UINT64Mask;
   UINTN Offset;
+  UINTN LowBit;
   UINT64Base;
   UINT64Length;
   UINT64Limit;
@@ -262,7 +263,10 @@ PcatPciRootBridgeParseBars (
 
   Base = Base | LShiftU64 ((UINT64) OriginalUpperValue, 32);
   Length = Length | LShiftU64 ((UINT64) UpperValue, 32);
-  Length = (~Length) + 1;
+  if (Length != 0) {
+LowBit = LowBitSet64 (Length);
+Length = LShiftU64 (1ULL, LowBit);
+  }
 
   if ((Value & BIT3) == BIT3) {
 MemAperture = PMemAbove4G;
-- 
1.9.5.msysgit.0

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[edk2] [PATCH] IntelFsp2Pkg/Tools: Add BSF bit field support in GenCfgOpt tool

2016-05-25 Thread Maurice Ma

The current GenCfgOpt tool does not generate bit fields in BSF.
This change will allow bit fields to be created in BSF for a specific
FSP UPD item. The argument for the tool is also updated to be in sync
with the old usage model in IntelFspPkg.

Cc: Jiewen Yao 
Cc: Giri P Mudusuru 
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Maurice Ma 
---
 IntelFsp2Pkg/Tools/GenCfgOpt.py | 224 
 1 file changed, 113 insertions(+), 111 deletions(-)

diff --git a/IntelFsp2Pkg/Tools/GenCfgOpt.py b/IntelFsp2Pkg/Tools/GenCfgOpt.py
index 4fd0562e7534..e8cec95aa735 100644
--- a/IntelFsp2Pkg/Tools/GenCfgOpt.py
+++ b/IntelFsp2Pkg/Tools/GenCfgOpt.py
@@ -310,6 +310,7 @@ EndList
 self._BuidinOption  = {'$EN_DIS' : 'EN_DIS'}
 
 self._MacroDict   = {}
+self._PcdsDict= {}
 self._CfgBlkDict  = {}
 self._CfgPageDict = {}
 self._CfgItemList = []
@@ -374,8 +375,21 @@ EndList
   Line = Line.replace(Each, Each[2:-1])
 return Line
 
+def ExpandPcds (self, Input):
+Line = Input
+Match = re.findall("(\w+\.\w+)", Input)
+if Match:
+for PcdName in Match:
+  if PcdName in self._PcdsDict:
+  Line = Line.replace(PcdName, self._PcdsDict[PcdName])
+  else:
+  if self.Debug:
+  print "WARN : %s is not defined" % PcdName
+return Line
+
 def EvaluateExpress (self, Expr):
-ExpExpr = self.ExpandMacros(Expr)
+ExpExpr = self.ExpandPcds(Expr)
+ExpExpr = self.ExpandMacros(ExpExpr)
 LogExpr = CLogicalExpression()
 Result  = LogExpr.evaluateExpress (ExpExpr)
 if self.Debug:
@@ -411,7 +425,7 @@ EndList
 ConfigDict['value'] = newvalue
 return ""
 
-def ParseDscFile (self, DscFile, FvDir, ConfigDscFile, ExtConfigDscFile):
+def ParseDscFile (self, DscFile, FvDir):
 self._CfgItemList = []
 self._CfgPageDict = {}
 self._CfgBlkDict  = {}
@@ -419,9 +433,9 @@ EndList
 self._FvDir   = FvDir
 
 IsDefSect   = False
+IsPcdSect   = False
 IsUpdSect   = False
 IsVpdSect   = False
-Found   = False
 
 IfStack = []
 ElifStack   = []
@@ -437,10 +451,14 @@ EndList
 Handle   = False
 Match= re.match("^\[(.+)\]", DscLine)
 if Match is not None:
+IsDefSect = False
+IsPcdSect = False
+IsVpdSect = False
+IsUpdSect = False
 if  Match.group(1).lower() == "Defines".lower():
 IsDefSect = True
-IsVpdSect = False
-IsUpdSect = False
+if  Match.group(1).lower() == "PcdsFeatureFlag".lower():
+IsPcdSect = True
 elif Match.group(1).lower() == "PcdsDynamicVpd.Upd".lower():
 ConfigDict = {}
 ConfigDict['header']  = 'ON'
@@ -453,16 +471,9 @@ EndList
 ConfigDict['embed']   = ''
 ConfigDict['comment'] = ''
 ConfigDict['subreg']  = []
-IsDefSect = False
 IsUpdSect = True
-IsVpdSect = False
-Found = True
-else:
-IsDefSect = False
-IsUpdSect = False
-IsVpdSect = False
 else:
-if IsDefSect or IsUpdSect or IsVpdSect:
+if IsDefSect or IsPcdSect or IsUpdSect or IsVpdSect:
 if re.match("^!else($|\s+#.+)", DscLine):
 if IfStack:
 IfStack[-1] = not IfStack[-1]
@@ -490,41 +501,7 @@ EndList
 else:
 Match  = re.match("!(if|elseif)\s+(.+)", DscLine)
 if Match:
-IsFoundInFile = False
-MatchPcdFormat = 
re.match("^\s*(.+)\.(.+)\s*==\s*(.+)", Match.group(2))
-if MatchPcdFormat:
-   ExtConfigDsc = open(ExtConfigDscFile, 
"r")
-   ExtConfigDscLines = 
ExtConfigDsc.readlines()
-   ExtConfigDsc.close()
-   
-   while len(ExtConfigDscLines):
-   ExtConfigDscLine  = 
ExtConfigDscLines.pop(0).strip()
-   MatchExtConfigPcd = 
re.match

[edk2] [PATCH 1/1] CorebootPayloadPkg: Consume PlatformHookLib in PlatformBootManagerLib

2016-05-23 Thread Maurice Ma

When coreboot uses different baud rate from the default (115200), the
current BDS driver will not be able to enable serial console display
due to the inconsistent serial port PCD settings.  By adding the
PlatformHookLib reference in the inf file, it will enforce the PCDs
to be aligned with what have been passed from coreboot.

Cc: Prince Agyeman 
Cc: Lee Leahy 
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Maurice Ma 
---
 .../Library/PlatformBootManagerLib/PlatformBootManagerLib.inf  | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git 
a/CorebootPayloadPkg/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf 
b/CorebootPayloadPkg/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf
index 59227c759886..475c65d8a16f 100644
--- 
a/CorebootPayloadPkg/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf
+++ 
b/CorebootPayloadPkg/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf
@@ -1,7 +1,7 @@
 ## @file
 #  Include all platform action which can be customized by IBV/OEM.
 #
-#  Copyright (c) 2012 - 2015, Intel Corporation. All rights reserved.
+#  Copyright (c) 2012 - 2016, Intel Corporation. All rights reserved.
 #  This program and the accompanying materials
 #  are licensed and made available under the terms and conditions of the BSD 
License
 #  which accompanies this distribution.  The full text of the license may be 
found at
@@ -52,6 +52,7 @@
   DevicePathLib
   HiiLib
   PrintLib
+  PlatformHookLib
 
 [Guids]
 
-- 
1.9.5.msysgit.0

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[edk2] [PATCH 2/5] CorebootModulePkg: Add video resolution PCD initialization

2016-05-18 Thread Maurice Ma

The video console resolution related PCDs are required to be
initialized after switching to use the generic BdsDxe driver
in MdeModulePkg.

Cc: Prince Agyeman 
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Maurice Ma 
---
 CorebootModulePkg/CbSupportDxe/CbSupportDxe.c   | 16 
 CorebootModulePkg/CbSupportDxe/CbSupportDxe.h   |  1 +
 CorebootModulePkg/CbSupportDxe/CbSupportDxe.inf |  9 -
 3 files changed, 25 insertions(+), 1 deletion(-)

diff --git a/CorebootModulePkg/CbSupportDxe/CbSupportDxe.c 
b/CorebootModulePkg/CbSupportDxe/CbSupportDxe.c
index d81b7c23b717..767130475324 100755
--- a/CorebootModulePkg/CbSupportDxe/CbSupportDxe.c
+++ b/CorebootModulePkg/CbSupportDxe/CbSupportDxe.c
@@ -134,6 +134,7 @@ CbDxeEntryPoint (
   EFI_HOB_GUID_TYPE  *GuidHob;
   SYSTEM_TABLE_INFO  *pSystemTableInfo;
   ACPI_BOARD_INFO*pAcpiBoardInfo;
+  FRAME_BUFFER_INFO  *FbInfo;
 
   Status = EFI_SUCCESS;
   //
@@ -184,6 +185,21 @@ CbDxeEntryPoint (
   DEBUG ((EFI_D_ERROR, "PmCtrlReg at 0x%lx\n", (UINT64)mPmCtrlReg));
 
   //
+  // Find the frame buffer information and update PCDs
+  //
+  GuidHob = GetFirstGuidHob (&gUefiFrameBufferInfoGuid);
+  ASSERT (GuidHob != NULL);
+  FbInfo  = (FRAME_BUFFER_INFO *)GET_GUID_HOB_DATA (GuidHob);
+  Status = PcdSet32S (PcdVideoHorizontalResolution, 
FbInfo->HorizontalResolution);
+  ASSERT_EFI_ERROR (Status);
+  Status = PcdSet32S (PcdVideoVerticalResolution, FbInfo->VerticalResolution);
+  ASSERT_EFI_ERROR (Status);
+  Status = PcdSet32S (PcdSetupVideoHorizontalResolution, 
FbInfo->HorizontalResolution);
+  ASSERT_EFI_ERROR (Status);
+  Status = PcdSet32S (PcdSetupVideoVerticalResolution, 
FbInfo->VerticalResolution);
+  ASSERT_EFI_ERROR (Status);
+
+  //
   // Register callback on the ready to boot event
   // in order to enable SCI
   //
diff --git a/CorebootModulePkg/CbSupportDxe/CbSupportDxe.h 
b/CorebootModulePkg/CbSupportDxe/CbSupportDxe.h
index bace2728e63b..4c59ed94d76c 100644
--- a/CorebootModulePkg/CbSupportDxe/CbSupportDxe.h
+++ b/CorebootModulePkg/CbSupportDxe/CbSupportDxe.h
@@ -29,6 +29,7 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER 
EXPRESS OR IMPLIED.
 #include 
 #include 
 #include 
+#include 
 
 #include 
 
diff --git a/CorebootModulePkg/CbSupportDxe/CbSupportDxe.inf 
b/CorebootModulePkg/CbSupportDxe/CbSupportDxe.inf
index c92db8ded45e..99245183eaeb 100644
--- a/CorebootModulePkg/CbSupportDxe/CbSupportDxe.inf
+++ b/CorebootModulePkg/CbSupportDxe/CbSupportDxe.inf
@@ -49,11 +49,18 @@
   IoLib
   HobLib
 
-[Guids]  
+[Guids]
   gEfiAcpiTableGuid
   gEfiSmbiosTableGuid
   gUefiSystemTableInfoGuid
   gUefiAcpiBoardInfoGuid
+  gUefiFrameBufferInfoGuid
+
+[Pcd]
+  gEfiMdeModulePkgTokenSpaceGuid.PcdVideoHorizontalResolution
+  gEfiMdeModulePkgTokenSpaceGuid.PcdVideoVerticalResolution
+  gEfiMdeModulePkgTokenSpaceGuid.PcdSetupVideoHorizontalResolution
+  gEfiMdeModulePkgTokenSpaceGuid.PcdSetupVideoVerticalResolution
 
 [Depex]
   TRUE
-- 
1.9.5.msysgit.0

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[edk2] [PATCH 4/5] CorebootPayloadPkg: Switch to use generic BdxDxe driver

2016-05-18 Thread Maurice Ma

Switch over to use BdxDxe generic driver in MdeModulePkg.

Cc: Prince Agyeman 
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Maurice Ma 
---
 CorebootPayloadPkg/CorebootPayloadPkg.fdf|  3 ++-
 CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc| 32 
 CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc | 31 +++
 CorebootPayloadPkg/FbGop/FbGop.inf   |  3 ---
 4 files changed, 55 insertions(+), 14 deletions(-)

diff --git a/CorebootPayloadPkg/CorebootPayloadPkg.fdf 
b/CorebootPayloadPkg/CorebootPayloadPkg.fdf
index 848438ffad30..decc1ac82cf8 100644
--- a/CorebootPayloadPkg/CorebootPayloadPkg.fdf
+++ b/CorebootPayloadPkg/CorebootPayloadPkg.fdf
@@ -86,7 +86,8 @@ INF 
IntelFrameworkModulePkg/Universal/StatusCode/RuntimeDxe/StatusCodeRuntimeDxe
 
 INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf
 INF UefiCpuPkg/CpuDxe/CpuDxe.inf
-INF IntelFrameworkModulePkg/Universal/BdsDxe/BdsDxe.inf
+INF MdeModulePkg/Universal/BdsDxe/BdsDxe.inf
+INF MdeModulePkg/Application/UiApp/UiApp.inf
 INF PcAtChipsetPkg/8254TimerDxe/8254Timer.inf
 INF MdeModulePkg/Universal/Metronome/Metronome.inf
 INF MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf
diff --git a/CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc 
b/CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc
index 7db4e15edc92..dcc015140d66 100644
--- a/CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc
+++ b/CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc
@@ -137,6 +137,7 @@
   DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf
   
DxeServicesTableLib|MdePkg/Library/DxeServicesTableLib/DxeServicesTableLib.inf
   UefiCpuLib|UefiCpuPkg/Library/BaseUefiCpuLib/BaseUefiCpuLib.inf
+  SortLib|MdeModulePkg/Library/UefiSortLib/UefiSortLib.inf
 
   #
   # Generic Modules
@@ -146,7 +147,7 @@
   
OemHookStatusCodeLib|MdeModulePkg/Library/OemHookStatusCodeLibNull/OemHookStatusCodeLibNull.inf
   CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf
   
SecurityManagementLib|MdeModulePkg/Library/DxeSecurityManagementLib/DxeSecurityManagementLib.inf
-  GenericBdsLib|IntelFrameworkModulePkg/Library/GenericBdsLib/GenericBdsLib.inf
+  
UefiBootManagerLib|MdeModulePkg/Library/UefiBootManagerLib/UefiBootManagerLib.inf
   
CustomizedDisplayLib|MdeModulePkg/Library/CustomizedDisplayLib/CustomizedDisplayLib.inf
 
   #
@@ -162,14 +163,13 @@
   ResetSystemLib|CorebootPayloadPkg/Library/ResetSystemLib/ResetSystemLib.inf
   
SerialPortLib|CorebootModulePkg/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.inf
   
PlatformHookLib|CorebootPayloadPkg/Library/PlatformHookLib/PlatformHookLib.inf
-  PlatformBdsLib|CorebootPayloadPkg/Library/PlatformBdsLib/PlatformBdsLib.inf
+  
PlatformBootManagerLib|CorebootPayloadPkg/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf
 
   #
   # Misc
   #
   
DebugPrintErrorLevelLib|MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.inf
   
PerformanceLib|MdePkg/Library/BasePerformanceLibNull/BasePerformanceLibNull.inf
-  PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
 !if $(SOURCE_DEBUG_ENABLE) == TRUE
   
PeCoffExtraActionLib|SourceLevelDebugPkg/Library/PeCoffExtraActionLibDebug/PeCoffExtraActionLibDebug.inf
   
DebugCommunicationLib|SourceLevelDebugPkg/Library/DebugCommunicationLibSerialPort/DebugCommunicationLibSerialPort.inf
@@ -179,6 +179,8 @@
 !endif
   CbParseLib|CorebootModulePkg/Library/CbParseLib/CbParseLib.inf
   
DebugLib|IntelFrameworkModulePkg/Library/PeiDxeDebugLibReportStatusCode/PeiDxeDebugLibReportStatusCode.inf
+  LockBoxLib|MdeModulePkg/Library/LockBoxNullLib/LockBoxNullLib.inf
+  FileExplorerLib|MdeModulePkg/Library/FileExplorerLib/FileExplorerLib.inf
 
 [LibraryClasses.IA32.SEC]
   DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf
@@ -224,7 +226,7 @@
   
ReportStatusCodeLib|MdeModulePkg/Library/RuntimeDxeReportStatusCodeLib/RuntimeDxeReportStatusCodeLib.inf
 
 [LibraryClasses.common.UEFI_DRIVER,LibraryClasses.common.UEFI_APPLICATION]
-  PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
+  PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf
   
MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
   
ReportStatusCodeLib|MdeModulePkg/Library/DxeReportStatusCodeLib/DxeReportStatusCodeLib.inf
   HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf
@@ -247,6 +249,7 @@
   gEfiMdeModulePkgTokenSpaceGuid.PcdVariableStoreSize|0x1
 
   gEfiMdeModulePkgTokenSpaceGuid.PcdVpdBaseAddress|0x0
+  gEfiMdeModulePkgTokenSpaceGuid.PcdBootManagerMenuFile|{ 0x21, 0xaa, 0x2c, 
0x46, 0x14, 0x76, 0x03, 0x45, 0x83, 0x6e, 0x8a, 0xb6, 0xf4, 0x66, 0x23, 0x31 }
 
 !if $(SOURCE_DEBUG_ENABLE)
   gEfiSourceLevelDebugPkgTokenSpaceGuid.PcdDebugLoadImageMethod|0x2
@@ -310,6 +313,19 @@
   gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase64|0
   gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase|0
   gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase|0

[edk2] [PATCH 5/5] CorebootPayloadPkg: Remove BdsPlatform library

2016-05-18 Thread Maurice Ma

Since the new BdsDxe driver in MdeModulePkg is used, the old
BdsPlatform library is not used any more and should be removed.

Cc: Prince Agyeman 
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Maurice Ma 
---
 .../Library/PlatformBdsLib/BdsPlatform.c   | 1019 
 .../Library/PlatformBdsLib/BdsPlatform.h   |  161 
 .../Library/PlatformBdsLib/PlatformBdsLib.inf  |   56 --
 .../Library/PlatformBdsLib/PlatformData.c  |   62 --
 4 files changed, 1298 deletions(-)
 delete mode 100644 CorebootPayloadPkg/Library/PlatformBdsLib/BdsPlatform.c
 delete mode 100644 CorebootPayloadPkg/Library/PlatformBdsLib/BdsPlatform.h
 delete mode 100644 CorebootPayloadPkg/Library/PlatformBdsLib/PlatformBdsLib.inf
 delete mode 100644 CorebootPayloadPkg/Library/PlatformBdsLib/PlatformData.c

diff --git a/CorebootPayloadPkg/Library/PlatformBdsLib/BdsPlatform.c 
b/CorebootPayloadPkg/Library/PlatformBdsLib/BdsPlatform.c
deleted file mode 100644
index c0a2b1964530..
--- a/CorebootPayloadPkg/Library/PlatformBdsLib/BdsPlatform.c
+++ /dev/null
@@ -1,1019 +0,0 @@
-/** @file
-  This file include all platform action which can be customized by IBV/OEM.
-
-Copyright (c) 2014, Intel Corporation. All rights reserved.
-This program and the accompanying materials
-are licensed and made available under the terms and conditions of the BSD 
License
-which accompanies this distribution.  The full text of the license may be 
found at
-http://opensource.org/licenses/bsd-license.php
-
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-
-**/
-
-#include "BdsPlatform.h"
-
-//
-// Global data
-//
-BOOLEAN   mDetectVgaOnly;
-
-
-//
-// Type definitions
-//
-
-typedef
-EFI_STATUS
-(EFIAPI *PROTOCOL_INSTANCE_CALLBACK)(
-  IN EFI_HANDLE   Handle,
-  IN VOID *Instance,
-  IN VOID *Context
-  );
-
-/**
-  @param[in]  Handle - Handle of PCI device instance
-  @param[in]  PciIo - PCI IO protocol instance
-  @param[in]  Pci - PCI Header register block
-**/
-typedef
-EFI_STATUS
-(EFIAPI *VISIT_PCI_INSTANCE_CALLBACK)(
-  IN EFI_HANDLE   Handle,
-  IN EFI_PCI_IO_PROTOCOL  *PciIo,
-  IN PCI_TYPE00   *Pci
-  );
-
-
-//
-// Function prototypes
-//
-
-EFI_STATUS
-VisitAllInstancesOfProtocol (
-  IN EFI_GUID*Id,
-  IN PROTOCOL_INSTANCE_CALLBACK  CallBackFunction,
-  IN VOID*Context
-  );
-
-EFI_STATUS
-VisitAllPciInstancesOfProtocol (
-  IN VISIT_PCI_INSTANCE_CALLBACK CallBackFunction
-  );
-  
-  
-//
-// BDS Platform Functions
-//
-
-/**
-  Platform Bds init. Include the platform firmware vendor, revision
-  and so crc check.
-
-**/
-VOID
-EFIAPI
-PlatformBdsInit (
-  VOID
-  )
-{
-  gUartDeviceNode.BaudRate = PcdGet64 (PcdUartDefaultBaudRate);
-  gUartDeviceNode.DataBits = PcdGet8 (PcdUartDefaultDataBits);
-  gUartDeviceNode.Parity   = PcdGet8 (PcdUartDefaultParity);
-  gUartDeviceNode.StopBits = PcdGet8 (PcdUartDefaultStopBits);
-}
-
-
-EFI_STATUS
-PrepareLpcBridgeDevicePath (
-  IN EFI_HANDLEDeviceHandle
-  )
-/*++
-
-Routine Description:
-
-  Add IsaKeyboard to ConIn,
-  add IsaSerial to ConOut, ConIn, ErrOut.
-  LPC Bridge: 06 01 00
-
-Arguments:
-
-  DeviceHandle- Handle of PCIIO protocol.
-
-Returns:
-
-  EFI_SUCCESS - LPC bridge is added to ConOut, ConIn, and ErrOut.
-  EFI_STATUS  - No LPC bridge is added.
-
---*/
-{
-  EFI_STATUSStatus;
-  EFI_DEVICE_PATH_PROTOCOL  *DevicePath;
-  CHAR16*DevPathStr;
-
-  DevicePath = NULL;
-  Status = gBS->HandleProtocol (
-  DeviceHandle,
-  &gEfiDevicePathProtocolGuid,
-  (VOID*)&DevicePath
-  );
-  if (EFI_ERROR (Status)) {
-return Status;
-  }
-
-  //
-  // Register COM1
-  //
-  DevicePath = AppendDevicePathNode ((EFI_DEVICE_PATH_PROTOCOL *)NULL, 
(EFI_DEVICE_PATH_PROTOCOL *)&gUartDeviceVendorNode);
-  DevicePath = AppendDevicePathNode (DevicePath, (EFI_DEVICE_PATH_PROTOCOL 
*)&gUartDeviceNode);
-  DevicePath = AppendDevicePathNode (DevicePath, (EFI_DEVICE_PATH_PROTOCOL 
*)&gTerminalTypeDeviceNode);
-
-  //
-  // Print Device Path
-  //
-  DevPathStr = DevicePathToStr(DevicePath);
-  DEBUG((
-EFI_D_INFO,
-"BdsPlatform.c+%d: COM%d DevPath: %s\n",
-__LINE__,
-gPnp16550ComPortDeviceNode.UID + 1,
-DevPathStr
-));
-  FreePool(DevPathStr);
-
-  BdsLibUpdateConsoleVariable (VarConsoleOut, DevicePath, NULL);
-  BdsLibUpdateConsoleVariable (VarConsoleInp, DevicePath, NULL);
-  BdsLibUpdateConsoleVariable (VarErrorOut, DevicePath, NULL);
-
-  return EFI_SUCCESS;
-}
-
-EFI_STATUS
-GetGopDevicePath (
-   IN  EFI_DEVICE_PATH_PROTOCOL *PciDevicePath,
-   OUT EFI_DEVICE_PATH_PROTOCOL **GopDevicePath
-   )
-{
-

[edk2] [PATCH 3/5] CorebootPayloadPkg: Add coreboot PlatfromBootManagerLib implementation

2016-05-18 Thread Maurice Ma

In order to use the generic BdsDxe in MdeModulePkg, a platform
specific PlatfromBootManagerLib is required. This library will
help update the ConIn, ConOut and ErrOut variables.

Cc: Prince Agyeman 
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Maurice Ma 
---
 CorebootPayloadPkg/CorebootPayloadPkg.dec  |  24 +-
 .../PlatformBootManagerLib/PlatformBootManager.c   | 198 +++
 .../PlatformBootManagerLib/PlatformBootManager.h   | 128 +
 .../PlatformBootManagerLib.inf |  77 +++
 .../PlatformBootManagerLib/PlatformConsole.c   | 617 +
 .../PlatformBootManagerLib/PlatformConsole.h   |  76 +++
 .../Library/PlatformBootManagerLib/PlatformData.c  |  25 +
 7 files changed, 1133 insertions(+), 12 deletions(-)
 create mode 100644 
CorebootPayloadPkg/Library/PlatformBootManagerLib/PlatformBootManager.c
 create mode 100644 
CorebootPayloadPkg/Library/PlatformBootManagerLib/PlatformBootManager.h
 create mode 100644 
CorebootPayloadPkg/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf
 create mode 100644 
CorebootPayloadPkg/Library/PlatformBootManagerLib/PlatformConsole.c
 create mode 100644 
CorebootPayloadPkg/Library/PlatformBootManagerLib/PlatformConsole.h
 create mode 100644 
CorebootPayloadPkg/Library/PlatformBootManagerLib/PlatformData.c

diff --git a/CorebootPayloadPkg/CorebootPayloadPkg.dec 
b/CorebootPayloadPkg/CorebootPayloadPkg.dec
index 54eb3d2257ba..b33b79c1d6bd 100644
--- a/CorebootPayloadPkg/CorebootPayloadPkg.dec
+++ b/CorebootPayloadPkg/CorebootPayloadPkg.dec
@@ -1,16 +1,16 @@
 ## @file
 # Coreboot Payload Package
 #
-# Provides drivers and definitions to create uefi payload for coreboot. 
+# Provides drivers and definitions to create uefi payload for coreboot.
 #
 # Copyright (c) 2014, Intel Corporation. All rights reserved.
-# This program and the accompanying materials are licensed and made available 
under 
-# the terms and conditions of the BSD License that accompanies this 
distribution.  
+# This program and the accompanying materials are licensed and made available 
under
+# the terms and conditions of the BSD License that accompanies this 
distribution.
 # The full text of the license may be found at
-# http://opensource.org/licenses/bsd-license.php.  

-# 
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
 
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR 
IMPLIED.  
+# http://opensource.org/licenses/bsd-license.php.
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
 #
 ##
 
@@ -19,15 +19,15 @@
   PACKAGE_NAME   = CorebootPayloadPkg
   PACKAGE_GUID   = 58ABC905-951E-472e-8590-77BA8A50BE63
   PACKAGE_VERSION= 0.1
-  
+
 [LibraryClasses]
-  
+
 [Guids]
   #
   ## Defines the token space for the Coreboot Payload Package PCDs.
   #
-  gUEfiCorebootPayloadPkgTokenSpaceGuid  = {0x1d127ea, 0xf6f1, 0x4ef6, {0x94, 
0x15, 0x8a, 0x0, 0x0, 0x93, 0xf8, 0x9d}}  
-  
+  gUEfiCorebootPayloadPkgTokenSpaceGuid  = {0x1d127ea, 0xf6f1, 0x4ef6, {0x94, 
0x15, 0x8a, 0x0, 0x0, 0x93, 0xf8, 0x9d}}
+
   #
   # Gop Temp
   #
@@ -51,4 +51,4 @@
 [PcdsFixedAtBuild, PcdsPatchableInModule]
 
 [PcdsDynamic, PcdsDynamicEx]
- 
+
diff --git 
a/CorebootPayloadPkg/Library/PlatformBootManagerLib/PlatformBootManager.c 
b/CorebootPayloadPkg/Library/PlatformBootManagerLib/PlatformBootManager.c
new file mode 100644
index ..200ea9580877
--- /dev/null
+++ b/CorebootPayloadPkg/Library/PlatformBootManagerLib/PlatformBootManager.c
@@ -0,0 +1,198 @@
+/** @file
+  This file include all platform action which can be customized
+  by IBV/OEM.
+
+Copyright (c) 2015, Intel Corporation. All rights reserved.
+This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD 
License
+which accompanies this distribution.  The full text of the license may be 
found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include "PlatformBootManager.h"
+#include "PlatformConsole.h"
+
+/**
+  Return the index of the load option in the load option array.
+
+  The function consider two load options are equal when the
+  OptionType, Attributes, Description, FilePath and OptionalData are equal.
+
+  @param KeyPointer to the load option to be found.
+  @param Array  Pointer to the array of load options to be found.
+  @param Count  Number of entries in the Array.
+
+  @retval -1  Key wasn't found in the Array.
+  @retval 0 ~ Count-1 The index of the Key in the Array.
+**/
+INTN
+PlatformFindLoa

[edk2] [PATCH 1/5] CorebootModulePkg: Convert TAB to white space for CbSupportDxe driver

2016-05-18 Thread Maurice Ma

Convert TAB to white space for CbSupportDxe driver.

Cc: Prince Agyeman 
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Maurice Ma 
---
 CorebootModulePkg/CbSupportDxe/CbSupportDxe.c | 142 +-
 1 file changed, 71 insertions(+), 71 deletions(-)

diff --git a/CorebootModulePkg/CbSupportDxe/CbSupportDxe.c 
b/CorebootModulePkg/CbSupportDxe/CbSupportDxe.c
index 68baad6d00e0..d81b7c23b717 100755
--- a/CorebootModulePkg/CbSupportDxe/CbSupportDxe.c
+++ b/CorebootModulePkg/CbSupportDxe/CbSupportDxe.c
@@ -1,7 +1,7 @@
 /** @file
-  This driver will report some MMIO/IO resources to dxe core, extract smbios 
and acpi 
+  This driver will report some MMIO/IO resources to dxe core, extract smbios 
and acpi
   tables from coreboot and install.
-  
+
   Copyright (c) 2014, Intel Corporation. All rights reserved.
   This program and the accompanying materials
   are licensed and made available under the terms and conditions of the BSD 
License
@@ -37,7 +37,7 @@ CbReserveResourceInGcd (
   IN EFI_HANDLEImageHandle
   )
 {
-   EFI_STATUS   Status;
+  EFI_STATUS   Status;
 
   if (IsMMIO) {
 Status = gDS->AddMemorySpace (
@@ -103,21 +103,21 @@ OnReadyToBoot (
   IN  EFI_EVENT  Event,
   IN  VOID   *Context
   )
-{  
-   //
-   // Enable SCI
-   //
-   IoOr16 (mPmCtrlReg, BIT0);
-   
-   DEBUG ((EFI_D_ERROR, "Enable SCI bit at 0x%lx before boot\n", 
(UINT64)mPmCtrlReg)); 
+{
+  //
+  // Enable SCI
+  //
+  IoOr16 (mPmCtrlReg, BIT0);
+
+  DEBUG ((EFI_D_ERROR, "Enable SCI bit at 0x%lx before boot\n", 
(UINT64)mPmCtrlReg));
 }
 
 /**
   Main entry for the Coreboot Support DXE module.
-  
+
   @param[in] ImageHandleThe firmware allocated handle for the EFI image.
   @param[in] SystemTableA pointer to the EFI System Table.
-  
+
   @retval EFI_SUCCESS   The entry point is executed successfully.
   @retval other Some error occurs when executing this entry point.
 
@@ -128,66 +128,66 @@ CbDxeEntryPoint (
   IN EFI_HANDLE ImageHandle,
   IN EFI_SYSTEM_TABLE   *SystemTable
   )
-{  
-   EFI_STATUS Status;
-   EFI_EVENT  ReadyToBootEvent;
-   EFI_HOB_GUID_TYPE  *GuidHob;
-   SYSTEM_TABLE_INFO  *pSystemTableInfo;
-   ACPI_BOARD_INFO*pAcpiBoardInfo;
-   
-   Status = EFI_SUCCESS;
-   //
-   // Report MMIO/IO Resources
-   //
-   Status = CbReserveResourceInGcd (TRUE, EfiGcdMemoryTypeMemoryMappedIo, 
0xFEE0, SIZE_1MB, 0, SystemTable); // LAPIC 
-   ASSERT_EFI_ERROR (Status);
-   
-   Status = CbReserveResourceInGcd (TRUE, EfiGcdMemoryTypeMemoryMappedIo, 
0xFEC0, SIZE_4KB, 0, SystemTable); // IOAPIC 
-   ASSERT_EFI_ERROR (Status);
-   
-   Status = CbReserveResourceInGcd (TRUE, EfiGcdMemoryTypeMemoryMappedIo, 
0xFED0, SIZE_1KB, 0, SystemTable); // HPET 
-   ASSERT_EFI_ERROR (Status);
-   
-   //
-   // Find the system table information guid hob
-   //
-   GuidHob = GetFirstGuidHob (&gUefiSystemTableInfoGuid);
-   ASSERT (GuidHob != NULL);
+{
+  EFI_STATUS Status;
+  EFI_EVENT  ReadyToBootEvent;
+  EFI_HOB_GUID_TYPE  *GuidHob;
+  SYSTEM_TABLE_INFO  *pSystemTableInfo;
+  ACPI_BOARD_INFO*pAcpiBoardInfo;
+
+  Status = EFI_SUCCESS;
+  //
+  // Report MMIO/IO Resources
+  //
+  Status = CbReserveResourceInGcd (TRUE, EfiGcdMemoryTypeMemoryMappedIo, 
0xFEE0, SIZE_1MB, 0, SystemTable); // LAPIC
+  ASSERT_EFI_ERROR (Status);
+
+  Status = CbReserveResourceInGcd (TRUE, EfiGcdMemoryTypeMemoryMappedIo, 
0xFEC0, SIZE_4KB, 0, SystemTable); // IOAPIC
+  ASSERT_EFI_ERROR (Status);
+
+  Status = CbReserveResourceInGcd (TRUE, EfiGcdMemoryTypeMemoryMappedIo, 
0xFED0, SIZE_1KB, 0, SystemTable); // HPET
+  ASSERT_EFI_ERROR (Status);
+
+  //
+  // Find the system table information guid hob
+  //
+  GuidHob = GetFirstGuidHob (&gUefiSystemTableInfoGuid);
+  ASSERT (GuidHob != NULL);
   pSystemTableInfo = (SYSTEM_TABLE_INFO *)GET_GUID_HOB_DATA (GuidHob);
-   
-   //
-   // Install Acpi Table
-   //
-   if (pSystemTableInfo->AcpiTableBase != 0 && 
pSystemTableInfo->AcpiTableSize != 0) { 
-   DEBUG ((EFI_D_ERROR, "Install Acpi Table at 0x%lx, length 
0x%x\n", pSystemTableInfo->AcpiTableBase, pSystemTableInfo->AcpiTableSize));  
-   Status = gBS->InstallConfigurationTable (&gEfiAcpiTableGuid, 
(VOID *)(UINTN)pSystemTableInfo->AcpiTableBase);
-   ASSERT_EFI_ERROR (Status);
-   }
-   
-   //
-   // Install Smbios Table
-   //
-   if (pSystemTableInfo->SmbiosTableBase != 0 && 
pSystemTableInfo->SmbiosTableSize != 0) { 
-   DEBUG ((EFI_D_ERROR, "Install Smbios Table at 0x%lx, length 
0x%x\n", pSystemTableInfo->SmbiosTableBase, 
pSystemTableInfo->SmbiosTableSize)

[edk2] [PATCH 0/5] CorebootPayloadPkg: Switch to use BdxDxe driver in MdeModulePkg

2016-05-18 Thread Maurice Ma

This is part of the clean-up for CorebootModulePkg and CorebootPayloadPkg.
The current CorebootPayloadPkg uses the BdxDxe driver from 
IntelFrameworkModulePkg. Now it will switch over to use the BdxDxe driver 
in MdeModulePkg instead. A new coreboot PlatformBootManagerLib instance is
created and the old PlatformBdsLib instance is removed.

These changes have been tested on MinnowMax board.

Maurice Ma (5):
  CorebootModulePkg: Convert TAB to white space for CbSupportDxe driver
  CorebootModulePkg: Add video resolution PCD initialization
  CorebootPayloadPkg: Add coreboot PlatfromBootManagerLib implementation
  CorebootPayloadPkg: Switch to use generic BdxDxe driver
  CorebootPayloadPkg: Remove BdsPlatform library

 CorebootModulePkg/CbSupportDxe/CbSupportDxe.c  |  158 +--
 CorebootModulePkg/CbSupportDxe/CbSupportDxe.h  |1 +
 CorebootModulePkg/CbSupportDxe/CbSupportDxe.inf|9 +-
 CorebootPayloadPkg/CorebootPayloadPkg.dec  |   24 +-
 CorebootPayloadPkg/CorebootPayloadPkg.fdf  |3 +-
 CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc  |   32 +-
 CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc   |   31 +-
 CorebootPayloadPkg/FbGop/FbGop.inf |3 -
 .../Library/PlatformBdsLib/BdsPlatform.c   | 1019 
 .../Library/PlatformBdsLib/BdsPlatform.h   |  161 
 .../Library/PlatformBdsLib/PlatformData.c  |   62 --
 .../PlatformBootManagerLib/PlatformBootManager.c   |  198 
 .../PlatformBootManagerLib/PlatformBootManager.h   |  128 +++
 .../PlatformBootManagerLib.inf}|   61 +-
 .../PlatformBootManagerLib/PlatformConsole.c   |  617 
 .../PlatformBootManagerLib/PlatformConsole.h   |   76 ++
 .../Library/PlatformBootManagerLib/PlatformData.c  |   25 +
 17 files changed, 1248 insertions(+), 1360 deletions(-)
 delete mode 100644 CorebootPayloadPkg/Library/PlatformBdsLib/BdsPlatform.c
 delete mode 100644 CorebootPayloadPkg/Library/PlatformBdsLib/BdsPlatform.h
 delete mode 100644 CorebootPayloadPkg/Library/PlatformBdsLib/PlatformData.c
 create mode 100644 
CorebootPayloadPkg/Library/PlatformBootManagerLib/PlatformBootManager.c
 create mode 100644 
CorebootPayloadPkg/Library/PlatformBootManagerLib/PlatformBootManager.h
 rename CorebootPayloadPkg/Library/{PlatformBdsLib/PlatformBdsLib.inf => 
PlatformBootManagerLib/PlatformBootManagerLib.inf} (51%)
 create mode 100644 
CorebootPayloadPkg/Library/PlatformBootManagerLib/PlatformConsole.c
 create mode 100644 
CorebootPayloadPkg/Library/PlatformBootManagerLib/PlatformConsole.h
 create mode 100644 
CorebootPayloadPkg/Library/PlatformBootManagerLib/PlatformData.c

-- 
1.9.5.msysgit.0

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[edk2] [PATCH] CorebootModulePkg: Use PCD for memory type information initialization

2016-05-18 Thread Maurice Ma

CorebootModulePkg currently uses a hardcoded table for memory type
initialization. It might need to be adjusted by platform to reduce
the memory fragmentation. So changing to use PCDs rather than constant
values to facilitate the customization.

Cc: Prince Agyeman 
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Maurice Ma 
---
 CorebootModulePkg/CbSupportPei/CbSupportPei.c   | 10 +-
 CorebootModulePkg/CbSupportPei/CbSupportPei.inf |  5 +
 CorebootModulePkg/CorebootModulePkg.dec |  6 ++
 3 files changed, 16 insertions(+), 5 deletions(-)

diff --git a/CorebootModulePkg/CbSupportPei/CbSupportPei.c 
b/CorebootModulePkg/CbSupportPei/CbSupportPei.c
index e58aa2d03d9d..80600a6b0e2f 100755
--- a/CorebootModulePkg/CbSupportPei/CbSupportPei.c
+++ b/CorebootModulePkg/CbSupportPei/CbSupportPei.c
@@ -18,11 +18,11 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER 
EXPRESS OR IMPLIED.
 #define LEGACY_8259_MASK_REGISTER_SLAVE   0xA1
 
 EFI_MEMORY_TYPE_INFORMATION mDefaultMemoryTypeInformation[] = {
-  { EfiACPIReclaimMemory,   0x008 },
-  { EfiACPIMemoryNVS,   0x004 },
-  { EfiReservedMemoryType,  0x004 },
-  { EfiRuntimeServicesData, 0x080 },
-  { EfiRuntimeServicesCode, 0x080 },
+  { EfiACPIReclaimMemory,   FixedPcdGet32 (PcdMemoryTypeEfiACPIReclaimMemory) 
},
+  { EfiACPIMemoryNVS,   FixedPcdGet32 (PcdMemoryTypeEfiACPIMemoryNVS) },
+  { EfiReservedMemoryType,  FixedPcdGet32 (PcdMemoryTypeEfiReservedMemoryType) 
},
+  { EfiRuntimeServicesData, FixedPcdGet32 
(PcdMemoryTypeEfiRuntimeServicesData) },
+  { EfiRuntimeServicesCode, FixedPcdGet32 
(PcdMemoryTypeEfiRuntimeServicesCode) },
   { EfiMaxMemoryType,   0 }
 };
 
diff --git a/CorebootModulePkg/CbSupportPei/CbSupportPei.inf 
b/CorebootModulePkg/CbSupportPei/CbSupportPei.inf
index b88b6f07ffe3..3c903e8712f6 100644
--- a/CorebootModulePkg/CbSupportPei/CbSupportPei.inf
+++ b/CorebootModulePkg/CbSupportPei/CbSupportPei.inf
@@ -68,6 +68,11 @@
   gUefiCorebootModulePkgTokenSpaceGuid.PcdPayloadFdMemBase
   gUefiCorebootModulePkgTokenSpaceGuid.PcdPayloadFdMemSize
   gUefiCorebootModulePkgTokenSpaceGuid.PcdCbHeaderPointer  
+  gUefiCorebootModulePkgTokenSpaceGuid.PcdMemoryTypeEfiACPIReclaimMemory
+  gUefiCorebootModulePkgTokenSpaceGuid.PcdMemoryTypeEfiACPIMemoryNVS
+  gUefiCorebootModulePkgTokenSpaceGuid.PcdMemoryTypeEfiReservedMemoryType
+  gUefiCorebootModulePkgTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesData
+  gUefiCorebootModulePkgTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesCode
   
 [Depex]
   TRUE
\ No newline at end of file
diff --git a/CorebootModulePkg/CorebootModulePkg.dec 
b/CorebootModulePkg/CorebootModulePkg.dec
index 4b97f9f24948..79c729dff25e 100644
--- a/CorebootModulePkg/CorebootModulePkg.dec
+++ b/CorebootModulePkg/CorebootModulePkg.dec
@@ -53,6 +53,12 @@
 gUefiCorebootModulePkgTokenSpaceGuid.PcdPayloadFdMemBase|0|UINT32|0x1001
 ## Provides the size of the payload binary in memory
 gUefiCorebootModulePkgTokenSpaceGuid.PcdPayloadFdMemSize|0|UINT32|0x1002
+## Used to help reduce fragmentation in the EFI memory map
+gUefiCorebootModulePkgTokenSpaceGuid.PcdMemoryTypeEfiACPIReclaimMemory|0x08|UINT32|0x1012
+gUefiCorebootModulePkgTokenSpaceGuid.PcdMemoryTypeEfiACPIMemoryNVS|0x04|UINT32|0x1013
+gUefiCorebootModulePkgTokenSpaceGuid.PcdMemoryTypeEfiReservedMemoryType|0x04|UINT32|0x0014
+gUefiCorebootModulePkgTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesData|0xC0|UINT32|0x0015
+gUefiCorebootModulePkgTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesCode|0x80|UINT32|0x0016
 
 [PcdsDynamicEx]
 gUefiCorebootModulePkgTokenSpaceGuid.PcdCbHeaderPointer|0|UINT32|0x1003
-- 
1.9.5.msysgit.0

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[edk2] [PATCH] CorebootPayloadPkg: Use generic PciBus/PciHostBridge driver

2016-05-16 Thread Maurice Ma

Current CorebootPayloadPkg uses PciBusNoEnumerationDxe and
PciRootBridgenoEnumerationDxe copied from the DuetPkg. Now it will
switch to use the standard PciBusDxe and PciHostBridgeDxe from
MdeModulePkg. As a result, a coreboot specific PciHostBridgeLib
is added to collect pre-allocated PCI resources.

Cc: Prince Agyeman 
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Maurice Ma 
---
 CorebootPayloadPkg/CorebootPayloadPkg.fdf  |   4 +-
 CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc  |  20 +-
 CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc   |  20 +-
 .../Library/PciHostBridgeLib/PciHostBridge.h   |  86 +++
 .../Library/PciHostBridgeLib/PciHostBridgeLib.c| 228 
 .../Library/PciHostBridgeLib/PciHostBridgeLib.inf  |  47 ++
 .../PciHostBridgeLib/PciHostBridgeSupport.c| 581 +
 7 files changed, 976 insertions(+), 10 deletions(-)
 create mode 100644 CorebootPayloadPkg/Library/PciHostBridgeLib/PciHostBridge.h
 create mode 100644 
CorebootPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeLib.c
 create mode 100644 
CorebootPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeLib.inf
 create mode 100644 
CorebootPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeSupport.c

diff --git a/CorebootPayloadPkg/CorebootPayloadPkg.fdf 
b/CorebootPayloadPkg/CorebootPayloadPkg.fdf
index 848438f..1aac1db 100644
--- a/CorebootPayloadPkg/CorebootPayloadPkg.fdf
+++ b/CorebootPayloadPkg/CorebootPayloadPkg.fdf
@@ -110,8 +110,8 @@ INF MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf
 #
 # PCI Support
 #
-INF 
CorebootModulePkg/PciRootBridgeNoEnumerationDxe/PciRootBridgeNoEnumeration.inf
-INF CorebootModulePkg/PciBusNoEnumerationDxe/PciBusNoEnumeration.inf
+INF MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
+INF MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf
 
 #
 # ISA Support
diff --git a/CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc 
b/CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc
index 7db4e15..6234548 100644
--- a/CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc
+++ b/CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc
@@ -39,6 +39,11 @@
   DEFINE MAX_LOGICAL_PROCESSORS  = 64
 
   #
+  # PCI options
+  #
+  DEFINE PCIE_BASE= 0xE000
+
+  #
   # Serial port set up
   #
   DEFINE BAUD_RATE= 115200
@@ -115,8 +120,9 @@
   PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf
   CpuLib|MdePkg/Library/BaseCpuLib/BaseCpuLib.inf
   IoLib|MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf
-  PciLib|MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf
-  PciCf8Lib|MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf
+  PciLib|MdePkg/Library/BasePciLibPciExpress/BasePciLibPciExpress.inf
+  PciExpressLib|MdePkg/Library/BasePciExpressLib/BasePciExpressLib.inf
+  PciSegmentLib|MdePkg/Library/BasePciSegmentLibPci/BasePciSegmentLibPci.inf
   PeCoffLib|MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf
   
PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.inf
   
CacheMaintenanceLib|MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf
@@ -248,6 +254,8 @@
 
   gEfiMdeModulePkgTokenSpaceGuid.PcdVpdBaseAddress|0x0
 
+  gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|$(PCIE_BASE)
+
 !if $(SOURCE_DEBUG_ENABLE)
   gEfiSourceLevelDebugPkgTokenSpaceGuid.PcdDebugLoadImageMethod|0x2
 !endif
@@ -279,6 +287,7 @@
   gEfiMdeModulePkgTokenSpaceGuid.PcdSerialFifoControl|$(SERIAL_FIFO_CONTROL)
   
gEfiMdeModulePkgTokenSpaceGuid.PcdSerialExtendedTxFifoSize|$(SERIAL_EXTENDED_TX_FIFO_SIZE)
 
+  gEfiMdeModulePkgTokenSpaceGuid.PcdPciDisableBusEnumeration|TRUE
   gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate|$(UART_DEFAULT_BAUD_RATE)
   gEfiMdePkgTokenSpaceGuid.PcdUartDefaultDataBits|$(UART_DEFAULT_DATA_BITS)
   gEfiMdePkgTokenSpaceGuid.PcdUartDefaultParity|$(UART_DEFAULT_PARITY)
@@ -396,8 +405,11 @@
   #
   # PCI Support
   #
-  
CorebootModulePkg/PciRootBridgeNoEnumerationDxe/PciRootBridgeNoEnumeration.inf
-  CorebootModulePkg/PciBusNoEnumerationDxe/PciBusNoEnumeration.inf
+  MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
+  MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf {
+
+  
PciHostBridgeLib|CorebootPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeLib.inf
+  }
 
   #
   # SCSI/ATA/IDE/DISK Support
diff --git a/CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc 
b/CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc
index 7301346..1f6eee4 100644
--- a/CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc
+++ b/CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc
@@ -39,6 +39,11 @@
   DEFINE MAX_LOGICAL_PROCESSORS  = 64
 
   #
+  # PCI options
+  #
+  DEFINE PCIE_BASE= 0xE000
+
+  #
   # Serial port set up
   #
   DEFINE BAUD_RATE= 115200
@@ -117,8 +122,9 @@
   PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf
   CpuLib|MdePkg/Library/BaseCpuLib/BaseCpuLib.inf
   IoLib|MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf
-  PciLib

[edk2] [PATCH] MdeModulePkg: Skip invalid bus number scanning in PciBusDxe driver

2016-05-16 Thread Maurice Ma

When PcdPciDisableBusEnumeration is enabled, the PciBus driver
might get into a dead loop if the secondary bus register on PCI
bridge is not programmed or programmed improperly. Adding this
check to avoid any potential dead loop caused by this.

Cc: Feng Tian 
Cc: Star Zeng 
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Maurice Ma 
---
 MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.c | 8 
 1 file changed, 8 insertions(+)

diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.c 
b/MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.c
index a6ade26e3a09..086c481130c8 100644
--- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.c
+++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.c
@@ -165,6 +165,14 @@ PciPciDeviceInfoCollector (
   }
 
   //
+  // Ensure secondary bus number is greater than the primary bus 
number to avoid
+  // any potential dead loop when PcdPciDisableBusEnumeration is set 
to TRUE
+  //
+  if (SecBus <= StartBusNumber) {
+break;
+  }
+
+  //
   // Get resource padding for PPB
   //
   GetResourcePaddingPpb (PciIoDevice);
-- 
1.9.5.msysgit.0

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[edk2] [PATCH] CorebootPayloadPkg: Use generic SerialDxe driver

2016-05-13 Thread Maurice Ma

Use generic SerialDxe driver in MdeModulePkg instead of the one
in CorebootModulePkg. By doing this the reference for
PciSioSerialDxe driver will also be removed from DSC and FDF file.

Cc: Prince Agyeman 
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Maurice Ma 
---
 CorebootPayloadPkg/CorebootPayloadPkg.fdf| 3 +--
 CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc| 3 +--
 CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc | 3 +--
 3 files changed, 3 insertions(+), 6 deletions(-)

diff --git a/CorebootPayloadPkg/CorebootPayloadPkg.fdf 
b/CorebootPayloadPkg/CorebootPayloadPkg.fdf
index 4aee5ac63133..848438ffad30 100644
--- a/CorebootPayloadPkg/CorebootPayloadPkg.fdf
+++ b/CorebootPayloadPkg/CorebootPayloadPkg.fdf
@@ -112,12 +112,11 @@ INF MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf
 #
 INF 
CorebootModulePkg/PciRootBridgeNoEnumerationDxe/PciRootBridgeNoEnumeration.inf
 INF CorebootModulePkg/PciBusNoEnumerationDxe/PciBusNoEnumeration.inf
-INF CorebootModulePkg/PciSioSerialDxe/PciSioSerialDxe.inf
 
 #
 # ISA Support
 #
-INF CorebootModulePkg/SerialDxe/SerialDxe.inf
+INF MdeModulePkg/Universal/SerialDxe/SerialDxe.inf
 
 #
 # Console Support
diff --git a/CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc 
b/CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc
index 725c912db808..7db4e15edc92 100644
--- a/CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc
+++ b/CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc
@@ -398,7 +398,6 @@
   #
   
CorebootModulePkg/PciRootBridgeNoEnumerationDxe/PciRootBridgeNoEnumeration.inf
   CorebootModulePkg/PciBusNoEnumerationDxe/PciBusNoEnumeration.inf
-  CorebootModulePkg/PciSioSerialDxe/PciSioSerialDxe.inf
 
   #
   # SCSI/ATA/IDE/DISK Support
@@ -438,7 +437,7 @@
   #
   # ISA Support
   #
-  CorebootModulePkg/SerialDxe/SerialDxe.inf
+  MdeModulePkg/Universal/SerialDxe/SerialDxe.inf
 
   #
   # Console Support
diff --git a/CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc 
b/CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc
index c2396592d19a..730134637fa6 100644
--- a/CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc
+++ b/CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc
@@ -402,7 +402,6 @@
   #
   
CorebootModulePkg/PciRootBridgeNoEnumerationDxe/PciRootBridgeNoEnumeration.inf
   CorebootModulePkg/PciBusNoEnumerationDxe/PciBusNoEnumeration.inf
-  CorebootModulePkg/PciSioSerialDxe/PciSioSerialDxe.inf
 
   #
   # SCSI/ATA/IDE/DISK Support
@@ -442,7 +441,7 @@
   #
   # ISA Support
   #
-  CorebootModulePkg/SerialDxe/SerialDxe.inf
+  MdeModulePkg/Universal/SerialDxe/SerialDxe.inf
 
   #
   # Console Support
-- 
1.9.5.msysgit.0

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[edk2] [PATCH v2] CorebootPayloadPkg/FbGop: Locate correct framebuffer device

[edk2] [PATCH] CorebootPayloadPkg/FbGop: Locate correct framebuffer device

[edk2] [PATCH 1/1] CorebootPayloadPkg: Add APRIORI file in FDF file

[edk2] [PATCH 1/1] CorebootPayloadPkg: Remove improper build flags in DSC file

[edk2] [PATCH 2/2] CorebootPayloadPkg/CbSupportPei: Fix the memory map issue

[edk2] [PATCH 1/2] CorebootPayloadPkg: Allow PciLib instance selection

[edk2] [PATCH] CorebootPayloadPkg: Fix GCC build issue on macro definition

[edk2] [PATCH] CorebootPayloadPkg: Add an option to use HPET timer driver

[edk2] [PATCH] CorebootPayloadPkg DSC: Change the section alignment option

[edk2] [PATCH] CorebootPayloadPkg: Switch to use StatusCode drvier in MdeModulePkg

[edk2] [PATCH] CorebootPayloadPkg DSC: Add build option to disable deprecated APIs

[edk2] [PATCH] CorebootPayloadPkg/PciHostBridgeLib: Fix the wrong PCI resource limit

[edk2] [PATCH] IntelFsp2Pkg/FspSecCore: Make FSP funcitons position independent

[edk2] [PATCH] IntelFsp2Pkg/Tools: Add PE32 section rebasing support

[edk2] [PATCH] IntelFsp2Pkg: Only include required header files in FspEas.h

[edk2] [PATCH] CorebootModulePkg/SecCore: Adding NASM files in SecCore module

[edk2] [PATCH] IntelFsp2Pkg/Tools: Add FSP rebasing function into SplitFspBin tool

[edk2] [PATCH] CorebootModulePkg/PciHostBridgeLib: Fix PCI 64bit memory BAR size issue

[edk2] [PATCH] IntelFsp2Pkg/Tools: Add BSF bit field support in GenCfgOpt tool

[edk2] [PATCH 1/1] CorebootPayloadPkg: Consume PlatformHookLib in PlatformBootManagerLib

[edk2] [PATCH 2/5] CorebootModulePkg: Add video resolution PCD initialization

[edk2] [PATCH 4/5] CorebootPayloadPkg: Switch to use generic BdxDxe driver

[edk2] [PATCH 5/5] CorebootPayloadPkg: Remove BdsPlatform library

[edk2] [PATCH 3/5] CorebootPayloadPkg: Add coreboot PlatfromBootManagerLib implementation

[edk2] [PATCH 1/5] CorebootModulePkg: Convert TAB to white space for CbSupportDxe driver

[edk2] [PATCH 0/5] CorebootPayloadPkg: Switch to use BdxDxe driver in MdeModulePkg

[edk2] [PATCH] CorebootModulePkg: Use PCD for memory type information initialization

[edk2] [PATCH] CorebootPayloadPkg: Use generic PciBus/PciHostBridge driver

[edk2] [PATCH] MdeModulePkg: Skip invalid bus number scanning in PciBusDxe driver

[edk2] [PATCH] CorebootPayloadPkg: Use generic SerialDxe driver

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